DRV8770PW [TI]
DRV8770: 100-V Brushed DC Gate Driver;
| 型号： | DRV8770PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV8770: 100-V Brushed DC Gate Driver 栅 |
| 文件： | 总27页 (文件大小：3001K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8770
SLVSFL8 – JULY 2021
DRV8770: 100-V Brushed DC Gate Driver
1 Features
3 Description
•
100-V H-bridge gate driver
The DRV8770 device provides two half-bridge gate
drivers, each capable of driving high-side and low-
side N-channel power MOSFETs. The integrated
bootstrap diode and external capacitor generate the
correct gate drive voltages for the high-side MOSFETs
while the GVDD drives the gates of the low-side
MOSFETs. The gate drive architecture supports gate
drive currents up to 750-mA source and 1.5-A sink.
– Drives N-channel MOSFETs (NMOS)
– Gate driver supply (GVDD): 5-20 V
– MOSFET supply (SHx) support up to 100 V
Integrated bootstrap diodes
Supports inverting and non-inverting INLx inputs
(QFN package)
•
•
•
Bootstrap gate drive architecture
– 750-mA source current
– 1.5-A Sink current
The high voltage tolerance of the gate drive pins
improves system robustness. The SHx phase pins
can tolerate significant negative voltage transients,
while the high-side gate driver supply can support
higher positive voltage transients (115-V absolute
maximum) on the BSTx and GHx pins. Small
propagation delay and delay matching specifications
minimize the dead-time requirement which further
improves efficiency. Undervoltage protection is
provided for both low and high side through GVDD
and BST undervoltage lockout.
•
•
•
•
Supports up to 15s battery powered applications
Low leakage current on SHx pins (<55 µA)
Absolute maximum BSTx voltage upto 115-V
Supports negative transients down to -22 V on
SHx pins
Adjustable deadtime through DT pin in QFN
package
Fixed Deadtime insertion of 200 ns in TSSOP
package
Supports 3.3-V, and 5-V logic inputs with 20-V abs
max
4-ns typical propogation delay matching
Compact QFN and TSSOP packages and
footprints
•
•
•
Device Information(1)
PART NUMBER
DRV8770PW
PACKAGE
TSSOP (20)
VQFN (24)
BODY SIZE (NOM)
6.40 mm × 4.40 mm
4.00 mm × 4.00 mm
•
•
DRV8770RGE
•
•
Efficient system design with Power Blocks
Integrated protection features
– BST undervoltage lockout (BSTUV)
– GVDD undervoltage (GVDDUV)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
PVDD
GVDD
DBx
BSTA, BSTB
2 Applications
GVDD
INHA
INHB
GHA, GHB
SHA, SHB
•
•
•
•
•
•
E-Bikes, E-Scooters, and E-Mobility
Cordless Garden and Power Tools, Lawnmowers
Cordless Vacuum Cleaners
Drones, Robotics, and RC Toys
Industrial and Logistics Robots
Power Tools
MCU
DRV8770
INLA
INLB
GLA, GLB
GND
Repeated for 2
half-bridges
Simplified Schematic for DRV8770
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8770
SLVSFL8 – JULY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings Comm ...................................................5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................8
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................13
8 Application and Implementation..................................14
8.1 Application Information............................................. 14
8.2 Typical Application.................................................... 14
9 Power Supply Recommendations................................17
9.1 Bulk Capacitance Sizing........................................... 17
10 Layout...........................................................................18
10.1 Layout Example...................................................... 18
10.2 Layout Guidelines................................................... 18
11 Device and Documentation Support..........................19
11.1 Receiving Notification of Documentation Updates..19
11.2 Support Resources................................................. 19
11.3 Trademarks............................................................. 19
11.4 Electrostatic Discharge Caution..............................19
11.5 Glossary..................................................................19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
July 2021
*
Initial Release
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5 Pin Configuration and Functions
INLA
INLB
1
2
3
4
5
6
18
17
16
15
14
13
SHA
BSTB
GHB
RSVD2
GVDD
MODE
GND
Thermal
Pad
SHB
RSVD6
RSVD5
Figure 5-1. DRV8770 RGE Package 24-Pin VQFN With Exposed Thermal Pad Top View
Table 5-1. Pin Functions—24-Pin DRV8770 Device
PIN
TYPE(1)
DESCRIPTION
NAME
BSTA
BSTB
DT
NO.
20
17
21
19
16
11
10
6
O
O
Bootstrap output pin. Connect capacitor between BSTA and SHA
Bootstrap output pin. Connect capacitor between BSTB and SHB
I
Deadtime input pin. Connect resistor to ground for variable deadtime, fixed deadtime when left it floating
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device ground.
GHA
GHB
GLA
O
O
O
GLB
O
GND
PWR
Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal to 10-uF local capacitance
between the GVDD and GND pins.
GVDD
4
PWR
INHA
INHB
INLA
INLB
22
23
1
I
I
I
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
2
Mode Input controls polarity of GLx compared to INLx inputs.
MODE
5
I
Mode pin floating: GLx output polarity same(Non-Inverted) as INLx input
Mode pin to GVDD: GLx output polarity inverted compared to INLx input
NC
7, 8
NC
No internal connection. This pin can be left floating or connected to system ground.
RSVD1,
RSVD2,
RSVD3,
RSVD5,
RSVD6
3, 9, 13, 14, 24
I
TI reserved pin. Leave pin floating.
RSVD4
SHA
12
18
15
I
I
I
TI reserved pin. Connect to GND
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
(1) PWR = power, I = input, O = output, NC = no connection
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INHA
INHB
1
2
20
19
18
17
16
15
14
13
12
11
BSTA
GHA
RSVD1
INLA
3
SHA
4
BSTB
GHB
INLB
5
RSVD2
GVDD
GND
6
SHB
7
RSVD6
RSVD5
RSVD4
GLA
8
RSVD3
GLB
9
10
Figure 5-2. DRV8770 PW Package 20-Pin TSSOP Top View
Table 5-2. Pin Functions—20-Pin DRV8770 Device
PIN
TYPE(1)
DESCRIPTION
NAME
BSTA
BSTB
GHA
GHB
GLA
NO.
20
17
19
16
11
10
8
O
O
Bootstrap output pin. Connect capacitor between BSTA and SHA
Bootstrap output pin. Connect capacitor between BSTB and SHB
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device ground.
O
O
O
GLB
O
GND
PWR
Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal to 10-uF local capacitance
between the GVDD and GND pins.
GVDD
7
PWR
INHA
INHB
INLA
INLB
1
2
4
5
I
I
I
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
RSVD1,
RSVD2,
RSVD3,
RSVD5,
RSVD6
3, 6, 9, 13, 14
I
TI reserved pin. Leave pin floating.
RSVD4
SHA
12
18
15
I
I
I
TI reserved pin. Connect to GND
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
(1) PWR = power, I = input, O = output, NC = no connection
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-22
-0.3
-5
MAX UNIT
Gate driver regulator pin voltage
Bootstrap pin voltage
GVDD
21.5
115
V
V
BSTx
Bootstrap pin voltage
BSTx with respect to SHx
21.5
V
Logic pin voltage
INHx, INLx, MODE, DT
VGVDD+0.3
115
V
High-side gate drive pin voltage
High-side gate drive pin voltage
Transient 500-ns high-side gate drive pin voltage
Low-side gate drive pin voltage
Transient 500-ns low-side gate drive pin voltage
High-side source pin voltage
Ambient temperature, TA
GHx
V
GHx with respect to SHx
22
V
GHx with respect to SHx
22
V
GLx
GLx
SHx
-0.3
-5
VGVDD+0.3
VGVDD+0.3
100
V
V
-22
–40
–40
–65
V
125
°C
°C
°C
Junction temperature, TJ
150
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings Comm
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
5
NOM
MAX UNIT
VGVDD
VSHx
Power supply voltage
GVDD
SHx
20
85
V
V
High-side source pin voltage
-2
Transient 2µs high-side source pin
voltage
VSHx
SHx
-22
85
V
VBST
VBST
VIN
Bootstrap pin voltage
BSTx
5
5
0
0
105
20
V
V
Bootstrap pin voltage
BSTx with respect to SHx
INHx, INLx, MODE, DT
INHx, INLx
Logic input voltage
GVDD
200
2
V
fPWM
VSHSL
CBOOT
TA
PWM frequency
kHz
V/ns
µF
°C
°C
Slew rate on SHx pin
(1)
Capacitor between BSTx and SHx
Operating ambient temperature
Operating junction temperature
1
–40
–40
125
150
TJ
(1) Current flowing through boot diode (DBOOT) needs to be limited for CBOOT > 1µF
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UNIT
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6.4 Thermal Information
DRV8770
PW (TSSOP)
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
49.3
20 PINS
97.4
38.3
48.8
4.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
42.5
RθJB
ΨJT
ΨJB
Junction-to-board thermal resistance
26.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.2
48.4
N/A
26.4
RθJC(bot) Junction-to-case (bottom) thermal resistance
11.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
4.8 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (GVDD, BSTx)
GVDD standby mode current
INHx = INLX = 0; VBSTx = VGVDD
400
400
2
800
825
4
1400
1400
7
µA
µA
µA
µA
IGVDD
INHx = INLX = Switching @20kHz; VBSTx
= VGVDD; NO FETs connected
GVDD active mode current
Bootstrap pin leakage current
ILBSx
VBSTx = VSHx = 85V; VGVDD = 0V
INHx = Switching@20kHz
Bootstrap pin active mode transient
leakage current
ILBS_TRAN
30
105
220
Bootstrap pin active mode leakage
static current
ILBS_DC
ILSHx
INHx = High
30
30
85
55
150
80
µA
µA
INHx = INLX = 0; VBSTx - VSHx = 12V;
VSHx = 0 to 85V
High-side source pin leakage current
LOGIC-LEVEL INPUTS (INHx, INLx, MODE)
VIL_MODE
VIL
VIH_MODE
VIH
VHYS_MODE
VHYS
Input logic low voltage
Input logic low voltage
Input logic high voltage
Input logic high voltage
Input hysteresis
Mode pin
0.6
0.8
V
V
INLx, INHx pins
Mode pin
3.7
2.0
V
INLx, INHx pins
Mode pin
V
1600
40
2000
100
2400
260
mV
mV
Input hysteresis
INLx, INHx pins
VPIN (Pin Voltage) = 0 V; INLx in non-
inverting mode
-1
5
0
20
1
30
µA
µA
µA
µA
IIL_INLx
INLx Input logic low current
INLx Input logic high current
VPIN (Pin Voltage) = 0 V; INLx in inverting
mode
VPIN (Pin Voltage) = 5 V; INLx in non-
inverting mode
5
20
30
IIH_INLx
VPIN (Pin Voltage) = 5 V; INLx in inverting
mode
0
0.5
1.5
IIL
INHx, MODE Input logic low current VPIN (Pin Voltage) = 0 V;
INHx, MODE Input logic high current VPIN (Pin Voltage) = 5 V;
-1
5
0
20
1
30
µA
µA
kΩ
kΩ
kΩ
kΩ
IIH
RPD_INHx
RPD_INLx
RPU_INLx
RPD_MODE
INHx Input pulldown resistance
INLx Input pulldown resistance
INLx Input pullup resistance
To GND
120
120
120
120
200
200
200
200
280
280
280
280
To GND, INLx in non-inverting mode
To INT_5V, INLx in inverting mode
To GND
MODE Input pulldown resistance
GATE DRIVERS (GHx, GLx, SHx, SLx)
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4.8 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
VGHx_LO
VGHx_HI
VGLx_LO
VGLx_HI
High-side gate drive low level voltage
High-side gate drive high level
0
0.15
0.35
V
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
0.3
0
0.6
0.15
0.6
1.2
0.35
1.2
V
V
V
voltage (VBSTx - VGHx
)
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
Low-side gate drive low level voltage
Low-side gate drive high level voltage IGHx = 100 mA; VGVDD = 12V; No FETs
0.3
(VGVDD - VGHx
)
connected
IDRIVEP_HS
IDRIVEN_HS
IDRIVEP_LS
IDRIVEN_LS
High-side peak source gate current
High-side peak sink gate current
Low-side peak source gate current
Low-side peak sink gate current
GHx-SHx = 12V
GHx-SHx = 0V
GLx = 12V
400
850
400
850
750
1500
750
1200
2100
1200
2100
mA
mA
mA
mA
GLx = 0V
1500
INHx, INLx to GHx, GLx; VGVDD = VBSTx
- VSHx > 8V; SHx = 0V, No load on GHx
and GLx
tPD
Input to output propagation delay
70
125
±4
180
30
ns
ns
GHx turning OFF to GLx turning ON, GLx
turning OFF to GHx turning ON; VGVDD =
VBSTx - VSHx > 8V; SHx = 0V, No load on
GHx and GLx
Matching propagation delay per
phase
tPD_match
-30
GHx/GLx turning ON to GHy/GLy turning
Matching propagation delay phase to ON, GHx/GLx turning OFF to GHy/GLy
tPD_match
-30
±4
30
ns
phase
turning OFF; VGVDD = VBSTx - VSHx
>
8V; SHx = 0V, No load on GHx and GLx
CLOAD = 1000 pF; VGVDD = VBSTx
VSHx > 8V; SHx = 0V
-
-
tR_GLx
tR_GHx
tF_GLx
tF_GHx
GLx rise time (10% to 90%)
GHx rise time (10% to 90%)
GLx fall time (90% to 10%)
GHx fall time (90% to 10%)
10
10
5
24
24
12
12
50
50
30
30
ns
ns
ns
ns
CLOAD = 1000 pF; VGVDD = VBSTx
VSHx > 8V; SHx = 0V
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx
8V; SHx = 0V
>
>
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx
8V; SHx = 0V
5
DT pin connected to GND
150
150
215
200
280
260
ns
ns
ns
tDEAD
Gate drive dead time
40 kΩ between DT pin and GND
400 kΩ between DT pin and GND
1500
2000
2600
Minimum input pulse width on INHx,
INLx that changes the output on
GHx, GLx
tPW_MIN
40
70
150
ns
BOOTSTRAP DIODES
IBOOT = 100 µA
IBOOT = 100 mA
0.45
2
0.7
2.3
0.85
3.1
V
V
VBOOTD Bootstrap diode forward voltage
Bootstrap dynamic resistance
(ΔVBOOTD/ΔIBOOT
RBOOTD
IBOOT = 100 mA and 80 mA
11
15
25
Ω
)
PROTECTION CIRCUITS
Supply rising
4.45
4.2
4.6
4.35
280
4.7
4.4
V
V
Gate Driver Supply undervoltage
lockout (GVDDUV)
VGVDDUV
Supply falling
VGVDDUV_HYS Gate Driver Supply UV hysteresis
Rising to falling threshold
250
310
mV
Gate Driver Supply undervoltage
deglitch time
tGVDDUV
5
3.6
3.5
10
4.2
4
13
4.8
4.5
µs
V
Boot Strap undervoltage lockout
Supply rising
Supply falling
(VBSTx - VSHx
Boot Strap undervoltage lockout
(VBSTx - VSHx
)
VBSTUV
V
)
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4.8 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
200
10
MAX
UNIT
mV
µs
VBSTUV_HYS
tBSTUV
Bootstrap UV hysteresis
Bootstrap undervoltage deglitch time
Rising to falling threshold
6
22
6.6 Typical Characteristics
Figure 6-2. Supply Current Over Temperature
Figure 6-1. Supply Current Over GVDD Voltage
Figure 6-4. Bootstrap Diode Forward Voltage over
GVDD Voltage
Figure 6-3. Bootstrap Resistance Over GVDD
Voltage
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7 Detailed Description
7.1 Overview
The DRV8770 device is a gate driver for brushed DC motor drive applications. This device decreases system
component count, reduces PCB area, and saves cost by integrating two independent half-bridge gate drivers
and bootstrap diodes.
DRV8770 device integrates bootstrap diode used along with boot capacitor to generate voltage to drive high
side N-channel MOSFET. The high-side and low-side gate drivers and can drive 750-mA source, 1.5-A sink
currents with total 30-mA average output current. DRV8770 is available in 0.5-mm pitch QFN and 0.65 TSSOP
surface-mount packages. The QFN size is 4 × 4 mm (0.5-mm pin pitch) for the 24-pin package, and TSSOP size
is 6.5 × 6.4 mm (0.65-mm pin pitch) for the 20-pin package.
7.2 Functional Block Diagram
GVDD
PVDD
CGVDD
GVDD
BSTA
CBSTA
RGHA
GHA
SHA
INHA
HS
HS
INT_5V
GVDD
LS
INLA/INLA
RGLA
GLA
LS
MODE**
Gate Driver
Input logic
control
GVDD
BDC
BSTB
GHB
SHB
PVDD
CBSTB
Shoot-
Through
Preven on
RGHB
HS
HS
INHB
INT_5V
GVDD
LS
Gate Driver
INLB/INLB
RGLB
GLB
LS
MODE**
GND
DT**
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
X
X
X
MODE**
X
X
PowerPAD**
** QFN-24 Package
Figure 7-1. Block Diagram for DRV8770
7.3 Feature Description
7.3.1 Gate Drivers
The DRV8770 integrates two half-bridge gate drivers, each capable of driving high-side and low-side N-channel
power MOSFETs. Input on GVDD provides the gate bias voltage for the low-side MOSFETs. The high voltage is
generated using a bootstrap capacitor and GVDD supply. DRV8770 device integrates the bootstrap diode. The
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half-bridge gate drivers can be used in combination to drive a brushed DC motor or separately to drive other
types of loads.
7.3.1.1 Gate Drive Timings
7.3.1.1.1 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the input deglitcher delay and the delay through the analog gate
drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. The analog gate drivers have a small delay that contributes to the overall propagation delay of the
device.
7.3.1.1.2 Deadtime and Cross-Conduction Prevention
In the DRV8770, high- and low-side inputs operate independently, with an exception to prevent cross conduction
when high and low side are turned ON at same time. The DRV8770 turns OFF high- and low- side output to
prevent shoot through when high- and low-side inputs are logic high at same time.
The DRV8770 also provides deadtime insertion to prevents both external MOSFETs of each power-stage from
switching on at the same time. In devices with DT pin (QFN package device), deadtime can be linearily adjusted
between 200 ns to 2000 ns by connecting resistor between DT and ground. When DT pin is connected to
ground, fixed deadtime of 200 ns (typical value) is inserted. The value of resistor can be caculated using
Equation 1.
(1)
In device without DT pin (TSSOP package device), fixed deadtime of 200 ns (Typical value) is inserted to
prevent high and low side gate output turning on at same time.
INHx/INLx Inputs
INHx
INLx
GHx/GLx outputs
GHx
GLx
DT
DT
Cross
Conduction
Prevention
Figure 7-2. Cross Conduction Prevention and Deadtime Insertion
7.3.1.2 Mode (Inverting and non-inverting INLx)
The DRV8770 has flexibility of accepting different kind of inputs on INLx. In the QFN (RGE) package variant,
the MODE pin provides option of GLx output inverted or non-inverted compared to polarity of signal on INLx pin.
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When the MODE pin is left floating, INLx is configured to be in non-inverting mode and GLx output is in phase
with INLx (see Figure 7-3). When MODE pin is connected to GVDD, GLx output is out of phase with inputs (see
Figure 7-4). The TSSOP (PW) package variant does not have a MODE pin, so the INLx pins are inverted by
default.
INHx
INLx
GHx
GLx
DT
DT
DT
Figure 7-3. Non-Inverted INLx inputs (MODE = floating)
INHx
INLx
GHx
GLx
DT
DT
DT
Figure 7-4. Inverted INLx inputs (MODE = GVDD or TSSOP package variant)
Table 7-1 shows the states of the gate drivers and FET half bridge when MODE = floating.
Table 7-1. Logic table when MODE = floating
INHx
INLx
GHx
GLx
Half Bridge State
Z, FETs disabled
0
0
1
0
1
0
L
L
L
H
L, low-side FET enabled
H, high-side FET enabled
H
L
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Table 7-1. Logic table when MODE = floating (continued)
INHx
INLx
GHx
GLx
Half Bridge State
1
1
L
L
Z, invalid state
Table 7-2 shows the states of the gate drivers and FET half bridge for the inverted mode (MODE = GVDD or the
default mode of the TSSOP package). In this mode, the INHx and INLx pins can be tied together to reduce the
number of control signals from a microcontroller, as shown in Table 7-3. In this configuration, the device controls
the deadtime as described in Section 7.3.1.1.2.
Table 7-2. Logic table when MODE = GVDD or TSSOP package variant
INHx
INLx
GHx
GLx
Half Bridge State
L, low-side FET enabled
Z, FETs disabled
0
0
1
1
0
1
0
1
L
L
H
L
L
L
Z, invalid state
H
L
H, high-side FET enabled
Table 7-3. Logic table when INHx = INLx for MODE = GVDD or TSSOP package variant
INHx = INLx
GHx
GLx
Half Bridge State
L, low-side FET enabled
H, high-side FET enabled
0
1
L
H
H
L
7.3.2 Pin Diagrams
Figure 7-5 shows the input structure for the logic level pins INHx, INLx. INHx and INLx has passive pull down, so
when inputs are floating the output of gate driver will be pulled low. Figure 7-6 shows the input structure for the
logic level pin inverted INLx. INLx in inverted mode has passive pull up, so when inputs are floating the output of
gate driver will be pulled low.
INT_5V
INPUT
INPUT
200 kꢀ
Logic High
Logic Low
Logic High
Logic Low
INHx
INLx
INLx
200 kꢀ
Figure 7-6. Inverted INLx Logic-Level Input Pin
Structure
Figure 7-5. INHx and Non-Inverted INLx Logic-
Level Input Pin Structure
7.3.3 Gate Driver Protective Circuits
The DRV8770 is protected against BSTx undervoltage and GVDD undervoltage events.
Table 7-4. Fault Action and Response
FAULT
CONDITION
GATE DRIVER
RECOVERY
Automatic:
VBSTx > VBSTUV and low to high
PWM edge detected on INHx pin
VBSTx undervoltage
(BSTUV)
VBSTx < VBSTUV
GHx - Hi-Z
GVDD undervoltage
(GVDDUV)
Automatic:
VGVDD > VGVDDUV
VGVDD < VGVDDUV
Hi-Z
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7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
The DRV8770 has separate voltage comparator to detect undervoltage condition for each phase. If at any time
the supply voltage on the BSTx pin falls lower than the VBSTUV threshold, high side external MOSFETs of
that particular phase is disabled by disabling (Hi-Z) GHx pin. Normal operation starts again when the BSTUV
condition clears and low to high PWM edge is detected on INHx input on the same phase BSTUV was detected.
BSTUV protection ensures that high side gate driver are not switched when BSTx pin has lower value.
7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
If at any time the voltage on the GVDD pin falls lower than the VGVDDUV threshold voltage, all of the external
MOSFETs are disabled. Normal operation starts again GVDDUV condition clears. GVDDUV protection ensures
that gate driver are not switched when GVDD input is at lower value.
7.4 Device Functional Modes
Whenever the GVDD > VGVDDUV and VBSTX > VBSTUV the device is in operating (active) mode, in this condition
gate driver output GHx and GLX will follow respective inputs INHx and INLx.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DRV8770 is primarily used for brushed DC motor control. The design procedures in the Section 8.2 section
highlight how to use and configure the DRV8770.
8.2 Typical Application
GVDD
External
Supply
DRV8770
GVDD
CGVDD
PVDD
GND
GND
INHA
INLA
BSTA
CBSTA
RGHA
PWM
GHA
SHA
INHB
INLB
MCU
RGLA
GLA
PVDD
BSTB
BDC
CBSTB
GVDD
RGHB
GHB
SHB
MODE**
DT**
GND or Floating
RGLB
GLB
** QFN-24 Package
R
R
IN-
INx+
IN+
INA+ INB+
R
R
INx-
IN-
–
OUT
IN+
+
Reference
Voltage
INA-
INB-
V
R
REF
Current Sense Amplifier 1x or 2x
+
–
Figure 8-1. Application Schematic
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8.2.1 Design Requirements
Table 8-1 lists the example design input parameters for system design.
Table 8-1. Design Parameters
EXAMPLE DESIGN PARAMETER
MOSFET
REFERENCE
EXAMPLE VALUE
-
CSD19532Q5B
12 V
Gate Supply Voltage
Gate Charge
VGVDD
QG
48 nC
8.2.2 Detailed Design Procedure
Bootstrap Capacitor and GVDD Capacitor Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for
normal operation. Equation 2 calculates the maximum allowable voltage drop across the bootstrap capacitor:
¿8$56: = 8)8&& F8$116&F8
$5678
(2)
= 12 V – 0.85 V – 4.5 V = 6.65 V
where
•
•
•
VGVDD is the supply voltage of the gate drive
VBOOTD is the forward voltage drop of the bootstrap diode
VBSTUV is the threshold of the bootstrap undervoltage lockout
In this example the allowed voltage drop across bootstrap capacitor is 6.65 V. It is generally recommended that
ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible.
Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.
The total charge needed per switching cycle can be estimated with Equation 3:
+.$5_64#05
3616 = 3) +
B
59
(3)
= 48 nC + 220 μA/20 kHz = 50 nC + 11 nC = 59 nC
where
•
•
•
QG is the total MOSFET gate charge
ILBS_TRAN is the bootstrap pin leakage current
fSW is the is the PWM frequency
The minimum bootstrap capacitor an then be estimated as below assuming 1-V ΔVBSTx
:
3
%
=
616W
$56_/+0
¿8
$56:
(4)
= 59 nC / 1 V = 59 nF
The calculated value of minimum bootstrap capacitor is 59 nF. It should be noted that, this value of capacitance
is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than calculated
value to allow for situations where the power stage may skip pulse due to various transient conditions. It is
recommended to use a 100 nF bootstrap capacitor in this example. It is also recommended to include enough
margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.
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Note
If the bootstrap capacitor value (CBSTx) is above 1 μF, then current flowing through internal bootstrap
diode needs to be limited.
The local GVDD bypass capacitor must be greater than the value of bootstrap capacitor value (generally 10
times the bootstrap capacitor value).
%
)8&&
R 10 × %$56:
(5)
= 10*100 nF = 1 μF
For this example application, choose 1-µF CGVDD capacitor. Choose a capacitor with a voltage rating at
least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant
capacitance when biased. This value also improves the long term reliability of the system.
Gate Resistance Selection
The slew rate of the SHx connection will be dependent on the rate at which the gate of the external MOSFETs is
controlled. The pull-up/pull-down strength of the DRV8770 is fixed internally, hence slew rate of gate voltage can
be controlled with an external series gate resistor. In some applications the gate charge, which is load on gate
driver device, is significantly larger than gate driver peak output current capability. In such applications external
gate resistors can limit the peak output current of the gate driver. External gate resistors are also used to damp
ringing and noise.
The specific parameters of the MOSFET, system voltage, and board parasitics will all affect the final slew rate,
so generally selecting an optimal value or configuration of external gate resistor is an iterative process.
8.2.3 Application Curves
GHA
GHA
SHA
SHA
GLA
GLA
Figure 8-2. Gate voltages, SHx rising with 15 ohm
gate resistor and CSD19532Q5B MOSFET
Figure 8-3. Gate voltages, SHx falling with 15 ohm
gate resistor and CSD19532Q5B MOSFET
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9 Power Supply Recommendations
The DRV8770 is designed to operate from an input voltage supply (GVDD) range from 4.8 V to 20 V. A local
bypass capacitor should be placed between the GVDD and GND pins. This capacitor should be located as close
to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is recommended
to use two capacitors across GVDD and GND: a low capacitance ceramic surface-mount capacitor for high
frequency filtering placed very close to GVDD and GND pin, and another high capacitance value surfacemount
capacitor for device bias requirements. In a similar manner, the current pulses delivered by the GHx pins are
sourced from the BSTx pins. Therefore, capacitor across the BSTx to SHx is recommended, it should be high
enough capacitance value capacitor to deliver GHx pulses.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply's type, capacitance, and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 9-1. Motor Drive Supply Parasitics Example
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10 Layout
10.1 Layout Example
S
S
S
G
D
D
D
D
GND
GND
OUT1
D
D
D
D
G
S
S
S
CBSTA
PVDD
GND
18
17
16
15
14
13
INLA
INLB
1
2
3
4
5
6
SHA
CBSTB
D
D
D
D
G
S
S
S
BSTB
GHB
RSVD2
GVDD
MODE
GND
Thermal
Pad
GVDD
CGVDD
SHB
RSVD6
RSVD5
CBULK
OUT2
S
S
S
G
D
D
D
D
Thermal vias
from pad to
GND layer
GND
10.2 Layout Guidelines
•
Low ESR/ESL capacitors must be connected close to the device between GVDD and GND and between
BSTx and SHx pins to support high peak currents drawn from GVDD and BSTx pins during the turn-on of the
external MOSFETs.
•
•
•
To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground.
In order to avoid large negative transients on the switch node (SHx) pin, the parasitic inductances between
the source of the high-side MOSFET and the source of the low-side MOSFET must be minimized.
In order to avoid unexpected transients, the parasitic inductance of the GHx, SHx, and GLx connections must
be minimized. Minimize the trace length and number of vias wherever possible. Minimum 10 mil and typical
15 mil trace width is recommended.
•
•
Resistance between DT and GND must be place as close as possible to device
Place the gate driver as close to the MOSFETs as possible. Confine the high peak currents that charge
and discharge the MOSFET gates to a minimal physical area by reducing trace length. This confinement
decreases the loop inductance and minimize noise issues on the gate terminals of the MOSFETs.
In QFN package device variants, NC pins can be connected to GND to increase ground conenction between
thermal pad and external ground plane.
•
•
Refer to sections General Routing Techniques and MOSFET Placement and Power Stage Routing in
Application Report
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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2-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8770RGER
ACTIVE
VQFN
RGE
24
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8770
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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3-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8770RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGE 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DRV8770RGER
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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