DRV8814_16 [TI]

DC Motor Driver IC;


型号：	DRV8814_16
厂家：	TEXAS INSTRUMENTS
描述：	DC Motor Driver IC
文件：	总16页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DRV8814

www.ti.com

SLVSAB9C –MAY 2010–REVISED MARCH 2011

DC MOTOR DRIVER IC

Check for Samples: DRV8814

FEATURES

•

8-V to 45-V Operating Supply Voltage Range

Thermally Enhanced Surface Mount Package

•

Dual H-Bridge Current-Control Motor Driver

APPLICATIONS

–

Drives Two DC Motors

Brake Mode

•

Printers

Scanners

Office Automation Machines

Gaming Machines

Factory Automation

Robotics

Two-Bit Winding Current Control Allows Up

to 4 Current Levels

–

Low MOSFET On-Resistance

•

2.5-A Maximum Drive Current at 24 V, 25°C

Built-In 3.3-V Reference Output

Industry Standard Parallel Digital Control

Interface

DESCRIPTION

The DRV8814 provides an integrated motor driver solution for printers, scanners, and other automated

equipment applications. The device has two H-bridge drivers, and is intended to drive DC motors. The output

driver block for each consists of N-channel power MOSFET’s configured as H-bridges to drive the motor

windings. The DRV8814 can supply up to 2.5-A peak or 1.75-A RMS output current (with proper heatsinking at

24 V and 25°C) per H-bridge.

A simple parallel digital control interface is compatible with industry-standard devices. Decay mode is

programmable to allow braking or coasting of the motor when disabled.

Internal shutdown functions are provided for over current protection, short circuit protection, under voltage

lockout and overtemperature.

TheDRV8814 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br).

ORDERING INFORMATION⁽¹⁾

ORDERABLE PART

NUMBER

TOP-SIDE

MARKING

T_A

PACKAGE⁽²⁾

–40°C to 85°C

PowerPAD™ (HTSSOP) - PWP

Reel of 2000

DRV8814PWPR

8814

(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DRV8814

SLVSAB9C –MAY 2010–REVISED MARCH 2011

www.ti.com

DEVICE INFORMATION

Functional Block Diagram

Int. VCC

Internal

CP1

CP2

Reference &

Regs

LS Gate

Drive

0.01mF

Charge

Pump

V3P3OUT

3.3V

VCP

Thermal

Shut down

0.1mF

HS Gate

Drive

AVREF

BVREF

VMA

AOUT1

Motor

Driver A

APHASE

AENBL

AI0

DCM

AOUT2

ISENA

AI1

BPHASE

BENBL

BI0

Control

Logic

VMB

BI1

BOUT1

DECAY

nRESET

nSLEEP

nFAULT

Motor

Driver B

DCM

BOUT2

ISENB

GND

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NAME

SLVSAB9C –MAY 2010–REVISED MARCH 2011

Table 1. TERMINAL FUNCTIONS

EXTERNAL COMPONENTS

OR CONNECTIONS

I/O⁽¹⁾

DESCRIPTION

POWER AND GROUND

GND

VMA

VMB

14, 28

Device ground

Bridge A power supply

Bridge B power supply

Connect to motor supply (8 - 45 V). Both pins

must be connected to same supply.

Bypass to GND with a 0.47-μF 6.3-V ceramic

capacitor. Can be used to supply VREF.

V3P3OUT

3.3-V regulator output

CP1

CP2

Charge pump flying capacitor

Connect a 0.01-μF 50-V capacitor between

CP1 and CP2.

Connect a 0.1-μF 16-V ceramic capacitor to

VM.

VCP

High-side gate drive voltage

CONTROL

AENBL

APHASE

AI0

Bridge A enable

Logic high to enable bridge A

Bridge A phase (direction)

Logic high sets AOUT1 high, AOUT2 low

Sets bridge A current: 00 = 100%,

01 = 71%, 10 = 38%, 11 = 0

Bridge A current set

AI1

BENBL

BPHASE

BI0

Bridge B enable

Logic high to enable bridge B

Bridge B phase (direction)

Logic high sets BOUT1 high, BOUT2 low

Sets bridge B current: 00 = 100%,

01 = 71%, 10 = 38%, 11 = 0

Bridge B current set

BI1

Low = brake (slow decay),

high = coast (fast decay)

DECAY

Decay (brake) mode

Reset input

Active-low reset input initializes internal logic

and disables the H-bridge outputs

nRESET

Logic high to enable device, logic low to enter

low-power sleep mode

nSLEEP

AVREF

Sleep mode input

Bridge A current set reference input

Reference voltage for winding current set.

Can be driven individually with an external

DAC for microstepping, or tied to a reference

(e.g., V3P3OUT).

BVREF

Bridge B current set reference input

STATUS

Logic low when in fault condition (overtemp,

overcurrent)

nFAULT

Fault

OUTPUT

ISENA

Bridge A ground / Isense

Bridge B ground / Isense

Bridge A output 1

Connect to current sense resistor for bridge A

Connect to current sense resistor for bridge B

ISENB

AOUT1

AOUT2

BOUT1

BOUT2

Connect to motor winding A

Connect to motor winding B

Bridge A output 2

Bridge B output 1

Bridge B output 2

(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

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SLVSAB9C –MAY 2010–REVISED MARCH 2011

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PWP PACKAGE

(TOP VIEW)

CP1

CP2

VCP

VMA

GND

BI1

BI0

AI1

AOUT1

ISENA

AOUT2

BOUT2

ISENB

BOUT1

VMB

AVREF

BVREF

GND

AI0

BPHASE

BENBL

AENBL

APHASE

DECAY

nFAULT

nSLEEP

nRESET

V3P3OUT

GND

(PPAD)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1) (2)

VALUE

–0.3 to 47

–0.5 to 7

UNIT

VMx

Power supply voltage range

Digital pin voltage range

VREF

Input voltage

–0.3 to 4

ISENSEx pin voltage

–0.3 to 0.8

Internally limited

2.5

Peak motor drive output current, t < 1 μS

Continuous motor drive output current⁽³⁾

Continuous total power dissipation

Operating virtual junction temperature range

Operating ambient temperature range

Storage temperature range

See Dissipation Ratings table

T_J

–40 to 150

–40 to 85

–60 to 150

°C

T_A

°C

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Power dissipation and thermal limits must be observed.

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SLVSAB9C –MAY 2010–REVISED MARCH 2011

THERMAL INFORMATION

DRV8814

THERMAL METRIC⁽¹⁾

PWP

28 PINS

31.6

15.9

5.6

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

θ_JCtop

θ_JB

°C/W

ψ_JT

0.2

ψ_JB

5.5

θ_JCbot

1.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_M

Motor power supply voltage range⁽¹⁾

VREF input voltage⁽²⁾

V_REF

I_V3P3

f_PWM

3.5

V3P3OUT load current

kHz

Externally applied PWM frequency

100

(1) All V_Mpins must be connected to the same supply voltage.

(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

POWER SUPPLIES

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_VM

VM operating supply current

VM sleep mode supply current

V_M= 24 V, f_PWM< 50 kHz

μA

I_VMQ

V_UVLO

V3P3OUT REGULATOR

V_M= 24 V

VM undervoltage lockout voltage V_Mrising

7.8

8.2

V_3P3

V3P3OUT voltage

IOUT = 0 to 1 mA

3.2

3.3

0.6

3.4

LOGIC-LEVEL INPUTS

V_IL

V_IH

V_HYS

I_IL

Input low voltage

0.7

5.25

0.6

Input high voltage

Input hysteresis

Input low current

Input high current

0.3

0.45

VIN = 0

–20

μA

I_IH

VIN = 3.3 V

100

nFAULT OUTPUT (OPEN-DRAIN OUTPUT)

V_OL

I_OH

Output low voltage

I_O= 5 mA

V_O= 3.3 V

0.5

Output high leakage current

μA

DECAY INPUT

V_IL

V_IH

I_IN

Input low threshold voltage

For slow decay (brake) mode

For fast decay (coast) mode

VIN = 0 V to 3.3 V

0.8

Input high threshold voltage

Input current

±40

μA

H-BRIDGE FETS

V_M= 24 V, I_O= 1 A, T_J= 25°C

V_M= 24 V, I_O= 1 A, T_J= 85°C

V_M= 24 V, I_O= 1 A, T_J= 25°C

V_M= 24 V, I_O= 1 A, T_J= 85°C

0.2

0.25

0.2

R_DS(ON)

HS FET on resistance

Ω

0.32

R_DS(ON)

I_OFF

LS FET on resistance

Ω

0.25

0.32

Off-state leakage current

–20

μA

MOTOR DRIVER

Internal current control PWM

frequency

f_PWM

kHz

t_BLANK

t_R

Current sense blanking time

Rise time

3.75

μs

300

t_F

Fall time

PROTECTION CIRCUITS

I_OCPOvercurrent protection trip level

t_TSDThermal shutdown temperature

CURRENT CONTROL

Die temperature

150

160

180

°C

I_REF

VREF input current

VREF = 3.3 V

–3

635

445

225

685

492

276

μA

V/V

xVREF = 3.3 V, 100% current setting

xVREF = 3.3 V, 71% current setting

xVREF = 3.3 V, 38% current setting

Reference only

660

469

251

V_TRIP

xISENSE trip voltage

A_ISENSE

Current sense amplifier gain

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SLVSAB9C –MAY 2010–REVISED MARCH 2011

FUNCTIONAL DESCRIPTION

PWM Motor Drivers

The DRV8814 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the

motor control circuitry is shown in Figure 1.

OCP

VCP, VGD

AOUT1

Pre-

DCM

AENBL

drive

APHASE

DECAY

AOUT2

PWM

OCP

AISEN

A = 5

AI[1:0]

AVREF

DAC

OCP

VCP, VGD

BOUT1

Pre-

BENBL

drive

DCM

BPHASE

BOUT2

PWM

OCP

BISEN

A = 5

BI[1:0]

BVREF

DAC

Figure 1. Motor Control Circuitry

Note that there are multiple VM pins. All VM pins must be connected together to the motor supply voltage.

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Bridge Control

The xPHASE input pins control the direction of current flow through each H-bridge, and hence the direction of

rotation of a DC motor. The xENBL input pins enable the H-bridge outputs when active high, and can also be

used for PWM speed control of the motor. Note that the state of the DECAY pin selects the behavior of the

bridge when xENBL = 0, allowing the selection of slow decay (brake) or fast decay (coast). Table 2 shows the

logic.

Table 2. H-Bridge Logic

DECAY

xENBL

xPHASE

xOUT1

xOUT2

Current Regulation

The maximum current through the motor winding is regulated by a fixed-frequency PWM current regulation, or

current chopping. When the H-bridge is enabled, current rises through the winding at a rate dependent on the

DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge

disables the current until the beginning of the next PWM cycle.

For DC motors, current regulation is used to limit the start-up and stall current of the motor. Speed control is

typically performed by providing an external PWM signal to the ENBLx input pins.

If the current regulation feature is not needed, it can be disabled by connecting the xISENSE pins directly to

ground, and connecting the xVREF pins to V3P3.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor

connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input

from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale,

plus zero.

The full-scale (100%) chopping current is calculated in Equation 1.

V_REFX

I_CHOP=

5 · R_ISENSE

(1)

Example:

If a 0.25-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current will be

2.5 V / (5 x 0.25 Ω) = 2 A.

Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the

full-scale current set by the VREF input pin and sense resistance. The function of the pins is shown in Table 3.

Table 3. H-Bridge Pin Functions

RELATIVE CURRENT

(% FULL-SCALE CHOPPING CURRENT)

xI1

xI0

0% (Bridge disabled)

38%

71%

100%

Note that when both xI bits are 1, the H-bridge is disabled and no current flows.

Example:

If a 0.25-Ω sense resistor is used and the VREF pin is 2.5 V, the chopping current will be 2 A at the 100%

setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the current will be 2 A x 0.71 = 1.42 A, and at the

38% setting (xI1, xI0 = 10) the current will be 2 A x 0.38 = 0.76 A. If (xI1, xI0 = 11) the bridge will be disabled

and no current will flow.

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SLVSAB9C –MAY 2010–REVISED MARCH 2011

Decay Mode and Braking

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM

current chopping threshold is reached. This is shown in Figure 2 as case 1. The current flow direction shown

indicates the state when the xENBL pin is high.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or

slow decay.

In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to

allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is

disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 2 as case 2.

In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is

shown in Figure 2 as case 3.

Figure 2. Decay Mode

The DRV8814 supports fast decay and slow decay mode. Slow or fast decay mode is selected by the state of

the DECAY pin - logic low selects slow decay, and logic high sets fast decay mode. Note that the DECAY pin

sets the decay mode for both H-bridges.

DECAY mode also affects the operation of the bridge when it is disabled (by taking the ENBL pin inactive). This

applies if the ENABLE input is being used for PWM speed control of the motor, or if it is simply being used to

start and stop motor rotation.

If the DECAY pin is high (fast decay), when the bridge is disabled fast decay mode will be entered until the

current through the bridge reaches zero. Once the current is at zero, the bridge is disabled to prevent the motor

from reversing direction. This allows the motor to coast to a stop.

If the DECAY pin is low (slow decay), both low-side FETs will be turned on when ENBL is made inactive. This

essentially shorts out the back EMF of the motor, causing the motor to brake, and stop quickly. The low-side

FETs will stay in the ON state even after the current reaches zero.

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Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time

before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also

sets the minimum on time of the PWM.

nRESET and nSLEEP Operation

The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs

are ignored while nRESET is active.

Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the

gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In

this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time

(approximately 1 ms) needs to pass before the motor driver becomes fully operational.

Protection Circuits

The DRV8814 is fully protected against undervoltage, overcurrent and overtemperature events.

Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this

analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the

nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is

removed and re-applied.

Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor

winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense

circuitry used for PWM current control, and is independent of the I_SENSEresistor value or VREF voltage.

Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be

driven low. Once the die temperature has fallen to a safe level operation will automatically resume.

Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the

device will be disabled and internal logic will be reset. Operation will resume when V_Mrises above the UVLO

threshold.

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SLVSAB9C –MAY 2010–REVISED MARCH 2011

THERMAL INFORMATION

Thermal Protection

The DRV8814 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately

150°C, the device will be disabled until the temperature drops to a safe level.

Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

Power Dissipation

Power dissipation in the DRV8814 is dominated by the power dissipated in the output FET resistance, or

RDS(ON). Average power dissipation of each H-bridge when running a DC motor can be roughly estimated by

Equation 2.

P = 2 · R_DS(ON)· (I_OUT)²

(2)

where P is the power dissipation of one H-bridge, R_DS(ON)is the resistance of each FET, and I_OUTis the RMS

output current being applied to each winding. I_OUTis equal to the average current drawn by the DC motor. Note

that at start-up and fault conditions this current is much higher than normal running current; these peak currents

and their duration also need to be taken into consideration. The factor of 2 comes from the fact that at any

instant two FETs are conducting winding current (one high-side and one low-side).

The total device dissipation will be the power dissipated in each of the two H-bridges added together.

The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and

heatsinking.

Note that R_DS(ON)increases with temperature, so as the device heats, the power dissipation increases. This must

be taken into consideration when sizing the heatsink.

Heatsinking

The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad

must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,

this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs

without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area

is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and

bottom layers.

For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally

Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.

In general, the more copper area that can be provided, the more power can be dissipated.

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PACKAGE OPTION ADDENDUM

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28-Mar-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

DRV8814PWP

ACTIVE

HTSSOP

PWP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

DRV8814PWPR

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

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DLP® Products

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dsp.ti.com

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interface.ti.com

logic.ti.com

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power.ti.com

Transportation and

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RFID

microcontroller.ti.com

www.ti-rfid.com

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www.ti.com/wireless-apps

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DRV8814_16 [TI]

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