DRV8824-Q1 [TI]
具有电流调节功能和 1/32 微步进的汽车类 47V、1.6A 双极步进电机驱动器;
| 型号： | DRV8824-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流调节功能和 1/32 微步进的汽车类 47V、1.6A 双极步进电机驱动器 电机 驱动 驱动器 |
| 文件： | 总29页 (文件大小：1259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8824-Q1
ZHCSCE6 –APRIL 2014
DRV8824-Q1 汽车用电机控制器集成电路 (IC)
1 特性
3 说明
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
DRV8824-Q1 为汽车应用提供一个集成电机驱动器解
决方案。 此器件具有两个 H 桥驱动器和一个微步进分
度器，并且专门用来驱动一个双极步进电机。 每个输
出驱动器块包含被配置为全 H 桥的 N 通道功率
MOSFET，以驱动电机绕组。 DRV8824-Q1 能够驱动
高达 1.6V 的输出电流（在 24V 和 25°C，具有适当散
热时）。
–
–
器件温度等级 1：-40°C 至 +125°C
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
–
器件充电器件模型 (CDM) ESD 分类等级 C4B
•
脉宽调制 (PWM) 微步进电机驱动器
–
–
–
内置微步进分度器
一个简单的步进/方向接口可轻松连接到控制器电路。
端子可实现全步进到 1/32 步进模式的电机配置。 衰减
模式可设定。
5 位绕组电流控制支持高达 32 个电流级
低金属氧化物半导体场效应晶体管 (MOSFET)
导通电阻
还提供用于过流保护、短路保护、欠压闭锁和过热保护
的内部关断功能。
•
•
•
•
24V，25°C 时 1.6A 最大驱动电流
内置 3.3V 基准输出
8.2V 至 45V 宽工作电源电压范围
DRV8824-Q1 采用具有 PowerPAD™ 的 28 引脚
HTSSOP 封装（环保型：符合 RoHS 标准且不含铅/
溴）。
耐热增强型带散热片超薄小外形尺寸 (HTSSOP) 表
面贴装封装
2 应用范围
器件信息
•
•
•
汽车制热、通风与空调控制 (HVAC)
汽车用阀门
订货编号
封装
封装尺寸
DRV8824QPWPRQ1 HTSSOP (28)
9.7mm x 4.4mm
车用信息娱乐
4 简化电路原理图
8.2 to 45 V
微步进电流波形
DRV8824-Q1
STEP/DIR
1.6 A
1.6 A
M
Step size
Stepper
Decreasing
Current
Increasing
Current
+
-
Motor Driver
Decay mode
Decreasing
Current
Increasing
Current
1/32 µstep
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCH0
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1 Trademarks........................................................... 22
12.2 Electrostatic Discharge Caution............................ 22
12.3 Glossary................................................................ 22
13 Mechanical, Packaging, and Orderable
8
Information ........................................................... 22
5 修订历史记录
日期
修订版本
注释
2014 年 4 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
6 Terminal Configuration and Functions
PWP Package
(Top View)
Terminal Functions
EXTERNAL COMPONENTS
NAME
TERMINAL
I/O
DESCRIPTION
OR CONNECTIONS
POWER AND GROUND
GND
VMA
VMB
14, 28
4
-
-
-
Device ground
Bridge A power supply
Bridge B power supply
Connect to motor supply (8.2 V - 45 V). Both terminals
must be connected to same supply.
11
Bypass to GND with a 0.47-μF 6.3-V ceramic
capacitor. Can be used to supply VREF.
V3P3OUT
15
O
3.3-V regulator output
CP1
CP2
1
2
IO
IO
Charge pump flying capacitor
Charge pump flying capacitor
Connect a 0.01-μF 50-V capacitor between CP1 and
CP2.
Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ
resistor to VM.
VCP
3
IO
High-side gate drive voltage
CONTROL
nENBL
Logic high to disable device outputs and indexer
operation, logic low to enable. Internal pulldown.
21
17
22
I
I
I
Enable input
Sleep mode input
Step input
Logic high to enable device, logic low to enter low-
power sleep mode. Internal pulldown.
nSLEEP
STEP
Rising edge causes the indexer to move one step.
Internal pulldown.
DIR
20
24
25
26
I
I
I
I
Direction input
Level sets the direction of stepping. Internal pulldown.
MODE0
MODE1
MODE2
Microstep mode 0
Microstep mode 1
Microstep mode 2
MODE0 - MODE2 set the step mode - full, 1/2, 1/4,
1/8/ 1/16, or 1/32 step. Internal pulldown.
Low = slow decay, open = mixed decay,
high = fast decay. Internal pulldown and pullup.
DECAY
19
I
Decay mode
Active-low reset input initializes the indexer logic and
disables the H-bridge outputs. Internal pulldown.
nRESET
AVREF
16
12
I
I
Reset input
Bridge A current set reference input
Reference voltage for winding current set. Normally
AVREF and BVREF are connected to the same
voltage. Can be connected to V3P3OUT. A 0.01-µF
bypass capacitor to GND is recommended.
BVREF
13
23
I
Bridge B current set reference input
No connect
NC
Leave this terminal unconnected.
STATUS
nHOME
27
18
OD
OD
Home position
Fault
Logic low when at home state of step table
Logic low when in fault condition (overtemp,
overcurrent)
nFAULT
Copyright © 2014, Texas Instruments Incorporated
3
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
Terminal Functions (continued)
EXTERNAL COMPONENTS
NAME
TERMINAL
I/O
DESCRIPTION
OR CONNECTIONS
OUTPUT
ISENA
6
9
IO
IO
O
Bridge A ground / Isense
Bridge B ground / Isense
Bridge A output 1
Connect to current sense resistor for bridge A.
Connect to current sense resistor for bridge B.
ISENB
AOUT1
AOUT2
BOUT1
BOUT2
5
Connect to bipolar stepper motor winding A.
Positive current is AOUT1 → AOUT2
7
O
Bridge A output 2
10
8
O
Bridge B output 1
Connect to bipolar stepper motor winding B.
Positive current is BOUT1 → BOUT2
O
Bridge B output 2
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
VALUE
–0.3 to 47
–0.5 to 7
UNIT
VMx
Power supply voltage range
V
V
V
V
A
A
Digital terminal voltage range
Input voltage
VREF
–0.3 to 4
ISENSEx terminal voltage
–0.3 to 0.8
Internally limited
1.6
Peak motor drive output current, t < 1 μS
Continuous motor drive output current(3)
Continuous total power dissipation
Operating virtual junction temperature range
See Thermal Information table
–40 to 150 °C
TJ
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
7.2 Handling Ratings
MIN
MAX
150
UNIT
Tstg
Storage temperature range
–60
°C
HBD (human body model), AEC-Q100 Classification H2
CDM (charged device model), AEC-Q100 Classification C4B
2000
750
VESD
V
7.3 Recommended Operating Conditions
MIN
8.2
1
NOM
MAX
45
UNIT
V
VM
Motor power supply voltage(1)
VREF input voltage(2)
VREF
IV3P3
3.5
1
V
V3P3OUT load current
mA
(1) All VM terminals must be connected to the same supply voltage.
(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.
4
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
7.4 Thermal Information
DRV8824-Q1
THERMAL METRIC
PWP
28 TERMINAL
38.9
UNIT
RθJA
Junction-to-ambient thermal resistance(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
Junction-to-top characterization parameter(4)
Junction-to-board characterization parameter(5)
Junction-to-case (bottom) thermal resistance(6)
RθJC(top)
RθJB
23.3
21.2
°C/W
ψJT
0.8
ψJB
20.9
RθJC(bot)
2.6
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
7.5 Electrical Characteristics
over operating free-air temperature range of -40°C to 125°C (unless otherwise noted)
PARAMETER
POWER SUPPLIES
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVM
VM operating supply current
VM sleep mode supply current
VM = 24 V, fPWM < 50 kHz
VM = 24 V
5
10
8
20
mA
μA
V
IVMQ
VUVLO
V3P3OUT REGULATOR
VM undervoltage lockout voltage VM rising
7.8
8.2
IOUT = 0 to 1 mA, VM = 24 V, TJ = 25°C
IOUT = 0 to 1 mA
3.18
3.10
3.30
3.30
3.45
3.50
V3P3
V3P3OUT voltage
V
LOGIC-LEVEL INPUTS
VIL
VIH
VHYS
IIL
Input low voltage
0.6
0.7
V
V
Input high voltage
Input hysteresis
Input low current
Input high current
2
5.25
0.45
V
VIN = 0
–20
20
μA
μA
kΩ
MΩ
IIH
VIN = 3.3 V
100
nENBL, nRESET, DIR, STEP, MODEx
nSLEEP
100
1
RPD
Internal pulldown resistance
nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)
VOL
IOH
Output low voltage
IO = 5 mA
VO = 3.3 V
0.5
1
V
Output high leakage current
μA
DECAY INPUT
VIL
Input low threshold voltage
For slow decay mode
For fast decay mode
0.8
V
VIH
IIN
Input high threshold voltage
Input current
2
V
–100
100
µA
kΩ
kΩ
RPU
RPD
Internal pullup resistance
Internal pulldown resistance
130
80
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5
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range of -40°C to 125°C (unless otherwise noted)
PARAMETER
H-BRIDGE FETS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VM = 24 V, I O = 1 A, TJ = 25°C
VM = 24 V, IO = 1 A, TJ = 85°C
VM = 24 V, IO = 1 A, TJ = 125°C
VM = 24 V, IO = 1 A, TJ = 25°C
VM = 24 V, IO = 1 A, TJ = 85°C
VM = 24 V, IO = 1 A, TJ = 125°C
0.63
0.76
0.85
0.65
0.78
0.85
RDS(ON)
HS FET on resistance
0.90
1
Ω
RDS(ON)
LS FET on resistance
0.90
1
Ω
IOFF
Off-state leakage current
–20
20
μA
MOTOR DRIVER
fPWM
tBLANK
tR
Internal PWM frequency
50
kHz
μs
Current sense blanking time
Rise time
3.75
VM = 24 V
VM = 24 V
100
80
360
250
ns
tF
Fall time
ns
tDEAD
Dead time
400
160
660
ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level
tTSD Thermal shutdown temperature
CURRENT CONTROL
1.8
5
A
Die temperature
150
180
°C
IREF
xVREF input current
xVREF = 3.3 V
–3
635
3
685
μA
VTRIP
xISENSE trip voltage
xVREF = 3.3 V, 100% current setting
xVREF = 3.3 V , 5% current setting
mV
–25%
25%
xVREF = 3.3 V , 10% - 34% current
setting
–15%
–10%
–5%
15%
10%
5%
Current trip accuracy
(relative to programmed value)
ΔITRIP
xVREF = 3.3 V, 38% - 67% current
setting
xVREF = 3.3 V, 71% - 100% current
setting
AISENSE
Current sense amplifier gain
Reference only
5
V/V
7.6 Timing Requirements
MIN
MAX UNIT
1
2
3
4
5
6
7
fSTEP
Step frequency
250
kHz
μs
tWH(STEP)
tWL(STEP)
tSU(STEP)
tH(STEP)
tENBL
Pulse duration, STEP high
Pulse duration, STEP low
1.9
1.9
200
200
200
1
μs
Setup time, command to STEP rising
Hold time, command to STEP rising
Enable time, nENBL active to STEP
Wakeup time, nSLEEP inactive to STEP
ns
ns
ns
tWAKE
ms
6
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
Figure 1. Timing Diagram
Copyright © 2014, Texas Instruments Incorporated
7
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
7.7 Typical Characteristics
7.0
6.5
6.0
5.5
5.0
4.5
4.0
14
13
12
11
10
9
-40°C
25°C
8
25°C
85°C
125°C
85°C
7
125°C
6
10
15
20
25
30
35
40
45
10
15
20
25
30
35
40
45
VM (V)
VM (V)
C001
C002
Figure 2. IVM vs VM
Figure 3. IVMQ vs VM
2000
1800
1600
1400
1200
1000
800
2000
1800
1600
1400
1200
1000
800
-40°C
85°C
25°C
125°C
10 V
24 V
45 V
10
15
20
25
30
35
40
45
0
25
50
75
100
125
±50
±25
VM (V)
TA (C)
C003
C004
Figure 4. RDS(ON) vs VM
Figure 5. RDS(ON) vs Temperature
8
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
8 Detailed Description
8.1 Overview
The DRV8824-Q1 is an integrated motor driver solution for bipolar stepper motors. The device integrates two
NMOS H-bridges, current sense and regulation circuitry, and a microstepping indexer. The DRV8824-Q1 can be
powered with a supply voltage between 8.2 V and 45 V, and is capable of providing an output current up to 1.6 A
full-scale or 1.1 A rms.
A simple STEP/DIR interface allows easy interfacing to the controller circuit. The internal indexer is able to
execute high-accuracy microstepping without requiring the processor to control the current level.
The current regulation is highly configurable, with three decay modes of operation. Fast, slow, and mixed decay
can be used.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
Copyright © 2014, Texas Instruments Incorporated
9
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
8.2 Functional Block Diagram
VM
LS Gate
Drive
3.3 V
V3P3OUT
CP1
CP2
VCP
Charge
Pump
HS Gate
Drive
Low Side
Gate
Drive
Internal
VCC
VM
V3P3OUT
3.3 V
VM
AVREF
BVREF
VM
VMA
+
nENBL
STEP
AOUT1
AOUT2
ISENA
+
Stepper
Motor
Motor Driver
A
±
DIR
+
±
DECAY
MODE0
MODE1
MODE2
nRESET
nSLEEP
nHOME
Control
Logic/
Indexer
VM
VMB
BOUT1
BOUT2
ISENB
Motor Driver
B
Thermal
Shut
nFAULT
Down
GND
PPAD
GND
10
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
8.3 Feature Description
8.3.1 PWM Motor Drivers
The DRV8824-Q1 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 6.
Figure 6. Motor Control Circuitry
Note that there are multiple VM motor power supply terminals. All VM terminals must be connected together to
the motor supply voltage.
Copyright © 2014, Texas Instruments Incorporated
11
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
Feature Description (continued)
8.3.2 Current Regulation
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current
chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the
current until the beginning of the next PWM cycle.
In stepping motors, current regulation is used to vary the current in the two windings in a semi-sinusoidal fashion
to provide smooth motion.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN terminals, multiplied by a factor of 5, with a reference voltage. The reference voltage is
input from the xVREF terminals.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP =
5 · RISENSE
(1)
Example:
If a 0.5-Ω sense resistor is used and the VREFx terminal is 3.3 V, the full-scale (100%) chopping current will
be 3.3 V / (5 x 0.5 Ω) = 1.32 A.
The reference voltage is scaled by an internal DAC that allows fractional stepping of a bipolar stepper motor, as
described in the microstepping indexer section below.
8.3.3 Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN terminal is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
8.3.4 Microstepping Indexer
Built-in indexer logic in the DRV8824-Q1 allows a number of different stepping configurations. The MODE0 -
MODE2 terminals are used to configure the stepping format as shown in .
Table 1. Stepping Format
MODE2
MODE1
MODE0
STEP MODE
Full step (2-phase excitation) with 71% current
1/2 step (1-2 phase excitation)
1/4 step (W1-2 phase excitation)
8 microsteps / step
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16 microsteps / step
32 microsteps / step
32 microsteps / step
32 microsteps / step
Table 2 shows the relative current and step directions for different settings of MODEx. At each rising edge of the
STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR terminal high; if
the DIR terminal is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to
xOUT2.
Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new
MODEx setting at the rising edge of STEP.
The home state is 45°. This state is entered at power-up or application of nRESET. This is shown in Table 2 by
the shaded cells. The logic inputs DIR, STEP, nRESET and MODEx have an internal pulldown resistors of
100 kΩ
12
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
Table 2. Relative Current and Step Directions
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
1/32 STEP 1/16 STEP 1/8 STEP
1/4 STEP
1/2 STEP
1
1
2
1
1
1
100%
100%
100%
99%
98%
97%
96%
94%
92%
90%
88%
86%
83%
80%
77%
74%
71%
67%
63%
60%
56%
51%
47%
43%
38%
34%
29%
24%
20%
15%
10%
5%
0%
5%
0
3
2
3
10%
15%
20%
24%
29%
34%
38%
43%
47%
51%
56%
60%
63%
67%
71%
74%
77%
80%
83%
86%
88%
90%
92%
94%
96%
97%
98%
99%
100%
100%
100%
100%
100%
99%
98%
97%
96%
94%
92%
90%
88%
86%
83%
80%
6
4
8
5
3
2
11
14
17
20
23
25
28
31
34
37
39
42
45
48
51
53
56
59
62
65
68
70
73
76
79
82
84
87
90
93
96
98
101
104
107
110
113
115
118
121
124
127
6
7
4
8
9
5
3
2
3
4
5
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
6
7
4
8
9
5
2
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
6
7
8
9
3
0%
–5%
–10%
–15%
–20%
–24%
–29%
–34%
–38%
–43%
–47%
–51%
–56%
–60%
10
11
12
Copyright © 2014, Texas Instruments Incorporated
13
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
Table 2. Relative Current and Step Directions (continued)
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
1/32 STEP 1/16 STEP 1/8 STEP
1/4 STEP
1/2 STEP
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
–63%
–67%
–71%
–74%
–77%
–80%
–83%
–86%
–88%
–90%
–92%
–94%
–96%
–97%
–98%
–99%
–100%
–100%
–100%
–100%
–100%
–99%
–98%
–97%
–96%
–94%
–92%
–90%
–88%
–86%
–83%
–80%
–77%
–74%
–71%
–67%
–63%
–60%
–56%
–51%
–47%
–43%
–38%
–34%
–29%
–24%
77%
74%
129
132
135
138
141
143
146
149
152
155
158
160
163
166
169
172
174
177
180
183
186
188
191
194
197
200
203
205
208
211
214
217
219
222
225
228
231
233
236
239
242
245
248
250
253
256
13
14
15
16
17
18
19
20
21
22
23
7
4
2
71%
67%
63%
60%
56%
51%
47%
43%
8
38%
34%
29%
24%
20%
15%
10%
5%
9
5
0%
–5%
–10%
–15%
–20%
–24%
–29%
–34%
–38%
–43%
–47%
–51%
–56%
–60%
–63%
–67%
–71%
–74%
–77%
–80%
–83%
–86%
–88%
–90%
–92%
–94%
–96%
–97%
10
11
12
6
3
14
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
Table 2. Relative Current and Step Directions (continued)
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
1/32 STEP 1/16 STEP 1/8 STEP
1/4 STEP
1/2 STEP
93
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
24
25
26
27
28
29
30
31
32
–20%
–15%
–10%
–5%
0%
–98%
–99%
–100%
–100%
–100%
–100%
–100%
–99%
–98%
–97%
–96%
–94%
–92%
–90%
–88%
–86%
–83%
–80%
–77%
–74%
–71%
–67%
–63%
–60%
–56%
–51%
–47%
–43%
–38%
–34%
–29%
–24%
–20%
–15%
–10%
–5%
259
262
264
267
270
273
276
278
281
284
287
290
293
295
298
301
304
307
309
312
315
318
321
323
326
329
332
335
338
340
343
346
349
352
354
357
94
95
96
97
13
7
98
5%
99
10%
15%
20%
24%
29%
34%
38%
43%
47%
51%
56%
60%
63%
67%
71%
74%
77%
80%
83%
86%
88%
90%
92%
94%
96%
97%
98%
99%
100%
100%
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
14
15
16
8
4
8.3.5 nRESET, nENBLE and nSLEEP Operation
The nRESET terminal, when driven active low, resets internal logic, and resets the step table to the home
position. It also disables the H-bridge drivers. The STEP input is ignored while nRESET is active.
The nENBL terminal is used to control the output drivers and enable/disable operation of the indexer. When
nENBL is low, the output H-bridges are enabled, and rising edges on the STEP terminal are recognized. When
nENBL is high, the H-bridges are disabled, the outputs are in a high-impedance state, and the STEP input is
ignored.
Copyright © 2014, Texas Instruments Incorporated
15
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize.
The nRESET and nENABLE terminals have internal pulldown resistors of 100 kΩ. The nSLEEP terminal has an
internal pulldown resistor of 1 MΩ.
8.3.6 Protection Circuits
The DRV8824-Q1 is fully protected against undervoltage, overcurrent and overtemperature events.
8.3.6.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT terminal will be driven low. The device will remain disabled until either nRESET terminal is applied, or
VM is removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
8.3.6.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT terminal will
be driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
8.3.6.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM terminals falls below the undervoltage lockout threshold voltage, all circuitry
in the device will be disabled and internal logic will be reset. Operation will resume when VM rises above the
UVLO threshold.
8.3.7 Thermal Information
8.3.7.1 Thermal Protection
The DRV8824-Q1 has thermal shutdown (TSD) as described above. If the die temperature exceeds
approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
8.3.7.2 Power Dissipation
Power dissipation in the DRV8824-Q1 is dominated by the power dissipated in the output FET resistance, or
RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.
2
· ·
PTOT = 4 RDS(ON) (IOUT(RMS)
)
(2)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
16
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
8.3.7.3 Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, "PowerPAD™ Thermally
Enhanced Package" and TI application brief SLMA004, "PowerPAD™ Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated. It can be seen that the
heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.
8.4 Device Functional Modes
8.4.1 Decay Mode
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 7 as case 1. The current flow direction shown
indicates positive current flow.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 7 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 7 as case 3.
Figure 7. Decay Mode
The DRV8824-Q1 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is
selected by the state of the DECAY terminal - logic low selects slow decay, open selects mixed decay operation,
and logic high sets fast decay mode. The DECAY terminal has both an internal pullup resistor of approximately
130 kΩ and an internal pulldown resistor of approximately 80 kΩ. This sets the mixed decay mode if the terminal
is left open or undriven.
Copyright © 2014, Texas Instruments Incorporated
17
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
Device Functional Modes (continued)
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow
decay mode for the remainder of the fixed PWM period. This occurs only if the current through the winding is
decreasing (per the indexer step table); if the current is increasing, then slow decay is used.
9 Application and Implementation
9.1 Application Information
The DRV8824-Q1 is used in bipolar stepper control. The following design procedure can be used to configure the
DRV8824-Q1.
9.2 Typical Application
DRV8824-Q1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CP1
GND
nHOME
MODE2
MODE1
MODE0
NC
0.01 µF
0.1 µF
2
CP2
VM
0.01 µF
3
VCP
1 MΩ
4
10 kΩ
V3P3
VMA
5
AOUT1
ISENA
AOUT2
BOUT2
ISENB
BOUT1
VMB
6
7
Step
Motor
400 mΩ
400 mΩ
STEP
8
+
-
nENBL
DIR
9
10
DECAY
nFAULT
nSLEEP
nRESET
V3P3OUT
11
VM
12
+
AVREF
BVREF
GND
0.01 µF
13
10 kΩ
14
10 kΩ
30 kΩ
0.47 µF
Figure 8. Typical Application Schematic
9.2.1 Design Requirements
Table 3 gives design input parameters for system design.
Table 3. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
EXAMPLE VALUE
VM
RL
24 V
Motor winding resistance
Motor winding inductance
Motor full step angle
1.0 Ω/phase
3.5 mH/phase
1.8°/step
LL
θstep
nm
v
Target microstepping level
Target motor speed
8 microsteps per step
120 rpm
Target full-scale current
IFS
1.25 A
18
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
9.2.2 Detailed Design Procedure
9.2.2.1 Stepper Motor Speed
The first step in configuring the DRV8824-Q1 requires the desired motor speed and microstepping level. If the
target application requires a constant speed, then a square wave with frequency fstep must be applied to the
STEP pin.
If the target motor speed is too high, the motor will not spin. Make sure that the motor can support the target
speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
·
v(rpm) nm(steps) 6
·
fstep(step/sec) =
qstep(°/step)
(3)
θstep can be found in the stepper motor datasheet or written on the motor itself.
For the DRV8824-Q1, the microstepping level is set by the USM pins and can be any of the settings in . Higher
microstepping will mean a smother motor motion and less audible noise, but will increase switching losses and
require a higher fstep to achieve the same motor speed.
9.2.2.2 Current Regulation
In a stepper motor, the full-scale current (IFS) is the maximum current driven through either winding. This quantity
will depend on the VREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS defines the
current chopping threshold (ITRIP) for the maximum current step.
VREF(V)
· RSENSE(W)
VREF(V)
·
IFS(A) =
=
5
Av
RSENSE(W)
(4)
IFS is set by a comparator which compares the voltage across RSENSE to a reference voltage. There is a current
sense amplifier built in with programmable gain through ISGAIN. Note that IFS must also follow the equation
below in order to avoid saturating the motor. VM is the motor supply voltage and RL is the motor winding
resistance.
VM(V)
RDS(ON)(W) + RSENSE(W)
IFS(A) <
·
RL(W) + 2
(5)
9.2.2.3 Decay Modes
The DRV8824-Q1 supports three different decay modes: slow decay, fast decay, and mixed decay. The current
through the motor windings is regulated using a fixed-frequency PWM scheme. This means that after any drive
phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8824-Q1 will place
the winding in one of the three decay modes until the PWM cycle has expired. Afterwards, a new drive phase
starts.
The blanking time tBLANK defines the minimum drive time for the current chopping. ITRIP is ignored during tBLANK
,
so the winding current may overshoot the trip level.
Copyright © 2014, Texas Instruments Incorporated
19
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
9.2.3 Application Curves
Figure 9. Microstepping Waveform, Phase A, Mixed Decay
Figure 10. Microstepping Waveform, Slow Decay on
Increasing Steps
Figure 11. Microstepping Waveform, Mixed Decay on Decreasing Steps
10 Power Supply Recommendations
The DRV8824-Q1 is designed to operate from an input voltage supply (VM) range between 8.2 V and 45 V. Two
0.01-µF ceramic capacitorS rated for VMA and VMB must be placed as close to the DRV8824-Q1 as possible. In
addition, a bulk capacitor must be included. If VMA and VMB are connected to the same board net, a single bulk
capacitor is sufficient.
20
Copyright © 2014, Texas Instruments Incorporated
DRV8824-Q1
www.ti.com.cn
ZHCSCE6 –APRIL 2014
11 Layout
11.1 Layout Guidelines
The VMA and VMB terminals should be bypassed to GND using low-ESR ceramic bypass capacitors with a
recommended value of 0.01 µF rated for VM. This capacitor should be placed as close to the VMA and VMB pins
as possible with a thick trace or ground plane connection to the device GND pin.
The VMA and VMB pins must be bypassed to ground using a bulk capacitor. This component may be an
electrolytic. If VMA and VMB are connected to the same board net, a single bulk capacitor is sufficient.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.01 µF rated for
VMA and VMB is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VMA and VCP pins. A value of 0.1 µF rated for 16
V is recommended. Place this component as close to the pins as possible. In addition place a 1-MΩ resistor
between VCP and VMA.
Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
11.2 Layout Example
0.01 µF
CP1
CP2
GND
nHOME
MODE2
MODE1
MODE0
NC
0.01 µF
0.1 µF
VCP
1 MΩ
VMA
AOUT1
ISENA
AOUT2
BOUT2
ISENB
BOUT1
VMB
STEP
RISENA
nEMBL
DIR
DECAY
nFAULT
nSLEEP
nRESET
V3P3OUT
RISENB
0.01 µF
AVREF
BVREF
GND
0.47 µF
Figure 12. DRV8824-Q1 Board Layout
Copyright © 2014, Texas Instruments Incorporated
21
DRV8824-Q1
ZHCSCE6 –APRIL 2014
www.ti.com.cn
12 Device and Documentation Support
12.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Copyright © 2014, Texas Instruments Incorporated
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Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8824QPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8824Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
DRV8824RHDT
45-V, 1.6-A bipolar stepper motor driver with current regulation and 1/32 microstepping 28-VQFN -40 to 85
TI
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