DRV8825 [TI]
STEPPER MOTOR CONTROLLER IC; 步进电机控制器IC
| 型号： | DRV8825 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | STEPPER MOTOR CONTROLLER IC |
| 文件： | 总22页 (文件大小：633K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8825
www.ti.com
SLVSA73C –APRIL 2010–REVISED MAY 2011
STEPPER MOTOR CONTROLLER IC
Check for Samples: DRV8825
1
FEATURES
APPLICATIONS
2
•
PWM Microstepping Motor Driver
•
•
•
•
•
•
•
•
•
Automatic Teller Machines
Money Handling Machines
–
–
Built-In Microstepping Indexer
Five-Bit Winding Current Control Allows Up
to 32 Current Levels
Video Security Cameras
Printers
–
Low MOSFET On-Resistance
Scanners
•
•
•
•
2.5-A Maximum Drive Current at 24 V, 25°C
Built-In 3.3-V Reference Output
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
8.2-V to 45-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
DESCRIPTION
The DRV8825 provides an integrated motor driver solution for printers, scanners, and other automated
equipment applications. The device has two H-bridge drivers, and can drive a bipolar stepper motor or two DC
motors. The output driver block for each consists of N-channel power MOSFET’s configured as full H-bridges to
drive the motor windings. The DRV8825 can supply up to 2.5-A peak or 1.75-A RMS output current (with proper
heatsinking at 24 V and 25°C).
A simple step/direction interface allows easy interfacing to controller circuits. Pins allow configuration of the
motor in full-step up to 1/32-step modes. Decay mode is programmable.
Internal shutdown functions are provided for overcurrent protection, short circuit protection, undervoltage lockout
and overtemperature.
The DRV8825 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br).
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
TA
PACKAGE(2)
–40°C to 85°C
PowerPAD™ (HTSSOP) - PWP
Reel of 2000
DRV8825PWPR
8825
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
SLVSA73C –APRIL 2010–REVISED MAY 2011
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
VM
VM
Int. VCC
Internal
Reference &
Regs
CP1
CP2
LS Gate
Drive
0.01 mF
Charge
Pump
V3P3OUT
3.3 V
VM
3.3 V
VCP
Thermal
Shut down
0.1 mF
HS Gate
Drive
VM
AVREF
BVREF
VMA
AOUT1
+
-
Step
Motor
Motor
Driver A
nENBL
AOUT2
ISENA
STEP
DIR
-
+
DECAY
MODE0
MODE1
Indexer /
Control
Logic
VM
MODE2
nRESET
nSLEEP
VMB
BOUT1
Motor
Driver B
nHOME
nFAULT
BOUT2
ISENB
GND
GND
2
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
www.ti.com
NAME
SLVSA73C –APRIL 2010–REVISED MAY 2011
Table 1. TERMINAL FUNCTIONS
EXTERNAL COMPONENTS
OR CONNECTIONS
PIN
I/O(1)
DESCRIPTION
POWER AND GROUND
GND
VMA
VMB
14, 28
-
-
-
Device ground
4
Bridge A power supply
Bridge B power supply
Connect to motor supply (8.2 - 45 V). Both
pins must be connected to same supply.
11
Bypass to GND with a 0.47-μF 6.3-V ceramic
capacitor. Can be used to supply VREF.
V3P3OUT
15
O
3.3-V regulator output
CP1
CP2
1
2
IO
IO
Charge pump flying capacitor
Charge pump flying capacitor
Connect a 0.01-μF 50-V capacitor between
CP1 and CP2.
Connect a 0.1-μF 16-V ceramic capacitor to
VM.
VCP
3
IO
High-side gate drive voltage
CONTROL
Logic high to disable device outputs and
indexer operation, logic low to enable. Internal
pulldown.
nENBL
21
I
Enable input
Logic high to enable device, logic low to enter
low-power sleep mode. Internal pulldown.
nSLEEP
STEP
17
22
I
I
Sleep mode input
Step input
Rising edge causes the indexer to move one
step
DIR
20
24
25
26
I
I
I
I
Direction input
Level sets the direction of stepping
MODE0
MODE1
MODE2
Microstep mode 0
Microstep mode 1
Microstep mode 2
MODE0 - MODE2 set the step mode - full,
1/2, 1/4, 1/8/ 1/16, or 1/32 step
Low = slow decay, open = mixed decay,
high = fast decay.
Internal pulldown and pullup.
DECAY
19
16
I
I
Decay mode
Reset input
Active-low reset input initializes the indexer
logic and disables the H-bridge outputs.
Internal pulldown.
nRESET
AVREF
BVREF
12
13
I
I
Bridge A current set reference input
Bridge B current set reference input
Reference voltage for winding current set.
Normally AVREF and BVREF are connected
to the same voltage. Can be connected to
V3P3OUT.
STATUS
nHOME
27
18
OD
OD
Home position
Fault
Logic low when at home state of step table
Logic low when in fault condition (overtemp,
overcurrent)
nFAULT
OUTPUT
ISENA
6
9
IO
IO
O
Bridge A ground / Isense
Bridge B ground / Isense
Bridge A output 1
Connect to current sense resistor for bridge A.
Connect to current sense resistor for bridge B.
ISENB
AOUT1
AOUT2
BOUT1
BOUT2
5
Connect to bipolar stepper motor winding A.
Positive current is AOUT1 → AOUT2
7
O
Bridge A output 2
10
8
O
Bridge B output 1
Connect to bipolar stepper motor winding B.
Positive current is BOUT1 → BOUT2
O
Bridge B output 2
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
Copyright © 2010–2011, Texas Instruments Incorporated
3
DRV8825
SLVSA73C –APRIL 2010–REVISED MAY 2011
www.ti.com
4
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
www.ti.com
SLVSA73C –APRIL 2010–REVISED MAY 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE
–0.3 to 47
–0.5 to 7
–0.3 to 4
–0.3 to 0.8
Internally limited
2.5
UNIT
V
VMx
Power supply voltage range
Digital pin voltage range
V
VREF
Input voltage
V
ISENSEx pin voltage
V
Peak motor drive output current, t < 1 μS
Continuous motor drive output current(3)
A
A
HBD (human body model)
2000
ESD rating
V
CDM (charged device model)
500
Continuous total power dissipation
Operating virtual junction temperature range
Operating ambient temperature range
Storage temperature range
See Dissipation Ratings table
TJ
–40 to 150
–40 to 85
–60 to 150
°C
TA
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
THERMAL INFORMATION
DRV8825
THERMAL METRIC(1)
PWP
28 PINS
31.6
15.9
5.6
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
0.2
ψJB
5.5
θJCbot
1.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
8.2
1
NOM
MAX
45
UNIT
V
VM
Motor power supply voltage range(1)
VREF input voltage(2)
VREF
IV3P3
fPWM
3.5
1
V
V3P3OUT load current
0
mA
kHz
Externally applied PWM frequency
0
100
(1) All VM pins must be connected to the same supply voltage.
(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.
Copyright © 2010–2011, Texas Instruments Incorporated
5
DRV8825
SLVSA73C –APRIL 2010–REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
POWER SUPPLIES
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVM
VM operating supply current
VM sleep mode supply current
VM undervoltage lockout voltage
VM = 24 V, fPWM < 50 kHz
VM = 24 V
5
10
8
20
mA
μA
V
IVMQ
VUVLO
VM rising
7.8
8.2
V3P3OUT REGULATOR
V3P3 V3P3OUT voltage
LOGIC-LEVEL INPUTS
IOUT = 0 to 1 mA
3.2
3.3
0.6
3.4
V
VIL
Input low voltage
0.7
5.25
0.6
V
V
VIH
VHYS
IIL
Input high voltage
Input hysteresis
2.2
0.3
0.45
V
Input low current
VIN = 0
–20
20
μA
μA
kΩ
IIH
Input high current
Internal pulldown resistance
VIN = 3.3 V
100
RPD
100
nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)
VOL
IOH
Output low voltage
IO = 5 mA
VO = 3.3 V
0.5
1
V
Output high leakage current
μA
DECAY INPUT
VIL
Input low threshold voltage
For slow decay mode
For fast decay mode
0.8
V
VIH
IIN
Input high threshold voltage
Input current
2
V
±40
µA
kΩ
kΩ
RPU
RPD
Internal pullup resistance (up to 3.3 V)
Internal pulldown resistance
130
80
H-BRIDGE FETS
VM = 24 V, IO = 1 A, TJ = 25°C
VM = 24 V, IO = 1 A, TJ = 85°C
VM = 24 V, IO = 1 A, TJ = 25°C
VM = 24 V, IO = 1 A, TJ = 85°C
0.2
0.25
0.2
HS FET on resistance
0.32
RDS(ON)
Ω
LS FET on resistance
0.25
0.32
20
IOFF
Off-state leakage current
–20
μA
MOTOR DRIVER
fPWM
tBLANK
tR
Internal current control PWM frequency
30
4
kHz
μs
Current sense blanking time
Rise time
30
30
200
200
ns
tF
Fall time
ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level
tTSD Thermal shutdown temperature
CURRENT CONTROL
3
A
Die temperature
150
160
660
180
°C
IREF
xVREF input current
xVREF = 3.3 V
–3
635
–25
3
685
25
μA
VTRIP
xISENSE trip voltage
xVREF = 3.3 V, 100% current setting
xVREF = 3.3 V, 5% current setting
mV
xVREF = 3.3 V, 10% - 34% current
setting
–15
–10
–5
15
10
5
Current trip accuracy
(relative to programmed value)
ΔITRIP
%
xVREF = 3.3 V, 38% - 67% current
setting
xVREF = 3.3 V, 71% - 100% current
setting
AISENSE Current sense amplifier gain
Reference only
5
V/V
6
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
www.ti.com
SLVSA73C –APRIL 2010–REVISED MAY 2011
TIMING REQUIREMENTS
MIN
MAX UNIT
1
2
3
4
5
6
7
fSTEP
Step frequency
250
kHz
μs
tWH(STEP)
tWL(STEP)
tSU(STEP)
tH(STEP)
tENBL
Pulse duration, STEP high
1.9
1.9
Pulse duration, STEP low
μs
Setup time, command to STEP rising
Hold time, command to STEP rising
Enable time, nENBL active to STEP
Wakeup time, nSLEEP inactive to STEP
650
650
650
1.7
ns
ns
ns
tWAKE
ms
Figure 1. Timing Diagram
Copyright © 2010–2011, Texas Instruments Incorporated
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DRV8825
SLVSA73C –APRIL 2010–REVISED MAY 2011
www.ti.com
FUNCTIONAL DESCRIPTION
PWM Motor Drivers
The DRV8825 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 2.
Figure 2. Motor Control Circuitry
Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor
supply voltage.
8
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
www.ti.com
SLVSA73C –APRIL 2010–REVISED MAY 2011
Current Regulation
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current
chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the
current until the beginning of the next PWM cycle.
In stepping motors, current regulation is used to vary the current in the two windings in a semi-sinusoidal fashion
to provide smooth motion.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the xVREF pins.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP =
5 · RISENSE
(1)
Example:
If a 0.25-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current will be
2.5 V / (5 x 0.25 Ω) = 2 A.
The reference voltage is scaled by an internal DAC that allows fractional stepping of a bipolar stepper motor, as
described in the microstepping indexer section below.
Decay Mode
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 3 as case 1. The current flow direction shown
indicates positive current flow.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 3 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 3 as case 3.
Figure 3. Decay Mode
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DRV8825
SLVSA73C –APRIL 2010–REVISED MAY 2011
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The DRV8825 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is
selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and
logic high sets fast decay mode. The DECAY pin has both an internal pullup resistor of approximately 130 kΩ
and an internal pulldown resistor of approximately 80 kΩ. This sets the mixed decay mode if the pin is left open
or undriven.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow
decay mode for the remainder of the fixed PWM period. This occurs only if the current through the winding is
decreasing (per the indexer step table); if the current is increasing, then slow decay is used.
Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
Microstepping Indexer
Built-in indexer logic in the DRV8825 allows a number of different stepping configurations. The MODE0 - MODE2
pins are used to configure the stepping format as shown in Table 2.
Table 2. Stepping Format
MODE2
MODE1
MODE0
STEP MODE
Full step (2-phase excitation) with 71% current
1/2 step (1-2 phase excitation)
1/4 step (W1-2 phase excitation)
8 microsteps / step
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16 microsteps / step
32 microsteps / step
32 microsteps / step
32 microsteps / step
Table 3 shows the relative current and step directions for different settings of MODEx. At each rising edge of the
STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the
DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2.
Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new
MODEx setting at the rising edge of STEP.
The home state is 45°. This state is entered at power-up or application of nRESET. This is shown in Table 3 by
the shaded cells.
Table 3. Relative Current and Step Directions
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
1/32 STEP 1/16 STEP 1/8 STEP
1/4 STEP
1/2 STEP
1
2
1
2
3
4
5
6
1
2
3
1
1
100%
100%
100%
99%
98%
97%
96%
94%
92%
90%
88%
0%
0
5%
3
3
10%
15%
20%
24%
29%
34%
38%
43%
47%
6
4
8
5
11
14
17
20
23
25
28
6
7
8
9
2
10
11
10
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
www.ti.com
SLVSA73C –APRIL 2010–REVISED MAY 2011
Table 3. Relative Current and Step Directions (continued)
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
1/32 STEP 1/16 STEP 1/8 STEP
1/4 STEP
1/2 STEP
12
86%
83%
51%
56%
60%
63%
67%
71%
74%
77%
80%
83%
86%
88%
90%
92%
94%
96%
97%
98%
99%
100%
100%
100%
100%
100%
99%
98%
97%
96%
94%
92%
90%
88%
86%
83%
80%
77%
74%
71%
67%
63%
60%
56%
51%
47%
43%
38%
31
34
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
7
4
5
80%
37
8
77%
39
74%
42
9
3
2
1
71%
45
67%
48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
63%
51
60%
53
6
56%
56
51%
59
47%
62
43%
65
7
4
5
6
7
8
38%
68
34%
70
29%
73
24%
76
8
20%
79
15%
82
10%
84
5%
87
9
3
0%
90
–5%
93
–10%
–15%
–20%
–24%
–29%
–34%
–38%
–43%
–47%
–51%
–56%
–60%
–63%
–67%
–71%
–74%
–77%
–80%
–83%
–86%
–88%
–90%
–92%
96
98
10
11
12
13
14
15
101
104
107
110
113
115
118
121
124
127
129
132
135
138
141
143
146
149
152
155
158
4
2
Copyright © 2010–2011, Texas Instruments Incorporated
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DRV8825
SLVSA73C –APRIL 2010–REVISED MAY 2011
www.ti.com
Table 3. Relative Current and Step Directions (continued)
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
1/32 STEP 1/16 STEP 1/8 STEP
1/4 STEP
1/2 STEP
58
–94%
–96%
–97%
–98%
–99%
–100%
–100%
–100%
–100%
–100%
–99%
–98%
–97%
–96%
–94%
–92%
–90%
–88%
–86%
–83%
–80%
–77%
–74%
–71%
–67%
–63%
–60%
–56%
–51%
–47%
–43%
–38%
–34%
–29%
–24%
–20%
–15%
–10%
–5%
34%
29%
160
163
166
169
172
174
177
180
183
186
188
191
194
197
200
203
205
208
211
214
217
219
222
225
228
231
233
236
239
242
245
248
250
253
256
259
262
264
267
270
273
276
278
281
284
287
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
24%
16
17
18
19
20
21
22
23
24
25
26
20%
15%
10%
5%
9
5
0%
–5%
–10%
–15%
–20%
–24%
–29%
–34%
–38%
–43%
–47%
–51%
–56%
–60%
–63%
–67%
–71%
–74%
–77%
–80%
–83%
–86%
–88%
–90%
–92%
–94%
–96%
–97%
–98%
–99%
–100%
–100%
–100%
–100%
–100%
–99%
–98%
–97%
–96%
10
11
12
13
6
3
7
0%
5%
10%
15%
20%
24%
29%
12
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
www.ti.com
SLVSA73C –APRIL 2010–REVISED MAY 2011
Table 3. Relative Current and Step Directions (continued)
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
1/32 STEP 1/16 STEP 1/8 STEP
1/4 STEP
1/2 STEP
104
34%
38%
43%
47%
51%
56%
60%
63%
67%
71%
74%
77%
80%
83%
86%
88%
90%
92%
94%
96%
97%
98%
99%
100%
100%
–94%
–92%
–90%
–88%
–86%
–83%
–80%
–77%
–74%
–71%
–67%
–63%
–60%
–56%
–51%
–47%
–43%
–38%
–34%
–29%
–24%
–20%
–15%
–10%
–5%
290
293
295
298
301
304
307
309
312
315
318
321
323
326
329
332
335
338
340
343
346
349
352
354
357
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
53
54
55
56
57
58
59
60
61
62
63
64
27
28
29
30
31
32
14
15
8
4
16
nRESET, nENBLE and nSLEEP Operation
The nRESET pin, when driven active low, resets internal logic, and resets the step table to the home position. It
also disables the H-bridge drivers. The STEP input is ignored while nRESET is active.
The nENBL pin is used to control the output drivers and enable/disable operation of the indexer. When nENBL is
low, the output H-bridges are enabled, and rising edges on the STEP pin are recognized. When nENBL is high,
the H-bridges are disabled, the outputs are in a high-impedance state, and the STEP input is ignored.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize. Note
that nRESET and nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be
driven to logic high for device operation.
Protection Circuits
The DRV8825 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Copyright © 2010–2011, Texas Instruments Incorporated
13
DRV8825
SLVSA73C –APRIL 2010–REVISED MAY 2011
www.ti.com
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
14
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8825
www.ti.com
SLVSA73C –APRIL 2010–REVISED MAY 2011
THERMAL INFORMATION
Thermal Protection
The DRV8825 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8825 is dominated by the power dissipated in the output FET resistance, or RDS(ON)
.
Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.
2
· ·
PTOT = 4 RDS(ON) (IOUT(RMS)
)
(2)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally
Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated. It can be seen that the
heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.
Copyright © 2010–2011, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DRV8825PWP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
28
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
DRV8825PWPR
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8825PWPR
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
DRV8825PWPR
2000
Pack Materials-Page 2
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