DRV8847 [TI]
具有电流调节和独立半桥控制的 18V、2A 双路 H 桥电机驱动器;
| 型号： | DRV8847 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流调节和独立半桥控制的 18V、2A 双路 H 桥电机驱动器 电机 驱动 驱动器 |
| 文件： | 总80页 (文件大小：3608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8847
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
DRV8847 双路 H 桥电机驱动器
1 特性
3 说明
1
•
双路 H 桥电机驱动器
DRV8847 器件是一款适用于工业 应用、家用电器、
ePOS 打印机以及其他机电产品 的双 H 桥电机驱动
器。本器件可用于驱动两个直流电机、一个双极步进电
机或继电器等其他负载。借助简单的 PWM 接口，可
与控制器轻松连接。DRV8847 器件由单一电源供电，
支持 2.7V 至 18V 的宽输入电源范围。
–
–
–
单路或双路刷式直流电机
一个双极步进电机
电磁阀负载
•
•
2.7V 至 18V 工作电压范围
每个 H 桥均提供高输出电流
–
–
TA = 25°C 时，驱动器电流为 1A RMS
驱动器的输出级由配置为两个全 H 桥的 N 沟道功率
MOSFET 构成，用于驱动电机绕组或四个独立半桥
（位于独立桥接式接口）。固定关断时间控制电桥中的
峰值电流，该电流能够驱动一个 1A 的负载（并行模式
下 25°C TA 时，在散热适当的条件下，可驱动 2A 的
负载）。
并行模式下 TA = 25°C 时，驱动器电流为 2A
RMS
•
•
VM > 5V 时具有低导通电阻
TA = 25°C 时，RDS(ON) (HS + LS) 为 1000mΩ
多种控制接口选项
–
–
–
–
–
4 引脚接口
提供了低功耗睡眠模式，以通过关断大量内部电路实现
较低的静态电流消耗。此外，附带的扭矩标量能够通过
数字输入引脚动态调节输出电流。该特性可降低控制器
所需电流，实现更低功耗。
2 引脚接口
并联桥接式接口
独立桥接式接口
•
•
•
•
采用 20μs 固定关断时间进行电流调节
输出电流调节至 50% 的扭矩标量
支持 1.8V、3.3V、5V 逻辑输入
低功耗睡眠模式
还提供了各种内部保护功能，如欠压锁定、每个 FET
的过流保护、短路保护、开路负载检测和过热保护等。
故障状态通过 nFAULT 引脚指示。I2C 器件版本
(DRV8847S) 提供详细诊断。
–
VVM = 12V、TA = 25°C 时，睡眠模式电源电流
为 1.7µA
器件信息(1)
•
•
•
提供 I2C 器件版本 (DRV8847S)
器件型号
封装
HTSSOP (16)
TSSOP (16)
WQFN (16)
封装尺寸（标称值）
5.00mm × 4.40mm
5.00mm × 4.40mm
3.00mm × 3.00mm
5.00mm × 4.40mm
–
–
–
I2C 寄存器上显示详细诊断
多从运行支持
支持标准和快速 I2C 模式
DRV8847
小型封装和尺寸
DRV8847S
TSSOP (16)
–
–
–
16 引脚 TSSOP（无散热垫）
16 引脚 HTSSOP PowerPAD™封装
16 引脚 WQFN 热封装
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
内置保护 特性
2.7 to 18 V
–
–
–
–
–
VM 欠压锁定
过流保护
DRV8847
INx
开路负载检测
热关断
1 A
Dual H-Bridge Driver
nSLEEP
nFAULT
TRQ
Controller
故障条件指示引脚 (nFAULT)
Stepper
Current Regulation
Built-in Protection
1 A
2 应用
MODE
•
•
•
•
冰箱风门和制冰机
洗衣机、烘干机和洗碗机
电子销售终端 (ePOS) 打印机
舞台照明设备
•
微型断路器和智能仪表
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSE65
DRV8847
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
7.6 Register Map........................................................... 43
Application and Implementation ........................ 48
8.1 Application Information............................................ 48
8.2 Typical Application ................................................. 48
Power Supply Recommendations...................... 60
9.1 Bulk Capacitance Sizing ......................................... 60
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 I2C Timing Requirements ......................................... 8
6.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 39
7.5 Programming........................................................... 41
8
9
10 Layout................................................................... 61
10.1 Layout Guidelines ................................................. 61
10.2 Layout Example .................................................... 61
10.3 Thermal Considerations........................................ 63
10.4 Power Dissipation ................................................. 63
11 器件和文档支持 ..................................................... 64
11.1 文档支持................................................................ 64
11.2 接收文档更新通知 ................................................. 64
11.3 社区资源................................................................ 64
11.4 商标....................................................................... 64
11.5 静电放电警告......................................................... 64
11.6 Glossary................................................................ 64
12 机械、封装和可订购信息....................................... 64
7
2
版权 © 2018–2019, Texas Instruments Incorporated
DRV8847
www.ti.com.cn
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (July 2018) to Revision B
Page
•
•
•
•
已更改 将“低导通电阻”更改为 VM > 5V 时的指示值............................................................................................................... 1
Changed nFAULT pin type to OD/I ........................................................................................................................................ 5
Changed VM description to indicate 0.1-uF capacitor should be ceramic ............................................................................. 5
Changed digital pin voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, nFAULT, SCL, SDA) maximum voltage from 5.5 V
to 5.75 V ................................................................................................................................................................................. 6
•
•
•
Changed the Phase node pin voltage specification’s name to Continuous phase node pin voltage .................................... 6
Added for ISEN12, ISEN34 specification a footnote stating transients of +- 1V for less than 25 ns are acceptable ........... 6
Added for both Peak drive current (OUT1, OUT2, OUT3, OUT4) specifications a footnote stating Power dissipation
and thermal limits must be observed ..................................................................................................................................... 6
•
•
•
Changed V(ESD) specification’s value to 4000 V .................................................................................................................. 6
Changed the VIL specification to be two specifications based on test conditions VM < 7 V and VM >= 7 V......................... 7
Changed the IIH specification’s minimum value to 18 uA for test condition IN1, IN2, IN3, IN4, TRQ, VIN = 5 V and to
10 uA for test condition nSLEEP, VIN = minimum (VM, 5 V) ................................................................................................. 7
•
•
•
•
•
•
•
•
Added to IOCP specification a minimum value......................................................................................................................... 8
已更改 pin naming of Block Diagram for DRV8847S figure ................................................................................................. 16
已删除 ceramic from CVM1 .................................................................................................................................................... 17
已更改 the relay or solenoid coils load bullet item for more clarity....................................................................................... 24
已添加 sentence to clarify nFAULT pin behavior when open load is detected ................................................................... 36
已添加 sentence to clarify nFAULT pin behavior during power-up ..................................................................................... 39
已添加 an Open Load Implementation section..................................................................................................................... 53
已添加 a Layout Recommendation of 16-Pin QFN Package for Double Layer Board figure .............................................. 62
Changes from Original (July 2018) to Revision A
Page
•
•
已更改 将数据表状态从预告信息 更改为生产数据 .................................................................................................................. 1
已更改 pin naming on Layout Recommendation of 16-Pin HTSSOP Package for Double Layer Board figure .................. 61
Copyright © 2018–2019, Texas Instruments Incorporated
3
DRV8847
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
5 Pin Configuration and Functions
DRV8847 PW Package
16-Pin TSSOP
Top View
DRV8847 PWP PowerPAD™ Package
16-Pin HTSSOP
Top View
nSLEEP
OUT1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
nSLEEP
OUT1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
IN2
IN2
ISEN12
OUT2
MODE
GND
VM
ISEN12
OUT2
MODE
GND
VM
Thermal
Pad
OUT4
OUT4
ISEN34
OUT3
TRQ
IN4
ISEN34
OUT3
TRQ
IN4
nFAULT
IN3
nFAULT
IN3
Not to scale
Not to scale
DRV8847 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
DRV8847S PW Package
16-Pin TSSOP
Top View
nSLEEP
OUT1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
IN2
ISEN12
OUT2
SDA
GND
VM
ISEN12
1
2
3
4
12
11
10
9
MODE
OUT2
OUT4
GND
VM
OUT4
Thermal
Pad
ISEN34
OUT3
SCL
IN4
ISEN34
TRQ
nFAULT
IN3
Not to scale
Not to scale
4
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8847
www.ti.com.cn
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
Pin Functions
PIN
DRV8847
DRV8847S
TSSOP
TYPE(1)
DESCRIPTION
NAME
TSSOP
WQFN
HTSSOP
Device ground. Recommended to connect the GND pin and device
thermal pad (HTSSOP and WQFN packages) to ground
GND
13
11
13
PWR
IN1
IN2
IN3
IN4
16
15
9
14
13
7
16
15
9
I
I
I
I
Half-bridge input 1
Half-bridge input 2
Half-bridge input 3
Half-bridge input 4
10
8
10
Full-bridge-12 sense. Connect this pin to the current sense resistor for full-
bridge-12. Connect this pin to the GND pin if current regulation is not
required.
ISEN12
3
1
3
O
Full-bridge-34 sense. Connect this pin to the to current sense resistor for
full-bridge-34. Connect this pin to the GND pin if current regulation is not
required.
ISEN34
MODE
6
14
8
4
12
6
6
—
8
O
I
Tri-state pin for selection of driver operating mode
Fault indication pin. This pin is pulled logic low with a fault condition. This
open-drain output requires an external pullup resistor. This pin is also
used as an input pin for the DRV8847S device for releasing the I2C bus.
nFAULT
OD / I
Sleep mode input. Set this pin to logic high to enable the device. Set this
pin to logic low to go to low-power sleep mode
nSLEEP
1
15
1
I
OUT1
OUT2
OUT3
OUT4
SCL
2
4
16
2
2
4
O
O
O
O
I
Half-bridge output 1
Half-bridge output 2
7
5
7
Half-bridge output 3
5
3
5
Half-bridge output 4
I2C clock signal.
I2C data signal. The SDA pin requires a pullup resistor.
—
—
11
—
—
9
11
14
—
SDA
OD
I
TRQ
Torque current scalar
Power supply. Connect the VM pin to the motor power supply. Bypass this
pin to ground with a VM-rated 0.1-µF (ceramic) and 10-μF (minimum)
capacitor.
VM
12
10
12
PWR
(1) I = input, O = output, OD = open-drain output, PWR = power
Copyright © 2018–2019, Texas Instruments Incorporated
5
DRV8847
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX
20
UNIT
V
Power supply pin voltage (VM)
-0.3
Power supply voltage ramp rate (VM)
0
2
V/µs
V
Digital pin voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, nFAULT, SCL, SDA)
Continuous phase node pin voltage (OUT1, OUT2, OUT3, OUT4)
Shunt amplifier input pin voltage (ISEN12, ISEN34)(2)
Peak drive current (OUT1, OUT2, OUT3, OUT4), VVM <= 16.5 V(3)
Peak drive current (OUT1, OUT2, OUT3, OUT4), VVM > 16.5 V(3)
Ambient temperature, TA
-0.3
5.75
-0.7
VM + 0.6
0.6
V
-0.6
V
Internally Limited
A
0
-40
-40
-65
4
125
150
150
A
°C
°C
°C
Junction temperature, TJ
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable.
(3) Power dissipation and thermal limits must be observed.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±4000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted). Typical limits apply for TA = 25°C and VVM = 12 V.
MIN
2.7
0
NOM
MAX
18
UNIT
V
VVM
VIN
Power supply voltage (VM)
Logic input voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, SCL, SDA)
Motor RMS current per bridge (OUT1, OUT2, OUT3, OUT4)
PWM frequency (IN1, IN2, IN3, IN4)
5
V
IRMS
fPWM
VOD
IOD
0
1(1)
250(1)
5
A
0
kHz
V
Open drain pullup voltage (nFAULT)
0
Open drain output current (nFAULT)
0
5
mA
°C
°C
TA
Operating Ambient Temperature
-40
-40
85
TJ
Operating Junction Temperature
150
(1) Power dissipation and thermal limits must be observed. Dependent on the package thermal performance.
6.4 Thermal Information
DRV8847, DRV8847S
DRV8847
PWP (HTSSOP)
16 PINS
46.5
DRV8847
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
107.9
RTE (QFN)
16 PINS
46.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
38.5
40.1
47.5
54.2
18.8
21.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8847
www.ti.com.cn
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
Thermal Information (continued)
DRV8847, DRV8847S
DRV8847
DRV8847
RTE (QFN)
16 PINS
0.9
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
3.1
PWP (HTSSOP)
UNIT
16 PINS
1.3
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
ΨJB
53.6
19.0
5.9
21.3
RθJC(bot)
N/A
6.1
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 12 V.
PARAMETER
POWER SUPPLIES (VM)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VM = 2.7 V; nSLEEP = 1; INX = 0
VM = 5 V; nSLEEP = 1; INX = 0
VM = 12 V; nSLEEP = 1; INX = 0
VM = 2.7 V; nSLEEP = 0; TA = 25°C
VM = 2.7 V; nSLEEP = 0; TA = 85°C
VM = 5 V; nSLEEP = 0; TA = 25°C
VM = 5 V; nSLEEP = 0; TA = 85°C
VM = 12 V; nSLEEP = 0; TA = 25°C
VM = 12 V; nSLEEP = 0; TA = 85°C
nSLEEP = 0 to sleep mode
2
3
2.5
3.5
3.5
mA
mA
mA
µA
µA
µA
µA
µA
µA
µs
IVM
VM operating supply current
VM sleep mode current
3
0.1
0.5
1
0.2
1.7
2
IVMQ
2.5
tSLEEP
tWAKE
Sleep time
Wake-up time
nSLEEP = 1 to output transition
1.5
1.5
ms
VM > UVLO to output transition
(nSLEEP = 1)
tON
Turnon-time
ms
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, NSLEEP, TRQ, SCL, SDA)
VM < 7 V
0
0
0.6
1.0
5.5
V
V
VIL
Input logic low voltage
(1)
VM >= 7 V
VIH
Input logic high voltage
Input logic hysteresis
Input logic hysteresis
Input logic low current
1.6
40
V
VHYS
VHYS
IIL
nSLEEP pin
mV
mV
µA
µA
µA
ns
ns
IN1, IN2, IN3, IN4, TRQ, SCL pins
VIN = 0 V
100
-1
1
35
IN1, IN2, IN3, IN4, TRQ, VIN = 5 V
nSLEEP, VIN = minimum (VM, 5 V)
INx edge to output
18
IIH
Input logic high current
10
25
tPD
Propagation Delay
Input logic deglitch
100
400
50
600
tDEGLITCH
TRI-LEVEL INPUTS (MODE)
VIL
VIZ
VIH
IIL
Tri-level input logic low voltage
0
0.6
V
V
Tri-level input hi-Z voltage
1.2
Tri-level input logic high voltage
Tri-level input logic low current
Tri-level input logic high current
1.6
-9
8
5.5
-4
V
VIN = 0 V
VIN = 5 V
µA
µA
IIH
25
OPEN-DRAIN OUTPUTS (nFAULT)
VOL
IOH
Output logic low voltage
Output logic high current
IOD = 5 mA
VOD = 3.3 V
0.5
1
V
-1
-1
µA
OPEN-DRAIN OUTPUTS (SDA)
VOL
IOH
Output logic low voltage
Output logic high current
IOD = 5 mA
VOD = 3.3 V
0.5
1
V
µA
(1) Specified by design and characterization
Copyright © 2018–2019, Texas Instruments Incorporated
7
DRV8847
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 12 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CB
Capacitive load for each bus line
400
pF
DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
VVM = 2.7 V; IOUT = 0.5 A; TA = 25°C
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C
VVM = 5 V; IOUT = 0.5 A; TA = 25°C
VVM = 5 V; IOUT = 0.5 A; TA = 85°C
VVM = 12 V; IOUT = 0.5 A; TA = 25°C
VVM = 12 V; IOUT = 0.5 A; TA = 85°C
VVM = 2.7 V; IOUT = 0.5 A; TA = 25°C
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C
VVM = 5 V; IOUT = 0.5 A; TA = 25°C
VVM = 5 V; IOUT = 0.5 A; TA = 85°C
VVM = 12 V; IOUT = 0.5 A; TA = 25°C
VVM = 12 V; IOUT = 0.5 A; TA = 85°C
VVM = 5 V; TJ = 25 °C; VOUT = 0 V
VVM = 12 V; IOUT = 0.5 A
690
530
520
570
460
450
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
µA
950
740
700
900
690
RDS(ON)_HS High-side MOSFET on resistance
RDS(ON)_LS Low-side MOSFET on resistance
680
1
IOFF
Off-state leakage current
Output rise time
-1
tRISE
tFALL
tDEAD
VSD
150
150
200
1.1
ns
Output fall time
VVM = 12 V, IOUT = 0.5 A
ns
Output dead time
Internal dead time
ns
Body diode forward voltage
IOUT = 0.5 A
V
PWM CURRENT CONTROL (ISEN12, SEN34)
Torque at 100% (TRQ = 0)
Torque at 50% (TRQ = 1)
140
150
75
160
mV
mV
µs
VTRIP
ISENxx trip voltage
63.75
86.25
tBLANK
tOFF
Current sense blanking time
1.8
20
Current control constant off time
µs
PROTECTION CIRCUITS
Supply rising
2.7
V
V
VUVLO
Supply undervoltage lockout
Supply falling
2.4
1.6
VUVLO_HYS Supply undervoltage hysteresis
Rising to falling theshold
VM falling; UVLO report
50
10
2
mV
µs
A
tUVLO
IOCP
Supply undervoltage deglitch time
(2)
Overcurrent protection trip point
VVM < 15 V
3
µs
µs
ms
µA
µA
V
tOCP
Overcurrent protection deglitch time
VVM >= 15 V
1
tRETRY
IOL_PU
IOL_PD
VOL_HS
VOL_LS
TTSD
Overcurrent protection retry time
Open load pull-up current
1
< 15 nF on OUTx Pin
< 15 nF on OUTx Pin
200
230
2.3
1.2
160
40
Open load pull-down current
Open load detect threshold (high side)
Open load detect threshold (low side)
Thermal shutdown temperature
Thermal shutdown hysteresis
V
150
180
°C
°C
THYS
(2) For VM > 16.5 V, the output current on OUTx must be limited to 4 A
6.6 I2C Timing Requirements
MIN
NOM
MAX
UNIT
STANDARD MODE
fSCL
SCL Clock frequency
0
100
kHz
8
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I2C Timing Requirements (continued)
MIN
NOM
MAX
UNIT
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
tHD,STA
4
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
4.7
4
µs
µs
µs
µs
ns
ns
ns
µs
µs
tHIGH
tSU,STA
tHD,DAT
tSU,DAT
tR
4.7
0
3.45
250
SDA and SCL rise time
1000
300
tF
SDA and SCL fall time
tSU,STO
tBUF
Set-up time for STOP condition
Bus free time between a STOP and START condition
4
4.7
FAST MODE
fSCL
SCL Clock frequency
0
400
kHz
µs
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
tHD,STA
0.6
tLOW
tHIGH
tSU,STA
tHD,DAT
tSU,DAT
tR
LOW period of the SCL clock
1.3
0.6
0.6
0
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
0.9
250
SDA and SCL rise time
300
300
tF
SDA and SCL fall time
tSU,STO
tBUF
Set-up time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes to be supressed by input noise filter
0.6
1.3
tSP
50
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xIN1
tpd
xIN2
tpd
tpd
xOUT1
Z
Z
Z
tpd
Z
xOUT2
90%
90%
10%
10%
trise
tfall
图 1. Timing Diagram
STO
STA
STA
STO
SDA
SCL
tBUF
tr
tHD,STA
tf
tSU,STO
tHD,DAT
tSU,DAT
tSU,STA
tHIGH
tLOW
tHD,STA
图 2. I2C Timing Diagram
10
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6.7 Typical Characteristics
5
4
3
2
1
0
4
3
2
1
0
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
TA = -40°C
TA = 25°C
TA = 85°C
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
-40
-20
0
20 40
Temperature (°C)
60
80
100
D001
D002
图 3. Operating Supply Current (IVM) vs Supply Voltage (VVM
)
图 4. Operating Supply Current (IVM) vs Ambient
Temperature (TA)
5
7
6
5
4
3
2
1
0
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
4
3
2
1
TA = -40°C
TA = 25°C
TA = 85°C
0
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
-40
-20
0
20 40
Temperature (°C)
60
80
100
D003
D004
图 5. Sleep Mode Supply Current (IVMQ) vs Supply Voltage
(VVM
图 6. Sleep Mode Supply Current (IVMQ) vs Ambient
)
Temperature (TA)
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Typical Characteristics (接下页)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = -40°C
TA = 25°C
TA = 85°C
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
-40
-20
0
20
40
60
80
100
Temperature (èC)
D005
D006
图 7. High Side On-State Resistance (RDS(ON)_HS) vs Supply
Voltage (VVM
图 8. High Side On-State Resistance (RDS(ON)_HS) vs Ambient
)
Temperature (TA)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
TA = -40°C
TA = 25°C
TA = 85°C
0.3
0.2
0.1
0
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
-40
-20
0
20
40
60
80
100
Temperature (èC)
D007
D008
图 9. Low Side On-State Resistance (RDS(ON)_LS) vs Supply
Voltage (VVM
图 10. Low Side On-State Resistance (RDS(ON)_LS) vs
)
Ambient Temperature (TA)
12
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Typical Characteristics (接下页)
225
250
225
200
175
150
125
100
200
175
150
125
100
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
D009
D001
图 11. Open Load Pull-Up Current (IOL_PU) vs Supply Voltage
图 12. Open Load Pull-Down Current (IOL_PD) vs Supply
Voltage (VVM
(VVM
)
)
2.6
2.4
2.2
2
1.3
1.2
1.1
1
1.8
1.6
1.4
1.2
0.9
0.8
0.7
0.6
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
2
4
6
8
Supply Voltage (V)
10
12
14
16
18
D001
D001
图 13. Open Load High-Side Threshold Voltage (VOL_HS) vs
图 14. Open Load Low-Side Threshold Voltage (VOL_LS) vs
Supply Voltage (VVM
Supply Voltage (VVM
)
)
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7 Detailed Description
7.1 Overview
The DRV8847 device is an integrated 2.7-V to 18-V dual motor driver for industrial brushed and stepper motor
applications. This driver can drive two DC motors, a bipolar stepper motor, or the solenoid loads. The device
integrates two H-bridges that use NMOS low-side and high-side drivers and current-sense regulation circuitry.
The DRV8847 device supports a high output current of 1-A RMS per H-bridge using low-RDS(ON) integrated
MOSFETs.
A simple PWM interface option allows easy interfacing to the H-bridge outputs. The interface options can be
configured using the MODE and IN3 pins in the DRV8847 device. The interface options can be configured
through a I2C interface in the I2C device variant (DRV8847S).
The current regulation uses a fixed off-time (tOFF) PWM scheme. The trip point for current regulation is controlled
by the value of the sense resistor and fixed internal VTRIP value.
A low-power sleep mode is included which lets the system save power when not driving the motor.
The DRV8847 device is available in three different packages:
•
•
•
16-pin TSSOP (no thermal pad)
16 pin HTSSOP (PowerPAD)
16 pin WQFN (thermal pad)
The I2C variant of the DRV8847 device is also available for a detailed diagnostics requirement and multi-slave
operation with multi-slave operation control over I2C bus.
The DRV8847S device variant is available in one package which is the 16-pin TSSOP (no thermal pad).
The DRV8847 device has a broad range of integrated protection features. These features include power supply
undervoltage lockout, open-load detection, overcurrent faults, and thermal shutdown.
14
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7.2 Functional Block Diagram
VM
Charge Pump
Power
VM
VM
Internal
Reference
and
0.1 µF
CVM1
bulk
CVM2
Regulators
OUT1
MODE
DC
Motor
Stepper
Gate
Drive
and
VM
Motor
OCP
TRQ
OUT2
nSLEEP
RSENSE12
(Optional)
ISENS12
ISEN
IN1
IN2
IN3
IN4
VM
Logic
OUT3
DC
Motor
Gate
Drive
and
VM
VEXT
OCP
RnFAULT
OUT4
Output
nFAULT
RSENSE34
(Optional)
ISENS34
ISEN
Overtemperature
GND
PPAD
图 15. Block Diagram for DRV8847
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Functional Block Diagram (接下页)
VM
Charge Pump
Power
VM
VM
Internal
Reference
and
0.1 µF
CVM1
bulk
CVM2
Regulators
OUT1
nSLEEP
DC
Motor
Stepper
Motor
Gate
Drive
and
IN1
IN2
IN3
IN4
VM
OCP
OUT2
RSENSE12
(Optional)
ISENS12
ISEN
VM
VEXT
RnFAULT
Logic
OUT3
Output
nFAULT
DC
Motor
Gate
Drive
and
VM
SCL
VEXT
I2C
Registers
OCP
RSDA
OUT4
SDA
RSENSE34
(Optional)
ISENS34
ISEN
Overtemperature
GND
PPAD
图 16. Block Diagram for DRV8847S
16
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7.3 Feature Description
表 1 lists the recommended values of the external components for the gate driver.
表 1. DRV8847 External Components
COMPONENT
CVM1
PIN 1
VM
PIN 2
GND
RECOMMENDED
10-µF (minimum) VM-rated capacitor
CVM2
VM
GND
0.1-µF VM-rated ceramic capacitor
>1 kΩ
RnFAULT
RISEN12
RISEN34
VEXT(1)
ISEN12
ISEN34
nFAULT
GND
Sense resistor, see the Typical Application for sizing
Sense resistor, see the Typical Application for sizing
GND
(1) VEXT is not a pin on the DRV8847 device, but a pullup resistor on the VEXT external supply voltage is required for the open-drain
output, nFAULT.
7.3.1 PWM Motor Drivers
The DRV8847 device has two identical H-bridge motor drivers with current-control PWM circuitry. 图 17 shows a
block diagram of the circuitry.
The two H-bridges can also be used as four independent half-bridges depending upon the interface option. The
ISENxx pin can be only used together with two half-bridges.
VM
IN1
OUT1
IN2
Stepper
VM
Motor
PWM
Predrive
OUT2
ISEN12
œ
RSENSE12
+
REF (VTRIP
)
图 17. PWM Motor Driver Circuitry
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7.3.2 Bridge Operation
The full-bridge can operate in four different operating modes: forward, reverse, coast (fast decay), and brake
(slow decay) operation.
7.3.2.1 Forward Operation
This operating mode refers to the forward rotation of the motor such that the current flows from terminal A (OUT1
or OUT3) to terminal B (OUT2 or OUT4) as shown in 图 18. In this mode, terminal A is connected to VM and
terminal B is connected to ground.
VM
B
A
图 18. Forward Operation
7.3.2.2 Reverse Operation
This operating mode refers to the reverse rotation of the motor such that the current flows from terminal B (OUT2
or OUT4) to terminal A (OUT1 or OUT3) as shown in 图 19. In this mode, terminal A is connected to ground and
terminal B is connected to VM.
VM
B
A
图 19. Reverse Operation
18
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7.3.2.3 Coast Operation (Fast Decay)
In this operating mode, all the FETs of the full-bridges are in the high impedance (Hi-Z) state. The motor also
goes to the Hi-Z state, and the motor starts coasting. This operating mode also helps to decay the motor current
faster and is therefore also referred to as a fast decay mode. If the motor was initially connected in forward
operation (current flows from terminal A to terminal B) and if the coast operation is applied, then, because of the
inductive nature of motor load, the current continues to flow in the same direction (A to B), and the anti-parallel
diodes of the alternate FETs starts conducting as shown in 图 20. This flow of current through anti-parallel diodes
lets the current decrease rapidly because of the higher negative potential created by the supply voltage, VM.
VM
A
B
图 20. Coast Operation (Fast Decay)
7.3.2.4 Brake Operation (Slow Decay)
This operating mode is realized by switching on both of the low-side FETs of the full-bridge as shown in 图 21. A
current circulation path is provided when both low-side FETs are turned on. Due to this circulation path, the
current decays to ground using the resistance of the motor and of the low-side FET. Because this current decay
is less when compared to the coast operation because of the low potential difference, this mode is also referred
to the slow decay mode.
VM
B
A
图 21. Brake Operation (Slow Decay)
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7.3.3 Bridge Control
The DRV8847 device can be configured in four different operating modes depending on user requirements. The
MODE and IN3 pins are used to configure the DRV8847 in one of the four different interfaces: 4-pin interface, 2-
pin interface, a parallel bridge interface, and the independent bridge interface. Mode selection is done using the
I2C registers in the DRV8847S device variant (see the Programming section). 表 2 lists the configurations to
select the operating mode of the bridges.
表 2. Bridge Mode Selection (DRV8847 Hardware Device Variant)
nSLEEP
MODE
IN3
X
INTERFACE
0
1
1
1
1
X
0
1
1
Z
Sleep mode
X
4-pin interface
0
2-pin interface
1
Parallel bridge interface
X
Independent bridge interface
注
The MODE pin is not latched during driver operation. Therefore, TI does not recommend
connecting this pin to a controller to use at any time.
7.3.3.1 4-Pin Interface
In the 4-pin interface, the DRV8847 device is configured to drive a stepper motor or two BDC motors with fully
functional modes. To configure 4-pin interface operation, connect the MODE pin to ground and use the IN1, IN2,
IN3, and IN4 pins to control the drivers. In this mode, the stepper or brushed DC motor can operate with all four
modes (forward, reverse, coast, and brake mode) and the stepper motor can operate in either full-stepping mode
or the non-circulating half-stepping mode. Sense resistors can be connected to the ISEN12 and ISEN34 pins for
independent current regulation in bridge-12 and bridge-34 respectively.
Use this interface option for the following loads:
•
•
•
Stepper motor in full-stepping mode (with or without current regulation)
Stepper motor in half-stepping mode (with or without current regulation)
Single or dual BDC motor (with or without current regulation) with full functional BDC modes (forward,
reverse, brake, and coast mode)
表 3 lists the configurations for 4-pin interface operation and 图 22 shows the application diagram for 4-pin
interface operation.
表 3. 4-Pin Interface (MODE = 0)
nSLEEP
IN1
X
IN2
X
IN3
IN4
OUT1
OUT2
OUT3
OUT4
FUNCTION (DC MOTOR)
Sleep mode
0
1
1
1
1
1
1
1
1
X
X
Z
Z
L
Z
Z
H
L
Z
Z
0
0
Motor coast (fast decay)
Reverse direction
0
1
1
0
H
L
Forward direction
1
1
L
Motor brake (slow decay)
Motor coast (fast decay)
Reverse direction
0
0
1
1
0
1
0
1
Z
L
Z
H
L
H
L
Forward direction
L
Motor brake (slow decay)
20
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VM
OUT1
DC
Motor
Gate
Drive
and
Stepper
VM
Motor
OCP
OUT2
IN1
RSENSE
(Optional)
ISEN12
ISEN
IN2
IN3
VM
Logic
Controller
IN4
OUT3
nSLEEP
DC
Motor
Gate
Drive
and
VM
OCP
MODE
GND
OUT4
RSENSE
(Optional)
ISEN34
ISEN
图 22. 4-Pin Interface Operation
7.3.3.2 2-Pin Interface
In the 2-pin interface, the DRV8847 device is configured to drive a stepper motor or two BDC motors with lower
number of control inputs from microcontroller. To configure 2-pin interface operation, connect the MODE pin to
the external supply (3.3 V or 5 V), connect the IN3 pin to ground, and use the IN1 and IN2 pins to control the
driver. In this mode, the stepper or brushed DC motor operate in only two modes (forward mode and reverse
mode) i.e. only full-step operation is supported for stepper motor. This 2-pin interface is very useful for low GPIO
applications such as refrigerator dampers. Sense resistors can be connected to the ISEN12 and ISEN34 pins for
current regulation.
Use this interface option for the following loads:
•
•
Stepper motor in full stepping mode (with or without current regulation)
Single or dual BDC motor (with or without current regulation) with reduced functional BDC modes (forward
and reverse mode only)
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表 4 lists the configurations for 2-pin interface operation and 图 23 shows the application diagram for 2-pin
interface operation.
表 4. 2-Pin Interface (MODE = 1, IN3 = 0)
nSLEEP
IN1
X
IN2
IN3
X
IN4
X
OUT1
OUT2
OUT3
OUT4
FUNCTION (DC MOTOR)
Sleep mode
0
1
1
1
1
X
Z
L
Z
H
L
Z
Z
0
0
X
Reverse direction
Forward direction
Reverse direction
Forward direction
1
0
X
H
0
1
0
X
L
H
L
0
X
H
VM
OUT1
VEXT
MODE
DC
Motor
Gate
Drive
and
Stepper
Motor
VM
IN3
OCP
GND
OUT2
IN4
Don‘t Care
RSENSE
(Optional)
ISEN12
ISEN
VM
Logic
OUT3
IN1
IN2
DC
Motor
Gate
Drive
and
Controller
VM
OCP
nSLEEP
OUT4
RSENSE
(Optional)
ISEN34
ISEN
图 23. 2-Pin Interface Operation
22
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注
In this mode, two of the OUTx pins are always 'ON' if the device is in non-sleep state
(nSLEEP = HIGH). Therefore, to completely de-energize the motor-coils connected to
OUTx pins, the user has to pull-down nSLEEP pin.
7.3.3.3 Parallel Bridge Interface
In the parallel bridge interface, the DRV8847 device is configured to drive a higher current BDC motor by using
the driver in parallel to deliver twice the motor current. To go to parallel bridge interface operation, connect the
MODE and IN3 pins to the external supply (3.3 V or 5 V) and use the IN1 and IN2 pins to control the driver. This
mode can deliver the full functionality of the BDC motor control with all four modes (forward, reverse, coast, and
brake mode).
Use this interface option for the following loads:
•
One high current BDC motor (with or without current regulation) with full functional BDC modes (forward,
reverse, brake, and coast mode)
•
Two independent BDC motors operating together (with or without current regulation) with full functional BDC
modes (forward, reverse, brake, and coast mode)
表 5 lists the configurations for parallel bridge interface operation, and 图 24 shows the application diagram for
parallel bridge interface operation.
表 5. Parallel Interface (MODE = 1, IN3 = 1)
nSLEEP
IN1
X
IN2
X
IN3
X
IN4
X
OUT1
OUT2
OUT3
OUT4
FUNCTION (DC MOTOR)
Sleep mode
0
1
1
1
1
Z
Z
L
Z
Z
H
L
Z
Z
L
Z
Z
H
L
0
0
1
X
Motor coast (fast decay)
Reverse direction
0
1
1
X
1
0
1
X
H
L
H
L
Forward direction
1
1
1
X
L
L
Motor brake (slow decay)
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VM
VEXT
OUT1
MODE
IN3
Gate
Drive
and
VM
OCP
IN4
Don‘t Care
OUT2
ISEN12
ISEN
VM
Logic
IN1
OUT3
IN2
Controller
DC
Motor
Gate
Drive
and
VM
nSLEEP
OCP
OUT4
RSENSE
(Optional)
ISEN34
ISEN
图 24. Parallel Mode Operation
7.3.3.4 Independent Bridge Interface
In the independent bridge interface, the DRV8847 device is configured for independent half-bridge operation. To
configure independent bridge interface operation, leave the MODE pin unconnected (Hi-Z state) and use the IN1,
IN2, IN3, and IN4 pins to independently control the OUT1, OUT2, OUT3, and OUT4 pins respectively. Only two
output states of the OUTx pin can be controlled (either connected to VM or connected to GND). This mode is
used to drive independent loads such as relays and solenoids.
Use this interface option for the following loads:
•
•
Relay or solenoid coils connected between OUTx and VM/ground pin without current regulation
Single or dual BDC motor (with or without current regulation) with three functional BDC modes (forward,
reverse, and braking mode only)
•
•
Stepper motor in full-stepping mode (with or without current regulation)
Stepper motor in half-stepping mode (with or without current regulation) using brake mode
24
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表 6 lists the configurations for independent bridge interface operation and 图 25 shows the application diagram
for independent bridge interface operation.
表 6. Independent Bridge Interface (MODE = Hi-Z)
nSLEEP
IN1
X
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
FUNCTION (DC MOTOR)
Sleep mode
0
1
1
1
1
1
1
1
1
X
X
X
Z
L
Z
Z
Z
0
OUT1 connected to GND
OUT1 connected to VM
OUT2 connected to GND
OUT2 connected to VM
OUT3 connected to GND
OUT3 connected to VM
OUT4 connected to GND
OUT4 connected to VM
1
H
0
1
L
H
0
1
L
H
0
1
L
H
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VM
OUT1
Gate
Drive
and
VM
OCP
OUT2
IN1
IN2
IN3
ISEN12
ISEN
Controller
IN4
VM
Logic
nSLEEP
OUT3
Gate
Drive
and
VM
OCP
MODE
Not Connected
OUT4
ISEN34
ISEN
图 25. Independent Bridge Interface
7.3.4 Current Regulation
The current through the motor windings is regulated by a fixed off-time PWM current regulation circuit. With
brushed DC motors, current regulation can be used to limit the stall current (which is also the start-up current) of
the motor.
Current regulation works as follows: When an H-bridge is enabled, current rises through the winding at a rate
dependent on the supply voltage and inductance of the winding. If the current reaches the current trip threshold,
the bridge disables the current for a time tOFF before starting the next PWM cycle.
注
Immediately after the current is enabled, the voltage on the ISENxx pin is ignored for a
period of time (tBLANK) before enabling the current sense circuitry. This blanking time also
sets the minimum on-time of the PWM cycle.
26
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The PWM trip current is set by a comparator which compares the voltage across a current sense resistor
connected to the ISENxx pin with a reference voltage. This reference voltage (VTRIP) is generated on-chip and
decides the current trip level.
The full-scale trip current in a winding is calculated as shown in 公式 1.
VTRIP
ITRIP = Torque
RSENSExx
where
•
•
•
•
ITRIP is the regulated current.
VTRIP is the internally generated trip voltage.
RSENSExx is the resistance of the sense resistor.
Torque is the torque scalar, the value of which depends on the input on TRQ pin. TRQ = 100% for TRQ pin
connected to GND (DRV8847) or TRQ bit set to 0 (DRV8847S) and TRQ = 50% connected to VEXT (DRV8847)
or TRQ bit set to 1 (DRV8847S).
(1)
For example, if the VTRIP voltage is 150 mV and the value of the sense resistor is 150 mΩ, the full-scale trip
current is 1 A (150 mV / (150 mΩ) = 1 A).
注
If current control is not needed, connect the ISENxx pins directly to ground.
7.3.5 Current Recirculation and Decay Modes
During PWM current trip operation, the H-bridge is enabled to drive current through the motor winding until the
trip threshold of the current regulation is reached. After the trip current threshold is reached, the drive current is
interrupted, but, because of the inductive nature of the motor, current must continue to flow for some time. This
continuous flow of current is called recirculation current. A mixed decay allows a better current regulation by
optimizing the current ripple by using fast and slow decay.
Mixed decay is a combination of fast and slow decay modes. In fast decay mode, the anti-parallel diodes of the
opposite FETs are conducting on to let the current decay faster as shown in 图 26 (see case 2). In slow decay
mode, winding current is recirculated by enabling both low-side FETs in the bridge (see case 3 in 图 26). Mixed
decay starts with fast decay, then goes to slow decay. In the DRV8847 device, the mixed decay ratio is 25% fast
decay and 75% slow decay as shown in 图 27.
VM
1
2
3
Drive Current
Fast Decay
Slow Decay
1
2
3
图 26. Decay Modes
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Fast Decay
ITRIP
Slow Decay
Motor
Current
25% of tOFF
Time
tON
tOFF
Mixed Decay (25% Fast Decay)
图 27. Mixed Decay
注
The current regulation scheme uses a single sense resistor and hence always works for
two half bridges even when used in "Independent Bridge Interface". It is recommended
that current regulation not be used for loads using independent half bridges.
7.3.6 Torque Scalar
The torque scalar is used to dynamically adjust the output current through a digital input pin, TRQ. This torque
scalar decreases the trip reference value of the output current to 50% (whenever the TRQ pin is pulled-high).
Torque scalar can be used to scale the holding torque of the stepper motor. For the I2C device variant
(DRV8847S), this feature is implemented through an I2C register.
When the TRQ pin is pulled-low (or the TRQ bit is reset in the DRV8847S device variant), then trip current is
calculated using 公式 2.
Torque ì VTRIP
RSENSExx
ITRIP
=
(2)
When the TRQ pin is pulled-high (or the TRQ bit is set in the DRV8847S device variant), then trip current is
calculated using 公式 3.
VTRIP
ITRIP = 0.5
RSENSExx
(3)
28
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7.3.7 Stepping Modes
The DRV8847 device is used to drive a stepper motor in full-stepping mode or non-circulating half-stepping mode
using the following bridge configurations:
•
Full-stepping mode (with or without current regulation)
–
–
Using 4-pin interface configuration
Using 2-pin interface configuration
•
Half-stepping mode (with or without current regulation)
Using 4-pin interface configuration
–
7.3.7.1 Full-Stepping Mode (4-Pin Interface)
In full-stepping mode, the full-bridge operates in either of two modes (forward or reverse mode) with a phase shift
of 90° between the two windings.
In 4-pin interface, the PWM input is applied to the IN1, IN2, IN3, and IN4 pins as shown in 图 28 and the driver
operates only in forward (FRW) and reverse (REV) mode.
90o
Phase
IN1
IN2
IN3
IN4
OUT12 FRW
OUT12 FRW
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
OUT34
OUT34 REV
OUT34 REV
Time
图 28. Full-Stepping Mode Using 4-Pin Interface
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7.3.7.2 Full-Stepping Mode (2-Pin Interface)
In full-stepping using the 2-pin interface, the PWM input is only applied to the IN1 and IN2 pins, and the IN3 is
connected to ground (see the 图 23 section). 图 29 shows the full-stepping mode of stepper motor using the 2-
pin interface
90o
Phase
IN1
IN2
OUT12 FRW
OUT12 FRW
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
OUT34
OUT34 REV
OUT34 REV
Time
图 29. Full-Stepping Mode Using 2-Pin Interface
30
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7.3.7.3 Half-Stepping Mode (With Non-Driving Fast Decay)
In half-stepping mode, the full-bridge operates in one of the three modes (forward, reverse, or coast mode) with a
phase shift of 45° between the two windings.
In 4-pin interface, the PWM input is connected to the IN1, IN2, IN3, and IN4 pins as shown in 图 30, and the
driver operates in forward, reverse, and coast mode.
45o
Phase
IN1
IN2
IN3
IN4
OUT12 FRW
OUT12 FRW
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
OUT34
OUT34 REV
OUT34 REV
Time
图 30. Half-Stepping Mode Using 4-Pin Interface (With Non-Driving Fast Decay)
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7.3.7.4 Half-Stepping Mode (With Non-Driving Slow Decay)
In this half-stepping mode, the non-driving state is slow decay (braking mode). Therefore, the full-bridge operates
in one of the three modes (forward, reverse, or brake mode) with a phase shift of 45° between the two windings.
In 4-pin interface, the PWM input is connected to the IN1, IN2, IN3, and IN4 pins as shown in 图 31, and the
driver operates in forward, reverse, and brake mode.
45o
Phase
IN1
IN2
IN3
IN4
OUT12 FRW
OUT12 FRW
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
OUT34
OUT34 REV
OUT34 REV
Time
图 31. Half-Stepping Mode Using 4-Pin Interface (With Non-Driving Slow Decay)
32
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7.3.8 Motor Driver Protection Circuits
The DRV8847 device is protected against VM undervoltage, overcurrent, open load, and over temperature
events.
7.3.8.1 Overcurrent Protection (OCP)
The DRV8847 is protected against overcurrent by overcurrent protection trip. The OCP circuit on each FET
disables the current flow through the FET by removing the gate drive. If this overcurrent detection continues for
longer than the OCP deglitch time (tOCP), all FETs in the H-bridge (or half-bridge in the independent interface) are
disabled and the nFAULT pin is driven low. The DRV8847 device stays disabled until the retry time tRETRY occurs
whereas the DRV8847S device has a programmable option for auto-retry or the latch mode.
7.3.8.1.1 OCP Automatic Retry (Hardware Device and Software Device (OCPR = 0b))
After an OCP event in this mode, the corresponding half-bridges, full-bridge, or both bridges (depending on the
MODE bits) are disabled and the nFAULT pin is driven low (see 表 13 and 表 14). The OCP and corresponding
OCPx bits are latched high in the I2C registers (see the Register Map section). Normal operation resumes
automatically (motor driver operation and the nFAULT pin is released) after the tRETRY time elapses as shown in
图 32. The OCP and OCPx bits remain latched until the tRETRY period expires.
Overshoot due to OCP
)
deglitch time (tOCP
IOCP
Motor
Current
Time
tOCP
tRETRY
图 32. OCP Operation
7.3.8.1.2 OCP Latch Mode (Software Device (OCPR = 1b))
OCP latch mode is only available in the DRV8847S device. After an OCP event, the corresponding half-bridges,
full-bridge, or both bridges (depending on the MODE bits) are disabled and the nFAULT pin is driven low. The
OCP and corresponding OCPx bits are latched high in the I2C registers (see the Register Map section). Normal
operation continues (motor driver operation and the nFAULT pin is released) when the OCP condition is removed
and a clear faults command is issued through the CLR_FLT bit.
注
For supply voltage, VVM > 16.5-V, if the OUTx current (FET current) exceeds 4-A, then the
device operation is pushed beyond the safe operating area (SOA) of the device. User has
to ensure that the FET-current is below 4-A for device safe operation for supply voltage
above 16.5-V.
7.3.8.2 Thermal Shutdown (TSD)
If the die temperature exceeds thermal shutdown limits (TTSD), all FETs in the H-bridge are disabled and the
nFAULT pin is driven low. After the die temperature decreases to a value within the specified limits, normal
operation resumes automatically. The nFAULT pin is released after operation starts again.
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7.3.8.3 VM Undervoltage Lockout (VM_UVLO)
Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, and all internal logic is reset. Operation continues when the VVM voltage rises above the
UVLO rising threshold as shown in 图 33. The nFAULT pin is driven low during an undervoltage condition and is
released after operation starts again.
VUVLO (max) rising
VUVLO (min) rising
VUVLO (max) falling
VUVLO (min) falling
VVM
DEVICE ON
DEVICE OFF
DEVICE ON
nFAULT
Time
图 33. VM UVLO Operation
7.3.8.4 Open Load Detection (OLD)
An open load detection feature is also implemented in this device. This diagnostic test runs at device power up or
when the DRV8847 device comes out from sleep mode (rising edge on the nSLEEP pin). The OLD diagnostic
test can run any time in the I2C variant device (DRV8847S) using the OLDOD (OLD On Demand) bit.
The OLD implementation is done on the full-bridge and the half-bridge. In the DRV8847 device, during an open-
load condition, the half-bridges, full-bridge, or both bridges (depending on the MODE pin) are always operating
and the nFAULT pin is pulled-low. The user must reset the power to release the nFAULT pin by doing the OLD
sequence again. 表 7 lists the different OLD scenarios for the DRV8847 device.
In the DRV8847S device, the user can program the full-bridge or half-bridge to be in the operating mode or the
Hi-Z state, whenever an open-load condition is detected by using the OLDBO (OLD Bridge Operation) bit.
Moreover, the nFAULT signaling on the OLD bit can be disabled using the OLDFD (OLD Fault Disable) bit. For
detailed I2C register settings, see the Register Map section. 表 8 lists the different OLD scenarios for the
DRV8847S device.
注
For accurate OLD operation, the user must ensure that the motor is stationary (or current
in connected load becomes zero) before the open load on-demand command is executed.
34
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表 7. Open Load Detection in DRV8847
BRIDGE
OPERATION
LOAD TYPE
OLD
nFAULT
Full-Bridge Connected
Half-Bridge Connected
Bridge Open
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
4-pin
2-pin
YES
YES
NO
YES
YES
NO
One Half-Bridge Open
Full-Bridge Connected
Half-Bridge Connected
Bridge Open
NO
NO
Parallel bridge
YES
YES
NO
YES
YES
NO
One Half-Bridge Open
Full-Bridge Connected
Half-Bridge Connected
Bridge Open
NO
NO
Independent
bridge
YES
YES
YES
YES
One Half-Bridge Open
表 8. Open Load Detection in DRV8847S (Full-bridge-12)
BRIDGE OPERATION(1)
OLD BITS
OLD1 OLD2 OLD3 OLD4
INTERFACE
LOAD TYPE
OLD
nFAULT
OLDBO = 0b
YES
OLDBO = 1b
YES
Full-bridge connected
Half-bridge connected
Bridge open
NO
NO
NO
NO
0b
0b
1b
0b
0b
1b
X
X
X
X
X
X
YES
YES
4-pin
2-pin
YES
YES
NO
YES
1b or 0b or
One half-bridge open
YES
YES
NO
YES
X
X
(2)
0b
1b
0b
0b
1b
Full-bridge connected
Half-bridge connected
Bridge open
NO
NO
YES
YES
YES
YES
YES
NO
NO
NO
0b
X
X
X
X
X
X
0b
1b
Parallel bridge
YES
YES
1b or 0b or
One half-Bridge Open
YES
YES
NO
YES
X
X
0b
0b
0b
1b
1b
0b
0b
1b
Full-Bridge Connected
Half-Bridge Connected
Bridge Open
NO
NO
YES
YES
YES
YES
YES
NO
NO
NO
X
X
X
X
X
X
Independent
bridge
YES
YES
1b or 0b or
0b 1b
One Half-Bridge Open
YES
YES
NO
YES
X
X
(1) The operation of the bridge is subjected to the selected mode type:
(a) In 4-pin or 2-pin interface, the corresponding bridge is in the operating or Hi-Z state.
(b) In parallel bridge (BDC) interface, both bridges are in the operating or Hi-Z state.
(c) In independent bridge interface, the corresponding half-bridge is in the operating or Hi-Z state.
(2) Depending on which half-bridge is open, the corresponding bit in the I2C register is set.
The open-load detect sequence comprise of three detection states in which the driver ensures that any of the
load is either connected or open as follows.
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7.3.8.4.1 Full-Bridge Open Load Detection
As shown in 图 34, during device wakeup, a constant current source pulls the OUT1 pin to the AVDD (internal)
fixed voltage which allows current flow from OUT1 to OUT2 terminal. The current drawn is completely dependent
on the motor resistance between OUT1 and OUT2. Depending on this current and the comparator threshold
voltage (VOL_HS and VOL_LS), the comparator output OL1_HS and OL2_LS are either set or reset which
determines the open load status. 表 9 shows the states of OL1_HS and OL2_LS for the open load detect. This
test executes before the tWAKE or tON time has elapsed. When an open load is detected, the nFAULT pin is
latched low until the device is power cycled or device reset with nSLEEP pin. A similar implementation is done
for the OUT3 and OUT4 pins.
表 9. Open Load Detection for Full-Bridge Connection
OL1_HS
OL2_LS
OLD STATUS
0
0
1
1
0
1
0
1
NO OLD
OLD
AVDD
VM
SW1_HS
VOL_HS
œ
12 kΩ
+
OL1_HS
X
IOL_PU
OUT1
SW1_LS
OLD1
IOL_PD
X
œ
+
OL1_LS
VOL_LS
15 kΩ
DC
Motor
Stepper
Motor
AVDD
VM
SW2_HS
œ
12 kΩ
VOL_HS
+
OL2_HS
X
IOL_PU
OUT2
SW2_LS
OLD2
To OUT3 and OUT4
IOL_PD
X
œ
+
OL2_LS
VOL_LS
15 kΩ
图 34. Open Load Detect Circuit for Full-Bridge Connection
36
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注
AVDD voltage is the internal regulator voltage and is determined as min (VVM, 4.2 V).
Hence, for supply voltage (VVM) higher than 4.2 V, this voltage is fixed at 4.2 V else it is
equal to supply voltage ( VVM).
7.3.8.4.2 Load Connected to VM
For detection of the VM connected load, a constant current source pull-down the OUT1 node as shown in 图 35.
This allows the current to flow from VM to OUT1 depending upon the value of load resistor (RL) connected
between OUT1 and VM. Higher current (not open load) will allow the OL1_LS comparator to set and higher
current resets the comparator output as shown in 表 10 for open load detection.
表 10. Open Load Detection for VM Connected Load
OL1_LS
OLD STATUS
NO OLD
OLD
0
1
VM
AVDD
VM
SW1_HS
œ
12 kΩ
VOL_HS
RL
+
OL1_HS
X
IOL_PU
X
OUT1
SW1_LS
OLD1
IOL_PD
X
œ
+
OL1_LS
VOL_LS
15 kΩ
图 35. Open Load Detect Circuit for Load Connected to VM
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7.3.8.4.3 Load Connected to GND
For detection of the GND connected load, the OUT1 node is pulled-up by the internal current source and the
internal (4.2-V) fixed voltage as shown in 图 36. This allows the current to flow from OUT1 to GND depending
upon the value of load resistor (RL) connected between OUT1 and GND. Higher current (not open load) will allow
the OL1_HS comparator to set and higher current resets the comparator output as shown in 表 11.
表 11. Open Load Detection for GND Connected Load
OL1_HS
OLD STATUS
NO OLD
OLD
0
1
AVDD
VM
SW1_HS
œ
12 kΩ
VOL_HS
+
OL1_HS
X
IOL_PU
OUT1
SW1_LS
OLD1
IOL_PD
X
RL
X
œ
+
OL1_LS
VOL_LS
15 kΩ
图 36. Open Load Detect Circuit for Load Connected to GND
38
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7.4 Device Functional Modes
The DRV8847 device is active until the nSLEEP pin is pulled logic low. In sleep mode, the internal circuitry
(charge pump and regulators) is disabled and all internal FETs are disabled (Hi-Z state).
The device goes to operating mode automatically if the nSLEEP pin is pulled logic high. tWAKE must elapse
before the device is ready for inputs. The nFAULT pin asserts for small duration during power-up. Various
functional modes are described in 表 12.
The DRV8847 device goes to a fault mode in the event of VM undervoltage (UVLO), overcurrent (OCP), open-
load detection (OLD), and thermal shutdown (TSD). The functionality of each fault depends on the type of fault
listed in 表 13 for the DRV8847 device and 表 14 for the DRV8847S device.
注
The tSLEEP time must elapse before the device goes to sleep mode.
表 12. Functional Modes
MODE
CONDITION
H-BRIDGE
INTERNAL CIRCUITS
2.7 V < VVM < 18 V
nSLEEP pin = 1
Operating
Operating
Operating
2.7 V < VVM < 18 V
nSLEEP pin = 0
Sleep
Fault
Disabled
Disabled
Any fault condition met
Depends on fault
Depends on fault
表 13. Fault Support for DRV8847
INTERNAL
CIRCUITS
FAULT
INTERFACE
CONDITION
REPORT
H-BRIDGE
RECOVERY
Automatic:
VM > VUVLO
VM undervoltage
(VM_UVLO)
Both H-bridges in
Hi-Z state
All interfaces
VM < VUVLO
nFAULT
Shutdown
Corresponding H-
bridges in Hi-Z
state
4-pin
2-pin
Overcurrent
(OCP)
Both H-bridges in
Hi-Z state
Automatic:
tRETRY
Parallel bridge
I > IOCP
nFAULT
Operating
Corresponding
half-bridges in Hi-
Z state
Independent
bridge
H-bridge in
operating mode
4-pin
Full-bridge open
Full-bridges open
Half-bridge open
nFAULT
nFAULT
nFAULT
nFAULT
Power cycle
/RESET: OUTx
Connected
2-pin
Parallel bridge
Open load detect
(OLD)
Both H-bridges in
operating mode
Operating
Operating
Independent
bridge
Half-bridge in
operating mode
TJ > TTSD
(min 150°C)
TJ < TTSD
(THYS typ 40°C)
Thermal shutdown
(TSD)
Both H-bridges in
Hi-Z state
All interfaces
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RECOVERY
表 14. Fault Support for DRV8847S
INTERNAL
CIRCUITS
FAULT
MODE
CONDITION
REPORT
H-BRIDGE
Automatic:
VM > VUVLO
VM undervoltage
(VM_UVLO)
Both H-bridges in
Hi-Z state
All interfaces
VM < VUVLO
nFAULT
Shutdown
Corresponding H-
bridges in Hi-Z
state
4-pin
2-pin
Overcurrent
(OCP)
Both H-bridges in
Hi-Z state
Automatic:
tRETRY
Parallel bridge
I > IOCP
nFAULT
Operating
Corresponding
half-bridges in Hi-
Z state
Independent
bridge Interface
H-bridge in
operating or Hi-Z
state(1)
4-pin
Full-bridge open
Full-bridges open
Half-bridge open
nFAULT
nFAULT
Both H-bridges in
operating or Hi-Z
state
Power cycle /
RESET: OUTx
Connected
2-pin
Parallel bridge
Open load detect
(OLD)
Operating
Operating
Half-bridge in
operating or Hi-Z
state
Independent
bridge
nFAULT
nFAULT
TJ > TTSD
(min 150°C)
TJ < TTSD
(THYS typ 40°C)
Thermal shutdown
(TSD)
Both H-bridges in
Hi-Z state
All interfaces
(1) The state of the bridge in OLD is dependent on the OLDBO bit as listed in 表 19.
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7.5 Programming
This section applies only to the DRV8847S device (I2C variant).
7.5.1 I2C Communication
7.5.1.1 I2C Write
To write on the I2C bus, the master device sends a START condition on the bus with the address of the 7-bit
slave device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the slave sends the
acknowledge bit, the master device then sends the register address of the register to be written. The slave
device sends an acknowledge (ACK) signal again which notifies the master device that the slave device is ready.
After this process, the master device sends 8-bit write data and terminates the transmission with a STOP
condition.
START
7-bit Slave Address
R/W=0
ACK
8-bit Register Address
ACK
8-bit Data
ACK
STOP
Write to Memory
图 37. I2C Write Sequence
7.5.1.2 I2C Read
To read from a slave device, the master device must first communicate to the slave device which register will be
read from. This communication is done by the master starting the transmission similarly to the write process
which is by setting the address with the R/W bit equal to 0b (signifying a write). The master device then sends
the register address of the register to be read from. When the slave device acknowledges this register address,
the master device sends a START condition again, followed by the slave address with the R/W bit set to 1b
(signifying a read). After this process, the slave device acknowledges the read request and the master device
releases the SDA bus, but continues supplying the clock to the slave device.
During this part of the transaction, the master device becomes the master-receiver, and the slave device
becomes the slave-transmitter. The master device continues sending out the clock pulses, but releases the SDA
line so that the slave device can transmit data. At the end of the byte, the master device send a negative-
acknowledge (NACK) signal, signaling to the slave device to stop communications and release the bus. The
master device then sends a STOP condition.
Repeated Start
START
7-bit Slave Address
R/W=0
ACK
8-bit Register Address
ACK
RSTRT
7-bit Slave Address
R/W=1
STOP
NACK
8-bit Data
ACK
图 38. I2C Read Sequence
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Programming (接下页)
7.5.2 Multi-Slave Operation
Multi-slave operation is used to control multiple DRV8847S devices through one I2C line as shown in 图 39. The
default device address of the DRV8847 device is 0x60 (7-bit address). Therefore, any DRV8847S device can be
accessed using this address. The steps for multi-slave configuration for programming device-1 out of 4
connected devices (as shown in 图 39) are as follows:
nFAULT1
nFAULT2
nFAULT4
nFAULT3
Microcontroller
(Master)
SDA
SCL
DRV8847S (2)
(Slave 2)
DRV8847S (3)
(Slave 3)
DRV8847S (4)
(Slave 4)
DRV8847S (1)
(Slave 1)
图 39. Multi-Slave Operation of DRV8847S
•
•
The DRV8847S device variant is configured for multi-slave operation by writing the DISFLT bit (IC2_CON
register) of all connected devices to 1b. This step will disable the nFAULT output pin of all DRV8847S, to
avoid any race condition between master and slave I2C device.
Pull the nFAULT pins (nFAULT2, nFAULT3, and nFAULT4 pins) of three devices (2, 3, and 4) to low to
release the I2C buses of the slave device (device-2, device-3 and device-4). Now only device-1 is connected
to master.
•
•
•
•
•
Since, only one device, DRV8847S (1), is connected to the controller, and, therefore, its slave address can be
reprogrammed from default 0x60 (7-bit address) to another unique address.
Similarly, the slave address (SLAVE_ADDR) of the other three devices (device-2, device-3 and device-4) can
be reprogrammed sequentially to unique addresses by a combination of nFAULT pins.
When all slave addresses are reprogrammed, write the DISFLT bit to 0b (IC2_CON register). This will enable
the nFAULT output pin for fault flagging.
All the nFAULT pins are released and a multi-slave setup is complete. Now all connected slave devices can
be accessed using the newly reprogrammed address.
The above steps should be repeated for any device in case of a power reset (nSLEEP). .
42
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7.6 Register Map
表 15 lists the memory-mapped I2c registers for the DRV8847 device. The I2C registers are used to configure the DRV8847S device and for device
diagnostics.
注
Do not modify reserved registers or addresses not listed in the register map (表 15). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0b.
表 15. I2C Registers
Address
0x00
Acronym
SLAVE_ADDR
IC1_CON
Register Name
Slave Address
7
6
5
4
3
SLAVE_ADDR
IN1
2
1
0
Access
RW
RW
RW
RW
R
Section
Go
RSVD
TRQ
0x01
IC1 Control
IN4
DISFLT
SLR
IN3
IN2
I2CBC
OLDOD
OLD
MODE
Go
0x02
IC2_CON
IC2 Control
CLRFLT
RSVD
OLD4
RSVD
RSVD
OLD2
DECAY
nFAULT
OLD1
OCPR
OLDFD
TSDF
OLDBO
UVLOF
OCP1
Go
0x03
SLR_STATUS1
STATUS2
Slew Rate and Fault Status-1
Fault Status-2
OCP
Go
0x04
OLD3
OCP4
OCP3
OCP2
Go
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Complex bit access types are encoded to fit into small table cells. 表 16 shows the codes that are used for
access types in this section.
表 16. Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.1 Slave Address Register (Address = 0x00) [reset = 0x60]
Slave Address is shown in 图 40 and described in 表 17.
图 40. Slave Address Register
7
6
5
4
3
2
1
0
RSVD
R-0b
SLAVE_ADDR
R/W-1100000b
表 17. Slave Address Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RSVD
R
0b
Reserved
6-0
SLAVE_ADDR
R/W
1100000b
Slave address (8 bit)
The default value is 0x60
7.6.2 IC1 Control Register (Address = 0x01) [reset = 0x00]
IC1 Control is shown in 图 41 and described in 表 18.
图 41. IC1 Control Register
7
6
5
4
3
2
1
0
TRQ
IN4
IN3
IN2
IN1
I2CBC
R/W-0b
MODE
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-00b
表 18. IC1 Control Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TRQ
R/W
0b
0b = Torque scalar set to 100%
1b = Torque scalar set to 50%
6
5
4
3
2
IN4
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
The INx bits are used to control the bridge operation.
The INx bits are used to control the bridge operation.
The INx bits are used to control the bridge operation.
The INx bits are used to control the bridge operation.
IN3
IN2
IN1
I2CBC
0b = Bridge control configured by using the INx pins
1b = Bridge control configured by using the INx bits
1-0
MODE
R/W
00b
00b = 4-pin interface
01b = 2-pin interface
10b = Parallel interface
11b = Independent mode
44
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7.6.3 IC2 Control Register (Address = 0x02) [reset = 0x00]
IC2 Control is shown in 图 42 and described in 表 19.
图 42. IC2 Control Register
7
6
5
4
3
2
1
0
CLRFLT
R/W-0b
DISFLT
R/W-0b
RSVD
R-0b
DECAY
R/W-0b
OCPR
R/W-0b
OLDOD
R/W-0b
OLDFD
R/W-0b
OLDBO
R/W-0b
表 19. IC2 Control Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CLRFLT
R/W
0b
Set this bit to issue a clear FAULT command. This command
clears all FAULT bits other than the OLD and OLDx bits. This bit
reset to 0b after clearing all the faults.
0b = No clear FAULT command issued
1b = Clear FAULT command issued
6
DISFLT
R/W
0b
0b = nFAULT pin not disable
1b = nFAULT pin is disabled
5
4
RSVD
R
0b
0b
Reserved
DECAY
R/W
0b = 25% fast decay
1b = 100% slow decay
3
2
1
0
OCPR
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b = OCP auto retry mode
1b = OCP latch mode
OLDOD
OLDFD
OLDBO
0b = Idle
1b = OLD on-demand is activated
0b = Fault signaling on OLD
1b = No fault signaling on OLD
0b = Bridge operating on OLD
1b = Bridge Hi-Z on OLD
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7.6.4 Slew-Rate and Fault Status-1 Register (Address = 0x03) [reset = 0x40]
Fault Status-1 is shown in 图 43 and described in 表 20.
图 43. Fault Status-1 Register
7
6
5
4
3
2
1
0
RSVD
R-0b
SLR
RSVD
R-0b
nFAULT
R-0b
OCP
R-0b
OLD
R-0b
TSDF
R-0b
UVLOF
R-0b
R/W-0b
表 20. Fault Status-1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
RSVD
R
0b
Reserved
SLR
R/W
0b
0b = 150 ns
1b = 300 ns
5
4
RSVD
R
R
0b
0b
Reserved
nFAULT
0b = No FAULT detected (mirrors the nFAULT pin)
1b = FAULT detected
3
2
1
0
OCP
R
R
R
R
0b
0b
0b
0b
0b = No OCP detected
1b = OCP detected
OLD
0b = No open load detected
1b = Open load detected
TSDF
UVLOF
0b = No TSD fault detected
1b = TSD fault detected
0b = No UVLO fault detected
1b = UVLO fault detected
46
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7.6.5 Fault Status-2 Register (Address = 0x04) [reset = 0x00]
Fault Status-2 is shown in 图 44 and described in 表 21.
图 44. Fault Status-2 Register
7
6
5
4
3
2
1
0
OLD4
R-0b
OLD3
R-0b
OLD2
R-0b
OLD1
R-0b
OCP4
R-0b
OCP3
R-0b
OCP2
R-0b
OCP1
R-0b
表 21. Fault Status-2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
2
1
0
OLD4
R
0b
0b = No open load detected on OUT4
1b = Open load detected on OUT4
OLD3
OLD2
OLD1
OCP4
OCP3
OCP2
OCP1
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0b = No open load detected on OUT3
1b = Open load detected on OUT3
0b = No open load detected on OUT2
1b = Open load detected on OUT2
0b = No open load detected on OUT1
1b = Open load detected on OUT1
0b = No OCP detected on OUT4
1b = OCP detected on OUT4
0b = No OCP detected on OUT3
1b = OCP detected on OUT3
0b = No OCP detected on OUT2
1b = OCP detected on OUT2
0b = No OCP detected on OUT1
1b = OCP detected on OUT1
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8847 device is used in applications for stepper or brushed DC motor control.
8.2 Typical Application
The user can configure the DRV8847 for stepper motor and dual BDC motor applications as described in this
section.
8.2.1 Stepper Motor Application
图 45 shows the typical application of the DRV8847 device to drive a stepper motor.
1
16
15
14
IN1
IN2
nSLEEP
OUT1
2
3
330 mꢀ
MODE
ISEN12
OUT2
4
13
12
GND
VM
10 µF
0.1 µF
DRV8847
5
6
Stepper
Motor
OUT4
330 mꢀ
11
10
9
ISEN34
OUT3
TRQ
IN4
7
8
nFAULT
IN3
VEXT
(Logic Supply)
To Controller
图 45. Typical Application Schematic of Device Driving Stepper Motor
8.2.1.1 Design Requirements
表 22 lists design input parameters for system design.
表 22. Design Parameters
DESIGN PARAMETER
Motor supply voltage
REFERENCE
EXAMPLE VALUE
12 V
VM
RL
Motor winding resistance
Motor winding inductance
Motor RMS current
34 Ω/phase
33 mH/phase
350 mA
LL
IRMS
ITRIP
VTRIP
Target trip current
350 mA
Trip current reference voltage (internal voltage)
150 mV
48
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Current Regulation
The trip current (ITRIP) is the maximum current driven through either winding. The amount of this current depends
on the sense resistor value (RSENSExx) as shown in 公式 4 (Considering torque setting (TRQ) as 100%).
Torque ì VTRIP
RSENSExx
ITRIP
=
(4)
The ITRIP current is set by a comparator which compares the voltage across the RSENSExx resistor to a reference
voltage. To avoid saturation of the motor, the ITRIP current must be calculated as shown in 公式 5.
VVM
ITRIP
=
RL (W) + RDS(ON)_HS (W) + RDS(ON)_LS (W) + RSENSExx (W)
where
•
•
•
VVM is the motor supply voltage.
RL is the motor winding resistance.
RDS(ON)_HS and RDS(ON)_LS are the high-side and low-side on-state resistance of the FET.
(5)
(6)
For an ITRIP value of 350 mA, the value of the sense resistor (RSENSExx) is calculated as shown in 公式 6.
VTRIP
150 mV
RSENSE12 = RSENSE34
=
=
= 428.6 mW
ITRIP
350 mA
Select the closest available value of 440 mΩ for the sense resistors. Selecting this value will effect the current
accuracy by 2.8%.
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8.2.1.3 Application Curves
图 46. Device Power-up with Supply Voltage (VM)
图 47. Device Power-up with nSLEEP
图 48. Stepper Motor Full-Step Operation
图 49. Stepper Motor Half-Step Operation With Off-State as
Hi-Z
图 50. Stepper Motor Half-Step Operation With Off-State as
图 51. Brushed DC Motor Operation in Parallel Mode
Brake
Showing Current Regulation at 2-A
50
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图 52. Zoomed Waveform Showing Current Regulation
图 53. Torque Pin Functionality for Current Scaling
图 54. Undervoltage Lockout Operation
图 55. Open Load Detect Operation
图 56. Over Current Protection and Recovery
图 57. Zoomed Waveform of Over Current Protection
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8.2.2 Dual BDC Motor Application
图 58 shows the typical application of DRV8847 device to drive dual BDC motors.
1
16
15
14
IN1
IN2
nSLEEP
OUT1
2
3
330 mꢀ
MODE
BDC
ISEN12
OUT2
4
13
12
GND
VM
10 µF
0.1 µF
DRV8847
5
6
OUT4
330 mꢀ
11
10
9
BDC
ISEN34
OUT3
TRQ
IN4
7
8
nFAULT
IN3
VEXT
(Logic Supply)
To Controller
图 58. Typical Application Schematic of Device Driving Two BDC Motors
8.2.2.1 Design Requirements
表 23 lists the design input parameters for system design.
表 23. Design Parameters
DESIGN PARAMETER
Motor supply voltage
REFERENCE
EXAMPLE VALUE
12 V
VM
RL
Motor winding resistance
Motor winding inductance
Motor RMS current
13.2 Ω
LL
500 µH
IRMS
ISTART
ITRIP
VTRIP
490 mA
900 mA
1.2 A
Motor start-up current
Target trip current
Trip current reference voltage (internal voltage)
150 mV
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Motor Voltage
The motor voltage used in an application depends on the rating of the selected motor and the desired revolutions
per minute (RPM). A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to
the power FETs. A higher voltage also increases the rate of current change through the inductive motor
windings.
8.2.2.2.2 Current Regulation
The trip current (ITRIP) is the maximum current driven through either winding. Because the peak current (start
current) of the motor is 900 mA, the ITRIP current level is selected to be just greater than the peak current. The
selected ITRIP value for this example is 1.2 A. Therefore, use 公式 7 to select the value of the sense resistors
(RSENSE12 and RSENSE34) connected to the ISEN12 and ISEN34 pins.
VTRIP
150 mV
RSENSE12 = RSENSE34
=
=
= 125 mW
ITRIP
1.2 A
(7)
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8.2.2.2.3 Sense Resistor
For optimal performance, the sense resistor must:
•
•
•
•
Be a surface mount component
Have low inductance
Be rated for high enough power
Be placed closely to the motor driver
2
The power dissipated by the sense resistor equals IRMS × R. In this example, the peak current is 900 mA, the
RMS motor current is 490 mA, and the sense resistor value is 125 mΩ. Therefore, the sense resistors (RSENSE12
and RSENSE34) dissipate 30 mW (490 mA2 × 125 mΩ = 30 mW). The power quickly increases with higher current
levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a printed circuit board (PCB) is shared with other components generating
heat, margin should be added. For best practice, measure the actual sense resistor temperature in a final
system, along with the power MOSFETs, because those components are often the hottest.
Because power resistors are larger and more expensive than standard resistors, the common practice is to use
multiple standard resistors in parallel, between the sense node and ground. This practice distributes the current
and heat dissipation.
8.2.3 Open Load Implementation
This section presents the open load detection circuit and the operation. The open load detection diagnostic test
runs during the device power up or when the DRV8847 device comes out from sleep mode. In the I2C variant
device (DRV8847S), the OLD diagnostic test can run any instant of time using the I2C register bits.
8.2.3.1 Open Load Detection Circuit
OLD circuit consists of four main components i.e. current source (and current sink), series sequencing switches
(sequenced by the digital core), resistors and comparators. For ground (GND) connected load, the current
source (IOL_PU) pulls up the OUTx node to internal regulator voltage (AVDD) and allows the current to flow from
internal regulator voltage (AVDD) to ground via the connected load as shown in 图 59. Moreover, for the supply
(VM) connected load, the current sink (IOL_PD) pulls down the current from supply voltage (VM) to ground via the
connected load as shown in 图 61. The resistance of the load connected at the OUTx terminal will change the
source / sink current and indirectly the voltage drop across two resistors (12-kΩ and 15-kΩ). This voltage drop
across resistors is compared with the reference voltage (VOL_HS and VOL_LS) by the internal comparators to give
the output as OL1_HS and OL1_LS. This comparator output is fed to the open load digital circuit to determine
the open load condition.
注
Following are the values of various parameter shown above: AVDD voltage = 4.2-V, IOL_PU
= 200-µA, IOL_PD = 230-µA, VOL_HS = 2.3-V, VOL_LS = 1.2-V.
Note that the values taken above are at the typical condition of supply voltage and
temperature. Refer to "Typical Characteristics" section in Specifications for detailed
specifications.
8.2.3.2 OLD for Ground Connected Load
图 59 shows the ground connected load with internal OLD circuit. When high-side open load sequence is
activated (i.e. SW1_HS is on and SW1_LS is off), the current source (IOL_PU) pulls up the OUT1 node to internal
regulator voltage (AVDD) and current flows from internal regulator voltage (AVDD) to ground via the connected
load (RL). Now, depending upon if the load is present or not, there can be three cases as follows:
8.2.3.2.1 Half Bridge Open
If no-load is connected at the OUT1, then no current flows from AVDD. This pulls up the positive terminal of
OL1_HS comparator to 4.2-V (AVDD). This if compared with 2.3-V (VOL_HS) sets the comparator output to "1",
which signifies an open load detect.
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AVDD
VM
SW1_HS
œ
12 kΩ
VOL_HS
+
OL1_HS
X
IOL_PU
OUT1
SW1_LS
OLD1
IOL_PD
X
RL
X
œ
+
OL1_LS
VOL_LS
15 kΩ
图 59. Open Load Detect Circuit for Load Connected to Ground (GND)
8.2.3.2.2 Half Bridge Short
If OUT1 pin is shorted to ground, then pull-up current of 200-µA (IOL_PU) flows from AVDD. Due to this, there is a
voltage drop at the positive terminal of OL1_HS comparator as:
VOL1_HS + = V
( )
-IOL _PU ì12kW
AVDD
(8)
Using 公式 8, the VOL1_HS(+) is calculated as shown in 公式 9,
VOL1_HS + = 4.2V - 200mA ì12kW = 1.8V
( )
(9)
This voltage, if compared with 2.3-V (VOL_HS) reset the OL1_HS comparator output to "0", which signifies a no
open load detect.
8.2.3.2.3 Load Connected
If a resistive load (RL) is connected between OUT1 and GND, then current flowing from AVDD depends on load
reistance (RL) as:
VAVDD
ILOAD
=
RL +12kW
(10)
Now, if the voltage drop at positive terminal of OL1_HS comparator is higher than 2.3-V (VOL_HS), the comparator
sets output to "1" showing as open load. Hence, the voltage required to trip the OL1_HS comparator is
calculated as:
VOL _HS < VAVDD -ILOAD ì12kW
(11)
By putting 公式 10 to 公式 11,
VAVDD ì12kW
VOL _HS < VAVDD
-
RL +12kW
(12)
By solving 公式 12, the load resistance (RL) is expressed as,
VAVDD ì12kW
RL >
-12kW
VAVDD - VOL _HS
(13)
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By putting the values of VAVDD and VOL_HS in 公式 13, the load resistance (RL) is calculated as 14.52-kΩ. Hence,
any resisitive load connected between OUTx and GND above this value is shown as an open-load.
注
The values of these parameters are taken for a typical case for understanding. These
parameters changes with supply voltage and temperature. User has to consider a design
margin based on the above calculations.
17
16
15
14
13
12
TA = -40°C
TA = 25°C
TA = 85°C
11
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
D001
图 60. Resistance Threshold's for Open Load Detect in Ground (GND) Connected Load
8.2.3.3 OLD for Supply (VM) Connected Load
图 61 shows the supply (VM) connected load with internal OLD circuit. When low-side open load sequence is
activated (i.e. SW1_HS is off and SW1_LS is on), the current sink (IOL_PD) pulls down the OUT1 node to supply
voltage (VVM) and current flows from supply (VM) to ground via the connected load (RL). Now, depending upon if
the load is present or not, there can be three cases as follows:
VM
AVDD
VM
SW1_HS
œ
12 kΩ
VOL_HS
RL
+
OL1_HS
X
X
IOL_PU
X
OUT1
SW1_LS
OLD1
IOL_PD
œ
+
OL1_LS
VOL_LS
15 kΩ
图 61. Open Load Detect Circuit for Load Connected to Supply Voltage (VM)
8.2.3.3.1 Half Bridge Open
If no-load is connected at the OUT1, then no current flows from supply (VM). This pulls down the negative
terminal of OL1_LS comparator to 0-V (GND). This if compared with 1.2-V (VOL_LS) sets the comparator output to
"1", which signifies an open load detect.
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8.2.3.3.2 Half Bridge Short
If OUT1 pin is shorted to supply (VM), then pull-down current of 230-µA (IOL_LS) flows from supply (VM). Due to
this, there is a voltage drop at the negative terminal of OL1_LS comparator as:
VOL1_LS - = IOL _PD ì15kW
( )
(14)
Using 公式 14, the VOL1_LS(-) is calculated as shown in 公式 15,
VOL1_LS - = 230mA ì15kW = 3.45V
( )
(15)
This voltage, if compared with 1.2-V (VOL_LS) reset the OL1_LS comparator output to "0", signifying a no open
load detect.
8.2.3.3.3 Load Connected
If a resistive load (RL) is connected between OUT1 and VM, then current flowing from supply (VM) is as:
VVM
ILOAD
=
RL +15kW
(16)
Now, if the voltage drop at negative terminal of OL1_LS comparator is lower than 1.2-V (VOL_LS), the comparator
sets output to "1" showing open load. Hence, the voltage required to trip OL1_LS comparator is calculated as:
VOL _LS > ILOAD ì15kW
(17)
By putting 公式 16 to 公式 17,
VVM ì15kW
VOL _LS
>
RL +15kW
(18)
By solving 公式 18, the load resistance (RL) is expressed as,
VVM ì15kW
VOL _LS
RL >
-15kW
(19)
By putting the values of VVM and VOL_HS in 公式 19, the load resistance (RL) is calculated as 135-kΩ for supply
voltage (VVM) of 12-V. Hence, any resistive load connected between VM and OUTx above this value (at VVM
12-V) is shown as an open-load.
=
250
200
150
100
50
TA = -40°C
TA = 25°C
TA = 85°C
0
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
D002
图 62. Resistance Threshold's for Open Load Detect in Supply (VM) Connected Load
注
In the open load detection for load connected to supply (VM) configuration, the resistive
load threshold for an open load also depends on the supply voltage (VVM).
56
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ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
8.2.3.4 OLD for Full Bridge Connected Load
图 63 shows the load connected as a full bridge configuration with internal OLD circuit. Full-bridge open load
sequence consists of turning-on the high-side switch (SW1_HS) of half-bridge-1 and low-side switch (SW2_LS)
of half-bridge-2 together. In a similar manner, the full-bridge open-load sequence for the other half bridge with
turning-on the high-side switch (SW2_HS) of half-bridge-2 and low-side switch (SW1_LS) of half-bridge-1
together is executed. Now, depending on the load presence, three cases are considered:
8.2.3.4.1 Full Bridge Open
If no-load is connected between the OUT1 and OUT2 terminals, then no current flows from internal regulator
(AVDD). Now, the voltage-drop at the positive terminal of high side comparator of half-bridge-1 (OL1_HS) and
the negative terminal of low side comparator of half-bridge-2 (OL2_LS) will be as follows:
8.2.3.4.1.1 High side comparator of half-bridge-1 (OL1_HS)
Since no current is flowing from the internal regulator (AVDD), the voltage at the OUT1 node (which is also the
positive terminal of OL1_HS comparator) is clamped to 4.2-V (i.e. AVDD). This if compared with 2.3-V (VOL_HS
)
sets the comparator output to "1".
8.2.3.4.1.2 Low side comparator of half-bridge-2 (OL2_LS)
For an open load condition, no current flows through the SW2_LS switch, which pulls down the negative terminal
of OL2_LS comparator to 0-V (GND). This if compared with 1.2-V (VOL_LS) sets the comparator output to "1".
Now, if both the comparator outputs (OL1_HS and OL2_LS) is high, it signifies an open load.
8.2.3.4.2 Full Bridge Short
If there is short between the OUT1 and OUT2 terminals, then a short current (ISC) will flows from internal
regulator (AVDD) depending upon the high-side (12-kΩ) and low-side (15-kΩ) resistors as,
VAVDD
VAVDD
ISC
=
=
15kW +12kW 27kW
(20)
Hence the short-current flowing using 公式 20 is calculated as,
VAVDD
4.2V
ISC
=
=
= 155.56mA
27kW 27kW
(21)
Now, the voltage-drop at the positive terminal of high side comparator of half-bridge-1 (OL1_HS) and the
negative terminal of low side comparator of half-bridge-2 (OL2_LS) will be as follows:
8.2.3.4.2.1 High side comparator of half-bridge-1 (OL1_HS)
Now, the pull up current of ISC (155.56-µA) is flowing from the internal regulator (AVDD), therefore the voltage at
the positive terminal of OL1_HS comparator (which is also the OUT1 node) is calculated as,
VOL1_HS + = V
( )
-ISC ì12kW
AVDD
(22)
using 公式 22, the VOL1_HS(+) is calculated as,
VOL1_HS + = 4.2V -155.56mA ì12kW = 2.33V
( )
(23)
This voltage, if compared with 2.3-V (VOL_HS) sets the OL1_HS comparator output to "1".
8.2.3.4.2.2 Low side comparator of half-bridge-2 (OL2_LS)
The pull down current of ISC (155.56-µA) is flowing from the internal regulator (AVDD) to the SW2_LS switch,
therefore the voltage at the negative terminal of OL2_LS comparator is calculated as,
VOL2_LS + = ISC ì15kW
( )
(24)
Using 公式 24, the VOL2_LS is calculated as,
版权 © 2018–2019, Texas Instruments Incorporated
57
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ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
VOL2_LS + = 155.56mA ì15kW = 2.33V
( )
(25)
This voltage, if compared with 1.2-V (VOL_LS) reset the OL2_LS comparator output to "0".
Since, OL1_HS comparator shows an output "1" and OL2_LS comparator shows and output "0", therefore this
case is considered as no-open load.
AVDD
VM
SW1_HS
œ
12 kΩ
VOL_HS
+
OL1_HS
X
X
IOL_PU
OUT1
SW1_LS
OLD1
IOL_PD
X
œ
+
OL1_LS
VOL_LS
15 kΩ
AVDD
VM
SW2_HS
œ
12 kΩ
VOL_HS
+
OL2_HS
X
IOL_PU
X
OUT2
SW2_LS
OLD2
IOL_PD
X
œ
+
OL2_LS
VOL_LS
15 kΩ
图 63. Open Load Detect Circuit for Motor Connected in Full Bridge Configuration
8.2.3.4.3 Load Connected in Full Bridge
If there is a load (RL) connected between the OUT1 and OUT2 terminals, then a load current (IL) is calculated as,
VAVDD VAVDD
12kW + RL +15kW RL + 27kW
ILOAD
=
=
(26)
Now, the voltage-drop at the positive terminal of high side comparator of half-bridge-1 (OL1_HS) and the
negative terminal of low side comparator of half-bridge-2 (OL2_LS) will be as follows:
58
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ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
8.2.3.4.3.1 High side comparator of half-bridge-1 (OL1_HS)
If the voltage drop at positive terminal of OL1_HS comparator is higher than 2.3-V (VOL_HS), the comparator sets
output to "1" (for open load). Hence, the voltage required to trip the OL1_HS comparator is calculated as:
VOL _HS < VAVDD -ILOAD ì12kW
(27)
By putting 公式 26 into 公式 27,
VAVDD ì12kW
VOL < VAVDD
-
HS
RL + 27kW
(28)
By solving 公式 28, the load resistance (RL) is expressed as,
VAVDD ì12kW
RL >
- 27kW
VAVDD - VOL _HS
(29)
By putting the values of VAVDD and VOL_HS in 公式 29, the load resistance (RL) is calculated as (-)10.2-kΩ. Since,
the value of resistance is negative, therefore, the voltage at positive terminal of OL1_HS comparator is always
higher than VOL_HS and comparator output is always high ("1").
8.2.3.4.3.2 Low side comparator of half-bridge-2 (OL2_LS)
If the voltage drop at negative terminal of OL2_LS comparator is lower than 1.2-V (VOL_LS), the comparator sets
output to "1" showing as open load. Hence, the voltage required to trip the OL2_LS comparator is calculated as:
VOL _LS > ILOAD ì15kW
(30)
By putting 公式 26 to 公式 30,
VAVDD ì15kW
VOL _LS
=
RL + 27kW
(31)
By solving 公式 31, the load resistance (RL) is expressed as,
VAVDD ì15kW
VOL _LS
RL >
- 27kW
(32)
By putting the values of VAVDD and VOL_LS in 公式 32, the load resistance (RL) is calculated as 25.5-kΩ.
Therefore, the output of OL2_HS comparator sets to 1, if the load resistance is greater than 25.5-kΩ.
Since, the OL1_HS comparator always outputs "1", therefore, the open load status is solely dependent on the
output of OL2_HS comparator. If OL2_HS comparator output is "1", then an open load is detected.
37.5
TA = -40°C
TA = 25°C
TA = 85°C
35
32.5
30
27.5
25
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
D003
图 64. Resistance Threshold's for Open Load Detect for Load Connected in Full-Bridge Configuration
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59
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ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
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9 Power Supply Recommendations
The DRV8847 device is designed to operate from an input voltage supply (VVM) range from 2.7 V to 18 V. Place
a 0.1-µF ceramic capacitor rated for VM as close to the DRV8847 device as possible. In addition, a bulk
capacitor with a value of at least 10 µF must be included on the VM pin.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. The amount of bulk capacitance
depends on a variety of factors including:
•
•
•
•
•
•
Type of power supply
Acceptable supply voltage ripple
Parasitic inductance in the power supply wiring
Type of motor (brushed DC, brushless DC, stepper)
Motor start-up current
Motor braking method
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet provides a recommended minimum value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图 65. Setup of Motor Drive System With External Power Supply
60
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DRV8847
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ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
10 Layout
10.1 Layout Guidelines
Bypass the VM pin to ground using a low-ESR ceramic bypass capacitor with a recommended value of 10 μF
and rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
10.2 Layout Example
I1N61
I1N52
nSLEEP
OUT1
MOD1E4/SDA
G1N3D
ISEN12
4
OUT2
V1M2
5
OUT4
TRQ1/1SCL
IN104
6
SEN34
7
OUT3
IN3
8
nFAULT
图 66. Layout Recommendation of 16-Pin TSSOP Package for Single-Layer Board
I1N61
I1N52
nSLEEP
OUT1
MO14DE
G1N3D
V1M2
ISEN12
4
OUT2
5
OUT4
T1R1Q
IN104
6
SEN34
7
OUT3
IN3
8
nFAULT
图 67. Layout Recommendation of 16-Pin HTSSOP Package for Double-Layer Board
版权 © 2018–2019, Texas Instruments Incorporated
61
DRV8847
ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Layout Example (接下页)
MODE
ISEN12
GND
VM
OUT2
OUT4
TRQ
ISEN34
图 68. Layout Recommendation of 16-Pin QFN Package for Double-Layer Board
62
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DRV8847
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ZHCSID2B –JULY 2018–REVISED SEPTEMBER 2019
10.3 Thermal Considerations
10.3.1 Maximum Output Current
In actual operation, the maximum output current that is achievable with a motor driver is a function of the die
temperature. This die temperature is greatly affected by ambient temperature and PCB design. Essentially, the
maximum motor current is the amount of current that results in a power dissipation level that, along with the
thermal resistance of the package and PCB, keeps the die at a low enough temperature to avoid thermal
shutdown.
The dissipation ratings given in the data sheet can be used as a guide to calculate the approximate maximum
power dissipation that can be expected without putting the device in thermal shutdown for several different PCB
constructions. However, for accurate data, the actual PCB design must be analyzed through measurement or
thermal simulation.
10.3.2 Thermal Protection
The DRV8847 device has thermal shutdown (TSD) as described in the Maximum Output Current section. If the
die temperature exceeds approximately 150°C, the device is disabled until the temperature decreases 40°C.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heat-
sinking, or too high an ambient temperature.
10.4 Power Dissipation
Power dissipation in the DRV8847 device is dominated by the DC power dissipated in the output FET resistance
(RDS(ON)_HS and RDS(ON)_LS). Additional power is dissipated because of PWM switching losses. These losses are
dependent on the PWM frequency, rise and fall times, and VM supply voltages. These switching losses are
typically on the order of 10% to 30% of the DC power dissipation.
Use 公式 33 to estimate the DC power dissipation of one H-bridge.
2
PTOT = RDS(ON)_LS ì IOUT(RMS)2 +RDS(ON)_HS ì IOUT(rms)
where
•
•
•
PTOT is the total power dissipation
IOUT(RMS) is the RMS output current being applied to motor
RDS(ON)_HS and RDS(ON)_LS are the high-side and low-side on-state resistance of the FET
(33)
注
The value of RDS(ON)_HS and RDS(ON)_LS increases with temperature. Therefore, as the
device heats, the power dissipation increases. This relationship must be considered when
sizing the heat-sink.
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63
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
德州仪器 (TI)，《DRV8847EVM 用户指南》
德州仪器 (TI)，《DRV8847EVM 和 DRV8847SEVM 软件用户指南》
德州仪器 (TI)， 《大型电器中的小型电机》TI 技术手册
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
64
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8847PWPR
DRV8847PWR
DRV8847RTER
DRV8847RTET
DRV8847SPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
TSSOP
WQFN
PWP
PW
16
16
16
16
16
2000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
8847PWP
NIPDAU
NIPDAU
NIPDAU
NIPDAU
8847PW
8847
RTE
RTE
PW
WQFN
250
RoHS & Green
8847
TSSOP
2000 RoHS & Green
8847SPW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8847PWPR
DRV8847PWR
DRV8847RTER
DRV8847RTET
DRV8847SPWR
HTSSOP PWP
16
16
16
16
16
2000
2000
3000
250
330.0
330.0
330.0
180.0
330.0
12.4
12.4
12.4
12.4
12.4
6.9
6.9
3.3
3.3
6.9
5.6
5.6
3.3
3.3
5.6
1.6
1.6
1.1
1.1
1.6
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q2
Q2
Q1
TSSOP
WQFN
WQFN
TSSOP
PW
RTE
RTE
PW
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8847PWPR
DRV8847PWR
DRV8847RTER
DRV8847RTET
DRV8847SPWR
HTSSOP
TSSOP
WQFN
PWP
PW
16
16
16
16
16
2000
2000
3000
250
356.0
356.0
367.0
210.0
356.0
356.0
356.0
367.0
185.0
356.0
35.0
35.0
35.0
35.0
35.0
RTE
RTE
PW
WQFN
TSSOP
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PWP0016C
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
6.6
6.2
C
TYP
A
PIN 1 INDEX
AREA
0.1 C
SEATING
PLANE
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
B
0.19
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
4X (0.3)
8
9
2X 0.23 MAX
NOTE 5
2.31
1.75
17
0.25
GAGE PLANE
1.2 MAX
0.15
0.05
0.75
0.50
0 -8
16
1
A
20
DETAIL A
TYPICAL
THERMAL
PAD
2.46
1.75
4224559/B 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.46)
16X (1.5)
METAL COVERED
BY SOLDER MASK
SYMM
1
16X (0.45)
16
(1.2) TYP
(2.31)
(R0.05) TYP
SYMM
17
(5)
NOTE 9
(0.6)
14X (0.65)
(
0.2) TYP
VIA
9
8
SOLDER MASK
DEFINED PAD
(1) TYP
SEE DETAILS
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4224559/B 01/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.46)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
METAL COVERED
BY SOLDER MASK
1
16
16X (0.45)
(R0.05) TYP
SYMM
(2.31)
17
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.75 X 2.58
2.46 X 2.31 (SHOWN)
2.25 X 2.11
0.125
0.15
0.175
2.08 X 1.95
4224559/B 01/2019
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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