DRV8872DDARQ1 [TI]
具有故障报告和电流调节功能的汽车类 50V、3.6A、H 桥电机驱动器 | DDA | 8 | -40 to 125;
| 型号： | DRV8872DDARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有故障报告和电流调节功能的汽车类 50V、3.6A、H 桥电机驱动器 | DDA | 8 | -40 to 125 电机 驱动 驱动器 |
| 文件： | 总23页 (文件大小：1528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
DRV8872-Q1 汽车类具有故障报告功能的 3.6A 刷式直流电机驱动器
1 特性
2 应用范围
1
•
符合汽车类应用的 AEC-Q100 标准：
•
•
•
•
车用信息娱乐
HUD 投影仪调整
电动移位旋钮
–
–
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
2
压电警报驱动器
3 说明
器件组件充电模式 (CDM) ESD 分类等级 C4B
•
H 桥电机驱动器
DRV8872-Q1 器件是一款刷式直流 (BDC) 电机驱动
器，适用于信息娱乐系统、HUD 投影仪调整、电动移
位器旋钮和压电警报驱动器。两个逻辑输入控制 H 桥
驱动器，该驱动器由四个 N 沟道金属氧化物半导体场
效应晶体管 (MOSFET) 组成，能够以高达 3.6A 的峰
值电流执行双向电机控制。利用电流衰减模式，可通过
对输入进行脉宽调制 (PWM) 来控制电机转速。如果将
两个输入均置为低电平，则电机驱动器将进入低功耗休
眠模式。
–
驱动一个直流电机、一个步进电机的绕组或其他
负载
•
•
•
•
•
•
•
•
6.8V 至 45V 宽工作电压范围
565mΩ（典型值）RDS(on) (HS + LS)
3.6A 峰值电流驱动能力
脉宽调制 (PWM) 控制接口
集成电流调节功能
低功耗休眠模式
故障状态输出引脚
DRV8872-Q1 器件 具备 集成电流调节功能。该功能基
于内部基准电压以及 ISEN 引脚电压（与流经外部感测
电阻的电机电流成正比）。该器件能够将电流限制在某
一已知水平，这可显著降低系统功耗要求，并且无需大
容量电容来维持稳定电压，尤其是在电机启动和停转
时。
小型封装尺寸
–
–
8 引脚 HSOP 封装，带有 PowerPAD™
4.9mm × 6mm
•
集成保护 功能
–
–
–
–
–
VM 欠压闭锁 (UVLO)
过流保护 (OCP)
热关断 (TSD)
该器件针对故障和短路问题提供了全面保护，包括欠压
锁定 (UVLO)、过流保护 (OCP) 和热关断 (TSD)。通
过将 nFAULT 输出拉为低电平来报告故障。故障排除
后，器件自动恢复正常状态。
故障报告 (nFAULT)
自动故障恢复
器件信息(1)
器件型号
封装
HSOP (8)
封装尺寸（标称值）
DRV8872-Q1
4.90mm x 6.00mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
H 桥状态
简化电路原理图
6.8 to 45 V
DRV8872-Q1
3.6 A
IN1
IN2
Brushed DC
Motor Driver
BDC
Controller
Current
Regulation
nFAULT
ISEN
Fault
Protection and
Reporting
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS175
DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
Power Supply Recommendations...................... 14
9.1 Bulk Capacitance .................................................... 14
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 10
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations....................................... 15
10.4 Power Dissipation ................................................. 15
11 器件和文档支持 ..................................................... 17
11.1 文档支持................................................................ 17
11.2 接收文档更新通知 ................................................. 17
11.3 社区资源................................................................ 17
11.4 商标....................................................................... 17
11.5 静电放电警告......................................................... 17
11.6 Glossary................................................................ 17
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2016 年 11 月
*
最初发布。
2
Copyright © 2016, Texas Instruments Incorporated
DRV8872-Q1
www.ti.com.cn
ZHCSFQ0 –NOVEMBER 2016
5 Pin Configuration and Functions
DDA Package
8-Pin HSOP With Exposed Thermal Pad
Top View
GND
IN2
1
2
3
4
8
7
6
5
OUT2
ISEN
OUT1
VM
Thermal
Pad
IN1
nFAULT
Pin Functions
PIN
TYPE
PWR
I
DESCRIPTION
Connect to board ground.
NAME
GND
NO.
1
Logic ground
Logic inputs
IN1
IN2
3
Controls the H-bridge output. Has internal pulldowns. (See 表 1.)
2
If using current regulation, connect ISEN to a resistor (low-value,
ISEN
7
PWR
High-current ground path high-power-rating) to ground. If not using current regulation, connect
ISEN directly to ground.
Low-level indicates UVLO, TSD, or OCP fault. Connect to a pullup
nFAULT
4
OD
O
Fault status (open-drain)
resistor.
OUT1
OUT2
6
8
H-bridge outputs
Connect directly to the motor, or other inductive load.
6.8-V to 45-V power
supply
Connect a 0.1-µF bypass capacitor to ground, as well as sufficient
bulk capacitance, rated for the VM voltage.
VM
5
PWR
Connect to board ground. For good thermal dissipation, use large
ground planes on multiple layers, and multiple nearby vias
connecting those planes.
PAD
—
—
Thermal pad
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.7
–0.5
MAX
UNIT
V
Power supply voltage (VM)
50
Logic input voltage (IN1, IN2)
7
6
V
Fault pin (nFAULT)
V
Continuous phase node pin voltage (OUT1, OUT2)
Current sense input pin voltage (ISEN)(2)
Output current (100% duty cycle)
Operating junction temperature, TJ
Storage temperature, Tstg
VM + 0.7
1
V
V
3.5
A
–40
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable
Copyright © 2016, Texas Instruments Incorporated
3
DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Electrostatic
V(ESD)
All pins
Corner pins (1, 4, 5, and 8)
V
Charged-device model (CDM), per AEC
Q100-011
discharge
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6.8
0
NOM
MAX
45
UNIT
V
VM
VI
Power supply voltage
Logic input voltage (IN1, IN2)
Logic input PWM frequency (IN1, IN2)
Peak output current(2)
5.5
200(1)
V
fPWM
Ipeak
TA
0
kHz
A
0
3.6
Operating ambient temperature
–40
125
°C
(1) The voltages applied to the inputs should have at least 800 ns of pulse width to ensure detection. Typical devices require at least 400
ns. If the PWM frequency is 200 kHz, the usable duty cycle range is 16% to 84%
(2) Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8872-Q1
(1)
THERMAL METRIC
DDA (HSOP)
8 PINS
41.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
53.7
12.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3
ψJB
12.6
RθJC(bot)
2.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
4
Copyright © 2016, Texas Instruments Incorporated
DRV8872-Q1
www.ti.com.cn
ZHCSFQ0 –NOVEMBER 2016
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 24 V
PARAMETER
POWER SUPPLY (VM)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVM
VM operating voltage
VM operating supply current
VM sleep current
6.8
45
10
13
50
V
IVM
3
mA
µA
µs
IVMSLEEP
tON
VM = 12 V
Turnon time(1)
VM > VUVLO with IN1 or IN2 high
40
LOGIC-LEVEL INPUTS (IN1, IN2)
VIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
0.5
V
V
VIH
VHYS
IIL
1.6
–1
0.5
V
VIN = 0 V
1
μA
μA
kΩ
μs
ms
IIH
VIN = 3.3 V
33
100
0.7
1
100
RPD
tPD
To GND
INx to OUTx change (see 图 6)
Inputs low to sleep
1
tsleep
Time to sleep
1.5
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
RDS(ON)
RDS(ON)
tDEAD
Vd
High-side FET on resistance
Low-side FET on resistance
Output dead time
VM = 24 V, I = 1 A, fPWM = 25 kHz
VM = 24 V, I = 1 A, fPWM = 25 kHz
307
258
250
0.8
610
500
mΩ
mΩ
ns
Body diode forward voltage
IOUT = 1 A
1
V
CURRENT REGULATION
ISEN voltage for current
chopping
VTRIP
0.32
0.35
0.38
V
tOFF
PWM off-time
PWM blanking time
25
2
μs
tBLANK
µs
PROTECTION CIRCUITS
VM falls until UVLO triggers
VM rises until operation recovers
Rising to falling threshold
6.3
6.4
6.5
6.7
VUVLO
VM undervoltage lockout
V
VUV,HYS
IOCP
VM undervoltage hysteresis
100
3.7
180
mV
A
Overcurrent protection trip
level
4.5
6.6
tOCP
Overcurrent deglitch time
Overcurrent retry time
2
3
μs
tRETRY
ms
Thermal shutdown
temperature(2)
TSD
155
180
40
°C
°C
Thermal shutdown
hysteresis(2)
THYS
nFAULT OPEN DRAIN OUTPUT
VOL
IOH
Output low voltage
IO = 5 mA
VO = 3.3 V
0.5
1
V
Output high leakage current
µA
(1) tON applies when the device initially powers up, and when it exits sleep mode.
(2) Ensured by design
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5
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ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
6.6 Typical Characteristics
0.37
0.36
0.35
0.34
0.33
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Ambient Temperature (èC)
D003
D001
图 2. VTRIP vs Temperature
图 1. RDS(on) vs Temperature
10
8
6
4
2
0
0
5
10
15
20
25
30
35
40
45
VM (V)
D004
图 3. IVMSLEEP vs VM at 25°C
6
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DRV8872-Q1
www.ti.com.cn
ZHCSFQ0 –NOVEMBER 2016
7 Detailed Description
7.1 Overview
The DRV8872-Q1 device is an optimized 8-pin device for driving brushed DC motors with 6.8 to 45 V and up to
3.6-A peak current. The integrated current regulation restricts motor current to a predefined maximum. Two logic
inputs control the H-bridge driver, which consists of four N-channel MOSFETs that have a typical Rds(on) of 565
mΩ (including one high-side and one low-side FET). A single power input, VM, serves as both device power and
the motor winding bias voltage. The integrated charge pump of the device boosts VM internally and fully
enhances the high-side FETs. Motor speed can be controlled with pulse-width modulation, at frequencies
between 0 to 200 kHz. The device has an integrated sleep mode that is entered by bringing both inputs low. An
assortment of protection features prevent the device from being damaged if a system fault occurs.
7.2 Functional Block Diagram
Power
VCP
VM
VCP
VM
VM
Charge
Pump
OUT1
Gate
Driver
bulk
0.1 µF
OCP
GND
BDC
PPAD
VCP
VM
OUT2
ISEN
IN1
IN2
Gate
Driver
Core
Logic
OCP
RSENSE
+
nFAULT
œ
VTRIP
Protection Features
Overcurrent
Monitoring
Temperature
Sensor
Voltage
Monitoring
Copyright © 2016, Texas Instruments Incorporated
版权 © 2016, Texas Instruments Incorporated
7
DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
7.3 Feature Description
7.3.1 Bridge Control
The DRV8872-Q1 output consists of four N-channel MOSFETs that are designed to drive high current. These
MOSFETs are controlled by the two logic inputs IN1 and IN2, according to 表 1.
表 1. H-Bridge Control
IN1
0
IN2
0
OUT1
OUT2
DESCRIPTION
Coast; H-bridge disabled to High-Z (sleep entered after 1 ms)
Reverse (current OUT2 → OUT1)
High-Z
High-Z
0
1
L
H
L
H
L
L
1
0
Forward (current OUT1 → OUT2)
1
1
Brake; low-side slow decay
The inputs can be set to static voltages for 100% duty-cycle drive, or they can be pulse-width modulated (PWM)
for variable motor speed. When using PWM, switching between driving and braking typically works best. For
example, to drive a motor forward with 50% of its max RPM, IN1 = 1 and IN2 = 0 during the driving period, and
IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current
decay is also available. The input pins can be powered before VM is applied.
VM
VM
1
2
3
1
2
3
Reverse drive
Forward drive
Slow decay (brake)
High-Z (coast)
Slow decay (brake)
High-Z (coast)
1
1
OUT1
OUT2
OUT1
OUT2
2
3
2
3
FORWARD
REVERSE
图 4. H-Bridge Current Paths
7.3.2 Sleep Mode
When IN1 and IN2 are both low for time tSLEEP (typically 1 ms), the DRV8872-Q1 device enters a low-power
sleep mode, where the outputs remain High-Z and the device uses IVMSLEEP (microamps) of current. If the device
is powered up while both inputs are low, sleep mode is immediately entered. After IN1 or IN2 are high for at least
5 µs, the device is operational 50 µs (tON) later.
7.3.3 Current Regulation
The DRV8872-Q1 device limits the output current based on the resistance of an external sense resistor on pin
ISEN, according to 公式 1.
8
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DRV8872-Q1
www.ti.com.cn
ZHCSFQ0 –NOVEMBER 2016
VTRIP (V)
0.35 (V)
ITRIP (A) =
=
RISEN (W) RISEN (W)
(1)
For example, if RISEN = 0.16 Ω, the DRV8872-Q1 device limits motor current to 2.2 A no matter how much load
torque is applied. For guidelines on selecting a sense resistor, see the Sense Resistor section.
When ITRIP has been reached, the device enforces slow current decay by enabling both low-side FETs, and it
does this for time tOFF (typically 25 µs).
ITRIP
tBLANK
tDRIVE
tOFF
图 5. Current Regulation Time Periods
After tOFF has elapsed, the output is re-enabled according to the two inputs INx. The drive time (tDRIVE) until
reaching another ITRIP event heavily depends on the VM voltage, the back-EMF of the motor, and the inductance
of the motor.
7.3.4 Dead Time
When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically
inserted to prevent shoot-through. tDEAD is the time in the middle when the output is High-Z. If the output pin is
measured during tDEAD, the voltage will depend on the direction of current. If current is leaving the pin, the
voltage is a diode drop below ground. If current is entering the pin, the voltage is a diode drop above VM. This
diode is the body diode of the high-side or low-side FET.
IN1
IN2
OUT1
tPD
tR
tDEAD
tPD
tF
tDEAD
OUT2
tPD
tF
tDEAD
tPD
tR
tDEAD
图 6. Propagation Delay Time
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DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
7.3.5 Protection Circuits
The DRV8872-Q1 device is fully protected against VM undervoltage, overcurrent, and overtemperature events.
When the device is in a protected state, nFAULT is driven low. When the fault condition is removed, nFAULT
becomes a high-impedance state.
7.3.5.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage-lockout threshold voltage, all FETs in the H-
bridge are disabled. Operation resumes when VM rises above the UVLO threshold.
7.3.5.2 Overcurrent Protection (OCP)
If the output current exceeds the OCP threshold IOCP for longer than tOCP, all FETs in the H-bridge are disabled
for a duration of tRETRY. After that, the H-bridge re-enables according to the state of the INx pins. If the
overcurrent fault is still present, the cycle repeats; otherwise normal device operation resumes.
7.3.5.3 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge is disabled. After the die temperature has
fallen to a safe level, operation automatically resumes.
表 2. Protection Functionality
FAULT
CONDITION
VM < VUVLO
IOUT > IOCP
TJ > 150°C
H-BRIDGE BECOMES
Disabled
NFAULT BECOMES
RECOVERY
VM > VUVLO
VM undervoltage lockout (UVLO)
Overcurrent (OCP)
Low
Low
Low
Disabled
Disabled
tRETRY
Thermal shutdown (TSD)
TJ < TSD - T HYS
7.4 Device Functional Modes
The DRV8872-Q1 device can be used in multiple ways to drive a brushed DC motor.
7.4.1 PWM With Current Regulation
This scheme uses all of the capabilities of the device. The ITRIP current is set above the normal operating current,
and high enough to achieve an adequate spin-up time, but low enough to constrain current to a desired level.
Motor speed is controlled by the duty cycle of one of the inputs, while the other input is static. Brake and slow
decay is typically used during the off-time.
7.4.2 PWM Without Current Regulation
If current regulation is not needed, the ISEN pin should be directly connected to the PCB ground plane. This
mode provides the highest possible peak current: up to 3.6 A for a few hundred milliseconds (depending on PCB
characteristics and the ambient temperature). If current exceeds 3.6 A, the device might reach overcurrent
protection (OCP) or over-temperature shutdown (TSD). If that occurs, the device disables and protects itself for
about 3 ms (tRETRY) and then resumes normal operation.
7.4.3 Static Inputs With Current Regulation
The IN1 and IN2 pins can be set high and low for 100% duty cycle drive, and ITRIP can be used to control the
current, speed, and torque capability of the motor.
7.4.4 VM Control
In some systems, varying VM as a means of changing motor speed is desirable. See the Motor Voltage section
for more information.
10
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DRV8872-Q1
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ZHCSFQ0 –NOVEMBER 2016
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8872-Q1 device is typically used to drive one brushed DC motor.
8.2 Typical Application
GND
OUT2
3.3 V
0.2 Ω
BDC
IN2
ISEN
OUT1
VM
DRV8872-Q1
PPAD
Controller
IN1
PU
nFAULT
+
6.8-V to 45-V
Power Supply
0.1 µF
47 µF
œ
Copyright © 2016, Texas Instruments Incorporated
图 7. Typical Connections
8.2.1 Design Requirements
表 3 lists the design parameters.
表 3. Design Parameters
DESIGN PARAMETER
REFERENCE
VM
EXAMPLE VALUE
Motor voltage
24 V
0.8 A
2 A
Motor RMS current
Motor startup current
Motor current trip point
Sense resistance
IRMS
ISTART
ITRIP
RISEN
fPWM
2.2 A
0.16 Ω
5 kHz
PWM frequency
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage used depends on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
8.2.2.2 Drive Current
The current path is through the high-side sourcing DMOS power driver, motor winding, and low-side sinking
DMOS power driver. Power dissipation losses in one source and sink DMOS power driver are shown in 公式 2.
PD = I2
R
+ RDS(on)Sink
DS(on)Source
(2)
11
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DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
The DRV8872-Q1 device has been measured to be capable of 2-A RMS current at 25°C on standard FR-4
PCBs. The maximum RMS current varies based on the PCB design, ambient temperature, and PWM frequency.
Typically, switching the inputs at 200 kHz compared to 20 kHz causes 20% more power loss in heat.
8.2.2.3 Sense Resistor
For optimal performance, the sense resistor must have the features that follow:
•
•
•
•
Surface-mount device
Low inductance
Rated for high enough power
Placed closely to the motor driver
2
The power dissipated by the sense resistor equals IRMS × R. For example, if peak motor current is 3 A, RMS
motor current is 1.5 A, and a 0.2-Ω sense resistor is used, the resistor dissipates 1.5 A2 × 0.2 Ω = 0.45 W. The
power quickly increases with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a PCB is shared with other components generating heat, the system
designer should add margin. It is always best to measure the actual sense resistor temperature in a final system.
Because power resistors are larger and more expensive than standard resistors, multiple standard resistors can
be used in parallel, between the sense node and ground. This configuration distributes the current and heat
dissipation.
8.2.3 Application Curves
图 8. Current Ramp With a 2-Ω, 1 mH,
图 9. Current Ramp With a 2-Ω, 1 mH,
RL Load and VM = 12 V
RL Load and VM = 24 V
12
版权 © 2016, Texas Instruments Incorporated
DRV8872-Q1
www.ti.com.cn
ZHCSFQ0 –NOVEMBER 2016
图 10. Current Ramp With a 2-Ω, 1 mH,
图 11. tPD
RL Load and VM = 45 V
图 12. Current Regulation With RSENSE = 0.26 Ω
图 13. OCP With 24 V and Outputs Shorted Together
版权 © 2016, Texas Instruments Incorporated
13
DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. More bulk
capacitance is generally beneficial but with the disadvantages of increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system limits the rate that the current can change
from the power supply. If the local bulk capacitance is too small, the system responds to excessive current
demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor
voltage remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VBB
+
Motor
Driver
+
œ
GND
Local
IC Bypass
Bulk Capacitor
Capacitor
图 14. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
14
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DRV8872-Q1
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ZHCSFQ0 –NOVEMBER 2016
10 Layout
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I2 × RDS(on) heat that is generated in the device.
图 15 shows the recommended layout and component placement.
10.2 Layout Example
GND
IN2
OUT2
ISEN
OUT1
VM
IN1
nFAULT
+
图 15. Layout Recommendation
10.3 Thermal Considerations
The DRV8872-Q1 device has thermal shutdown (TSD) as described in the Thermal Shutdown (TSD) section. If
the die temperature exceeds approximately 175°C, the device is disabled until the temperature drops below the
temperature hysteresis level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high of an ambient temperature.
10.4 Power Dissipation
Power dissipation in the DRV8872-Q1 device is dominated by the power dissipated in the output FET resistance,
RDS(on). Use 公式 2 from the Drive Current section to calculate the estimated average power dissipation of when
driving a load.
Note that at startup, the output current is much higher than normal running current; this peak current and its
duration must be also be considered.
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15
DRV8872-Q1
ZHCSFQ0 –NOVEMBER 2016
www.ti.com.cn
Power Dissipation (接下页)
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
注
RDS(on) increases with temperature, so as the device heats, the power dissipation
increases. This fact must be taken into consideration when sizing the heatsink.
The power dissipation of the DRV8872-Q1 is a function of RMS motor current and the FET resistance (RDS(ON)
)
of each output.
2
Power ö IRMS ì High-side RDS(ON) + Low-side RDS(ON)
(3)
For this example, the ambient temperature is 58°C, and the junction temperature reaches 80°C. At 58°C, the
sum of RDS(ON) is about 0.72 Ω. With an example motor current of 0.8 A, the dissipated power in the form of heat
is 0.8 A2 × 0.72 Ω = 0.46 W.
The temperature that the DRV8872-Q1 reaches depends on the thermal resistance to the air and PCB. Soldering
the device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers, is important to
dissipate heat into the PCB and reduce the device temperature. In the example used here, the DRV8872-Q1 had
an effective thermal resistance RθJA of 48°C/W, and a TJ value as shown in 公式 4.
TJ = TA + (PD ì RqJA ) = 58èC + (0.46 W ì 48èC/W) = 80èC
(4)
10.4.1 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane.
On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
For details about how to design the PCB, refer to the TI application report, PowerPAD™ Thermally Enhanced
Package (SLMA002), and the TI application brief, PowerPAD Made Easy™ (SLMA004), available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
16
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DRV8872-Q1
www.ti.com.cn
ZHCSFQ0 –NOVEMBER 2016
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
相关文档如下：
•
•
•
•
•
•
《电流再循环和衰减模式》（文献编号：SLVA321）
《计算电机驱动器功耗》（文献编号：SLVA504）
《使用 DRV8872-Q1 操纵电动进气栅格电机》（文献编号：SLVA858）
《PowerPAD™ 耐热增强型封装》（文献编号：SLMA002）
《PowerPAD™ 速成》（文献编号：SLMA004）
《了解电机驱动器电流额定值》（文献编号：SLVA505）
11.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8872DDARQ1
ACTIVE SO PowerPAD
DDA
8
2500 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-40 to 125
8872Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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