DRV8873-Q1 [TI]
具有集成电流感应和电流感应反馈功能的汽车类 40V、10A H 桥电机驱动器;
| 型号： | DRV8873-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电流感应和电流感应反馈功能的汽车类 40V、10A H 桥电机驱动器 电机 驱动 驱动器 |
| 文件： | 总60页 (文件大小：2321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8873-Q1
ZHCSIO5B –OCTOBER 2017 –REVISED JANUARY 2021
DRV8873-Q1 汽车类H 桥电机驱动器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
– 器件温度等级1：–40°C 至+125°C，TA
• N 沟道H 桥电机驱动器
DRV8873-Q1 器件是用于驱动汽车应用中的有刷直流
电机的集成式驱动器 IC。两个逻辑输入控制 H 桥驱动
器，该驱动器包含四个能够以高达 10A 的峰值电流双
向驱动电机的 N 沟道 MOSFET。该器件由单一电源供
电，支持4.5V 至38V 的宽输入电源电压范围。
– 可驱动一个双向有刷直流电机
– 两个单向有刷直流电机
– 电磁阀或其他电阻和电感负载
• 4.5V 至38V 工作电压范围
• 10A 峰值电流驱动能力
该器件可通过 PH/EN 或 PWM 接口轻松连接至控制器
电路。或者，可以使用独立的半桥控制来驱动两个电磁
阀负载。
• 低HS + LS RDS(ON)
集成电流检测提供与两个隐藏侧 FET 的电机负载电流
成比例的输出电流，无需大功率检测电阻。这种特性可
用于检测负载条件下的电机堵转或变化。
– TJ = 25°C 且电压为13.5V 时为150mΩ
– TJ = 150°C 且电压为13.5V 时为250mΩ
• 集成电流检测
• 成比例电流输出(IPROPI)
• 可配置控制接口
提供了低功耗睡眠模式，以通过关断大量内部电路来实
现超低的静态电流消耗。还提供了用于欠压锁定、电荷
泵故障、过流保护、短路保护、开路负载检测和过热的
内部保护功能。可通过 nFAULT 引脚和 SPI 寄存器来
指示故障状况。
– PH/EN
– PWM (IN1/IN2)
– 独立半桥控制
• 支持1.8V、3.3V、5V 逻辑输入
• SPI 或硬件接口选项
• 小型封装和外形尺寸
– 24 引脚HTSSOP PowerPAD™ IC 封装
• 保护特性
器件信息(1)
封装尺寸（标称值）
器件型号
封装
DRV8873-Q1
HTSSOP (24)
7.70mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– VM 欠压锁定(UVLO)
– 电荷泵欠压(CPUV)
4.5 to 38 V
– 过流保护(OCP)
– 输出对电池短路和接地短路保护
– 开路负载检测
DRV8873-Q1
PWM
H-Bridge Driver
DISABLE
SPI or HW
nFAULT
– 热关断(TSD)
– 故障状况输出(nFAULT/SPI)
• 适用于低电磁干扰(EMI) 的展频时钟
• 功能安全型
BDC
Current Sense
Current Regulation
Built-In Protection
Monitor
– 有助于进行功能安全系统设计的文档
2 应用
• 电子节流控制
• 废气再循坏
简化版原理图
• 侧后视镜倾斜
• 电子换挡器
• 气流转向阀控制
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDY7
DRV8873-Q1
ZHCSIO5B –OCTOBER 2017 –REVISED JANUARY 2021
www.ti.com.cn
Table of Contents
7.5 Programming............................................................ 31
7.6 Register Maps...........................................................36
8 Application and Implementation..................................42
8.1 Application Information............................................. 42
8.2 Typical Application.................................................... 42
9 Power Supply Recommendations................................49
9.1 Bulk Capacitance Sizing........................................... 49
10 Layout...........................................................................50
10.1 Layout Guidelines................................................... 50
10.2 Layout Example...................................................... 50
11 Device and Documentation Support..........................51
11.1 Documentation Support.......................................... 51
11.2 Receiving Notification of Documentation Updates..51
11.3 支持资源..................................................................51
11.4 Trademarks............................................................. 51
11.5 静电放电警告...........................................................51
11.6 术语表..................................................................... 51
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 SPI Timing Requirements........................................... 8
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................31
Information.................................................................... 51
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (August 2018) to Revision B (January 2021)
Page
• 添加了功能安全项目符号....................................................................................................................................1
Changes from Revision * (October 2017) to Revision A (August 2018)
Page
• 将器件状态从预告信息 更改为量产数据 ............................................................................................................ 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDY7
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DRV8873-Q1
ZHCSIO5B –OCTOBER 2017 –REVISED JANUARY 2021
www.ti.com.cn
5 Pin Configuration and Functions
DVDD
nFAULT
MODE
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
CPL
DVDD
nFAULT
SDO
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
CPL
2
2
3
CPH
VCP
VM
3
CPH
VCP
VM
SR
4
SDI
4
nITRIP
nOL
5
SCLK
5
6
OUT1
OUT1
SRC
SRC
OUT2
OUT2
VM
nSCS
6
OUT1
OUT1
SRC
SRC
OUT2
OUT2
VM
Thermal
Pad
Thermal
Pad
EN/IN1
PH/IN2
DISABLE
IPROPI1
nSLEEP
IPROPI2
7
EN/IN1
PH/IN2
DISABLE
IPROPI1
nSLEEP
IPROPI2
7
8
8
9
9
10
11
12
10
11
12
Not to scale
Not to scale
图5-1. DRV8873H-Q1 PWP PowerPAD Package 24- 图5-2. DRV8873S-Q1 PWP PowerPAD Package 24-
Pin HTSSOP Top View
Pin HTSSOP Top View
Pin Functions
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8873H-Q1 DRV8873S-Q1
Charge pump switching node. Connect a X7R capacitor with a value of 47 nF
between the CPH and CPL pins.
CPH
22
23
1
22
23
1
PWR
PWR
PWR
I
Charge pump switching node. Connect a X7R capacitor with a value of 47 nF
between the CPH and CPL pins.
CPL
Digital regulator. This pin is the 5-V internal digital-supply regulator. Bypass
this pin to GND with a 6.3-V, 1-µF ceramic capacitor.
DVDD
EN/IN1
Control Inputs. For details, see the 节7.3.1.1 section. This pin has an internal
pulldown resistor to GND.
7
7
Bridge disable input. A logic high on this pin disables the H-bridge Hi-Z.
Internal pullup to DVDD.
DISABLE
GND
9
9
I
24
10
24
10
PWR
O
Ground pin
High-side FET current. The analog current proportional to the current flowing
in the half bridge.
IPROPI1
High-side FET current. The analog current proportional to the current flowing
in the half bridge.
IPROPI2
nITRIP
nOL
12
5
12
—
—
O
I
Internal current-regulation control pin (ITRIP). To enable the ITRIP feature, do
not connect this pin (or tie it to GND). To disable the ITRIP feature, connect
this pin to the DVDD pin.
Open-load diagnostic control pin. To run the open-load diagnostic at power
up, tie it to ground. Connect it to DVDD, open-load diagnostic will be disabled.
6
I
MODE
OUT1
OUT1
OUT2
OUT2
3
I
Input mode pin. Sets the PH/EN, PWM, or independent-PWM mode.
Half-bridge output 1. Connect this pin to the motor or load.
Half-bridge output 1. Connect this pin to the motor or load.
Half-bridge output 2. Connect this pin to the motor or load.
Half-bridge output 2. Connect this pin to the motor or load.
—
18
19
14
15
18
19
14
15
O
O
O
O
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English Data Sheet: SLVSDY7
DRV8873-Q1
ZHCSIO5B –OCTOBER 2017 –REVISED JANUARY 2021
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PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8873H-Q1 DRV8873S-Q1
Control inputs. For details, see the 节7.3.1.1 section. This pin has an internal
pulldown resistor to GND.
PH/IN2
8
8
I
Serial clock input. Serial data is shifted out and captured on the
corresponding rising and falling edge on this pin.
SCLK
SDI
5
4
3
I
I
—
—
—
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This
is a push-pull output.
SDO
PP
SR
4
I
Slew rate adjust. This pin sets the slew rate of the H-bridge outputs.
Power FET source. Tie this pin to GND through a low-impedance path.
Power FET source. Tie this pin to GND through a low-impedance path.
—
16
17
SRC
SRC
16
17
O
O
Charge pump output. Connect a 16-V, 1-µF ceramic capacitor from this pin to
the VM supply.
VCP
VM
21
13
20
2
21
13
20
2
PWR
PWR
PWR
OD
Power supply. This pin is the motor supply voltage. Bypass this pin to GND
with a 0.1-µF ceramic capacitor and a bulk capacitor.
Power supply. This pin is the motor supply voltage. Bypass this pin to GND
with a 0.1-µF ceramic capacitor and a bulk capacitor.
VM
Fault indication pin. This pin is pulled logic low with a fault condition. This
open-drain output requires an external pullup resistor.
nFAULT
Serial chip select. An active low on this pin enables the serial interface
communications. Internal pullup to nSLEEP.
nSCS
6
I
I
—
nSLEEP
11
11
Sleep input. To enter a low-power sleep mode, set this pin logic low.
(1) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output, PP = push-pull output
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English Data Sheet: SLVSDY7
DRV8873-Q1
ZHCSIO5B –OCTOBER 2017 –REVISED JANUARY 2021
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
40
UNIT
Power supply voltage
Charge pump voltage
Charge pump switching pin
VM
V
V
V
V
VCP, CPH
CPL
VVM + 5.7
VVM
Internal logic regulator voltage DVDD
5.7
EN/IN1, PH/IN2, nSLEEP, DISABLE, nFAULT,
MODE, SR, SCLK, SDI, SDO, nSCS
Digital pin voltage
5.7
V
–0.3
VTRIP
VSRC
Analog pin voltage
IPROPI1, IPROPI2
0
–0.3
SRC –1
0
5.5
0.3
V
V
H-Bridge source pin voltage
Phase node pin voltage
Open drain output current
Push-pull output current
Operating junction temperature
Storage temperature
OUTx
nFAULT
SDO
VVM + 1
10
V
V
mA
mA
°C
°C
0
10
TJ
150
–40
–65
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100–002 HBM ESD Classification Level
±2000
2(1)
Electrostatic
discharge
V(ESD)
V
Corner pins (1, 12, 13,
and 24)
±750
±500
Charged device model (CDM), per AEC Q100–011
CDM ESD Classification Level C4B
Other pins
(1) AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
0
MAX
38
UNIT
V
VVM
VI
Power supply voltage
Logic level input voltage
5.5
V
fPWM
TA
Applied PWM signal (EN/IN1, PH/IN2)
Operating ambient temperature
Operating junction temperature
100
125
150
kHz
°C
–40
–40
TJ
°C
6.4 Thermal Information
DRV8873-Q1
PWP (HTSSOP)
24 PINS
27.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
18.8
5.1
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English Data Sheet: SLVSDY7
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ZHCSIO5B –OCTOBER 2017 –REVISED JANUARY 2021
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UNIT
DRV8873-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
24 PINS
0.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
ΨJT
5.2
ΨJB
RθJC(bot)
1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, DVDD)
VVM
IVM
VM operating voltage
4.5
38
10
V
VVM = 13.5 V; nSLEEP = 1; DISABLE
=0
VM operating supply current
5
mA
IVM(Q)
VM sleep mode supply current
Internal logic regulator voltage
Sleep time
VVM = 13.5 V; nSLEEP = 0
15
5
30
µA
V
VDVDD
t(SLEEP)
t(RESET)
2-mA load, VVM > 5.5 V
4.7
50
5
5.3
nSLEEP low to start device shutdown
nSLEEP low to only clear fault registers
µs
µs
nSLEEP reset pulse
20
nSLEEP high to device ready for input
signals
t(WAKE)
ton
Wake-up time
Turn-on time
1.5
ms
VM > V(UVLO); nSLEEP = 1, to output
transition
1.5
ms
µs
t(DISABLE) DISABLE deglitch time
DISABLE signal transition
2.5
CHARGE PUMP (VCP, CPH, CPL)
VVCP
IVCP
VCP operating voltage
VCP current
with respect to VM
VVM = 13.5 V
VVM+5
7
V
10
mA
kHz
f(VCP)
Charge pump switching frequency
VVM > V(UVLO); nSLEEP = 1
400
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP, SCLK, SDI)
VIL
Input logic-low voltage
Input logic-high voltage
Input logic hysteresis
0
0.8
5.3
V
VIH
VHYS
IIL
1.6
V
150
mV
µA
µA
kΩ
Input logic-low current
Input logic-high current
Internal pulldown resistance
VIN = 0 V
5
–5
IIH
VIN = 5 V
50
100
1.2
1.6
2.6
3.4
4.1
5.2
7.8
13.3
RPD
to GND
SR = 000b; IO = 1 A
SR = 001b; IO = 1 A
SR = 010b; IO = 1 A
SR = 011b; IO = 1 A
SR = 100b; IO = 1 A
SR = 101b; IO = 1 A
SR = 110b; IO = 1 A
SR = 111b; IO = 1 A
Propagation delay (EN/IN1, PH/IN2
to OUTx = 50%)
tpd
µs
LOGIC-LEVEL INPUT (DISABLE)
RPU,DIS
VIL,DIS
VIH,DIS
Internal pull-up resistance
Input logic-low voltage
Input logic-high voltage
DISABLE to DVDD
100
kΩ
V
0
0.8
5.3
1.6
V
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Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
LOGIC-LEVEL INPUT (nSCS)
VIL,nSCS Input logic-low voltage
VIH,nSCS Input logic-high voltage
RPU,nSCS Internal pull-up resistance
LOGIC-LEVEL INPUT (nSLEEP)
VIL,SLEEP Input logic-low voltage
VIH,SLEEP Input logic-high voltage
IIH,SLEEP Input logic-high current
THREE-LEVEL INPUT (MODE)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
0.8
5.3
V
V
1.6
nSCS to nSLEEP
450
kΩ
0
0.8
V
V
2.7
5.3
(1)
VIN = 5 V; nSCS is High
80+ISDO
µA
RIN-1
RIN-2
RIN-3
Input mode 1
Input mode 2
Input mode 3
Tied to GND
Tied to GND
Tied to DVDD
105
105
Ω
kΩ
Ω
190
PUSH-PULL OUTPUT (SDO)
RPD,SDO Internal pull-down resistance
RPU,SDO Internal pull-up resistance
OPEN DRAIN OUTPUT (nFAULT)
With respect to GND
30
50
Ω
Ω
With respect to nSLEEP
120
240
VOL
IOZ
Output logic-low voltage
IO = 2 mA
VO = 5 V
0.1
2
V
Output high-impedance leakage
µA
–2
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
VVM = 13.5 V; TA = 25°C; TJ = 25°C
VVM = 13.5 V; TA = 25°C; TJ = 150°C
VVM = 13.5 V; TA = 25°C; TJ = 25°C
VVM = 13.5 V; TA = 25°C; TJ = 150°C
SR = 100b
75
125
75
RDS(ON)
High-side FET on-resistance
mΩ
mΩ
155
155
RDS(ON)
t(DEAD)
Low-side FET on-resistance
Output dead time
125
500
0.8
62
ns
V
VF(DIODE) Body diode forward voltage
IO = 1 A
nSLEEP = 0
ISINK
Sink current when OUTx = Hi-Z
µA
nSLEEP = 1, DISABLE = 1
IO = 1 A; Connect to GND
IO = 1 A; R(SR) = 22 kΩ± 5% to GND
IO = 1 A; R(SR) = 68 kΩ± 5% to GND
IO = 1 A; No connect (Hi-Z)
IO = 1 A; R(SR) = 51 kΩ± 5% to DVDD
IO = 1 A; Connect to DVDD
IO = 1 A; SR = 000b
340
53.2
34
18.3
13
Slew rate (H/W Device)
OUTx 10% to 90% changing
SR
V/µs
7.9
2.6
53.2
34
IO = 1 A; SR = 001b
IO = 1 A; SR = 010b
18.3
13
IO = 1 A; SR = 011b
Slew rate (SPI Device)
OUTx 10% to 90% changing
SR
V/µs
IO = 1 A; SR = 100b
10.8
7.9
5.3
2.6
IO = 1 A; SR = 101b
IO = 1 A; SR = 110b
IO = 1 A; SR = 111b
CURRENT SENSE OUTPUTS (IPROPI1, IPROPI2)
k
Current mirror scaling
1100
A/A
mA
%
IO < 1 A
50
5
–50
–5
kERR
Current mirror scaling
IO ≥1 A
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DRV8873-Q1
ZHCSIO5B –OCTOBER 2017 –REVISED JANUARY 2021
www.ti.com.cn
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO = 2 V; SR = 000b
2.2
t(IPROPI)
OUTx to IPROPI
µs
VO = 2 V; SR = 111b
10.5
CURRENT REGULATION
ITRIP_LVL = 00b; VVM = 13.5 V
ITRIP_LVL = 01b; VVM = 13.5 V
ITRIP_LVL = 10b; VVM = 13.5 V
ITRIP_LVL = 11b; VVM = 13.5 V
TOFF = 00b
3.27
4.6
3.85
5.4
6.5
7
4.43
6.2
7.5
8.1
ITRIP
Current limit threshold
A
5.5
5.95
20
40
60
80
5
TOFF = 01b
tOFF
PWM off-time
µs
µs
V
TOFF = 10b
TOFF = 11b
tBLANK
PWM blanking time
PROTECTION CIRCUITS
VM falling; UVLO report
4.35
4.5
10
4.45
4.7
V(UVLO)
VM undervoltage lockout
VM rising; UVLO recovery
t(UVLO)
V(RST)
VM UVLO falling deglitch time
VM UVLO reset
VM falling; UVLO report
µs
V
VM falling; UVLO report; device reset
VVM = 12 V; TA = 25°C; CPUV report
4.1
5
VVCP(UV) Charge pump undervoltage
VVM + 2.25
V
I(OCP)
Overcurrent protection trip level
Overcurrent deglitch time
10
A
t(OCP)
3
4
µs
ms
t(RETRY)
Overcurrent retry time (H/W Device)
OCP_TRETRY = 00b
OCP_TRETRY = 01b
OCP_TRETRY = 10b
OCP_TRETRY = 11b
0.5
1
t(RETRY)
Overcurrent retry time (SPI Device)
ms
2
4
VOLA
td(OL)
Open load active mode
150
300
0.3
1.2
3
450
mV
ms
OL_DLY = 0b
OL_DLY = 1b
Open load diagnostic delay time
IOL
Open load current
mA
°C
°C
°C
TOTW
TTSD
Thys
Thermal warning temperature
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature (TJ)
Die Temperature (TJ)
Die temperature (TJ)
140
165
150
175
20
160
185
(1) SDO output current external to the device
6.6 SPI Timing Requirements
MIN
NOM
MAX
UNIT
ms
ns
t(READY)
t(CLK)
SPI ready, VM > V(UVLO)
SCLK minimum period
SCLK minimum high time
SCLK minimum low time
SDI input setup time
1
100
50
50
20
30
t(CLKH)
t(CLKL)
tsu(SDI)
th(SDI)
ns
ns
ns
SDI input hold time
ns
td(SDO)
tsu(nSCS)
th(nSCS)
SDO output delay time, SCLK high to SDO valid, CL = 20 pF
nSCS input setup time
30
ns
50
50
ns
nSCS input hold time
ns
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MIN
NOM
MAX
UNIT
ns
t(HI_nSCS)
tdis(nSCS)
nSCS minimum high time before active low
500
nSCS disable time, nSCS high to SDO high impedance
10
ns
t(HI_nSCS)
th(nSCS)
tsu(nSCS)
t(CLK)
t(CLKH)
t(CLKL)
LSB
MSB
tsu(SDI)
th(SDI)
LSB
MSB
td(SDO)
tdis(nSCS)
图6-1. SPI Slave-Mode Timing Definition
6.7 Typical Characteristics
160
140
120
100
80
6
5
4
3
2
1
0
60
40
20
0
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (èC)
Temperature (èC)
D001
D002
图6-2. RDS(on) vs Temperature
图6-3. Operating Current (IVM) vs Temperature
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20
18
16
14
12
10
8
6.2
6
5.8
5.6
5.4
5.2
5
6
4
2
0
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (èC)
Temperature (èC)
D004
D003
ITRIP = 01b
图6-4. Sleep Current (IVM(Q)) vs Temperature
图6-5. ITRIP Current vs Temperature
8
7
6
5
4
3
2
1
0
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7
6.9
6.8
6.7
6.6
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (èC)
Temperature (èC)
D006
D005
ITRIP = 11b
ITRIP = 10b
图6-7. ITRIP Current vs Temperature
图6-6. ITRIP Current vs Temperature
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7 Detailed Description
7.1 Overview
The device is an integrated, 4.5-V to 38-V motor driver for automotive brushed-motor applications. The device is
capable of high output-current drive using low-RDS(ON) integrated MOSFETs.
A standard 4-wire serial peripheral interface (SPI) decreases the device pin count by allowing the various device
settings and fault reporting to be managed through an external controller. Alternatively a hardware interface
option device is available for easy configuration with less detailed control of all device functions.
The device integrates a current mirror which provides an output current proportional to the current through the
high-side FETs. This feature allows the system to monitor the motor current without the need for a large high-
power resistor for current sensing. The device has a built-in current regulation feature with a fixed off-time
current-chopping scheme. The current-chopping level is selected through SPI in the SPI version of the device
and in the hardware version of the device is it a fixed value.
In addition to the high level of driver integration, the device provides a broad range of integrated protection
features. These features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage
lockout, overcurrent faults, open-load detection, output short to battery and short to ground protection, and
thermal shutdown. Device faults are indicated by the nFAULT pin with detailed information available in the device
registers.
The device integrates a spread spectrum clocking feature for both the internal digital oscillator and internal
charge pump. This feature combined with output slew rate control minimizes the radiated emissions from the
device.
The device is available in a 24-pin HTSSOP package with a thermal pad.
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7.2 Functional Block Diagram
1 µF
DVDD
VM
VM
VM
VCP
VM
Power
1 µF
VCP
+
bulk
0.1 µF
0.1 µF
CPH
Charge
Pump
Internal
Regulators
OUT1
47 nF
Predriver
CPL
IN1
IN2
BDC
VCP
VM
Core
Logic
nSLEEP
OUT2
SRC
Predriver
DVDD
DISABLE
Control
Inputs
nSLEEP
VTRIP
nOL
SR
IPROPI1
IPROPI2
Protection
Undervoltage
Overcurrent
Thermal
RSENSE-1
Current
Sense
Output
MODE
nITRIP
Open Load
RSENSE-2
RnFAULT
Output
nFAULT
GND
PPAD
图7-1. Hardware Device Block Diagram
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1 µF
DVDD
VM
VM
VCP
VM
Power
VM
1 µF
VCP
CPH
+
bulk
0.1 µF
0.1 µF
Charge
Pump
Internal
Regulators
OUT1
47 nF
Predriver
CPL
IN1
IN2
BDC
VCP
VM
Core
Logic
Control
Inputs
nSLEEP
OUT2
SRC
Predriver
DVDD
DISABLE
nFAULT
RnFAULT
VTRIP
Output
IPROPI1
IPROPI2
Protection
nSLEEP
Undervoltage
Overcurrent
Thermal
RSENSE-1
Current
Sense
Output
nSCS
SDI
SPI
nSLEEP
Open Load
RSENSE-2
SDO
SCLK
GND
PPAD
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图7-2. SPI Device Block Diagram
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7.3 Feature Description
表7-1 lists the recommended external components for the device.
表7-1. External Components
COMPONENT
CVM1
PIN 1
VM
PIN 2
GND
RECOMMENDED
0.1-µF ceramic capacitor rated for VM
Bulk capacitor rated for VM
16-V, 1-µF ceramic capacitor
47-nF capacitor rated for VM
6.3-V, 1-µF ceramic capacitor
≥10-kΩ pullup resistor
CVM2
VM
GND
CVCP
VCP
VM
CFLY
CPH
CPL
CDVDD
DVDD
VCC(1)
MODE
IPROPI1
IPROPI2
GND
RnFAULT
RMODE
RSENSE-1
RSENSE-2
nFAULT
GND or DVDD
GND
Device hardware interface
Resistors to convert mirrored current into a voltage
Resistors to convert mirrored current into a voltage
GND
(1) VCC is not a pin on the device, but a VCC supply-voltage pullup is required for the open-drain output nFAULT.
7.3.1 Bridge Control
The device output has four N-channel MOSFETs configured in a H-bridge. The driver can be controlled using a
PH/EN, PWM, or independent half-bridge input mode. 表7-2 lists the control mode configurations.
表7-2. Control Mode Configuration
HARDWARE DEVICE
MODE PIN
SPI DEVICE
MODE REGISTER
CONTROL MODE
L
H
00b
01b (default)
10b
PH/EN
PWM
Independent half bridge
Input disabled, bridge Hi-Z
200 kΩ± 5% to GND
Not applicable
11b
In the hardware version of the device, the MODE pin determines the control interface and latches on power-up
or when exiting sleep mode. During the device power-up sequence, the DVDD pin is enabled first, and then the
MODE pin latches. Tying the MODE pin directly to ground sets the mode to phase and enable. Tying the MODE
pin to the DVDD pin, or an external 5 V rail, sets the mode to PWM. Connecting the MODE pin to ground with a
200 kΩ ± 5% resistor sets the mode to independent half-bridge where the two half-bridges can be independently
controlled by their respective input (INx) pins. 表7-3 lists the different MODE pin settings.
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表7-3. DRV8873H-Q1 MODE Pin Settings
CONNECTION
MODE
CIRCUIT
MODE
Connect to GND
Phase and Enable
MODE
Independent half-bridge
200 kΩ ± 5% to GND
RMODE
DVDD
MODE
Connect to DVDD
PWM
In the SPI version of the device, the mode setting can be changed by writing to the MODE register in the IC1
control register because this device version has no dedicated MODE pin. The device mode gets latched when
the DISABLE signal transitions from high to low.
7.3.1.1 Control Modes
The device output consists of four N-channel MOSFETs that are designed to drive high current. The MOSFETs
are controlled by two logic inputs, EN/IN1 and PH/IN2, in three different input modes to support various
commutation and control methods, as shown in the logic tables (表 7-4, 表 7-5, and 表 7-6). In the Independent
PWM mode, the fault handling is performed independently for each half bridge. For example, if an overcurrent
condition (OCP) is detected in half-bridge 1, only the half-bridge 1 output (OUT1) is disabled and half-bridge 2
continues to operate based on the IN2 input.
表7-4. PH/EN Mode Truth Table
nSLEEP
DISABLE
EN/IN1
PH/IN2
OUT1
Hi-Z
Hi-Z
H
OUT2
Hi-Z
Hi-Z
H
0
1
1
1
1
X
1
0
0
0
X
X
0
1
1
X
X
X
0
L
H
1
H
L
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表7-5. PWM Mode Truth Table
nSLEEP
DISABLE
EN/IN1
PH/IN2
OUT1
Hi-Z
Hi-Z
Hi-Z
L
OUT2
Hi-Z
Hi-Z
Hi-Z
H
0
1
1
1
1
1
X
1
0
0
0
0
X
X
0
0
1
1
X
X
0
1
0
1
H
L
H
H
表7-6. Independent Mode Truth Table
nSLEEP
DISABLE
EN/IN1
PH/IN2
OUT1
Hi-Z
Hi-Z
L
OUT2
Hi-Z
Hi-Z
L
0
1
1
1
1
1
X
1
0
0
0
0
X
X
0
0
1
1
X
X
0
1
0
1
L
H
H
L
H
H
The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM)
for variable motor speed. When using PWM mode (MODE = 1), switching between driving and braking typically
is best. For example, to drive a motor forward with 50% of its maximum revolutions per minute (RPM), the IN1
pin is high and the IN2 pin is low during the driving period. During the other period in this example, the IN1 pin is
high and the IN2 pin is high.
VM
VM
VM
VM
2
2
1
3
SH2
SH2
SH2
SH2
SH1
SH1
SH1
SH1
1
2
3
Forward drive
High-side recirculation (brake)
Reverse drive
图7-3. Half-Bridge Current Paths
In the Independent PWM mode, to independently put the outputs of the half bridge in the high-impedance (Hi-Z)
state, the OUT1_DIS or OUT2_DIS bit in the IC3 register must be set to 1b. Writing a logic 1 to the OUT1_DIS
bit disables the OUT1 output. Writing a logic 1 to the OUT2_DIS bit disables the OUT2 output. The default value
in these registers is 0b. The option to independently set the outputs of the half bridge in the Hi-Z state is not
available for the hardware version of the device.
7.3.1.2 Half-Bridge Operation
The device can be used to drive two solenoids or unidirectional brushed DC-motor loads instead of a brushed-
DC motor in full H-bridge configuration. Independent half-bridge control is preferred for operation in this mode;
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however, using the PH/EN or PWM modes is not restricted if the correct driving and braking states can be
achieved.
VCP
VM
VM
+
0.1 µF
bulk
OUT1
Predriver
BDC
VCP
VM
OUT2
SRC
Predriver
BDC
Copyright © 2017, Texas Instruments Incorporated
图7-4. Independent Half bridge Mode Driving Two Low-Side Loads
7.3.1.3
TI does not recommend tying the OUT1 and OUT2 pins together and drive a load. The half bridges may be out
of synchronization in this configuration and any mismatch in the input commands can momentarily result in shoot
through condition. This mismatch can be mitigated by adding an inductor in-line with the outputs.
If loads are connected between the OUTx and VM pins, the device can draw more current than specified in the
节6.5 table. To avoid this condition, TI recommends connecting loads in the configuration shown in 图7-4.
Depending on how the loads are connected on the outputs pin, some of the features offered by the device could
have reduced functionality. For example, having a load between the OUTx and GND pins, as shown in 图 7-4,
results in false trips of the open-load diagnosis in active-mode (OLA). Having a load tied between the OUTx and
VM pins restricts the use of internal current regulation because no means of measuring current flowing through
the load with the current mirror block is available. 表7-7 lists these use cases.
表7-7. Control Mode Configuration
LOAD CONNECTIONS
FUNCTIONALITY
NODE 1
OUTx
NODE 2
GND
OLA
CURRENT REGULATION (ITRIP)
Not Available
Operational
Operational
OUTx
VM
Not Available
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7.3.1.4 Internal Current Sense and Current Regulation
The IPROPI pin outputs an analog current that is proportional to the current flowing in the H-bridge. The output
current is typically 1/1100 of the current in both high-side FETs. The IPROPI pin is derived from the current
through either of the high-side FETs. Because of this, the IPROPI pin does not represent the half bridge current
when operating in a fast decay mode or low-side slow decay mode. The IPROPI pin represents the H-bridge
current under forward drive, reverse drive, and high-side slow decay. The IPROPI output is delayed by
approximately 2 µs for the fastest slew-rate setting (43.2 V/µs) after the high-side FET is switched on.
VM
HS1
SENSE_FET
1/1100 scaled
HS1
PWR_FET
OUT1
Current Sense
IPROPI1
and
Current Regulation
RSENSE-1
VM
HS2
SENSE_FET
1/1100 scaled
HS2
PWR_FET
OUT2
Current Sense
IPROPI2
and
Current Regulation
RSENSE-2
图7-5. Current-Sense Block Diagram
The selection of the external resistor should be such that the voltage on the IPROPI pin is less than 5 V.
Therefore the resistor must be sized less than this value based on 方程式 1. The range of current that can be
monitored is from 100 mA to 10 A assuming the selected external resistor meets the calculated value from 方程
式 1. If the current exceeds 10 A, the device could reach overcurrent protection (OCP) or overtemperature
shutdown (TSD). If OCP occurs, the device disables the internal MOSFETs and protects itself (for the hardware
version of the device) or based on the OCP_MODE setting (for the SPI version of the device). For guidelines on
selecting a sense resistor, see the 节8.2.1.3 section.
R(SENSE) = k × 5 V / IO
(1)
where
• k is the current mirror scaling factor, which is typically 1100.
• IO is the maximum drive current to be monitored.
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备注
Texas Instruments recommends the load current not exceed 8 A during normal operation. If slew rate
setting of 2.6 V/µs (SR = 111b) is used when the load current is about 8 A, choose TOFF to be either
40 µs or 60 µs.
The SPI version of the device limits the output current based on the trip level set in the SPI registers. In the
hardware version of the device, the current trip limit is set to 6.5 A. The current regulation feature is enabled by
default on both the outputs (OUT1 and OUT2). To disable current regulation in the hardware version of the
device, the nITRIP pin must be connected to DVDD. To disable current regulation in the SPI version of the
device, the DIS_ITRIP bits in the IC4 Control register must be written to. The bit settings are:
• 01b to disable current regulation only on the OUT1 pin
• 10b to disable current regulation only on the OUT2 pin
• 11b to disable current regulation on both the OUT1 and OUT2 pins
表7-8. Control Regulation Threshold
PARAMETER
ITRIP_LVL BIT
ITRIP_LVL = 00b
ITRIP_LVL = 01b
ITRIP_LVL = 10b
ITRIP_LVL = 11b
MIN
3.4
4.6
5.5
6
TYP
MAX
4.6
6.2
7.5
8
UNIT
4
A
A
A
A
5.4
6.5
7
ITRIP
Current limit threshold
When the ITRIP current has been reached, the device enforces slow current decay by enabling both the high-side
FETs for a time of tOFF . In the hardware version of the device, the tOFF time is 40 µs. The tOFF time is selectable
through SPI in the SPI version of the device, as shown in 表7-9. The default setting is 01b (tOFF = 40 µs).
表7-9. PWM Off Time Settings
PARAMETER
TOFF BIT
TOFF = 00b
TOFF = 01b
TOFF = 10b
TOFF = 11b
tOFF DURATION
UNIT
µs
20
40
60
80
µs
tOFF
PWM off time
µs
µs
ITRIP
tBLANK
Drive
tDRIVE
Brake or Slow Decay
tOFF
Drive
tDRIVE
Brake or Slow Decay
tOFF
图7-6. Current Regulation Time Periods
When the tOFF time has elapsed and the current level falls below the current regulation (ITRIP) level, the output is
re-enabled according to the inputs. If, after the tOFF time has elapsed the current is still higher than the ITRIP
level, the device enforces another tOFF time period of the same duration.
The drive time (tDRIVE) occurs until another ITRIP event is reached and depends heavily on the VM voltage, the
back-EMF of the motor, and the inductance of the motor. During the tDRIVE time, the current-sense regulator
does not enforce the ITRIP limit until the tBLANK time has elapsed. While in current regulation, the inputs can be
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toggled to drive the load in the opposite direction to decay the current faster. For example, if the load was in
forward drive prior to entering current regulation it can only go into reverse drive when the driver enforces current
regulation.
The IPROPI1 pin represents the current flowing through the HS1 MOSFET of half-bridge 1. The IPROPI2 pin
represents the current flowing through the HS2 MOSFET of half-bridge 2. To measure current with one sense
resistor, the IPROPI1 and IPROPI2 pins must be connected together with the RSENSE resistor as shown in 图
7-7. In this configuration, the current-sense output is proportional to the sum of the currents flowing through the
both high-side FETs.
IPROPI1
Current-Sense
Output
RSENSE-1
IPROPI2
GND
PPAD
图7-7. Current Sense Output
7.3.1.5 Slew-Rate Control
The rise and fall times (tr and tf) of the outputs can be adjusted on the hardware version of the device by
changing the value of an external resistor connected from the SR pin to ground. On the SPI version of the
device, the slew rate can be adjusted through the SPI. The output slew rate is adjusted internally to the device
by controlling the ramp rate of the driven FET gate. The voltage or resistance on the SR pin sets the output rise
and fall times in the hardware version of the device.
表7-10. DRV8873H-Q1 Slew Rate (SR) Pin Connections
CONNECTION
SR
CIRCUIT
SR
Connect to GND
53.2 V/µs
SR
34 V/µs
22 kΩ ± 5% to GND
RSR
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表7-10. DRV8873H-Q1 Slew Rate (SR) Pin Connections (continued)
CONNECTION
SR
CIRCUIT
SR
18.3 V/µs
68 kΩ ± 5% to GND
RSR
SR
13 V/µs
> 2 MΩto GND (Hi-Z)
DVDD
SR
7.9 V/µs
51 kΩ ± 5% to DVDD
DVDD
SR
Connect to DVDD
2.6 V/µs
图7-8 shows the internal circuit block for the SR pin.
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SLEW RATE
53.2 V/µs
+
œ
VREF
VREF
VREF
34 V/µs
DVDD
+
œ
SR
18.3 V/µs
+
œ
13 V/µs
+
œ
VREF
7.9 V/µs
2.6 V/µs
+
œ
VREF
图7-8. SR Block Diagram
表7-11 lists the settings in the SPI register that set the output rise and fall times in the SPI version of the device.
表7-11. DRV8873S-Q1 Slew Rate Settings
SR
RISE TIME (V/µs)
FALL TIME (V/µs)
000b
001b
010b
011b
100b
101b
110b
111b
53.2
34
53.2
34
18.3
13
18.3
13
10.8
7.9
5.3
2.6
10.8
7.9
5.3
2.6
The typical voltage on the SR pin is 3 V and is driven internally. Changing the resistor value on the SR pin
changes the slew-rate setting from approximately 2.6 V/µs to 53.2 V/µs. The recommended values for the
external resistor are shown in the 节 7.3.3.2 section. If the SR pin is grounded then the slew rate is 53.2 V/µs.
Leaving the SR pin as a no-connect pin sets the slew rate to 13 V/µs. Tying it to the DVDD pin sets the slew rate
to 2.6 V/µs.
7.3.1.6 Dead Time
The dead time (t(DEAD)) is measured as the time when the OUTx pin is in the Hi-Z state between turning off one
of the half bridge MOSFETs and turning on the other. For example, the output is in the Hi-Z state between
turning off the high-side MOSFET and turning on the low-side MOSFET, or turning on the high-side MOSFET
and turning off the low-side MOSFET.
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IN1
IN2
OUT1
tPD
t(DEAD)
tF
tPD
t(DEAD)
tR
OUT2
tPD
t(DEAD)
tR
tPD
t(DEAD)
tF
图7-9. Propagation Delay Time
If the output pin is measured during the tDEAD time the voltage depends on the direction of the current. If the
current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage
is a diode drop above VM. The diode drop is associated with the body diode of the high-side or the low-side FET.
The dead time is dependent on the slew-rate setting because a portion of the FET gate ramp includes the
observable dead time.
7.3.1.7 Propagation Delay
The propagation delay time (tPD) is measured as the time between an input edge to an output change. This time
comprises two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on the
input pins from affecting the output state. The adjustable slew rate also contributes to the propagation delay
time. For the fastest slew-rate setting, the tPD time is typically 1.5 µs, and for the slowest slew-rate setting, the
tPD time is typically 4.5 µs. For the output to change state during normal operation, one FET must first be turned
off.
7.3.1.8 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is
detected, the nFAULT line is logic low. For a 5-V pullup the nFAULT pin can be tied to the DVDD pin with a
resistor (see the 节8 section). For a 3.3-V pullup, an external 3.3-V supply must be used.
Output
nFAULT
图7-10. nFAULT Pin
During the device power-up sequence, or when exiting sleep mode, the nFAULT pin is held low until the digital
core is alive and functional. This low level signal on the nFAULT line does not represent a fault condition. The
signal can be used by the external MCU to determine when the digital core of the device is ready; however, this
does not mean that the device is ready to accept input commands via the INx pins.
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7.3.1.9 nSLEEP as SDO Reference
The nSLEEP pin manages the state of the device. The device goes into sleep mode with a logic-low signal, and
comes out of sleep mode when the nSLEEP pin goes high. The signal level when the nSLEEP pin goes high
determines the logic level on the SDO output in the SPI version of the device. A 3.3-V signal on the nSLEEP pin
provides a 3.3-V output on the SDO output. A 5-V signal on the nSLEEP pin provides a 5-V output on the SDO
pin. If the sleep feature is not required, the nSLEEP pin can be connected to the MCU power supply. In that
case, when the MCU is powered-up, the motor driver device is also be powered-up.
DVDD
nSLEEP
Digital
Core
400 kꢀ
100 kꢀ
nSCS
图7-11. nSCS and nSLEEP Circuit
In the SPI version of the device, if the nSLEEP reset pulse is used to clear faults, the SDO voltage reference is
not available for the duration of the nSLEEP reset pulse. No data can be transmitted on the SDO line for the
duration when the nSLEEP pin is held low. Therefore, TI recommends using the CLR_FLT bit in the IC3 control
register to clear the faults.
7.3.2 Motor Driver Protection Circuits
The device is protected against VM undervoltage conditions, charge-pump undervoltage conditions, overcurrent
events, and overtemperature events.
7.3.2.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the UVLO-threshold voltage, V(UVLO), for the voltage supply,
all the outputs (OUTx) are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this
condition. The FAULT and UVLO bits are latched high in the SPI registers. Normal operation resumes (motor-
driver operation and nFAULT released) when the VM undervoltage condition is removed. The UVLO bit remains
set until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse.
备注
During the power-up sequence VM must exceed V(UVLO) recovery max limit in order to power-up and
function properly. After a successful power-up sequence, the device can operate down to the V(UVLO)
report limit before going into the undervoltage lockout condition.
7.3.2.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the VVCP(UV) voltage for the charge pump, all the outputs
(OUTx) are disabled, and the nFAULT pin is driven low. The charge pump remains active during this condition.
The FAULT and CPUV bits are latched high in the SPI registers. Normal operation resumes (motor-driver
operation and nFAULT released) when the VCP undervoltage condition is removed. The CPUV bit remains set
until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse. This protection feature can be disabled by
setting the DIS_CPUV bit high.
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7.3.2.3 Overcurrent Protection (OCP)
If the current in any FET exceeds the I(ocp) limits for longer than the t(OCP) time, all FETs in the half bridge are
disabled and the nFAULT pin is driven low. The charge pump remains active during this condition. The
overcurrent protection can operate in four different modes: latched shutdown, automatic retry, report only, and
disabled. In the independent PWM mode (MODE = 10b or MODE pin to ground with a 200-kΩ± 5% resistor) the
fault handling is performed independently for each half-bridge based on the OCP mode selected. This protection
scheme protects the outputs from shorts to battery and shorts to ground.
7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
In this mode, after an OCP event, all the outputs (OUTx) are disabled and the nFAULT pin are driven low. The
FAULT, OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation
resumes (motor-driver operation and nFAULT released) when the OCP condition is removed and a clear faults
command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the default
mode for an OCP event for both the hardware version and SPI version of the device.
7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
In this mode, after an OCP event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The
FAULT, OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation
resumes automatically (motor-driver operation and nFAULT released) after the t(RETRY) time has elapsed and the
fault condition is removed.
7.3.2.3.3 Report Only (OCP_MODE = 10b)
In this mode, no protective action is performed when an overcurrent event occurs. The overcurrent event is
reported by driving the nFAULT pin low and latching the FAULT, OCP, and corresponding MOSFET OCP bits
high in the SPI registers. The motor driver continues to operate. The external controller acts appropriately to
manage the overcurrent condition. The reporting is cleared (nFAULT released) when the OCP condition is
removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset
pulse.
7.3.2.3.4 Disabled (OCP_MODE = 11b)
In this mode, no protective or reporting action is performed when an overcurrent event occurs. The device
continues to drive the load based on the input signals.
7.3.2.4 Open-Load Detection (OLD)
If the motor is disconnected from the device, an open-load condition is detected and the nFAULT pin is latched
low until a clear faults command is issued by the MCU either through the CLR_FLT bit or an nSLEEP reset
pulse. The fault also clears when the device is power cycled or comes out of sleep mode. The OLD test is
designed for applications that have capacitance less than 15 nF when the OLP_DLY bit set to 0b and for less
than 60 nF when the OLP_DLY bit is set to 1b on the OUTx pins. This setting is equivalent to measuring the
resistance values listed in 表7-12.
表7-12. Resistance for Open Load Detection
NODE 1
OUT1
OUTx
NODE 2
OUT2
VM
RESISTANCE
COMMENTS
2 kΩ
VVM = 13.5 V
12 kΩ
OUTx
GND
3 kΩ
Open load detection works in both standby mode (OLP) and active mode (OLA). OLP detects the presence of
the motor prior to commutating the motor. OLA detects the motor disconnection from the driver during
commutation.
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7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
The open-load passive diagnostic (OLP) is different for the hardware and SPI version of the device. The OLP
test is available in all three modes of operation (PN/EN, PWM, and independent half-bridge). When the open-
load test is running, the internal power MOSFETs are disabled.
For the hardware version of the device, the OLP test is performed at power-up or after exiting sleep mode if the
nOL pin is left as a no connect pin (or tied to GND). If the nOL pin is tied to the DVDD pin (or an external 5-V
rail), the OLP test is not performed by the device.
For the SPI version of the device, the OLP test is performed when commanded. The following sequence shows
how to perform the OLP test directly after the device powers up:
1. Power up the device (DISABLE pin high).
2. Select the mode through SPI.
3. Wait for the t(DISABLE) time to expire.
4. Write 1b to the EN_OL bit in the IC1 register.
5. Perform the OLP test.
• If an open load (OL) is detected, the nFAULT pin is driven low, the FAULT and OLx bits are latched high.
When the OL condition is removed, a clear faults command must be issued by the MCU either through
the CLR_FLT bit or an nSLEEP reset pulse which resets the OLx register bit.
• If an OL condition is not detected, the EN_OL bits return to the default setting (0b) after the td(OL) time
expires.
6. Set the DISABLE pin low so that the device drives the motor or load based on the input signals.
If an open-load diagnostic is performed at any other time, the following sequence must be followed:
1. Set the pin DISABLE high (to disable the half bridge outputs).
2. Wait for the t(DISABLE) time to expire.
3. Write 1b to the EN_OL bit in the IC1 register.
4. Perform the OLP test.
• If an OL condition is detected, the nFAULT pin is driven low, and the FAULT and OLx bits are latched
high. When the OL condition is removed, a clear faults command must be issued by the MCU either
through the CLR_FLT bit or an nSLEEP reset pulse which resets the OLx register bits.
• If an OL condition is not detected, the EN_OL bits return to the default setting (0b) after the td(OL) time
expires.
5. Set the DISABLE pin low so that the device drives the motor or load based on the input signals.
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DVDD
DVDD
VM
OL1_PU
output
4 V
OUT1
1 V
OL1_PD
output
VM
DVDD
Digital
Core
OL2_PU
output
4 V
OUT2
SRC
1 V
OL2_PD
output
图7-12. Open-Load Detection Circuit
The EN_OL register maintains the written command until the diagnostic is complete. The signal on the DISABLE
pin must remain high for the entire duration of the test. While the OLP test is running, if the DISABLE pin goes
low, the OLP test is aborted to resume normal operation and no fault is reported. The OLP test is not performed
if the motor is energized.
The OLD test checks for a high-impedance connection on the OUTx pins. The diagnostic runs in two steps. First
the pullup current source is enabled. If a load is connected, the current passes through the pullup resistor and
the OLx_PU comparator output remains low. If an OL condition exists, the current through the pullup resistor
goes to 0 A and the OLx_PU comparator trips high. Second the pulldown current source is enabled. In the same
way, the OLx_PD comparator output either remains low to indicate that a load is connected, or trips high to
indicate an OL condition.
If both the OLx_PU and OLx_PD comparators report an OL condition, the OLx bit in the SPI register latches high
and the nFAULT line goes low to indicate an OL fault. When the OL condition is removed, a clear faults
command must be issued by the MCU either through the CLR_FLT bit or an nSLEEP reset pulse which resets
the OL1 and OL2 register bits. The charge pump remains active during this fault condition.
7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
Open load in active mode is detected when the OUT1 and OUT2 voltages do not exhibit overshoot greater than
the VOLA over VM between the time the low-side FET is switched off and the high-side FET is switched on during
an output PWM cycle, as shown in 图 7-13. An open load is not detected if the energy stored in the inductor is
high enough to cause an overshoot greater than the VOLA over VM caused by the flyback current flowing through
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the body diode of the high-side FET. The OLA diagnostic is disabled by default and can be enabled by writing a
1b to the EN_OLA bit in IC4 control register.
VM
VM
VM
SH2
SH2
SH2
SH1
SH1
SH1
Detects OLD No OLD detected
if the diode VF
drop > VOLA
if the diode VF
drop < VOLA
图7-13. Open-Load Active Mode Circuit
In PH/EN and PWM mode, the motor current decays by high-side recirculation. In independent PWM mode, the
motor can enter the brake state either by high-side or low-side recirculation. If the motor enters the brake state
using low-side recirculation, the diode VF voltage of high-side FET is less than the VOLA voltage which flags an
open load fault even though the load is connected across the OUT1 and OUT2 pins. In this case, the OLA mode
should not be used. If high-side current recirculation is done with independent PWM mode, the OLA mode
functions properly.
备注
The OLA mode is functional only when high-side recirculation of the motor current occurs. Depending
on the operation conditions and external circuitry, such as the output capacitors, an open load
condition could be indicated even though the load is present. This case might occur, for example,
during a direction change or for small load currents with respectively small PWM duty cycles.
Therefore, TI recommends evaluating the open load diagnosis only in known, suitable operating
conditions and to ignore it otherwise.
To avoid inadvertently triggering the open load diagnosis, a failure counter is implemented. Three consecutive
occurrences of the internal open-load signal must occur, essentially three consecutive PWM pulses without
freewheeling detected, before an open load condition is reported by the nFAULT pin and in the SPI register.
In the hardware version of the device, OLA mode is active when the nOL pin is left as a no-connect pin or tied to
ground. If low-side current recirculation is done with independent PWM control, an open load condition is
detected even though the load is connected. To avoid this false trip, the OLD must be disabled by taking the nOL
pin high; however, both OLA and OLP diagnostics will be disabled.
7.3.2.5 Thermal Shutdown (TSD)
If the die temperature exceeds the thermal shutdown limit, the half bridge are disabled, and the nFAULT pin is
driven low. The charge pump remains active during this condition. In addition, the FAULT bit and TSD bit are
latched high. This protection feature cannot be disabled. The overtemperature protection can operate in two
different modes: latched shutdown and automatic recovery.
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7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
In this mode, after a TSD event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The
FAULT and TSD bits are latched high in the SPI register. Normal operation resumes (motor-driver operation and
the nFAULT line released) when the TSD condition is removed and a clear faults command has been issued
either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the default mode for a TSD event in the
SPI version of the device.
7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
In this mode, after a TSD event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The
FAULT and TSD bits are latched high in the SPI register. Normal operation resumes (motor-driver operation and
the nFAULT line released) when the junction temperature falls below the overtemperature threshold limit minus
the hysteresis (TTSD – THYS). The TSD bit remains latched high indicating that a thermal event occurred until a
clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the
default mode for a TSD event in the hardware version of the device.
7.3.2.6 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW) the OTW bit is set in the registers of
SPI devices. The device performs no additional action and continues to function. When the die temperature falls
below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be
configured to report on the nFAULT pin, and set the FAULT bit in the SPI version of the device, by setting the
OTW_REP bit to 1b through the SPI registers. The charge pump remains active during this condition.
表7-13. Fault Response
CONFIGURATI
FAULT
CONDITION
REPORT
HALF BRIDGE
LOGIC
RECOVERY
ON
Automatic: VVM
V(UVLO)
(maximum 4.55 V)
>
VM undervoltage
(UVLO)
VVM < V(UVLO)
(maximum 4.45 V)
nFAULT
Hi-Z
Reset
—
Automatic: VVCP
VVCP(UV) (typical VVM
+ 2.25 V)
>
DIS_CPUV =
0b
nFAULT
Hi-Z
Active
Charge pump
VVCP < VVCP(UV)
undervoltage (CPUV) (typical VVM + 2.25 V)
DIS_CPUV =
1b
none
Active
Hi-Z
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
No action
OCP_MODE =
00b
Latched: CLR_FLT/
nSLEEP
nFAULT
nFAULT
nFAULT
none
OCP_MODE =
01b
Hi-Z
Retry: t(RETRY)
No action
IO > I(OCP)
Overcurrent (OCP)
(minimum 10 A)
OCP_MODE =
10b
Active
Active
Active
Active
Active
Active
Hi-Z
OCP_MODE =
11b
No action
Latched: CLR_FLT/
nSLEEP
EN_OLP = 1b
EN_OLA = 1b
nFAULT
nFAULT
none
Open load (OLD)
No load detected
IO > ITRIP_LVL
Latched: CLR_FLT/
nSLEEP
ITRIP_REP =
0b
No action
No action
Current regulation
(ITRIPx)
ITRIP_REP =
1b
nFAULT
nFAULT
TSD_MODE =
0b
Latched: CLR_FLT/
nSLEEP
Thermal shutdown
(TSD)
TJ > TTSD
(minimum 165°C)
Automatic:
TSD_MODE =
1b
nFAULT
Hi-Z
Active
TJ > TTSD –THYS
(THYS typical 20°C)
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表7-13. Fault Response (continued)
CONFIGURATI
ON
FAULT
CONDITION
REPORT
none
HALF BRIDGE
Active
LOGIC
Active
Active
RECOVERY
OTW_REP = 0b
No action
Thermal Warning
(OTW)
TJ > TOTW
(minimum 140°C)
Automatic: TJ < TOTW
OTW_REP = 1b
nFAULT
Active
–THYS
7.3.3 Hardware Interface
The hardware-interface device option lets the device be configured without a SPI, however not all of the
functionality is configurable. The following configuration settings are fixed for the hardware interface device
option:
• CPUV is enabled
• OCP_MODE is latched shutdown
• TSD_MODE is automatic recovery
• OLP_DLY is 300 µs
• ITRIP level is 6.5-A if current regulation is enabled by the nITRIP pin
• OLA is activated when the open load diagnostic is enabled by the nOL pin
• No option to independently set the outputs (OUTx) to the Hi-Z state
7.3.3.1 MODE (Tri-Level Input)
The MODE pin of the hardware version of the device determines the control interface and latches on power-up
or when exiting sleep mode. 表7-14 lists the different control interfaces that can be set with the MODE pin.
表7-14. DRV8873H-Q1 MODE Settings
MODE
CONTROL MODE
L
PH/EN
H
PWM
Independent half bridge
Hi-Z (200 kΩ ± 5% to GND)
When the MODE pin is latched on power-up or when exiting sleep mode; any additional changes to the signal at
the MODE pin are ignored by the device. To change the mode settings, a power cycle or sleep reset must be
performed on the device. To use the device in PWM mode, tie the MODE pin to either the DVDD pin or an
external 5-V rail. To use the device in independent half-bridge mode, the MODE pin must be connected to with a
200-kΩ ± 5% resistor (or left as a no connect). Tying the MODE pin to the GND pin puts the device in phase and
enable (PH/EN) mode.
7.3.3.2 Slew Rate
The rise and fall times of the outputs can be selected based on the configuration listed in 表 7-15 for the
hardware version of the device.
表7-15. Slew Rate Settings in H/W Device
SR PIN CONNECTION
RISE TIME (V/µs)
FALL TIME (V/µs)
Connect to GND
53.2
34
53.2
34
22 kΩ ± 5% to GND
68 kΩ ± 5% to GND
> 2MΩ to GND (Hi-Z)
51 kΩ ± 5% to DVDD
Connect to DVDD
18.3
13
18.3
13
7.9
2.6
7.9
2.6
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7.4 Device Functional Modes
7.4.1 Motor Driver Functional Modes
7.4.1.1 Sleep Mode (nSLEEP = 0)
The nSLEEP pin sets the state of the device. When the nSLEEP pin is low, the device goes to a low-power sleep
mode. In sleep mode, all the internal MOSFETs are disabled, DVDD output is disabled; the charge pump is
disabled, and the SPI is disabled. The t(SLEEP) time must elapse after a falling edge on the nSLEEP pin before
the device enters sleep mode. The device goes from sleep mode automatically if the nSLEEP pin is brought
high. The t(WAKE) time must elapse before the device is ready for inputs.
7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
The DISABLE pin is used to enable or disable the half bridge in the device. When the DISABLE pin is high, the
output drivers are disabled in the Hi-Z state. In this mode, the open-load diagnostic can be performed for the SPI
version of the device because the SPI remains active.
7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
When the nSLEEP pin is high, the DISABLE pin is low, and VM > V(UVLO), the device enters the active mode.
The t(WAKE) time must elapse before the device is ready for inputs. In this mode, the charge pump and low-side
gate regulator are enabled.
7.4.1.4 nSLEEP Reset Pulse
In addition to the CLR_FLT bit in the SPI register, a latched fault can be cleared through a quick nSLEEP pulse.
This pulse must be greater than the nSLEEP deglitch time of 5 µs and shorter than 20 µs. If nSLEEP is low for
longer than 20 µs, the faults are cleared and the device may or may not shutdown, as shown in the timing
diagram (see 图 7-14). This reset pulse resets any SPI faults and does not affect the status of the charge pump
or other functional blocks.
nSLEEP
50 µs
5 µs
20 µs
30 µs
60 µs
No Action. nSLEEP
low pulse is too short
(deglitch)
All faults cleared, device stays active
All faults cleared, device may or may not shutdown
Device shutdowns down (goes into sleep mode, faults cleared by default)
Device shutdowns down (sleep mode)
图7-14. nSLEEP Reset Pulse
7.5 Programming
7.5.1 Serial Peripheral Interface (SPI) Communication
The SPI version of the device has full duplex, 4-wire synchronous communication. This section describes the
SPI protocol, the command structure, and the control and status registers. The device can be connected with the
MCU in the following configurations:
• One slave device
• Multiple slave devices in parallel connection
• Multiple slave devices in series (daisy chain) connection
7.5.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit 14)
• 5 address bits, A (bits 13 through 9)
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• 8 data bits, D (bits 7 through 0)
The SDO output-data word is 16 bits long and the first 8 bits make up the Status Register (S1). The Report word
(R1) is the content of the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read
表7-16. SDI Input Data Word Format
R/W
B14
W0
ADDRESS
DATA
B15
0
B13
A4
B12
A3
B11
A2
B10
A1
B9
A0
B8
X
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
表7-17. SDO Output Data Word Format
STATUS
REPORT
B15
1
B14
1
B13
B12
B11
B10
B9
B8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
OTW UVLO CPUV OCP
TSD
OLD
7.5.1.2 SPI for a Single Slave Device
The SPI is used to set device configurations, operating parameters, and read out diagnostic information. The
device SPI operates in slave mode. The SPI input-data (SDI) word consists of a 16-bit word, with 8 bits
command and 8 bits of data. The SPI output data (SDO) word consists of 8 bits of status register with fault status
indication and 8 bits of register data. 图 7-15 shows the data sequence between the MCU and the SPI slave
driver.
nSCS
A1
S1
D1
R1
SDI
SDO
图7-15. SPI Transaction Between MCU and SPI version of the device
A valid frame must meet the following conditions:
• The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
• The nSCS pin should be taken high for at least 500 ns between frames.
• When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is
in the high-impedance state (Hi-Z).
• Full 16 SCLK cycles must occur.
• Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.
• The most-significant bit (MSB) is shifted in and out first.
• If the data word sent to SDI pin is less than 16 bits or more than 16 bits, a frame error occurs and the data
word is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 8-bit command data.
7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
Multiple devices can be connected in parallel as shown in 图7-16. In this configuration, all the slave devices can
share the same SDI, SDO, and CLK lines from the micro-controller, but has dedicated chip-select pin (CSx) for
each device from the micro-controller.
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The micro-controller activates the SPI of a given device via that device's chip-select input, the other devices
remain inactive for SPI transactions. This configuration helps reduce micro-controller resources for SPI
transactions if multiple slave devices are connected to the same micro-controller.
Microcontroller
DRV8873_1
DRV8873_2
DRV8873_3
SDI1
SDO1
SDI2
SDO2
SDI3
SDO3
SPI
SPI
SPI
M-CS1
M-CS2
M-CS3
M-CLK
M-SDO
M-SDI
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图7-16. Three DRV8873S-Q1 Devices Connected in Parallel Configuration
7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
The device can be connected in a daisy chain configuration to keep GPIO ports available when multiple devices
are communicating to the same MCU. 图7-17 shows the topology when three devices are connected in series.
Slave Device
(1)
Slave Device
(3)
Master
Device
Slave Device
(2)
SDO1 / SDI2
SDI1
SDO1 / SDI2
SDO3
M-SDO
M-nSCS
M-SCLK
M-SDI
图7-17. Three DRV8873S-Q1 Devices Connected in Daisy Chain
The first device in the chain receives data from the MCU in the following format for 3-device configuration: 2
bytes of header (HDRx) followed by 3 bytes of address (Ax) followed by 3 bytes of data (Dx).
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nSCS
HDR1
S1
HDR2
HDR1
A3
A2
A3
A1
A2
D3
R1
D2
D3
D1
D2
SDI1
HDR2
SDO1 / SDI2
S2
S3
S1
S2
HDR1
S1
HDR2
HDR1
A3
R2
R3
R1
R2
D3
R1
SDO2 / SDI3
SDO3
HDR2
All Address bytes
reach destination
All Data bytes
reach destination
Status response here
Reads executed here
Writes executed here
图7-18. SPI Frame With Three DRV8873S-Q1 Devices
After the data has been transmitted through the chain, the MCU receives the data string in the following format
for 3-device configuration: 3 bytes of status (Sx) followed by 2 bytes of header followed by 3 bytes of report (Rx).
nSCS
HDR1
S3
HDR2
S2
A3
S1
A2
A1
D3
R3
D2
R2
D1
R1
SDI
HDR1
HDR2
SDO
图7-19. SPI Data Sequence for Three DRV8873S-Q1 Devices
The header bytes contain information of the number of devices connected in the chain, and a global clear fault
command that will clear the fault registers of all the devices on the rising edge of the chip select (nSCS) signal.
Header values N5 through N0 are 6 bits dedicated to show the number of devices in the chain. Up to 63 devices
can be connected in series for each daisy chain connection.
The 5 LSBs of the HDR2 register are don’t care bits that can be used by the MCU to determine integrity of the
daisy chain connection. Header bytes must start with 1 and 0 for the two MSBs.
HDR 1
N4 N3
HDR 2
1
0
N5
N2
N1
N0
1
0
CLR
x
x
x
x
x
Don‘t care
No. of devices in the chain
(up to 26 œ 1= 63)
1 = global FAULT clear
0 = don‘t care
图7-20. Header Bytes
The status byte provides information about the fault status register for each device in the daisy chain so that the
MCU does not have to initiate a read command to read the fault status from any particular device. This keeps
additional read commands for the MCU and makes the system more efficient to determine fault conditions
flagged in a device. Status bytes must start with 1 and 1 for the two MSBs.
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1
1
0
0
N5
N4
X
N3
X
N2
X
N1
X
N0
X
Header Bytes
(HDRx)
CLR
Status Byte
(Sx)
1
0
1
OTW
A4
UVLO
A3
CPUV
A2
OCP
A1
TSD
A0
OLD
X
Address Byte
(Ax)
R/W
D6
Data Byte
(Dx)
D7
D5
D4
D3
D2
D1
D0
图7-21. Contents of Header, Status, Address, and Data Bytes
When data passes through a device, it determines the position of itself in the chain by counting the number of
status bytes it receives followed by the first header byte. For example, in this 3-device configuration, device 2 in
the chain receives two status bytes before receiving the HDR1 byte which is then followed by the HDR2 byte.
From the two status bytes, the data can determine that its position is second in the chain. From the HDR2 byte,
the data can determine how many devices are connected in the chain. In this way, the data only loads the
relevant address and data byte in its buffer and bypasses the other bits. This protocol allows for faster
communication without adding latency to the system for up to 63 devices in the chain.
The address and data bytes remain the same with respect to a 1-device connection. The report bytes (R1
through R3), as shown in 图7-19, are the content of the register being accessed.
nSCS
SCLK
X
Z
MSB
MSB
LSB
LSB
X
Z
SDI
SDO
Capture
Point
Propagate
Point
图7-22. SPI Transaction
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7.6 Register Maps
表 7-18 lists the memory-mapped registers for the device. All register addresses not listed in 表 7-18 should be
considered as reserved locations and the register contents should not be modified.
表7-18. Memory Map
Register
Name
Access
Type
7
6
5
4
3
2
1
0
Address
FAULT Status
DIAG Status
IC1 Control
IC2 Control
IC3 Control
IC4 Control
RSVD
OL1
FAULT
OL2
OTW
ITRIP1
UVLO
CPUV
OCP_H1
SR
OCP
TSD
OLD
R
0x00
0x01
0x02
0x03
0x04
0x05
ITRIP2
OCP_L1
OCP_H2
OCP_L2
R
TOFF
SPI_IN
MODE
OCP_MODE
EN_IN1 PH_IN2
DIS_ITRIP
RW
RW
RW
RW
ITRIP_REP
CLR_FLT
RSVD
TSD_MODE
EN_OLP
OTW_REP
LOCK
DIS_CPUV
EN_OLA
OCP_TRETRY
OUT1_DIS
OUT2_DIS
OLP_DLY
ITRIP_LVL
Complex bit access types are encoded to fit into small table cells. 表 7-19 shows the codes that are used for
access types in this section.
表7-19. Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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7.6.1 Status Registers
The status registers are used to reporting warning and fault conditions. Status registers are read-only registers
表 7-20 lists the memory-mapped registers for the status registers. All register offset addresses not listed in 表
7-20 should be considered as reserved locations and the register contents should not be modified.
表7-20. Status Registers Summary Table
Address
0x00
Register Name
FAULT status
DIAG status
Section
Go
0x01
Go
7.6.2 FAULT Status Register Name (address = 0x00)
FAULT status is shown in 图7-23 and described in 表7-21.
Read-only
图7-23. FAULT Status Register
7
6
5
4
3
2
1
0
RSVD
FAULT
OTW
R-0b
UVLO
R-0b
CPUV
R-0b
OCP
R-0b
TSD
R-0b
OLD
R-0b
R-0b
表7-21. FAULT Status Register Field Descriptions
Bit
Field
Type
Default
Description
7
6
5
4
3
2
1
0
RSVD
FAULT
OTW
UVLO
CPUV
OCP
R
0b
Reserved
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
Global FAULT status register. Compliments the nFAULT pin
Indicates overtemperature warning
Indicates UVLO fault condition
Indicates charge-pump undervoltage fault condition
Indicates an overcurrent condition
TSD
Indicates an overtemperature shutdown
Indicates an open-load detection
OLD
7.6.3 DIAG Status Register Name (address = 0x01)
DIAG status is shown in 图7-24 and described in 表7-22.
Read-only
图7-24. DIAG Status Register
7
6
5
4
3
2
1
0
OL1
R-0b
OL2
R-0b
ITRIP1
R-0b
ITRIP2
R-0b
OCP_H1
R-0b
OCP_L1
R-0b
OCP_H2
R-0b
OCP_L2
R-0b
表7-22. DIAG Status Register Field Descriptions
Bit
Field
Type
Default
Description
7
6
OL1
R
0b
Indicates open-load detection on half bridge 1
Indicates open-load detection on half bridge 2
OL2
R
0b
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表7-22. DIAG Status Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
5
ITRIP1
R
0b
Indicates the current regulation status of half bridge 1.
0b = Indicates output 1 is not in current regulation
1b = Indicates output 1 is in current regulation
4
ITRIP2
R
0b
Indicates the current regulation status of half bridge 2.
0b = Indicates output 2 is not in current regulation
1b = Indicates output 2 is in current regulation
3
2
1
0
OCP_H1
OCP_L1
OCP_H2
OCP_L2
R
R
R
R
0b
0b
0b
0b
Indicates overcurrent fault on the high-side FET of half bridge 1
Indicates overcurrent fault on the low-side FET of half bridge 1
Indicates overcurrent fault on the high-side FET of half bridge 2
Indicates overcurrent fault on the low-side FET of half bridge 2
7.6.4 Control Registers
The IC control registers are used to configure the device. Status registers are read and write capable.
表 7-23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in 表
7-23 should be considered as reserved locations and the register contents should not be modified.
表7-23. Control Registers Summary Table
Address
0x02
Register Name
IC1 control
IC2 control
IC3 control
IC4 control
Section
Go
0x03
Go
0x04
Go
0x05
Go
7.6.5 IC1 Control Register (address = 0x02)
IC1 control is shown in 图7-25 and described in 表7-24.
Read/Write
图7-25. IC1 Control Register
7
6
5
4
3
2
1
0
TOFF
SPI_IN
R/W-0b
SR
MODE
R/W-01b
R/W-100b
R/W-01b
表7-24. IC1 Control Register Field Descriptions
Bit
Field
Type
Default
Description
7-6
TOFF
R/W
01b
00b = 20 µs
01b = 40 µs
10b = 60 µs
11b = 80 µs
5
SPI_IN
R/W
0b
0b = Outputs follow input pins (INx)
1b = Outputs follow SPI registers EN_IN1 and PH_IN2
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表7-24. IC1 Control Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
4-2
SR
R/W
100b
000b = 53.2-V/µs rise time
001b = 34-V/µs rise time
010b = 18.3-V/µs rise time
011b = 13-V/µs rise time
100b = 10.8-V/µs rise time
101b = 7.9-V/µs rise time
110b = 5.3-V/µs rise time
111b = 2.6-V/µs rise time
1-0
MODE
R/W
01b
00b = PH/EN
01b = PWM
10b = Independent half bridge
11b = Input disabled; bridge Hi-Z
7.6.6 IC2 Control Register (address = 0x03)
IC2 control is shown in 图7-26 and described in 表7-25.
Read/Write
图7-26. IC2 Control Register
7
6
5
4
3
2
1
0
ITRIP_REP
R/W-0b
TSD_MODE
R/W-0b
OTW_REP
R/W-0b
DIS_CPUV
R/W-0b
OCP_TRETRY
R/W-11b
OCP_MODE
R/W-00b
表7-25. IC2 Control Register Field Descriptions
Bit
Field
ITRIP_REP
Type
Default
Description
7
R/W
0b
0b = ITRIP is not reported on nFAULT or the FAULT bit
1b = ITRIP is reported on nFAULT and the FAULT bit
6
TSD_MODE
R/W
0b
0b = Overtemperature condition causes a latched fault
1b = Overtemperature condition causes an automatic recovery
fault
5
4
OTW_REP
R/W
R/W
R/W
0b
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
DIS_CPUV
0b
0b = Charge pump undervoltage fault is enabled
1b = Charge pump undervoltage fault is disabled
3-2
OCP_TRETRY
11b
00b = Overcurrent retry time is 0.5 ms
01b = Overcurrent retry time is 1 ms
10b = Overcurrent retry time is 2 ms
11b = Overcurrent retry time is 4 ms
1-0
OCP_MODE
R/W
00b
00b = Overcurrent condition causes a latched fault
01b = Overcurrent condition causes an automatic retrying fault
10b = Overcurrent condition is report only but no action is taken
11b = Overcurrent condition is not reported and no action is
taken
7.6.7 IC3 Control Register (address = 0x04)
IC3 control is shown in 图7-27 and described in 表7-26.
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Read/Write
图7-27. IC3 Control Register
7
6
5
4
3
2
1
0
CLR_FLT
R/W-0b
LOCK
OUT1_DIS
R/W-0b
OUT2_DIS
R/W-0b
EN_IN1
R/W-0b
PH_IN2
R/W-0b
R/W-100b
表7-26. IC3 Control Register Field Descriptions
Bit
Field
Type
Default
Description
7
CLR_FLT
R/W
0b
Write a 1b to this bit to clear the fault bits. This bit is
automatically reset after a write.
6-4
LOCK
R/W
100b
Write 011b to this register to lock all register settings in the IC1
control register except to these bits and address 0x04, bit 7
(CLR_FLT)
Write 100b to this register to unlock all register settings in the
IC1 control register
3
2
OUT1_DIS
OUT2_DIS
R/W
R/W
0b
0b
Enabled only in the Independent PWM mode
0b = Half bridge 1 enabled
1b = Half bridge 1 disabled (Hi-Z)
Enabled only in the Independent PWM mode
0b = Half bridge 2 enabled
1b = Half bridge 2 disabled (Hi-Z)
1
0
EN_IN1
PH_IN2
R/W
R/W
0b
0b
EN/IN1 bit to control the outputs through SPI (when SPI_IN =
1b)
PH/IN2 bit to control the outputs through SPI (when SPI_IN =
1b)
7.6.8 IC4 Control Register (address = 0x05)
IC4 control is shown in 图7-28 and described in 表7-27.
Read/Write
图7-28. IC4 Control Register
7
6
5
4
3
2
1
0
RSVD
R/W-0b
EN_OLP
R/W-0b
OLP_DLY
R/W-0b
EN_OLA
R/W-0b
ITRIP_LVL
R/W-10b
DIS_ITRIP
R/W-00b
表7-27. IC4 Control Register Field Descriptions
Bit
Field
Type
Default
Description
7
RSVD
R/W
0b
Reserved
6
5
4
EN_OLP
R/W
R/W
R/W
0b
0b
0b
Write 1b to run open load diagnostic in standby mode. When
open load test is complete EN_OLP returns to 0b (status check)
OLP_DLY
EN_OLA
0b = Open load diagnostic delay is 300 µs
1b = Open load diagnostic delay is 1.2 ms
0b = Open load diagnostic in active mode is disabled
1b = Enable open load diagnostics in active mode
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表7-27. IC4 Control Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
3-2
ITRIP_LVL
R/W
10b
00b = 4 A
01b = 5.4 A
10b = 6.5 A
11b = 7 A
1-0
DIS_ITRIP
R/W
00b
00b = Current regulation is enabled
01b = Current regulation is disabled for OUT1
10b = Current regulation is disabled for OUT2
11b = Current regulation is disabled for both OUT1 and OUT2
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The device is used mainly to drive a brushed DC motor. The on-board current regulation allows for limiting the
motor current during start-up and stall conditions. The design procedures in the 节 8.2 section highlight how to
use and configure the SPI version of the device.
8.2 Typical Application
图8-1 shows the typical application schematic for the SPI version of the device.
1 …F
VCC
1
24
23
22
21
20
19
DVDD
GND
10 kΩ
2
3
nFAULT
SDO
CPL
CPH
VCP
VM
47 nF
4
5
6
7
8
SDI
VVM
1 …F
SCLK
0.1 …F
>10 …F
nSCS
OUT1
OUT1
SRC
SRC
OUT2
OUT2
VM
SPI
Device
18
17
EN/IN1
PH/IN2
DISABLE
IPROPI1
nSLEEP
IPROPI2
16
15
14
13
9
BDC
10
11
VVM
12
0.1 …F
1.5 kΩ
1.5 kΩ
图8-1. Typical Application Schematic
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8.2.1 Design Requirements
表8-1 lists the example input parameters for the system design.
表8-1. Design Parameters
DESIGN PARAMETERS
Supply voltage
REFERENCE
VM
EXAMPLE VALUE
13.5 V
Motor RMS current
IRMS
2.5 A
Motor winding inductance
Motor current trip point
PWM frequency
LM
2.9 mH
6.5 A
ITRIP
fPWM
10 kHz
Sense resistor
RSENSE
tSR
1.5 kΩ
1 µs
Rise and fall times (slew rate)
8.2.1.1 Motor Voltage
The motor voltage used depends on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
8.2.1.2 Drive Current and Power Dissipation
The current path is through the high-side sourcing power driver, motor winding, and low-side sinking power
driver. The amount of current the device can drive depends on the power dissipation without going into thermal
shutdown. The amount of current that can be power dissipation losses in one source and sink power driver are
calculated in 方程式2.
PD = (IRMS)2 × (RDS(on)High-side + RDS(on)Low-side
)
(2)
The IOUT current is equal to the average current drawn by the DC motor. At 25°C ambient temperature, the
power dissipation becomes (2.5 A)2 × (150 mΩ) = 0.94 W.
The temperature that the device reaches depends on the thermal resistance to the air and PCB. Soldering the
device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers, is important to
dissipate heat into the PCB and reduce the device temperature. In the example used here, the device had an
effective thermal resistance RθJA of 27.8°C/W. The junction temperature TJ value becomes as shown in 方程式
3.
TJ = TA + (PD × RθJA) = 25°C + (0.94 W × 27.8°C/W) = 51°C
(3)
备注
The values of RDS(on) increases with temperature, so as the device heats, the power dissipation
increases. This fact must be taken into consideration when sizing the heatsink.
At start-up and fault conditions, the current flowing through the motor is much higher than normal running
current; these peak currents and their duration must also be considered. High PWM frequency also results in
higher switching losses. Typically, switching the inputs at 100 kHz compared to 10 kHz causes 20% more power
loss in heat.
Power dissipation in the device is dominated by the power dissipated of the internal MOSFET resistance. The
maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Total power dissipation for the device is composed of three main components. These are the quiescent supply
current dissipation, the power MOSFET switching losses, and the power MOSFET RDS(ON) (conduction) losses.
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While other factors may contribute additional power losses, these other items are typically insignificant compared
to the three main items.
PTOT = PVM + PSW + PD
(4)
PVM can be calculated from the nominal supply voltage (VM) and the supply current (IVM) in active mode.
PVM = VM × IVM = 13.5 V × 5 mA = 67.5 mW
(5)
PSW can be calculated from the nominal supply voltage (VM), average output current (IRMS), switching frequency
(fPWM) and the device output rise and fall times (tSR) time specifications.
PSW = PSW_RISE + PSW_FALL = 0.17 W + 0.17 W = 0.34 W
(6)
(7)
(8)
PSW_RISE = 0.5 × VM × IRMS × tSR × fPWM = 0.5 × 13.5 V × 2.5 A × 1 µs × 10 kHz = 0.17 W
PSW_FALL = 0.5 × VM × IRMS × tSR × fPWM = 0.5 × 13.5 V × 2.5 A × 1 µs × 10 kHz = 0.17 W
Therefore, total power dissipation (PTOT) at 25°C ambient temperature becomes = PVM + PSW + PD = 67.5 mW +
0.34 W + 0.94 W = 1.35 W
PTOT makes the junction temperature (TJ) of the device to be
TJ = TA + (PTOT × RθJA) = 25°C + (1.35 W × 27.8°C/W) = 63°C
(9)
The power dissipation from power MOSFET switching losses and quiescent supply current dissipation results is
approximately 12°C rise in the junction temperature (different between 方程式 9 and 方程式 3). Care must be
taken when doing the PCB layout and heatsinking the motor driver device so that the thermal characteristics are
properly managed.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDY7
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Trace 0.22 × 34.5mm
at 0.65mm pitch
A
PTH via at 2.54mm pitch
Drill 300u; plate 18µ
Array to fit the copper area
PTH via at 1.2mm pitch
Drill 300µ; plate 18µ
A
3.2mm
Copper (Cu)
Area
Dimension A
(mm)
(cm2)
2
4
17.9
23.9
32.2
44.0
60.6
74.2
8
16
32
49.23
8.2mm
图8-2. PCB Model (4-Layer PCB Shown, 2-Layer PCB Has No Vias)
30
29
28
27
26
25
24
23
22
21
6.1
1oz
2oz
1oz
2oz
6.05
6
5.95
5.9
5.85
5.8
5.75
20
0
0
10
20
30
40
50
10
20
30
40
50
Copper Area (cm2)
Copper Area (cm2)
D008
D007
图8-4. 4-Layer PCB Junction-to-Board
Characterization Parameter vs Copper Area
图8-3. 4-Layer PCB Junction-to-Ambient Thermal
Resistance vs Copper Area
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80
70
60
50
40
30
20
13
12
11
10
9
1oz
2oz
1oz
2oz
8
7
0
10
20
30
40
50
0
10
20
30
40
50
Copper Area (cm2)
Copper Area (cm2)
D009
Dd0r1v08
图8-5. 2-Layer PCB (No Vias) Junction-to-Ambient 图8-6. 2-Layer PCB (No Vias) Junction-to-Board
Thermal Resistance vs Copper Area
Characterization Parameter vs Copper Area
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8.2.1.3 Sense Resistor
For optimal performance, the sense resistor must have the following features:
• Surface-mount device
• Low inductance
• Placed closely to the motor driver device
Use 方程式10 to calculate the power dissipation (PD) of the sense resistor.
PD = (I(RMS) / k)2 × R(SENSE)
(10)
In this example, for the RMS motor current is 2.5 A, the sense resistor of 1.5 kΩ dissipates approximately 7.5
mW of power. The power quickly increases with higher current levels. Resistors typically have a rated power
within some ambient temperature range, along with a derated power curve for high ambient temperatures. When
a PCB is shared with other components that generate heat, the system designer should add margin. Measuring
the actual sense resistor temperature in a final system is best.
8.2.2 Detailed Design Procedure
8.2.2.1 Thermal Considerations
The device has thermal shutdown (TSD) at 165°C (mininum). If the die temperature exceeds this TSD threshold,
the device will be disabled until the temperature drops below the temperature hysteresis level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high of an ambient temperature.
8.2.2.2 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground
plane.
On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
For details about how to design the PCB, refer to the PowerPAD™ Thermally Enhanced Package application
report, and the PowerPAD™ Made Easy application report, available at www.ti.com. In general, the more copper
area that can be provided, the more power can be dissipated.
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8.2.3 Application Curves
图8-8. Current Regulation (ITRIP)
图8-7. Overcurrent (OCP) Detection
图8-9. ITRIP Across TOFF and Load Current
图8-10. Motor Motion at Different Speeds
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9 Power Supply Recommendations
The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic
capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk
capacitor must be placed on the VM pin.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图9-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values
of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace
or ground plane connection to the device GND pin.
Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed
such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as
possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk
capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.
The current sense resistors should be placed as close as possible to the device pins to minimize trace
inductance between the device pin and resistors.
10.2 Layout Example
+
1 µF
0.1 µF
1
2
24
23
22
21
20
19
18
17
16
15
14
13
DVDD
nFAULT
SDO
GND
CPL
CPH
VCP
VM
3
47 nF
1 µF
4
SDI
5
SCLK
6
nSCS
OUT1
OUT1
SRC
7
EN/IN1
PH/EN2
DISABLE
IPROPI1
nSLEEP
IPROPI2
8
9
SRC
10
11
12
OUT2
OUT2
VM
0.1 µF
图10-1. Layout Example
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDY7
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Daisy Chain Implementation for Serial Peripheral Interface application report
• Texas Instruments, DRV8873x-Q1EVM User’s Guide
• Texas Instruments, DRV8873x-Q1EVM GUI User's Guide
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430™ application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
PowerPAD™ and MSP430™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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English Data Sheet: SLVSDY7
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8873HPWPRQ1
DRV8873SPWPRQ1
PDRV8873SPWPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
24
24
2000 RoHS & Green
2000 RoHS & Green
TBD
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
-40 to 125
-40 to 125
8873HQ
8873SQ
Samples
Samples
NIPDAU
Call TI
OBSOLETE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV8873-Q1 :
Catalog : DRV8873
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8873HPWPRQ1
DRV8873SPWPRQ1
HTSSOP PWP
HTSSOP PWP
24
24
2000
2000
330.0
330.0
16.4
16.4
6.95
6.95
8.3
8.3
1.6
1.6
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8873HPWPRQ1
DRV8873SPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
24
24
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 24
4.4 x 7.6, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024J
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
22X 0.65
PLANE
24
1
2X
7.9
7.7
7.15
NOTE 3
12
B
13
0.30
24X
4.5
4.3
0.19
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 2.08 MAX
NOTE 5
4X 0.3 MAX
13
4X 0.1 MAX
NOTE 5
12
0.25
GAGE PLANE
1.2 MAX
5.26
5.11
25
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
24
3.20
3.05
4225860/A 04/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0024J
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.2)
METAL COVERED
BY SOLDER MASK
SYMM
24X (1.5)
1
24
24X (0.45)
SEE DETAILS
(R0.05) TYP
(5.26)
22X (0.65)
SYMM
25
(7.8)
NOTE 9
(1.2) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
13
12
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4225860/A 04/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024J
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.2)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
24X (1.5)
1
24
24X (0.45)
(R0.05) TYP
22X (0.65)
SYMM
(5.26)
25
BASED ON
0.125 THICK
STENCIL
12
13
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.58 X 5.88
3.20 X 5.26 (SHOWN)
2.92 X 4.80
0.125
0.15
0.175
2.70 X 4.45
4225860/A 04/2020
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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Copyright © 2023，德州仪器 (TI) 公司
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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