DRV8880RHRT [TI]
具有电流调节、1/16 微步进和智能调优功能的 45V、2A 双极步进电机驱动器 | RHR | 28 | -40 to 125;
| 型号： | DRV8880RHRT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流调节、1/16 微步进和智能调优功能的 45V、2A 双极步进电机驱动器 | RHR | 28 | -40 to 125 电机 驱动 驱动器 |
| 文件： | 总51页 (文件大小：2518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8880
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
DRV8880 具有 AutoTune™ 功能的 2A 步进电机驱动器
1 特性
2 应用
1
•
微步进电机驱动器
•
•
•
•
•
•
自动取款机和验钞机
视频安保摄像机
–
–
–
STEP/DIR 接口
多功能打印机和文档扫描仪
3D 打印机
最高 1/16 的微步进分度器
非循环和标准 ½ 步进模式
办公自动化设备
•
•
6.5V 至 45V 的工作电源电压范围
工厂自动化和机器人
多种衰减模式，可为任何电机提供支持
–
–
–
–
AutoTune™
混合衰减
慢速衰减
快速衰减
3 说明
DRV8880 是一款适用于工业 应用的双极步进电机驱动
器。该器件具有两个 N 沟道功率金属氧化物半导体场
效应晶体管 (MOSFET) H 桥驱动器和一个微步进分度
器。DRV8880 能够驱动高达 2.0A 的满量程电流或
1.4A 均方根 (rms) 电流（采用适当的印刷电路板
(PCB) 接地层进行散热，电压为 24V，TA = 25°C）。
•
•
平滑步进的自适应消隐时间
可配置关断时间脉宽调制 (PWM) 斩波
–
10、20 或 30μs 关断时间
•
•
•
3.3V，10mA 低压降 (LDO) 稳压器
低电流休眠模式 (28μA)
小型封装尺寸
AutoTune™ 可自动调整步进电机以实现最佳电流调节
性能，并且能够对电机变化和老化问题进行补偿。此
外，该器件还提供慢速、快速和混合三种衰减模式。
–
–
28 HTSSOP (PowerPAD™)
28 WQFN
STEP/DIR 引脚提供简单的控制接口。器件可配置为多
种步进模式，从全步进模式到 1/16 步进模式。凭借专
用的 nSLEEP 引脚，该器件可提供一种低功耗的休眠
模式，从而实现超低静态电流待机。
•
保护 特性
–
–
–
–
VM 欠压锁定 (UVLO2)
逻辑欠压 (UVLO1)
电荷泵电压 (CPUV)
过流保护 (OCP)
该器件内置以下保护功能：欠压、电荷泵故障、过流、
短路以及过热保护。故障条件通过 nFAULT 引脚指
示。
–
–
锁存过流保护 (OCP) 模式
重试过流保护 (OCP) 模式
器件信息(1)
–
–
热关断 (TSD)
故障条件指示引脚 (nFAULT)
器件型号
DRV8880
封装
HTSSOP (28)
WQFN (28)
封装尺寸（标称值）
9.70mm x 4.40mm
5.50mm × 3.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化系统图
微步进电流波形
Full-scale current
6.ꢁ to 4ꢁ ë
RMS current
5wë8880
{Ç9ꢀ/5Lw
2.0 !
2.0 !
M
{tepper
ꢃotor 5river
{tep size
+
-
5ecay mode
!µš}ǵvꢀ¡
AOUT
BOUT
1/16 µstep
Step Input
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD18
DRV8880
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 30
Application and Implementation ........................ 31
8.1 Application Information............................................ 31
8.2 Typical Application ................................................. 31
Power Supply Recommendations...................... 35
9.1 Bulk Capacitance Sizing ......................................... 35
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Indexer Timing Requirements................................... 8
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 36
11 器件和文档支持 ..................................................... 37
11.1 文档支持................................................................ 37
11.2 接收文档更新通知 ................................................. 37
11.3 社区资源................................................................ 37
11.4 商标....................................................................... 37
11.5 静电放电警告......................................................... 37
11.6 Glossary................................................................ 37
12 机械、封装和可订购信息....................................... 37
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (August 2017) to Revision C
Page
•
Changed the maximum value for VREF from V3P3 + 0.5 V to 4.1 V in the Absolute Maximum Ratings table .................... 5
Changes from Revision A (July 2015) to Revision B
Page
•
•
Added the Power Supplies and Input Pins section .............................................................................................................. 27
已添加 接收文档更新通知部分.............................................................................................................................................. 37
Changes from Original (June 2015) to Revision A
Page
•
•
已将器件状态更新为量产数据 ................................................................................................................................................. 1
Updated from "PowerPAD" to "thermal pad" ......................................................................................................................... 4
2
Copyright © 2015–2017, Texas Instruments Incorporated
DRV8880
www.ti.com.cn
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
5 Pin Configuration and Functions
PWP PowerPAD™ Package
28-Pin HTSSOP
RHR Package
28-Pin WQFN With Exposed Thermal Pad
Top View
Top View
1
2
28
27
26
/t[
/tI
Db5
Çwv0
Çwv1
a0
3
ë/t
1
2
24
23
22
21
20
19
18
17
16
15
VCP
VM
TRQ1
M0
4
25
24
23
22
21
20
19
18
17
16
15
ëa
5
!hÜÇ1
!L{9b
!hÜÇ2
.hÜÇ2
.L{9b
.hÜÇ1
ëa
a1
3
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
M1
4
6
STEP
{Ç9t
5
DIR
7
5Lw
6
ENABLE
DECAY0
DECAY1
nFAULT
nSLEEP
8
9b!.[9
59/!ò0
59/!ò1
nC!Ü[Ç
n{[99t
ÇhCC
7
9
8
10
11
12
13
14
9
10
GND
Db5
!Ç9
ëw9C
ë3t3
Pin Functions
PIN
PWP
1
TYPE
DESCRIPTION
NAME
CPL
RHR
27
Charge pump switching
pins
Connect a VM rated, 0.1-µF ceramic capacitor between
CPH and CPL
PWR
CPH
VCP
2
28
3
1
O
Charge pump output
Power supply
Connect a 16 V, 0.47 µF ceramic capacitor to VM
Connect to motor supply voltage; bypass to GND with two
0.1 µF (for each pin) plus one bulk capacitor rated for VM
VM
4, 11
2, 9
PWR
AOUT1
AOUT2
5
7
3
5
H-bridge outputs, drives one winding of a stepper motor
O
O
O
Winding A output
Winding A sense
Winding B output
Requires sense resistor to GND; value sets peak current
in winding A
AISEN
6
4
BOUT2
BOUT1
8
6
8
H-bridge outputs, drives one winding of a stepper motor
10
Requires sense resistor to GND; value sets peak current
in winding B
BISEN
GND
9
7
O
Winding B sense
Device ground
12, 28
10, 26
PWR
Must be connected to ground
Logic high enables AutoTune operation; when logic low,
the decay mode is set through the DECAYx pins;
AutoTune must be pulled high prior to power-up or coming
out of sleep, or else tied to V3P3 in order to enable
AutoTune; internal pulldown; see AutoTune
ATE
13
11
I
AutoTune enable pin
Full scale current
reference input
Voltage on this pin sets the full scale chopping current.
VREF
14
12
I
Internal supply voltage; bypass to GND with a 6.3 V, 0.47
µF ceramic capacitor; up to 10 mA external load
V3P3
15
16
17
13
14
15
PWR
Internal regulator
TOFF
I
I
Decay mode off time set
Sleep mode input
Sets the off-time during current chopping; tri-level pin
Logic high to enable device; logic low to enter low-power
sleep mode; internal pulldown
nSLEEP
Pulled logic low with fault condition; open-drain output
requires an external pullup
nFAULT
18
16
O
I
Fault indication pin
DECAY1
DECAY0
19
20
17
18
Sets the decay mode; see description section; tri-level pin
Decay mode setting pins
Logic high to enable device outputs and internal indexer;
logic low to disable; internal pulldown
ENABLE
DIR
21
22
19
20
I
I
Enable driver input
Direction input
Logic level sets the direction of stepping; internal pulldown
Copyright © 2015–2017, Texas Instruments Incorporated
3
DRV8880
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
STEP
PWP
RHR
A rising edge causes the indexer to advance one step;
internal pulldown
23
21
I
I
Step input
M1
24
25
22
23
Sets the step mode; full, 1/2, 1/4, 1/8, 1/16; tri-level pin
Microstepping mode
setting pins
M0
TRQ1
TRQ0
PAD
26
24
Scales the current by 100%, 75%, 50%, or 25%; internal
pulldown
Torque DAC current
scalar
I
27
25
PAD
PAD
PWR
Thermal pad
Must be connected to ground
4
Copyright © 2015–2017, Texas Instruments Incorporated
DRV8880
www.ti.com.cn
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
MIN
MAX
50
UNIT
V
Power supply voltage (VM)
–0.3
0
Power supply voltage ramp rate (VM)
Charge pump voltage (VCP, CPH)
Charge pump negative switching pin (CPL)
Internal regulator voltage (V3P3)
Internal regulator current output (V3P3)
2
V/µs
V
–0.3
–0.3
–0.3
0
VM + 12
VM
V
3.8
V
10
mA
Control pin voltage (STEP, DIR, ENABLE, nSLEEP, nFAULT, M0, M1, DECAY0,
DECAY1, TRQ0, TRQ1, ATE)
–0.3
7.0
V
Open drain output current (nFAULT)
0
10
4.1
mA
V
Reference input pin voltage (VREF)
–0.3
–0.7
–0.55
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
VM + 0.7
0.55
V
(2)
Continuous shunt amplifier input pin voltage (AISEN, BISEN)
V
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN)
Operating junction temperature, TJ
Internally limited
A
–40
–65
150
150
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
Electrostatic
discharge
V(ESD)
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
45
UNIT
V
(1)
VM
Power supply voltage range
Digital pin voltage range
Reference rms voltage range
Applied STEP signal
6.5
VIN
0
5.3
V
(2)
VREF
ƒPWM
IV3P3
IFS
0.3
V3P3
V
(3)
0
0
0
0
100
kHz
mA
A
(4)
V3P3 external load current
Motor full scale current
Motor rms current
10
2.0
1.4
Irms
A
TA
Operating ambient temperature
–40
125
°C
(1) Internal logic and indexer remain active down to VUVLO2 (4.9 V maximum) even though the output H-bridges are disabled
(2) Operational at VREF ≈ 0 to 0.3 V, but accuracy is degraded
(3) STEP input can operate up to 1 MHz, but system bandwidth is limited by the motor load
(4) Power dissipation and thermal limits must be observed
Copyright © 2015–2017, Texas Instruments Incorporated
5
DRV8880
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
www.ti.com.cn
6.4 Thermal Information
DRV8880
PWP (HTSSOP)
(1)
THERMAL METRIC
RHR (WQFN)
UNIT
28 PINS
33.1
16.6
14.4
0.4
28 PINS
37.5
23.0
8.0
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
14.2
1.3
7.8
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, V3P3)
VM
VM operating voltage
6.5
45
18
V
nSLEEP high; ENABLE high; no motor
load; VM = 24 V
IVM
VM operating supply current
8
mA
nSLEEP low; VM = 24 V; TA = 25°C
28
IVMQ
VM sleep mode supply current
μA
nSLEEP low; VM = 24 V; TA = 125°C
77
(1)
tSLEEP
tWAKE
tON
Sleep time
nSLEEP low to sleep mode
nSLEEP high to output transition
VM > VUVLO2 to output transition
External load 0 to 10 mA
100
1.5
1.5
3.6
μs
ms
ms
V
Wake-up time
Turn-on time
V3P3
LDO regulator voltage
2.9
3.3
CHARGE PUMP (VCP, CPH, CPL)
VM > 12 V
VM + 11.5
VCP
VCP operating voltage
V
VUVLO2 < VM < 12 V
2×VM – 1.5
Charge pump switching
frequency
(1)
ƒVCP
VM > VUVLO2
175
715
kHz
LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, TRQ0, TRQ1, ATE)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
0
1.6
100
–1
0.6
5.3
V
V
mV
μA
μA
kΩ
ns
VIN = 0 V
1
IIH
VIN = 5.0 V
50
100
450
100
RPD
tPD
Measured between the pin and GND
STEP input to current change
TRI-LEVEL INPUTS (M0, M1, DECAY0, DECAY1, TOFF)
VIL
VIZ
VIH
VHYS
IIL
Tri-level input logic low voltage
Tri-level input Hi-Z voltage
Tri-level input logic high voltage
Tri-level input hysteresis
0
0.6
5.3
V
V
1.1
1.6
100
–55
V
mV
μA
μA
μA
kΩ
kΩ
Tri-level input logic low current
Tri-level input Hi-Z current
Tri-level input logic high current
Tri-level pulldown resistance
Tri-level pullup resistance
VIN = 0 V
–35
IIZ
VIN = 1.3 V
15
85
40
45
IIH
VIN = 3.3 V
RPD
RPU
Measured between the pin and GND
Measured between V3P3 and the pin
(1) Specified by design and characterization data
6
Copyright © 2015–2017, Texas Instruments Incorporated
DRV8880
www.ti.com.cn
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONTROL OUTPUTS (nFAULT)
VOL
IOH
Output logic low voltage
Output logic high leakage
IO = 4 mA
External pullup resistor to 3.3 V
0.5
1
V
–1
μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
VM = 24 V, I = 1 A, TA = 25°C
330
400
430
500
300
370
370
450
(1)
VM = 24 V, I = 1 A, TA = 125°C
VM = 6.5 V, I = 1 A, TA = 25°C
VM = 6.5 V, I = 1 A, TA = 125°C
VM = 24 V, I = 1 A, TA = 25°C
VM = 24 V, I = 1 A, TA = 125°C
VM = 6.5 V, I = 1 A, TA = 25°C
VM = 6.5 V, I = 1 A, TA = 125°C
440
560
400
490
RDS(ON)
High-side FET on resistance
Low-side FET on resistance
mΩ
mΩ
(1)
(1)
RDS(ON)
(1)
VM = 24 V, 50 Ω load from xOUTx to
GND
tRISE
tFALL
Output rise time
Output fall time
70
70
ns
ns
VM = 24 V, 50 Ω load from VM to
xOUTx
(2)
tDEAD
Vd
Output dead time
200
0.7
ns
V
Body diode forward voltage
IOUT = 0.5 A
1
PWM CURRENT CONTROL (VREF, AISEN, BISEN)
TRQ at 100%, VREF = 3.3 V
500
375
250
125
6.58
6.56
6.51
6.38
20
TRQ at 75%, VREF = 3.3 V
TRQ at 50%, VREF = 3.3 V
TRQ at 25%, VREF = 3.3 V
TRQ at 100% (TRQ0 = 0, TRQ1 = 0)
TRQ at 75% (TRQ0 = 1, TRQ1 = 0)
TRQ at 50% (TRQ0 = 0, TRQ1 = 1)
TRQ at 25% (TRQ0 = 1, TRQ1 = 1)
TOFF Logic Low
VTRIP
xISENSE trip voltage, full scale
mV
6.25
6.2
6.91
6.92
6.94
6.93
AV
Amplifier attenuation
PWM off-time
V/V
μs
6.09
5.83
tOFF
TOFF Logic High
30
TOFF Hi-Z
10
1.8
1.5
tBLANK
PWM blanking time
See Table 9 for details
µs
1.2
0.9
PROTECTION CIRCUITS
VUVLO2 VM undervoltage lockout
VM falling; UVLO2 report
VM rising; UVLO2 recovery
VM falling; logic disabled
VM rising; logic enabled
Rising to falling threshold
VCP falling; CPUV report
VCP rising; CPUV recovery
Rising to falling threshold
Current through any FET
Voltage at AISEN or BISEN
5.8
6.1
4.5
4.8
6.4
6.5
4.9
5
V
VUVLO1
VUVLO,HYS undervoltage hysteresis
VCPUV Charge pump undervoltage
VCPUV,HYS CP undervoltage hysteresis
Logic undervoltage
V
mV
V
100
VM + 1.8
VM + 1.9
50
2.5
0.9
mV
A
IOCP
VOCP
tOCP
Overcurrent protection trip level
Sense pin overcurrent trip level
Overcurrent deglitch time
3.6
1.25
2
V
μs
(2) Specified by design and characterization data
Copyright © 2015–2017, Texas Instruments Incorporated
7
DRV8880
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.5
TYP
MAX
UNIT
ms
tRETRY
Overcurrent retry time
2
(2)
TTSD
THYS
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature TJ
Die temperature TJ
150
°C
(2)
35
°C
6.6 Indexer Timing Requirements
NO.
MIN
MAX
UNIT
(1)
1
2
3
4
5
ƒSTEP
Step frequency
1
MHz
ns
tWH(STEP)
tWL(STEP)
tSU(DIR, Mx)
tH(DIR, Mx)
Pulse duration, STEP high
Pulse duration, STEP low
Setup time, DIR or Mx to STEP rising
Hold time, DIR or Mx to STEP rising
470
470
200
200
ns
ns
ns
(1) STEP input can operate up to 1 MHz, but system bandwidth is limited by the motor load
1
3
2
STEP
DIR, Mx
5
4
Figure 1. Timing Diagram
8
Copyright © 2015–2017, Texas Instruments Incorporated
DRV8880
www.ti.com.cn
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
6.7 Typical Characteristics
Over recommended operating conditions (unless otherwise noted)
6.5
6.45
6.4
6.35
6.3
6.25
6.2
6.35
6.3
6.15
6.1
6.25
6.2
6.15
6.1
6.05
6
6.05
6
5.95
5.9
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
5.95
5.85
5.8
5.9
VM = 24 V
VM = 12 V
5.85
5.8
5.75
5
10
15
20
25
30
35
40
45
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D001
D002
Figure 2. Supply Current over VM
Figure 3. Supply Current over Temperature
28
26
24
22
20
18
16
14
12
10
8
25.5
25
24.5
24
23.5
23
22.5
22
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VM = 24 V
VM = 12 V
21.5
6
21
6
9
12
15
18
21
24
27
30
33
36
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D003
D004
Figure 4. Sleep Current over VM
Figure 5. Sleep Current over Temperature
700
650
600
550
500
450
400
350
300
250
200
550
500
450
400
350
300
250
200
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
5
10
15
20
25
30
35
40
45
50
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D005
D006
Figure 6. High-Side RDS(ON) over VM
Figure 7. High-Side RDS(ON) over Temperature (VM = 12 V)
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Typical Characteristics (continued)
Over recommended operating conditions (unless otherwise noted)
600
480
450
420
390
360
330
300
270
240
210
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
550
500
450
400
350
300
250
200
5
10
15
20
25
30
35
40
45
50
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D007
D008
Figure 8. Low-Side RDS(ON) over VM
Figure 9. Low-Side RDS(ON) over Temperature (VM = 12 V)
3.36
0.5
TRQ = 00
TRQ = 01
TRQ = 10
TRQ = 11
0.45
0.4
3.355
3.35
0.35
0.3
3.345
3.34
0.25
0.2
3.335
0.15
0.1
3.33
3.325
3.32
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.05
0
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
2.5
3
3.5
VREF Pin Voltage (V)
V3P3 Load (mA)
D009
D010
Figure 10. xISEN Full-Scale Trip Voltage over VREF Input
Figure 11. V3P3 Regulator over Load (VM = 24 V)
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7 Detailed Description
7.1 Overview
The DRV8880 is an integrated motor driver solution for bipolar stepper motors. The device integrates two NMOS
H-bridges, current regulation circuitry, and a microstepping indexer. The DRV8880 can be powered with a supply
voltage between 6.5 and 45 V, and is capable of providing an output current up to 2.5 A peak current, 2.0 A full-
scale current, or 1.4 A rms current. Actual operable full-scale and rms current will depend on ambient
temperature, supply voltage, and PCB ground plane size. Between VM = 6.4 V and VM = 4.9 V the H-bridge
outputs are shut down, but the internal logic remains active in order to prevent missed steps.
A simple STEP/DIR interface allows easy interfacing to the controller circuit. The internal indexer is able to
execute high-accuracy microstepping without requiring the processor to control the current level. The indexer is
capable of full step and half step as well as microstepping to 1/4, 1/8, and 1/16. In addition to the standard half
stepping mode, a non-circular 1/2-stepping mode is avaialble for increased torque output at higher motor rpm.
The current regulation is highly configurable, with several decay modes of operation. The decay mode can be
selected as a fixed slow, slow/mixed, mixed, slow/fast, or fast decay. The slow/mixed decay mode uses slow
decay on increasing steps and mixed decay on decreasing steps. Similarly, the slow/fast decay mode uses slow
decay on increasing steps and fast decay on decreasing steps.
In addition, an AutoTune mode can be used which automatically adjusts the decay setting to minimize current
ripple while still reacting quickly to step changes. This feature greatly simplifies stepper driver integration into a
motor drive system.
The PWM off-time, tOFF, can be adjusted to 10, 20, or 30 µs.
An adaptive blanking time feature automatically scales the minimum drive time with output current. This helps
alleviate zero-crossing distortion by limiting the drive time at low-current steps.
A torque DAC feature allows the controller to scale the output current without needing to scale the analog
reference voltage input VREF. The torque DAC is accessed using digital input pins. This allows the controller to
save power by decreasing the current consumption when not required.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
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7.2 Functional Block Diagram
VM
+
0.1 µF
0.1 µF
bulk
VM
VM
VM
VM
Power
0.47 µF
0.1 µF
VCP
CPH
CPL
AutoTune
AOUT1
AOUT2
+
Charge
Pump
Off-
time
PWM
Gate
Drive
Step
Motor
VM
-
V3P3
10 mA
3.3-V LDO
0.47 µF
+
-
STEP
DIR
AISEN
RSENSE
+
Core Logic
-
VREF
TRQ[1:0]
ENABLE
nSLEEP
ATE
4
{Lb9 5!/
1ꢀ!v
Control
Inputs
TRQ[1:0]
M[1:0]
VM
V3P3
V3P3
BOUT1
BOUT2
DECAY[1:0]
TOFF
Indexer
V3P3
Off-
time
PWM
VM
Gate
Drive
VREF
Analog
Input
Protection
Overcurrent
BISEN
RSENSE
Output
+
nFAULT
Undervoltage
Thermal
-
VREF
TRQ[1:0]
4
{Lb9 5!/
1ꢀ!v
GND GND PPAD
12
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7.3 Feature Description
Table 1 lists the recommended values of the external components.
Table 1. External Components
COMPONENT
CVM1
PIN 1
VM
PIN 2
GND
GND
RECOMMENDED
0.1-µF ceramic capacitor rated for VM per VM pin
CVM1
VM
Bulk electrolytic capacitor rated for VM, recommended value is 100
µF, see Bulk Capacitance Sizing
CVCP
CSW
VCP
CPH
V3P3
VM
CPL
16-V, 0.47-µF ceramic capacitor
0.1-µF X7R capacitor rated for VM
6.3-V, 0.47-µF ceramic capacitor
> 5 kΩ pullup
CV3P3
RnFAULT
RAISEN
RBISEN
GND
(1)
VMCU
nFAULT
GND
AISEN
BISEN
Sense resistor, see Sense Resistor
GND
(1) VMCU is not a pin on the DRV8880, but a supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled up to
V3P3
7.3.1 Stepper Motor Driver Current Ratings
Stepper motor drivers can be classified using three different numbers to describe the output current: peak, rms,
and full-scale.
7.3.1.1 Peak Current Rating
The peak current in a stepper driver is limited by the overcurrent protection trip threshold IOCP. The peak current
describes any transient duration current pulse, for example when charging capacitance, when the overall duty
cycle is very low. In general the minimum value of IOCP specifies the peak current rating of the stepper motor
driver. For the DRV8880, the peak current rating is 2.5 A per bridge.
7.3.1.2 RMS Current Rating
The rms (average) current is determined by the thermal considerations of the IC. The rms current is calculated
based on the RDS(ON), rise and fall time, PWM frequency, device quiescent current, and package thermal
performance in a typical system at 25°C. The real operating rms current may be higher or lower depending on
heatsinking and ambient temperature. For the DRV8880, the rms current rating is 1.4 A per bridge.
7.3.1.3 Full-Scale Current Rating
The full-scale current describes the top of the sinusoid current waveform while microstepping. Since the
sineusoid amplitude is related to the rms current, the full-scale current is also determined by the thermal
considerations of the IC. The full-scale current rating is approximately √2 × Irms. The full-scale current is set by
VREF, the sense resistor, and Torque DAC when configuring the DRV8880 , see Current Regulation for details.
For the DRV8880, the full-scale current rating is 2.0 A per bridge.
Full-scale current
RMS current
AOUT
BOUT
Step Input
Figure 12. Full-Scale and rms Current
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7.3.2 PWM Motor Drivers
The DRV8880 contains drivers for two full H-bridges. A block diagram of the circuitry is shown in Figure 13.
VM
xOUT1
+
Step
Motor
tía
[ogic
Dꢀꢁe
5rive
VM
-
5evice
[ogic
xOUT2
xISEN
+
-
+
-
VREF
TRQ[1:0]
RSENSE
4
{Lb9 5!/
1ꢀ!v
Figure 13. PWM Motor Driver Block Diagram
7.3.3 Microstepping Indexer
Built-in indexer logic in the DRV8880 allows a number of different stepping configurations. The Mx pins are used
to configure the stepping format as shown in Table 2.
Table 2. Microstepping Settings
M1
M0
STEP MODE
Full step (2-phase excitation) with 71%
current
0
0
0
1
1
0
1
Z
Z
Z
1
0
1
Z
Z
0
1
Z
Non-circular 1/2 step
1/2 step
1/4 step
1/8 step
1/16 step
Reserved
Reserved
Reserved
Table 3 shows the relative current and step directions for full-step through 1/16-step operation. The AOUT
current is the sine of the electrical angle; BOUT current is the cosine of the electrical angle. Positive current is
defined as current flowing from xOUT1 to xOUT2 while driving.
At each rising edge of the STEP input the indexer travels to the next state in the table. The direction is shown
with the DIR pin logic high. If the DIR pin is logic low, the sequence is reversed.
Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new
MODE setting at the rising edge of STEP.
The home state is an electrical angle of 45°. This state is entered after power-up, after exiting logic undervoltage
lockout, or after exiting sleep mode. This is shown in Table 3 with the highlighted row.
14
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Table 3. Microstepping Relative Current Per Step
FULL
STEP
ELECTRICAL ANGLE
(°)
AOUT CURRENT
(% full-scale)
BOUT CURRENT
(% full-scale)
1/2 STEP 1/4 STEP 1/8 STEP 1/16 STEP
1
2
3
4
5
6
1
1
1
0.000°
5.625°
0%
10%
20%
29%
38%
47%
56%
63%
71%
77%
83%
88%
92%
96%
98%
100%
100%
100%
98%
96%
92%
88%
83%
77%
71%
63%
56%
47%
38%
29%
20%
10%
0%
100%
100%
98%
2
2
3
11.250°
16.875°
22.500°
28.125°
33.750°
39.375°
45.000°
50.625°
56.250°
61.875°
67.500°
73.125°
78.750°
84.375°
90.000°
95.625°
101.250°
106.875°
112.500°
118.125°
123.750°
129.375°
135.000°
140.625°
146.250°
151.875°
157.500°
163.125°
168.750°
174.375°
180.000°
185.625°
191.250°
196.875°
202.500°
208.125°
213.750°
219.375°
225.000°
230.625°
236.250°
241.875°
247.500°
253.125°
258.750°
4
96%
2
3
5
92%
6
88%
4
7
83%
8
77%
1
2
3
3
5
9
71%
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
63%
6
56%
47%
4
7
38%
29%
8
20%
10%
5
9
0%
–10%
–20%
–29%
–38%
–47%
–56%
–63%
–71%
–77%
–83%
–88%
–92%
–96%
–98%
–100%
–100%
–100%
–98%
–96%
–92%
–88%
–83%
–77%
–71%
–63%
–56%
–47%
–38%
–29%
–20%
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
6
7
8
9
–10%
–20%
–29%
–38%
–47%
–56%
–63%
–71%
–77%
–83%
–88%
–92%
–96%
–98%
10
11
12
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Table 3. Microstepping Relative Current Per Step (continued)
FULL
STEP
ELECTRICAL ANGLE
(°)
AOUT CURRENT
(% full-scale)
BOUT CURRENT
(% full-scale)
1/2 STEP 1/4 STEP 1/8 STEP 1/16 STEP
48
264.375°
270.000°
275.625°
281.250°
286.875°
292.500°
298.125°
303.750°
309.375°
315.000°
320.625°
326.250°
331.875°
337.500°
343.125°
348.750°
354.375°
360.000°
–100%
–100%
–100%
–98%
–96%
–92%
–88%
–83%
–77%
–71%
–63%
–56%
–47%
–38%
–29%
–20%
–10%
0%
–10%
0%
7
8
1
13
14
15
16
1
25
26
27
28
29
30
31
32
1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
10%
20%
29%
38%
47%
56%
63%
71%
77%
83%
88%
92%
96%
98%
100%
100%
4
Non-circular 1/2–step operation is shown in Table 4. This stepping mode consumes more power than circular
1/2-step operation, but provides a higher torque at high motor rpm.
Table 4. Non-Circular 1/2-Stepping Current
NON-CIRCULAR
1/2 STEP
ELECTRICAL ANGLE
(°)
AOUT CURRENT
(% FULL-SCALE)
BOUT CURRENT
(% FULL-SCALE)
1
2
3
4
5
6
7
8
0°
0
100
100
0
45°
100
100
100
0
90°
135°
180°
225°
270°
315°
-100
-100
-100
0
–100
–100
–100
100
16
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7.3.4 Current Regulation
The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage,
inductance of the winding, and the magnitude of the back EMF present. After the current hits the current
chopping threshold, the bridge enters a decay mode for a fixed period of time to decrease the current, which is
configurable between 10 and 30 µs through the tri-level input TOFF. After the off time expires, the bridge is re-
enabled, starting another PWM cycle.
Table 5. Off-Time Settings
TOFF
OFF-TIME tOFF
20 µs
0
1
Z
30 µs
10 µs
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pin with a reference voltage. To generate the reference voltage for the current chopping
comparator, the output of a sine lookup table is applied to a sine-weighted DAC, whose full-scale output voltage
is set by VREF. This voltage is attenuated by a factor of Av. In addition, the TRQx pins further scale the
reference.
VM
xOUT1
+
Step
Motor
tía
[ogic
Dꢀꢁe
5rive
VM
-
5evice
[ogic
xOUT2
xISEN
+
-
+
-
VREF
TRQ[1:0]
RSENSE
4
{Lb9 5!/
1ꢀ!v
Figure 14. Current Regulation Block Diagram
The full-scale (100%) chopping current is calculated as follows:
VREF (V) ì TRQ (%) VREF (V) ì TRQ (%)
IFS (A) =
=
AV ì RSENSE (W)
6.6 ì RSENSE (W)
(1)
The TRQx pins are the inputs to a Torque DAC used to scale the output current. The current scalar value for
different inputs is shown below.
Table 6. Torque DAC Settings
TRQ1
TRQ0
CURRENT SCALAR
(TRQ)
EFFECTIVE
ATTENUATION
1
1
0
0
1
0
1
0
25%
50%
26.4 V/V
13.2 V/V
8.8 V/V
6.6 V/V
75%
100%
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Table 7 gives the xISEN trip voltage at a given DAC code and TRQ[1:0] setting for 1/16 step mode. In this table,
VREF = 3.3 V.
Table 7. xISEN Trip Voltages over Torque DAC and Microsteps
TORQUE DAC TRQ[1:0] SETTING
1/16 STEP (SINE
DAC CODE)
00 – 100%
500.0 mV
490.0 mV
480.0 mV
460.0 mV
440.0 mV
415.0 mV
385.0 mV
355.0 mV
315.0 mV
280.0 mV
235.0 mV
190.0 mV
145.0 mV
100.0 mV
50.0 mV
01 – 75%
375.0 mV
367.5 mV
360.0 mV
345.0 mV
330.0 mV
311.3 mV
288.8 mV
266.3 mV
236.3 mV
210.0 mV
176.3 mV
142.5 mV
108.8 mV
75.0 mV
10 – 50%
250.0 mV
245.0 mV
240.0 mV
230.0 mV
220.0 mV
207.5 mV
192.5 mV
177.5 mV
157.5 mV
140.0 mV
117.5 mV
95.0 mV
72.5 mV
50.0 mV
25.0 mV
0.0 mV
11 – 25%
125.0 mV
122.5 mV
120.0 mV
115.0 mV
110.0 mV
103.8 mV
96.3 mV
88.8 mV
78.8 mV
70.0 mV
58.8 mV
47.5 mV
36.3 mV
25.0 mV
12.5 mV
0.0 mV
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
37.5 mV
1
0.0 mV
0.0 mV
18
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7.3.5 Decay Modes
A fixed decay mode is selected by setting the tri-level DECAYx pins as shown in Table 8. Please note that if the
ATE pin is logic high, the DECAYx pins are ignored and AutoTune is used.
Table 8. Decay Mode Settings
DECAY1
DECAY0
INCREASING STEPS
Slow Decay
DECREASING STEPS
Slow Decay
0
0
1
1
0
1
Z
Z
Z
0
1
0
1
Z
Z
0
1
Z
Slow Decay
Mixed Decay: 2 tBLANK
Mixed Decay: 30% Fast
Mixed Decay: 30% Fast
Mixed Decay: 60% Fast
Fast Decay
Slow Decay
Mixed Decay: 30% Fast
Slow Decay
Slow Decay
Mixed Decay: 1 tBLANK
Mixed Decay: 60% Fast
Fast Decay
Mixed Decay: 30% Fast
Mixed Decay: 60% Fast
Fast Decay
Increasing and decreasing current are defined in the chart below. For the Slow/Mixed decay mode, the decay
mode is set as slow during increasing current steps and mixed decay during decreasing current steps. In full step
mode, the increasing step decay mode is always used.
Figure 15. Definition of Increasing and Decreasing Steps
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7.3.5.1 Mode 1: Slow Decay for Increasing and Decreasing Current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
Figure 16. Slow/Slow Decay Mode
During slow decay, both of the low-side FETs of the H-bridge are turned on, allowing the current to be
recirculated.
Slow decay exhibits the least current ripple of the decay modes for a given tOFF. However on decreasing current
steps, slow decay will take a long time to settle to the new ITRIP level because the current decreases very
slowly.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow
decay may not properly regulate current because no back-EMF is present across the motor windings. In this
state, motor current can rise very quickly, and may require a large off-time. In some cases this may cause a loss
of current regulation, and a more aggressive decay mode is recommended.
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7.3.5.2 Mode 2: Slow Decay for Increasing Current, Mixed Decay for Decreasing current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
ITRIP
tBLANK
tFAST
tBLANK
tDRIVE
tFAST
tDRIVE
tOFF
tOFF
Figure 17. Slow/Mixed Decay Mode
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of tOFF. In this mode,
mixed decay only occurs during decreasing current. Slow decay is used for increasing current.
This mode exhibits the same current ripple as slow decay for increasing current, since for increasing current, only
slow decay is used. For decreasing current, the ripple is larger than slow decay, but smaller than fast decay. On
decreasing current steps, mixed decay will settle to the new ITRIP level faster than slow decay.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow
decay may not properly regulate current because no back-EMF is present across the motor windings. In this
state, motor current can rise very quickly, and may require a large off-time. In some cases this may cause a loss
of current regulation, and a more aggressive decay mode is recommended.
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7.3.5.3 Mode 3: Mixed Decay for Increasing and Decreasing Current
ITRIP
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
tDRIVE
ITRIP
tBLANK
tFAST
tBLANK
tDRIVE
tFAST
tDRIVE
tOFF
tOFF
Figure 18. Mixed/Mixed Decay Mode
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of tOFF. In this mode,
mixed decay occurs for both increasing and decreasing current steps.
This mode exhibits ripple larger than slow decay, but smaller than fast decay. On decreasing current steps,
mixed decay will settle to the new ITRIP level faster than slow decay.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow
decay may not properly regulate current because no back-EMF is present across the motor windings. In this
state, motor current can rise very quickly, and requires an excessively large off-time. Increasing/decreasing
mixed decay mode allows the current level to stay in regulation when no back-EMF is present across the motor
windings.
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7.3.5.4 Mode 4: Slow Decay for Increasing Current, Fast Decay for Decreasing current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
Please note that these graphs are not the same scale; tOFF is the same
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
Figure 19. Slow/Fast Decay Mode
During fast decay, the polarity of the H-bridge is reversed. The H-bridge will be turned off as current approaches
zero in order to prevent current flow in the reverse direction. In this mode, fast decay only occurs during
decreasing current. Slow decay is used for increasing current.
Fast decay exhibits the highest current ripple of the decay modes for a given tOFF. Transition time on decreasing
current steps is much faster than slow decay since the current is allowed to decrease much faster.
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7.3.5.5 Mode 5: Fast Decay for Increasing and Decreasing Current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
Figure 20. Fast/Fast Decay Mode
During fast decay, the polarity of the H-bridge is reversed. The H-bridge will be turned off as current approaches
zero in order to prevent current flow in the reverse direction.
Fast decay exhibits the highest current ripple of the decay modes for a given tOFF. Transition time on decreasing
current steps is much faster than slow decay since the current is allowed to decrease much faster.
24
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7.3.6 AutoTune
To enable the AutoTune mode, pull the ATE pin logic high. Ensure the DECAYx pins are logic low. The
AutoTune mode is registered internally when exiting from sleep mode or the power-up sequence. The ATE pin
can be shorted to V3P3 to pull it logic high for this purpose.
AutoTune greatly simplifies the decay mode selection by automatically configuring the decay mode between
slow, mixed, and fast decay. In mixed decay, AutoTune dynamically adjusts the fast decay percentage of the
total mixed decay time. This feature eliminates motor tuning by automatically determining the best decay setting
that results in the lowest ripple for the motor.
The decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip
level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle in order to
prevent regulation loss. If there is a long drive time to reach the target trip level, the decay mode becomes less
aggressive (remove fast decay percentage) on the next cycle in order to operate with less ripple and more
efficiently. On falling steps, AutoTune will automatically switch to fast decay in order to reach the next step
quickly.
AutoTune will automatically adjust the decay scheme based on operating factors like:
•
•
•
•
•
•
•
Motor winding resistance and inductance
Motor aging effects
Motor dynamic speed and load
Motor supply voltage variation
Motor back-EMF difference on rising and falling steps
Step transitions
Low-current vs. high-current dI/dt
7.3.7 Adaptive Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a period of time before
enabling the current sense circuitry. Note that the blanking time also sets the minimum drive time of the PWM.
The blanking time is automatically scaled so that the drive time is reduced at lower current steps.
The time tBLANK is determined by the sine DAC code and the torque DAC setting. The timing information for
tBLANK is given in Table 9.
Table 9. Adaptive Blanking Time Settings over Torque DAC and Microsteps
TORQUE DAC TRQ[1:0] SETTING
SINE DAC CODE
00 – 100%
1.80 µs
1.80 µs
1.80 µs
1.80 µs
1.80 µs
1.80 µs
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
01 – 75%
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
10 – 50%
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
11 – 25%
1.20 µs
1.20 µs
1.20 µs
1.20 µs
1.20 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
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7.3.8 Charge Pump
A charge pump is integrated in order to supply a high-side NMOS gate drive voltage. The charge pump requires
a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins
CPH and CPL.
VM
0.47 µF
VCP
VM
CPH
/harge
VM
0.1 µF
tump
CPL
Figure 21. Charge Pump Diagram
7.3.9 LDO Voltage Regulator
An LDO regulator is integrated into the DRV8880. It can be used to provide the supply voltage for low-current
devices. For proper operation, bypass V3P3 to GND using a ceramic capacitor.
The V3P3 output is nominally 3.3 V. When the V3P3 LDO current load exceeds 10 mA, the LDO will behave like
a constant current source. The output voltage will drop significantly with currents greater than 10 mA.
VM
+
3.3 V
V3P3
-
10 mA
0.47 µF max
Figure 22. LDO Diagram
If a digital input needs to be tied permanently high (that is, M or TOFF), it is preferable to tie the input to V3P3
instead of an external regulator. This will save power when VM is not applied or in sleep mode: V3P3 is disabled
and current will not be flowing through the input pulldown resistors. For reference, logic level inputs have a
typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 40 kΩ.
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7.3.10 Logic and Tri-Level Pin Diagrams
The diagram below gives the input structure for logic-level pins STEP, DIR, ENABLE, nSLEEP, TRQ0, TRQ1,
and ATE:
ë3t3
100 kΩ
Figure 23. Logic-level Input Pin Diagram
Tri-level logic pins TOFF, M0, M1, DECAY0, and DECAY1 have the following structure:
ë3t3
+
ë3t3
t
45 kΩ
40 kΩ
ë3t3
+
t
Figure 24. Tri-level Input Pin Diagram
7.3.11 Power Supplies and Input Pins
The control pins and reference input pin can be driven within the recommended operating conditions without the
VM power supply present, or when the device is in sleep mode.
Each control pin has a weak pulldown resistor to ground. TI recommends setting the inputs to a logic low when in
sleep mode to minimize current through the pulldown resistors.
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7.3.12 Protection Circuits
The DRV8880 is fully protected against undervoltage, charge pump undervoltage, overcurrent, and
overtemperature events.
7.3.13 VM UVLO (UVLO2)
If at any time the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (VUVLO2), all
FETs in the H-bridge will be disabled, the charge pump will be disabled, and the nFAULT pin will be driven low.
Operation will resume when VM rises above the UVLO2 threshold. The nFAULT pin will be released after
operation has resumed.
The indexer position is not reset by this fault even though the output drivers are disabled. The indexer position is
maintained and internal logic remains active until VM falls below the logic undervoltage threshold (VUVLO1).
7.3.14 Logic Undervoltage (UVLO1)
If at any time the voltage on the VM pin falls below the logic undervoltage threshold voltage (VUVLO1), the internal
logic is reset, and the V3P3 regulator is disabled. Operation will resume when VM rises above the UVLO1
threshold. The nFAULT pin is logic low during this state since it is pulled low upon encountering VM
undervoltage. Decreasing VM below this undervoltage threshold will reset the indexer position.
7.3.15 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the charge pump undervoltage lockout threshold voltage, all
FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Operation will resume when VCP
rises above the CPUV threshold. The nFAULT pin will be released after operation has resumed.
7.3.16 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume. The nFAULT
pin will be released after operation has resumed.
7.3.17 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than tOCP, all FETs in the H-bridge will be disabled and nFAULT will be
driven low. In addition to this FET current limit, an overcurrent condition is also detected if the voltage at xISEN
exceeds VOCP
.
The overcurrent fault response can be set to either latched mode or retry mode:
V3P3
5.1 kΩ
ENABLE
FAULTn
ENABLE
FAULTn
V3P3
{hort
5etect
5evice
[ogic
5evice
[ogic
Figure 25. Latched OCP Mode
Figure 26. Retry OCP Mode
In latched mode, operation will resume after the ENABLE pin is brought logic low for at least 1 μs to reset the
output driver. The nFAULT pin will be released after ENABLE is returned logic high. Removing and re-applying
VM or toggling nSLEEP will also reset the latched fault.
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In retry mode, the driver will be re-enabled after the OCP retry period (tRETRY) has passed. nFAULT becomes
high again after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer
present, normal operation resumes and nFAULT remains deasserted.
A microcontroller can retain control of the ENABLE pin while in retry mode if it is operated like an open-drain
output. Many microcontrollers support this. When the DRV8880 is operating normally, configure the MCU GPIO
as an input. In this state, the MCU can detect whenever nFAULT is pulled low. In order to disable the DRV8880
output, configure the GPIO output state as low, and then configure the GPIO as an output.
Alternatively, a logic-level FET may be used to create an open drain external to the MCU. In this case, an
additional MCU GPIO may be required in order to monitor the nFAULT pin.
V3P3
V3P3
DRV8880
DRV8880
MCU
MCU
5.1 kΩ
5.1 kΩ
ENABLE
ENABLE
5evice
[ogic
5evice
[ogic
FAULTn
FAULTn
Figure 27. Methods For Operating in Retry Mode
Table 10. Fault Condition Summary
ERROR
REPORT
CHARGE
PUMP
FAULT
CONDITION
H-BRIDGE
Disabled
Disabled
Disabled
Disabled
INDEXER
Operating
Disabled
V3P3
RECOVERY
VM undervoltage
(UVLO2)
VM < VUVLO2
(max 6.4 V)
VM > VUVLO2
(max 6.5 V)
nFAULT
None
Disabled
Disabled
Operating
Operating
Operating
Operating
Operating
Operating
Logic undervoltage
(UVLO1)
VM < VUVLO2
(max 4.9 V)
VM > VUVLO2
(max 4.8 V)
VCP undervoltage
(CPUV)
VCP < VCPUV
(typ VM + 1.8 V)
VCP > VCPUV
(typ VM + 1.9 V)
nFAULT
nFAULT
Operating
Operating
Thermal Shutdown
(TSD)
TJ > TTSD
(min 150°C)
TJ < TTSD - THYS
(THYS typ 35°C)
IOUT > IOCP
(min 2.5 A)
VxISEN > VOCP
(min 0.9 V)
ENABLE
-or-
tRETRY
Overcurrent
(OCP)
nFAULT
Disabled
Operating
Operating
Operating
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7.4 Device Functional Modes
The DRV8880 internal logic, indexer, and charge pump are operating unless the nSLEEP pin is brought logic
low. In sleep mode the charge pump is disabled, the H-bridge FETs are disabled Hi-Z, and the V3P3 regulator is
disabled. tSLEEP must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The
DRV8880 is brought out of sleep mode automatically if nSLEEP is brought logic high. tWAKE must elapse before
the outputs change state after wake-up.
If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the charge pump and internal logic
will remian active. A rising edge on STEP will advance the indexer, but the outputs will not change state until
ENABLE brought logic high.
When VM falls below the VM undervoltage lockout threshold VUVLO2, the output driver and charge pump are
disabled, but the internal logic and V3P3 remain active. In this mode, STEP inputs will advance the indexer, but
the outputs will remain disabled. If VM falls below the logic undervoltage threshold VUVLO1, the internal logic is
reset and the indexer will lose position.
Table 11. Functional Modes Summary
CONDITION
H-BRIDGE
CHARGE PUMP
INDEXER
V3P3
6.5 V < VM < 45 V
nSLEEP pin = 1
ENABLE pin = 1
Operating
Operating
Operating
Operating
Operating
6.5 V < VM < 45 V
nSLEEP pin = 1
ENABLE pin = 0
Disabled
Disabled
Disabled
Operating
Disabled
Operating
Disabled
Operating
Disabled
5.0 V < VM < 45 V
nSLEEP pin = 0
Sleep mode
VM undervoltage (UVLO2)
Logic undervoltage (UVLO1)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Operating
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Operating
Operating
Fault encountered VCP undervoltage (CPUV)
Thermal shutdown (TSD)
Operating
Operating
Operating
Overcurrent (OCP)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8880 is used in stepper control.
8.2 Typical Application
The following design procedure can be used to configure the DRV8880.
5wë8880tít
28
27
26
2ꢀ
24
23
22
21
20
1ꢁ
18
17
16
1ꢀ
1
Db5
/t[
/tI
2
0.1 µF
Çwv0
Çwv1
a0
VM
0.1 µF
3
ë/t
4
0.47 µF
ëa
ꢀ
a1
!hÜÇ1
!L{9b
!hÜÇ2
.hÜÇ2
.L{9b
.hÜÇ1
ëa
250 mΩ
6
Step
{Ç9t
Motor
7
5Lw
8
+
-
9b!.[9
59/!ò0
59/!ò1
nC!Ü[Ç
n{[99t
ÇhCC
250 mΩ
ꢁ
10
11
12
13
14
VM
+
Db5
100 µF
0.1 µF
10 kΩ
!Ç9
ë3t3
ëw9C
R1
R2
0.47 µF
Figure 28. Typical Application Schematic
8.2.1 Design Requirements
Table 12 gives design input parameters for system design.
Table 12. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
EXAMPLE VALUE
24 V
VM
RL
LL
Motor winding resistance
Motor winding inductance
Motor full step angle
0.8 Ω/phase
1.4 mH/phase
1.8°/step
θstep
nm
v
Target microstepping level
Target motor speed
1/8 step
120 rpm
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Table 12. Design Parameters (continued)
DESIGN PARAMETER
Target full-scale current
REFERENCE
EXAMPLE VALUE
IFS
1.5 A
8.2.2 Detailed Design Procedure
8.2.2.1 Stepper Motor Speed
The first step in configuring the DRV8880 requires the desired motor speed and microstepping level. If the target
application requires a constant speed, then a square wave with frequency ƒstep must be applied to the STEP pin.
If the target motor speed is too high, the motor will not spin. Make sure that the motor can support the target
speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
v (rpm) ì 360 (è / rot)
step (è / step) ìnm (steps / microstep) ì 60 (s / min)
ƒstep (steps / s) =
q
(2)
θstep can be found in the stepper motor data sheet or written on the motor itself.
For the DRV8880, the microstepping level is set by the Mx pins and can be any of the settings in the table below.
Higher microstepping will mean a smother motor motion and less audible noise, but will increase switching
losses and require a higher ƒstep to achieve the same motor speed.
Table 13. Microstepping Indexer Settings
M1
M0
STEP MODE
0
0
Full step (2-phase excitation) with 71%
current
0
1
1
0
1
1
0
1
Z
Z
Non-circular 1/2 step
1/2 step
1/4 step
1/8 step
1/16 step
Example: Target 120 rpm at 1/8 microstep mode. The motor is 1.8°/step
120 rpm ì 360è / rot
ƒstep (steps / s) =
= 3.2 kHz
1.8è / step ì1/ 8 steps / microstep ì 60 s / min
(3)
8.2.2.2 Current Regulation
In a stepper motor, the full-scale current (IFS) is the maximum current driven through either winding. This quantity
will depend on the TRQ pins, the VREF analog voltage, and the sense resistor value (RSENSE). During stepping,
IFS defines the current chopping threshold (ITRIP) for the maximum current step.
VREF (V) ì TRQ (%) VREF (V) ì TRQ (%)
IFS (A) =
=
Av ì RSENSE (W)
6.6 ì RSENSE (W)
(4)
TRQ is a DAC used to scale the output current. The current scalar value for different inputs is shown below.
Table 14. Torque DAC Settings
TRQ1
TRQ0
CURRENT SCALAR (TRQ)
1
1
0
0
1
0
1
0
25%
50%
75%
100%
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Example: If the desired full-scale current is 1.5 A
Set RSENSE = 100 mΩ, assume TRQ = 100%.
VREF would have to be 0.99 V.
Create a resistor divider from V3P3 (3.3 V) to set VREF ≈ 0.99 V.
Set R2 = 10 kΩ, set R1 = 22 kΩ
Note that IFS must also follow the equation below in order to avoid saturating the motor. VM is the motor supply
voltage, and RL is the motor winding resistance.
VM (V)
IFS (A) <
RL (W) + 2 ì RDS(ON) (W) + RSENSE (W)
(5)
8.2.2.3 Decay Modes
The DRV8880 supports several different decay modes: slow decay, fast decay, mixed decay, and AutoTune. The
current through the motor windings is regulated using an adjustable fixed-time-off scheme. This means that after
any drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8880 will
place the winding in one of the decay modes for tOFF. After tOFF, a new drive phase starts. For fixed decay modes
(slow, fast, and mixed), the best setting can be determined by operating the motor and choosing the best setting.
8.2.2.4 Sense Resistor
For optimal performance, it is important for the sense resistor to be:
•
•
•
•
Surface-mount
Low inductance
Rated for high enough power
Placed closely to the motor driver
2
The power dissipated by the sense resistor equals Irms × R. For example, if the rms motor current is 1.4A and a
250 mΩ sense resistor is used, the resistor will dissipate 1.4 A2 × 0.25 Ω = 0.49 W. The power quickly increases
with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be
added. It is always best to measure the actual sense resistor temperature in a final system, along with the power
MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.
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8.2.3 Application Curves
Figure 29. Mixed Decay 30% Fast on Increasing and
Decreasing Steps
Figure 30. Slow Decay on Increasing and Decreasing
Steps
Figure 31. Slow Decay on Increasing and Mixed Decay
30% Fast on Decreasing Steps
Figure 32. AutoTune
Figure 33. Mixed Decay 30% Fast on Increasing and
Decreasing Steps
Figure 34. AutoTune
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9 Power Supply Recommendations
The DRV8880 is designed to operate from an input voltage supply (VM) range between 6.5 V and 45 V. The
device has an absolute maximum rating of 50 V. A 0.1-µF ceramic capacitor rated for VM must be placed at
each VM pin as close to the DRV8880 as possible. In addition, a bulk capacitor must be included on VM.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
œ
GND
Local
IC Bypass
Bulk Capacitor
Capacitor
Figure 35. Setup of Motor Drive System With External Power Supply
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10 Layout
10.1 Layout Guidelines
Each VM terminal must be bypassed to GND using a low-ESR ceramic bypass capacitors with recommended
values of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a
thick trace or ground plane connection to the device GND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an
electrolytic.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.1 μF rated for VM
is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.47 μF rated for 16
V is recommended. Place this component as close to the pins as possible.
Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
The current sense resistors should be placed as close as possible to the device pins in order to minimize trace
inductance between the pin and resistor.
10.2 Layout Example
+
0.1 µF
CPL
CPH
GND
TRQ0
TRQ1
M0
0.1 µF
VCP
VM
0.47 µF
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
M1
STEP
DIR
ENABLE
DECAY0
DECAY1
nFAULT
nSLEEP
TOFF
0.1 µF
GND
ATE
VREF
V3P3
0.1 µF
Figure 36. Layout Recommendation
36
版权 © 2015–2017, Texas Instruments Incorporated
DRV8880
www.ti.com.cn
ZHCSDY8C –JUNE 2015–REVISED AUGUST 2017
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
•
•
•
•
•
德州仪器 (TI)，《PowerPAD™ 热增强型封装》应用报告
德州仪器 (TI)，《PowerPAD™ 速成》应用报告
德州仪器 (TI)，《电流再循环和衰减模式》应用报告
德州仪器 (TI)，《计算电机驱动器的功耗》应用报告
德州仪器 (TI)，《了解电机驱动器电流额定值》应用报告
11.2 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
AutoTune, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2015–2017, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8880PWP
DRV8880PWPR
DRV8880RHRR
DRV8880RHRT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
WQFN
PWP
PWP
RHR
RHR
28
28
28
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DRV8880
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
DRV8880
DRV8880
DRV8880
WQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8880PWPR
DRV8880RHRR
DRV8880RHRT
HTSSOP PWP
28
28
28
2000
3000
250
330.0
330.0
180.0
16.4
12.4
12.4
6.9
3.8
3.8
10.2
5.8
1.8
1.2
1.2
12.0
8.0
16.0
12.0
12.0
Q1
Q1
Q1
WQFN
WQFN
RHR
RHR
5.8
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8880PWPR
DRV8880RHRR
DRV8880RHRT
HTSSOP
WQFN
PWP
RHR
RHR
28
28
28
2000
3000
250
350.0
346.0
210.0
350.0
346.0
185.0
43.0
33.0
35.0
WQFN
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DRV8880PWP
28
50
530
10.2
3600
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
PACKAGE OUTLINE
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
8.45
NOTE 3
14
15
0.30
0.19
28X
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
14
15
2X 0.2 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
5.18
4.48
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
28
3.1
2.4
4223582/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
(5.18)
(0.6)
26X (0.65)
SYMM
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
(
0.2) TYP
VIA
14
15
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4223582/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28X (0.45)
28
(R0.05) TYP
26X (0.65)
SYMM
(5.18)
BASED ON
0.125 THICK
STENCIL
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.47 X 5.79
3.10 X 5.18 (SHOWN)
2.83 X 4.73
0.125
0.15
0.175
2.62 X 4.38
4223582/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RHR 28
3.5 x 5.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4210249/B
www.ti.com
PACKAGE OUTLINE
RHR0028A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
0.5
0.3
5.6
5.4
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
2±0.1
2X 1.5
(0.2) TYP
EXPOSED
THERMAL PAD
11
14
24X 0.5
10
15
2X
4.5
4±0.1
SEE TERMINAL
DETAIL
1
24
0.3
28X
28
25
0.5
0.2
PIN 1 ID
(OPTIONAL)
0.1
C A
B
28X
0.3
0.05
4219075/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
SYMM
28X (0.6)
28X (0.25)
25
28
1
24
24X (0.5)
(0.66)
(5.3)
TYP
SYMM
(4)
(
0.2) TYP
VIA
15
10
11
14
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219075/A 11/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.55) TYP
28
25
28X (0.6)
28X (0.25)
1
24
24X (0.5)
SYMM
(1.32)
TYP
(5.3)
METAL
TYP
6X (1.12)
15
10
14
11
6X (0.89)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219075/A 11/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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