DRV8881PRHRR [TI]
具有电流调节和智能调优功能的 45V、2A 双极双步进或四路 H 桥电机驱动器 | RHR | 28 | -40 to 125;
| 型号： | DRV8881PRHRR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流调节和智能调优功能的 45V、2A 双极双步进或四路 H 桥电机驱动器 | RHR | 28 | -40 to 125 电机 驱动 驱动器 |
| 文件： | 总50页 (文件大小：2306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8881
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
DRV8881 2.5A 双路 H 桥电机驱动器
1 特性
2 应用
1
•
双路 H 桥电机驱动器
•
•
•
•
•
自动取款机和验钞机
视频安保摄像机
–
–
双极步进电机驱动器
多功能打印机和文档扫描仪
工厂自动化和机器人
舞台照明设备
单路或双路刷式直流电机驱动器
•
•
6.5V 至 45V 的工作电源电压范围
两个控制接口选项
–
–
PHASE/ENABLE (DRV8881E)
PWM (DRV8881P)
3 说明
DRV8881 是一款面向工业应用的双极步进或刷式直流
电机驱动器。 该器件的输出级由两个 N 沟道功率金属
氧化物半导体场效应晶体管 (MOSFET) H 桥驱动器组
成。 DRV8881 的每个 H 桥能够驱动高达 2.5A 的峰值
电流或 1.4A 均方根 (rms) 电流（采用适当的印刷电路
板 (PCB) 接地层进行散热，电压为 24V，TA =
25°C）。
•
多种衰减模式，可为任何电机提供支持
–
–
–
–
AutoTune™（仅限 DRV8881E）
混合衰减
慢速衰减
快速衰减
•
•
•
平滑运动的自适应消隐时间
并行工作模式（仅限 DRV8881P）
可配置关断时间脉宽调制 (PWM) 斩波
AutoTune™ 可自动调整电机以实现最佳电流调节性
能，并且能够对电机变化和老化问题进行补偿。
DRV8881E 上提供 AutoTune 功能。 此外，该器件还
提供慢速、快速和混合三种衰减模式。
–
10、20 或 30μs 关断时间
•
•
•
3.3V，10mA 低压降 (LDO) 稳压器
低电流休眠模式 (28μA)
小型封装尺寸
该器件可通过 PH/EN (DRV8881E) 或 PWM
(DRV8881P) 引脚提供一个简单的控制接口。 内置的
感测放大器能够实现可调节的电流控制。 凭借专用的
nSLEEP 引脚，该器件可提供一种低功耗的休眠模
式，从而实现超低静态电流待机。
–
28 引脚散热薄型小外形尺寸 (HTSSOP)
(PowerPAD) 封装
–
28 引脚超薄型四方扁平无引线 (WQFN)
(PowerPAD) 封装
空白
•
保护特性
该器件内置以下保护功能：欠压、电荷泵故障、过流、
短路以及过热保护。 故障条件通过 nFAULT 引脚指
示。
–
–
–
–
–
–
VM 欠压闭锁 (UVLO)
电荷泵电压 (CPUV)
过流保护 (OCP)
器件信息(1)
自动过流保护 (OCP) 重试
热关断 (TSD)
器件型号
DRV8881
封装
HTSSOP (28)
WQFN (28)
封装尺寸（标称值）
9.70mm × 6.40mm
5.50mm × 3.50mm
故障条件指示引脚 (nFAULT)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD19
DRV8881
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
DRV8881E 简化系统图
DRV8881P 简化系统图
6.5 to 45 V
6.5 to 45 V
APH/AEN
BPH/BEN
DRV8881E
AIN1/AIN2
DRV8881P
STEPPER
STEPPER
BDC
BDC
2.5 A
2.5 A
2.5 A
2.5 A
BIN1/BIN2
Dual
H-Bridge
Motor Driver
Dual
H-Bridge
Motor Driver
Current scalar
Decay mode
Current scalar
Decay mode
+
-
+
-
BDC
BDC
ꢀµ}dµvꢀ¡ꢁ
Parallel Mode
2
版权 © 2015, Texas Instruments Incorporated
DRV8881
www.ti.com.cn
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
目录
7.4 Device Functional Modes........................................ 27
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Applications ................................................ 28
Power Supply Recommendations...................... 34
9.1 Bulk Capacitance Sizing ......................................... 34
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Typical Characteristics............................................ 10
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagrams ..................................... 13
7.3 Feature Description................................................. 15
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 35
11 器件和文档支持 ..................................................... 36
11.1 文档支持................................................................ 36
11.2 社区资源................................................................ 36
11.3 商标....................................................................... 36
11.4 静电放电警告......................................................... 36
11.5 Glossary................................................................ 36
12 机械、封装和可订购信息....................................... 36
7
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2015) to Revision A
Page
•
•
•
已将器件状态更新为量产数据 ................................................................................................................................................. 1
Updated from "PowerPAD" to "thermal pad" ......................................................................................................................... 5
Corrected ATE pin number for RHR package to 23............................................................................................................... 5
Copyright © 2015, Texas Instruments Incorporated
3
DRV8881
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP
Top View DRV8881E
RHR Package
28-Pin WQFN
Top View DRV8881E
1
2
28
27
26
CPL
CPH
GND
TRQ0
TRQ1
ATE
3
VCP
1
2
24
23
22
21
20
19
18
17
16
15
VCP
VM
TRQ1
ATE
4
25
24
23
22
21
20
19
18
17
16
15
VM
5
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
APH
3
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
APH
4
6
AEN
AEN
5
BPH
7
BPH
6
BEN
8
BEN
7
ADECAY
BDECAY
nFAULT
nSLEEP
9
ADECAY
BDECAY
nFAULT
nSLEEP
TOFF
V3P3
8
10
11
12
13
14
9
10
GND
GND
AVREF
BVREF
PWP Package
28-Pin HTSSOP
Top View DRV8881P
RHR Package
28-Pin WQFN
Top View DRV8881P
1
2
28
27
26
CPL
CPH
GND
TRQ0
TRQ1
PARA
AIN1
3
VCP
1
2
24
23
22
21
20
19
18
17
16
15
VCP
VM
TRQ1
4
25
24
23
22
21
20
19
18
17
16
15
VM
PARA
5
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
3
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
AIN1
4
6
AIN2
AIN2
5
BIN1
7
BIN1
6
BIN2
8
BIN2
7
ADECAY
BDECAY
nFAULT
nSLEEP
9
ADECAY
BDECAY
nFAULT
nSLEEP
TOFF
8
10
11
12
13
14
9
10
GND
GND
AVREF
BVREF
V3P3
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
CPL
PWP
RHR
27
1
2
3
Connect a VM rated, 0.1-µF ceramic capacitor between CPH
and CPL
PWR Charge pump output
Charge pump output
PWR Power supply
CPH
VCP
28
1
O
Connect a 16-V, 0.47-µF ceramic capacitor to VM
Connect to motor supply voltage; bypass to GND with two 0.1
µF (for each pin) plus one bulk capacitor rated for VM
VM
4, 11
2, 9
AOUT1
AOUT2
5
7
3
5
H-bridge outputs, drives one winding of a stepper motor
O
O
O
O
Winding A output
Winding A sense
Winding B output
Winding B sense
Requires sense resistor to GND; value sets peak current in
winding A
AISEN
6
4
BOUT2
BOUT1
8
6
8
H-bridge outputs, drives one winding of a stepper motor
10
Requires sense resistor to GND; value sets peak current in
winding B
BISEN
GND
9
7
12, 28
10, 26
PWR Device ground
Must be connected to ground
4
Copyright © 2015, Texas Instruments Incorporated
DRV8881
www.ti.com.cn
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
Pin Functions (continued)
PIN
PWP
TYPE
DESCRIPTION
NAME
RHR
Voltage on this pin sets the full scale chopping current in H-
bridge A
AVREF
13
14
11
I
Reference voltage input
Voltage on this pin sets the full scale chopping current in H-
bridge B
BVREF
12
Internal supply voltage; bypass to GND with a 6.3-V, 0.47-µF
ceramic capacitor; up to 10-mA external load
V3P3
15
16
17
13
14
15
—
Internal regulator
TOFF
I
I
Decay mode off time set
Sleep mode input
Sets the off-time during current chopping; tri-level pin
Logic high to enable device; logic low to enter low-power sleep
mode; internal pulldown
nSLEEP
Pulled logic low with fault condition; open-drain output requires
an external pullup
nFAULT
BDECAY
ADECAY
18
19
20
16
17
18
O
I
Fault indication pin
Set the decay mode for bridge B; see Decay Modes ; tri-level
pin
Decay mode setting pins
Set the decay mode for bridge A; see Decay Modes ; tri-level
pin
TRQ1
TRQ0
PAD
26
27
24
25
Scales the current by 100%, 75%, 50%, or 25%; internal
pulldown
I
Torque DAC current scalar
PAD
PAD
PWR Thermal pad
Must be connected to ground
DRV8881E PH/EN Pin Functions
PIN
TYPE
DESCRIPTION
NAME
BEN
PWP
21
RHR
19
I
I
I
I
Bridge B enable input
Logic high enables bridge B; logic low disables the bridge Hi-Z
Logic high drives current from BOUT1 → BOUT2
BPH
22
20
Bridge B phase input
Bridge A enable input
Bridge A phase input
AEN
23
21
Logic high enables bridge A; logic low disables the bridge Hi-Z
Logic high drives current from AOUT1 → AOUT2
APH
24
22
Logic high enables AutoTune operation; when logic low, the
decay mode is set through the DECAYx pins; AutoTune must
be pulled high prior to power-up or coming out of sleep, or else
tied to V3P3 in order to enable AutoTune; internal pulldown;
see AutoTune
ATE
25
23
I
AutoTune enable pin
DRV8881P PWM Pin Functions
PIN
TYPE
DESCRIPTION
NAME
BIN2
PWP
21
RHR
19
I
Bridge B PWM input
Logic controls the state of H-bridge B; internal pulldown
BIN1
22
20
AIN2
23
21
I
I
Bridge A PWM input
Parallel mode input
Logic controls the state of H-bridge A; internal pulldown
Logic high enables parallel mode
AIN1
24
22
PARA
25
23
Copyright © 2015, Texas Instruments Incorporated
5
DRV8881
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
External Components
COMPONENT
CVM1
PIN 1
VM
PIN 2
RECOMMENDED
GND
GND
0.1-µF ceramic capacitor rated for VM per VM pin
CVM1
VM
Bulk electrolytic capacitor rated for VM, recommended value is 100
µF, see Bulk Capacitance Sizing
CVCP
CSW
VCP
CPH
V3P3
VM
CPL
16 V, 0.47 µF ceramic capacitor
0.1-µF X7R capacitor rated for VM
6.3 V, 0.47-µF ceramic capacitor
> 5 kΩ
CV3P3
RnFAULT
RAISEN
RBISEN
GND
(1)
VMCU
nFAULT
GND
AISEN
BISEN
Optional sense resistor, see Sense Resistor
GND
(1) VMCU is not a pin on the DRV8881, but a supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled up to
V3P3
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
(1)
MIN
–0.3
0
MAX
50
UNIT
V
Power supply voltage (VM)
Power supply voltage ramp rate (VM)
Charge pump voltage (VCP, CPH)
Charge pump negative switching pin (CPL)
Internal regulator voltage (V3P3)
Internal regulator current output (V3P3)
2
V/µs
V
–0.3
–0.3
–0.3
0
VM + 12
VM
V
3.8
V
10
mA
Control pin voltage (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nSLEEP,
nFAULT, ADECAY, BDECAY, TRQ0, TRQ1, ATE, PARA)
–0.3
7.0
V
Open drain output current (nFAULT)
0
10
mA
V
Reference input pin voltage (AVREF, BVREF)
–0.3
–0.7
–0.55
V3P3 + 0.5
VM + 0.7
0.55
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
V
(2)
Continuous shunt amplifier input pin voltage (AISEN, BISEN)
V
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN)
Operating junction temperature, TJ
Internally limited
A
–40
–65
150
150
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
V(ESD)
Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6
Copyright © 2015, Texas Instruments Incorporated
DRV8881
www.ti.com.cn
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
45
UNIT
V
VM
Power supply voltage range
6.5
VIN
Digital pin voltage range
0
5.3
V
(1)
VREF
ƒPWM
IV3P3
Irms
Reference rms voltage range (AVREF, BVREF)
Applied PWM signal (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2)
V3P3 external load current
0.3
V3P3
100
V
0
0
kHz
mA
A
(2)
10
Motor rms current per H-bridge
0
1.4
TA
Operating ambient temperature
–40
125
°C
(1) Operational at VREF ≈ 0 to 0.3 V, but accuracy is degraded
(2) Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8881
(1)
THERMAL METRIC
PWP (HTSSOP)
RHR (WQFN)
UNIT
28 PINS
33.1
16.6
14.4
0.4
28 PINS
37.5
23.0
8.0
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
14.2
1.3
7.8
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
7
DRV8881
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, V3P3)
VM
VM operating voltage
6.5
45
18
V
nSLEEP high; ENABLE high; no motor
load; VM = 24 V
IVM
VM operating supply current
8
mA
nSLEEP low; VM = 24 V; TA = 25°C
28
IVMQ
VM sleep mode supply current
μA
nSLEEP low; VM = 24 V; TA = 125°C
77
(1)
tSLEEP
tWAKE
tON
Sleep time
nSLEEP low to sleep mode
nSLEEP high to output transition
VM > VUVLO to output transition
External load 0 to 10 mA
100
1.5
1.5
3.6
μs
ms
ms
V
Wake-up time
Turn-on time
V3P3
Internal regulator voltage
2.9
3.3
CHARGE PUMP (VCP, CPH, CPL)
VM > 12 V
VM + 11.5
VCP
VCP operating voltage
V
VUVLO < VM < 12 V
2×VM – 1.5
Charge pump switching
frequency
(1)
ƒVCP
VM > VUVLO
175
715
kHz
LOGIC-LEVEL INPUTS (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nSLEEP, TRQ0, TRQ1, PARA)
VIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
0
1.6
100
–1
0.6
5.3
V
V
VIH
VHYS
IIL
mV
μA
μA
kΩ
VIN = 0 V
1
IIH
VIN = 5.0 V
50
100
RPD
Measured between the pin and GND
100
xPH, xEN, xINx input to current
change
tPD
Propagation delay
450
ns
TRI-LEVEL INPUTS (ADECAY, BDECAY, TOFF)
VIL
VIZ
VIH
VHYS
IIL
Tri-level input logic low voltage
Tri-level input Hi-Z voltage
Tri-level input logic high voltage
Tri-level input hysteresis
0
0.6
5.3
V
V
1.1
1.6
100
–55
V
mV
μA
μA
μA
kΩ
kΩ
Tri-level input logic low current
Tri-level input Hi-Z current
Tri-level input logic high current
Tri-level pulldown resistance
Tri-level pullup resistance
VIN = 0 V
–35
IIZ
VIN = 1.3 V
15
85
40
45
IIH
VIN = 3.3 V
RPD
RPU
Measured between the pin and GND
Measured between V3P3 and the pin
CONTROL OUTPUTS (nFAULT)
VOL
IOH
Output logic low voltage
Output logic high leakage
IO = 4 mA
0.5
1
V
External pullup resistor to 3.3 V
–1
μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
VM = 24 V, I = 1 A, TA = 25°C
330
400
430
500
300
370
370
450
(1)
VM = 24 V, I = 1 A, TA = 125°C
VM = 6.5 V, I = 1 A, TA = 25°C
VM = 6.5 V, I = 1 A, TA = 125°C
VM = 24 V, I = 1 A, TA = 25°C
VM = 24 V, I = 1 A, TA = 125°C
VM = 6.5 V, I = 1 A, TA = 25°C
VM = 6.5 V, I = 1 A, TA = 125°C
440
560
400
490
RDS(ON)
High-side FET on resistance
Low-side FET on resistance
mΩ
mΩ
(1)
(1)
RDS(ON)
(1)
(1) Specified by design and characterization data
8
Copyright © 2015, Texas Instruments Incorporated
DRV8881
www.ti.com.cn
ZHCSDY9A –JUNE 2015–REVISED JULY 2015
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VM = 24 V, 50 Ω load from xOUTx to
GND
tRISE
tFALL
Output rise time
70
ns
VM = 24 V, 50 Ω load from VM to
xOUTx
Output fall time
70
ns
(2)
tDEAD
Vd
Output dead time
200
0.7
ns
V
Body diode forward voltage
IOUT = 0.5 A
1
PWM CURRENT CONTROL (VREF, AISEN, BISEN)
TRQ at 100%, VREF = 3.3 V
500
375
250
125
6.58
6.56
6.51
6.38
20
TRQ at 75%, VREF = 3.3 V
TRQ at 50%, VREF = 3.3 V
TRQ at 25%, VREF = 3.3 V
Torque = 100% (TRQ0 = 0, TRQ1 = 0)
Torque = 75% (TRQ0 = 1, TRQ1 = 0)
Torque = 50% (TRQ0 = 0, TRQ1 = 1)
Torque = 25% (TRQ0 = 1, TRQ1 = 1)
TOFF logic low
xISENSE trip voltage, full scale
current step
VTRIP
mV
6.25
6.2
6.91
6.92
6.94
6.93
AV
Amplifier attenuation
PWM off-time
V/V
μs
6.09
5.83
tOFF
TOFF logic high
30
TOFF Hi-Z
10
1.8
1.5
tBLANK
PWM blanking time
See Table 6 for details
µs
1.2
0.9
PROTECTION CIRCUITS
VM falling; UVLO report
VM rising; UVLO recovery
Rising to falling threshold
VCP falling; CPUV report
VCP rising; CPUV recovery
Rising to falling threshold
Current through any FET
Voltage at AISEN or BISEN
5.8
6.1
6.4
6.5
VUVLO
VM undervoltage lockout
V
mV
V
VUVLO,HYS Undervoltage hysteresis
100
VM + 1.8
VM + 1.9
VCPUV
Charge pump undervoltage
VCPUV,HYS CP undervoltage hysteresis
50
2.5
0.9
mV
A
IOCP
Overcurrent protection trip level
Sense pin overcurrent trip level
Overcurrent deglitch time
3.6
1.25
2
VOCP
tOCP
V
μs
ms
°C
°C
tRETRY
Overcurrent retry time
0.5
2
(2)
TTSD
THYS
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature TJ
Die temperature TJ
150
(2)
35
(2) Specified by design and characterization data
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6.6 Typical Characteristics
Over recommended operating conditions (unless otherwise noted)
6.5
6.45
6.4
6.35
6.3
6.25
6.2
6.35
6.3
6.15
6.1
6.25
6.2
6.15
6.1
6.05
6
6.05
6
5.95
5.9
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
5.95
5.85
5.8
5.9
VM = 24 V
VM = 12 V
5.85
5.8
5.75
5
10
15
20
25
30
35
40
45
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (qC)
D001
D002
Figure 1. Supply Current over VM
Figure 2. Supply Current over Temperature
28
26
24
22
20
18
16
14
12
10
8
25.5
25
24.5
24
23.5
23
22.5
22
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VM = 24 V
VM = 12 V
21.5
6
21
6
9
12
15
18
21
24
27
30
33
36
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (qC)
D003
D004
Figure 3. Sleep Current over VM
Figure 4. Sleep Current over Temperature
700
650
600
550
500
450
400
350
300
250
200
550
500
450
400
350
300
250
200
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
5
10
15
20
25
30
35
40
45
50
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (qC)
D005
D006
Figure 5. High-Side RDS(ON) over VM
Figure 6. High-Side RDS(ON) over Temperature (VM = 12 V)
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Typical Characteristics (continued)
Over recommended operating conditions (unless otherwise noted)
600
480
450
420
390
360
330
300
270
240
210
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
550
500
450
400
350
300
250
200
5
10
15
20
25
30
35
40
45
50
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (qC)
D007
D008
Figure 7. Low-Side RDS(ON) over VM
Figure 8. Low-Side RDS(ON) over Temperature (VM = 12 V)
3.36
0.5
TRQ = 00
TRQ = 01
TRQ = 10
TRQ = 11
0.45
0.4
3.355
3.35
0.35
0.3
3.345
3.34
0.25
0.2
3.335
0.15
0.1
3.33
3.325
3.32
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.05
0
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
2.5
3
3.5
VREF Pin Voltage (V)
V3P3 Load (mA)
D009
D010
Figure 9. xISEN Trip Voltage over VREF Input
Figure 10. V3P3 Regulator over Load (VM = 24 V)
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7 Detailed Description
7.1 Overview
The DRV8881 is an integrated motor driver solution for bipolar stepper motors or single/dual brushed-DC motors.
The device integrates two NMOS H-bridges and current regulation circuitry. The DRV8881 can be powered with
a supply voltage between 6.5 and 45 V, and is capable of providing an output current up to 2.5 A peak or 1.4 A
rms per H-bridge. Actual operable rms current will depend on ambient temperature, supply voltage, and PCB
ground plane size.
A simple PH/EN (DRV8881E) or PWM (DRV8881P) interface allows easy interfacing to the controller circuit.
The current regulation is highly configurable, with several decay modes of operation. The decay mode can be
selected as a fixed slow, mixed, or fast decay.
In addition, an AutoTune mode can be used which automatically adjusts the decay setting to minimize current
ripple while still reacting quickly to step changes. This feature greatly simplifies stepper driver integration into a
motor drive system. AutoTune is only available on the DRV8881E.
The PWM off-time, tOFF, can be adjusted to 10, 20, or 30 μs.
An adaptive blanking time feature automatically scales the minimum drive time with output current. This helps
alleviate current waveform distortion by limiting the drive time at low-currents.
A torque DAC feature allows the controller to scale the output current without needing to scale the analog
reference voltage inputs AVREF and BVREF. The torque DAC is accessed using digital input pins. This allows
the controller to save power by decreasing the current consumption when not required.
In the DRV8881P, a parallel mode allows the user to parallel the two H-bridge outputs in order to double the
current capacity.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
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7.2 Functional Block Diagrams
VM
+
0.1 µF
0.1 µF
bulk
VM
VM
VM
VM
Power
0.47 µF
0.1 µF
VCP
CPH
CPL
AutoTune
AOUT1
+
Charge
Pump
Off-
time
PWM
Gate
Drive
Step
Motor
VM
BDC
AOUT2
-
V3P3
10 mA
3.3-V LDO
0.47 µF
+
-
APH
AEN
BPH
BEN
AISEN
RSENSE
+
Core Logic
-
TRQ[1:0]
AVREF
1/Av
nSLEEP
ATE
Control
Inputs
VM
TRQ[1:0]
ADECAY
BDECAY
TOFF
V3P3
BOUT1
BOUT2
V3P3
V3P3
Off-
time
PWM
VM
Gate
Drive
BDC
AVREF
BVREF
Protection
Analog
Inputs
Overcurrent
BISEN
RSENSE
+
Undervoltage
Thermal
nFAULT
Output
-
TRQ[1:0]
BVREF
1/Av
GND GND PPAD
Figure 11. DRV8881E Block Diagram
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Functional Block Diagrams (continued)
VM
+
0.1 µF
0.1 µF
bulk
VM
VM
VM
VM
Power
0.47 µF
0.1 µF
VCP
CPH
CPL
Parallel Mode
AOUT1
AOUT2
+
Charge
Pump
Off-
time
PWM
Gate
Drive
Step
Motor
VM
BDC
-
V3P3
10 mA
3.3-V LDO
0.47 µF
+
-
AIN1
AIN2
BIN1
BIN2
AISEN
RSENSE
+
Core Logic
-
TRQ[1:0]
AVREF
1/Av
nSLEEP
PARA
Control
Inputs
VM
TRQ[1:0]
ADECAY
BDECAY
TOFF
V3P3
BOUT1
BOUT2
V3P3
V3P3
Off-
time
PWM
VM
Gate
Drive
BDC
AVREF
BVREF
Protection
Analog
Inputs
Overcurrent
BISEN
RSENSE
+
Undervoltage
Thermal
nFAULT
Output
-
TRQ[1:0]
BVREF
1/Av
GND GND PPAD
Figure 12. DRV8881P Block Diagram
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7.3 Feature Description
7.3.1 Motor Driver Current Ratings
Brushed motor drivers can be classified using two different numbers to describe the output current: peak and
rms. Stepper motor drivers can be described with three numbers: peak, rms, and full-scale.
7.3.1.1 Peak Current Rating
The peak current in a motor driver is limited by the overcurrent protection trip threshold IOCP. The peak current
describes any transient duration current pulse, for example when charging capacitance, when the overall duty
cycle is very low. In general the minimum value of IOCP specifies the peak current rating of the motor driver. For
the DRV8881, the peak current rating is 2.5 A per bridge.
7.3.1.2 RMS Current Rating
The rms (average) current is determined by the thermal considerations of the IC. The rms current is calculated
based on the RDS(ON), rise and fall time, PWM frequency, device quiescent current, and package thermal
performance in a typical system at 25°C. The real operating rms current may be higher or lower depending on
heatsinking and ambient temperature. For the DRV8881, the rms current rating is 1.4 A per bridge. In parallel
mode, the DRV8881P is capable of double the rms output current, or 2.8 A.
7.3.1.3 Full-Scale Current Rating
The full-scale current for a stepper motor describes the top of the sinusoid current waveform while stepping.
Since the sineusoid amplitude is related to the rms current, the full-scale current is also determined by the
thermal considerations of the IC. The full-scale current rating is approximately √2 × Irms. The full-scale current is
set by xVREF, the sense resistor, and Torque DAC when configuring the DRV8881. For the DRV8881, the full-
scale current rating is 2.0 A per bridge.
full-scale current
rms current
Figure 13. Full-Scale and rms Current
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Feature Description (continued)
7.3.2 PWM Motor Drivers
The DRV8881 contains drivers for two full H-bridges. Figure 14 shows a block diagram of the circuitry.
VM
AOUT1
+
Step
Motor
PWM
Logic
Gate
Drive
VM
BDC
-
Device
Logic
AOUT2
AISEN
+
-
+
-
TRQ[1:0]
RSENSE
AVREF
1/Av
Figure 14. PWM Motor Driver Block Diagram
7.3.3 Bridge Control
The DRV8881E is controlled using a PH/EN interface. Table 1 gives the full H-bridge state. Note that this table
does not take into account the current control built into the DRV8881E. Positive current is defined in the direction
of xOUT1 → xOUT2.
Table 1. DRV8881E (PH/EN) Control Interface
nSLEEP
ENx
X
PHx
X
xOUT1
Hi-Z
Hi-Z
L
xOUT2
Hi-Z
Hi-Z
H
V3P3
DESCRIPTION
Sleep mode; H-bridge disabled Hi-Z
H-bridge disabled Hi-Z
0
1
1
1
Disabled
Enabled
Enabled
Enabled
0
X
1
0
Reverse (current xOUT2 → xOUT1)
Forward (current xOUT1 → xOUT2)
1
1
H
L
The DRV8881P is controlled using a PWM interface. Table 2 gives the full H-bridge state. Note that this table
does not take into account the current control built into the DRV8881P. Positive current is defined in the direction
of xOUT1 → xOUT2.
Table 2. DRV8881P (PWM) Control Interface
nSLEEP
xIN1
xIN2
xOUT1
xOUT2
V3P3
DESCRIPTION
Sleep mode; H-bridge disabled Hi-Z
Coast; H-bridge disabled Hi-Z
Reverse (current xOUT2 → xOUT1)
Forward (current xOUT1 → xOUT2)
Brake; low-side slow decay
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Hi-Z
Hi-Z
L
Hi-Z
Hi-Z
H
Disabled
Enabled
Enabled
Enabled
Enabled
H
L
L
L
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7.3.4 Current Regulation
The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage,
inductance of the winding, and the magnitude of the back EMF present. Once the current hits the current
chopping threshold, the bridge enters a decay mode for a fixed period of time to decrease the current, which is
configurable between 10 and 30 µs through the tri-level input TOFF. After the off time expires, the bridge is re-
enabled, starting another PWM cycle.
Table 3. Off-Time Settings
TOFF
OFF-TIME tOFF
20 µs
0
1
Z
30 µs
10 µs
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pin with a reference voltage. To generate the reference voltage for the current chopping
comparator, the xVREF input is attenuated by a factor of Av. In addition, the TRQx pins further scale the
reference.
VM
AOUT1
+
Step
Motor
PWM
Logic
Gate
Drive
VM
BDC
-
Device
Logic
AOUT2
AISEN
+
-
+
-
TRQ[1:0]
RSENSE
AVREF
1/Av
Figure 15. Current Regulation Block Diagram
The chopping current is calculated as follows:
V R E F ( V ) u T R Q (% )
V R E F ( V ) u T R Q (% )
IT R IP ( A )
A
u R S E N S E (: )
6 .6 u R S E N S E (: )
v
(1)
TRQ is a DAC used to scale the output current. The current scalar value for different inputs is shown in Table 4.
Table 4. Torque DAC Settings
TRQ1
TRQ0
CURRENT SCALAR (TRQ)
EFFECTIVE ATTENUATION
1
1
0
0
1
0
1
0
25%
50%
26.4 V/V
13.2 V/V
8.8 V/V
6.6 V/V
75%
100%
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7.3.5 Decay Modes
A fixed decay mode is selected by setting the tri-level ADECAY and BDECAY pins as shown in Table 5. Note
that if the ATE pin is logic high, the ADECAY and BDECAY pins are ignored and AutoTune is used.
Table 5. Decay Mode Settings
xDECAY
DECAY MODE
Slow decay
0
Z
1
Fast decay
Mixed decay: 30% fast
The ADECAY pin sets the decay mode for H-bridge A (AOUT1, AOUT2), and the BDECAY pin sets the decay
mode for H-bridge B (BOUT1, BOUT2).
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7.3.5.1 Mode 1: Slow Decay
To configure the DRV8881 into this mode, pull DECAY1 and DECAY0 logic low.
ITRIP
tBLANK
tDRIVE
tBLANK
tOFF
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
Figure 16. Slow Decay Mode
During slow decay, both of the low-side FETs of the H-bridge are turned on, allowing the current to be
recirculated.
Slow decay exhibits the least current ripple of the decay modes for a given tOFF. However, if the current trip level
is decreasing, slow decay will take a long time to settle to the new ITRIP level because the current decreases very
slowly.
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7.3.5.2 Mode 2: Fast Decay
To configure the DRV8881 into this mode, pull DECAY1 and DECAY0 logic high.
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
Figure 17. Fast Decay Mode
During fast decay, the polarity of the H-bridge is reversed. The H-bridge will be turned off as current approaches
zero in order to prevent current flow in the reverse direction.
Fast decay exhibits the highest current ripple of the decay modes for a given tOFF. Transition time on decreasing
current is much faster than slow decay since the current is allowed to decrease much faster.
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7.3.5.3 Mode 3: 30%/70% Mixed Decay
To configure the DRV8881 into this mode, pull DECAY1 logic high and pull DECAY0 logic low.
ITRIP
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
tDRIVE
ITRIP
tBLANK
tDRIVE
tFAST
tBLANK
tDRIVE
tFAST
tOFF
tOFF
Figure 18. Mixed Decay Mode (30% Fast, 70% Slow)
Mixed decay begins as fast decay for 30% of tOFF, followed by slow decay for the remainder of tOFF. In this mode,
mixed decay occurs for both increasing and decreasing current steps.
This mode exhibits ripple larger than slow decay, but smaller than fast decay. Mixed decay will settle to the new
ITRIP level faster than slow decay when dealing with decreasing current trip levels.
In cases where current is held for a long time or at very-low stepping speeds, slow decay may not properly
regulate current because no back-EMF is present across the motor windings. In this state, motor current can rise
very quickly, and requires an excessively large off-time. Increasing/decreasing mixed decay mode allows the
current level to stay in regulation when no back-EMF is present across the motor windings.
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7.3.6 AutoTune
AutoTune is available on DRV8881E only.
To enable the AutoTune mode, pull the ATE pin logic high. Ensure the xDECAY pins are logic low. The
AutoTune mode is registered internally when exiting from sleep mode or the power-up sequence. The ATE pin
can be shorted to V3P3 to pull it logic high for this purpose.
AutoTune greatly simplifies the decay mode selection by automatically configuring the decay mode between
slow, mixed, and fast decay. In mixed decay, AutoTune dynamically adjusts the fast decay percentage of the
total mixed decay time. This feature eliminates motor tuning by automatically determining the best decay setting
that results in the lowest ripple for the motor.
The decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip
level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle in order to
prevent regulation loss. If there is a long drive time to reach the target trip level, the decay mode becomes less
aggressive (remove fast decay percentage) on the next cycle in order to operate with less ripple and more
efficiently.
AutoTune will automatically adjust the decay scheme based on operating factors like:
•
•
•
•
•
•
Motor winding resistance and inductance
Motor aging effects
Motor dynamic speed and load
Motor supply voltage variation
Motor back-EMF difference on rising and falling steps
Low-current vs. high-current dI/dt
7.3.7 Adaptive Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a period of time before
enabling the current sense circuitry. Note that the blanking time also sets the minimum drive time of the PWM.
The time tBLANK is determined by VREF and the torque DAC setting. The timing information for tBLANK is given in
Table 6.
Table 6. Adaptive Blanking Time Settings over Torque DAC and xVREF Input
Voltage
xVREF
TORQUE DAC TRQ[1:0] SETTING
00 - 100%
1.80 µs
1.50 µs
1.20 µs
0.90 µs
01 - 75%
1.50 µs
1.20 µs
0.90 µs
0.90 µs
10 - 50%
1.20 µs
0.90 µs
0.90 µs
0.90 µs
11 - 25%
0.90 µs
0.90 µs
0.90 µs
0.90 µs
2.475 → 3.300 V
1.650 → 2.475 V
0.825 → 1.650 V
0.000 → 0.825 V
22
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7.3.8 Parallel Mode
To enter parallel mode on the DRV8881P, the PARA pin must be logic high during device power-up or when
exiting the sleep mode. The PARA pin can be shorted to V3P3 to pull it logic high for this purpose.
In this mode, the AIN1 and AIN2 pins control the state of the outputs and the BIN1 and BIN2 pins are ignored.
Similarly, the ADECAY pin controls the decay mode of the output and AVREF is used as the analog reference
voltage. The BIN1, BIN2, BDECAY, and BVREF pins can be tied to GND or left Hi-Z.
VM
+
0.1 µF
0.1 µF
bulk
VM
VM
VM
VM
Power
0.47 µF
0.1 µF
VCP
CPH
CPL
Parallel Mode
AOUT1
Charge
Pump
Off-
time
PWM
Gate
Drive
VM
BDC
AOUT2
AISEN
V3P3
10 mA
3.3-V LDO
0.47 µF
AIN1
AIN2
BIN1
BIN2
+
Core Logic
-
TRQ[1:0]
AVREF
1/Av
nSLEEP
PARA
Control
Inputs
VM
TRQ[1:0]
ADECAY
BDECAY
TOFF
V3P3
BOUT1
BOUT2
V3P3
V3P3
Off-
time
PWM
VM
Gate
Drive
AVREF
BVREF
Protection
Analog
Inputs
Overcurrent
BISEN
RSENSE
Undervoltage
Thermal
nFAULT
Output
GND GND PPAD
Figure 19. Parallel Mode Diagram
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7.3.9 Charge Pump
A charge pump is integrated in order to supply a high-side NMOS gate drive voltage. The charge pump requires
a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins
CPH and CPL.
VM
0.47 µF
VCP
VM
CPH
Charge
VM
0.1 µF
Pump
CPL
Figure 20. Charge Pump Diagram
7.3.10 LDO Voltage Regulator
An LDO regulator is integrated into the DRV8881. It can be used to provide the supply voltage for a low-power
microcontroller or other low-current devices. For proper operation, bypass V3P3 to GND using a ceramic
capacitor.
The V3P3 output is nominally 3.3 V. When the V3P3 LDO current load exceeds 10 mA, the LDO will behave like
a constant current source. The output voltage will drop significantly with currents greater than 10 mA.
VM
+
3.3 V
V3P3
-
10 mA
0.47 µF max
Figure 21. LDO Diagram
If a digital input needs to be tied permanently high (that is, TOFF or ADECAY), it is preferable to tie the input to
V3P3 instead of an external regulator. This will save power when VM is not applied or in sleep mode: V3P3 is
disabled and current will not be flowing through the input pulldown resistors. For reference, logic level inputs
have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 40 kΩ.
24
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7.3.11 Logic and Tri-Level Pin Diagrams
Figure 22 gives the input structure for logic-level pins APH/AIN1, AEN/AIN2, BPH/BIN1, BEN/BIN2, nSLEEP,
ATE/PARA, TRQ0, TRQ1:
V3P3
100 k
Figure 22. Logic-level Input Pin Diagram
Tri-level logic pins TOFF, ADECAY, and BDECAY have the following structure as shown in Figure 23.
V3P3
+
V3P3
±
45 k
40 k
V3P3
+
±
Figure 23. Tri-Level Input Pin Diagram
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7.3.12 Protection Circuits
The DRV8881 is fully protected against VM undervoltage, charge pump undervoltage, overcurrent, and
overtemperature events.
7.3.12.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all FETs in the H-
bridge will be disabled, the charge pump will be disabled, and the nFAULT pin will be driven low. Operation will
resume when VM rises above the UVLO threshold. The nFAULT pin will be released after operation has
resumed.
7.3.12.2 VCP UVLO (CPUV)
If at any time the voltage on the VCP pin falls below the undervoltage lockout threshold voltage, all FETs in the
H-bridge will be disabled and the nFAULT pin will be driven low. Operation will resume when VCP rises above
the CPUV threshold. The nFAULT pin will be released after operation has resumed.
7.3.12.3 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than tOCP, all FETs in the H-bridge will be disabled and nFAULT will be
driven low. In addition to this FET current limit, an overcurrent condition is also detected if the voltage at xISEN
exceeds VOCP
.
For the DRV8881E (PH/EN), both H-bridges are shut down when either bridge encounters an overcurrent fault.
For the DRV8881P (PWM), only the H-bridge driver experiencing the overcurrent fault is shut down, and the
other bridge will remain active.
The driver will be re-enabled after the OCP retry period (tRETRY) has passed. nFAULT becomes high again after
the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal
operation resumes and nFAULT remains deasserted.
7.3.12.4 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. After the die temperature has fallen to a safe level, operation will automatically resume. The nFAULT
pin will be released after operation has resumed.
Table 7. Fault Condition Summary
ERROR
REPORT
CHARGE
PUMP
FAULT
CONDITION
H-BRIDGE
Disabled
Disabled
Disabled
V3P3
RECOVERY
VM < VUVLO
(max 6.4 V)
VM > VUVLO
(max 6.5 V)
VM undervoltage (UVLO)
nFAULT
nFAULT
nFAULT
Disabled
Operating
Operating
Operating
Operating
Operating
VCP undervoltage
(CPUV)
VCP < VCPUV
(typ VM + 1.8 V)
VCP > VCPUV
(typ VM + 1.9 V)
TJ > TTSD
(min 150°C)
TJ < TTSD- THYS
(THYS typ 35°C)
Thermal shutdown (TSD)
IOUT > IOCP
(min 2.5 A)
VxISEN > VOCP
(min 0.9 V)
Overcurrent (OCP)
nFAULT
Disabled
Operating
Operating
tRETRY
26
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ZHCSDY9A –JUNE 2015–REVISED JULY 2015
7.4 Device Functional Modes
The DRV8881 is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled,
the H-bridge FETs are disabled Hi-Z, and the V3P3 regulator is disabled. Note that tSLEEP must elapse after a
falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8881 is brought out of sleep mode
automatically if nSLEEP is brought logic high. Note that tWAKE must elapse before the outputs change state after
wake-up.
Table 8. Functional Modes Summary
FAULT
Operating
CONDITION
H-BRIDGE
CHARGE PUMP
V3P3
6.5 V < VM < 45 V
nSLEEP pin = 1
Operating
Operating
Operating
6.5 V < VM < 45 V
nSLEEP pin = 0
Sleep mode
Disabled
Disabled
Disabled
VM undervoltage (UVLO)
VCP undervoltage (CPUV)
Overcurrent (OCP)
Disabled
Disabled
Disabled
Disabled
Disabled
Operating
Operating
Operating
Operating
Operating
Operating
Operating
Fault encountered
Thermal shutdown (TSD)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8881 is used in stepper or brushed motor control.
8.2 Typical Applications
8.2.1 DRV8881P Typical Application
The following design procedure can be used to configure the DRV8881. In this application, the DRV8881P will be
used to drive a stepper motor.
DRV8881PPWP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
GND
CPL
CPH
2
0.1 µF
TRQ0
TRQ1
PARA
AIN1
VM
0.1 µF
3
VCP
4
0.47 µF
VM
5
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
250 m
6
Step
AIN2
Motor
7
BIN1
8
+
-
BIN2
250 m
9
ADECAY
BDECAY
nFAULT
nSLEEP
TOFF
10
11
12
13
14
VM
+
GND
100 µF
0.1 µF
10 k
AVREF
BVREF
V3P3
R1
R2
0.47 µF
Figure 24. Typical Application Schematic
28
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Typical Applications (continued)
8.2.1.1 Design Requirements
Table 9 gives design input parameters for system design.
Table 9. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
EXAMPLE VALUE
24 V
VM
RL
Motor winding resistance
Motor winding inductance
Motor full step angle
4.5 Ω/phase
10.5 mH/phase
1.8°/step
LL
θstep
nm
v
Target microstepping level
Target motor speed
Non-circular 1/2 step
120 rpm
Target full-scale current
IFS
800 mA
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Current Regulation
In a stepper motor, the full-scale current (IFS) is the maximum current driven through either winding. This quantity
will depend on the TRQ pins, the xVREF analog voltage, and the sense resistor value (RSENSE). AVREF and
BVREF can be configured to drive different currents, but in this example the same full-scale current is used in
both coils.
xV R E F ( V ) u T R Q (% )
xV R E F ( V ) u T R Q (% )
IF S ( A )
A
u R S E N S E (: )
6 .6 u R S E N S E ( : )
v
(2)
TRQ is a DAC used to scale the output current. The current scalar value for different inputs is shown in Table 10.
Table 10. Torque DAC Settings
TRQ1
TRQ0
CURRENT SCALAR (TRQ)
1
1
0
0
1
0
1
0
25%
50%
75%
100%
Example: If the desired full-scale current is 800 mA
Set RSENSE = 250 mΩ, assume TRQ = 100%.
xVREF would have to be 1.32 V.
Create a resistor divider from V3P3 (3.3 V) to set AVREF and BVREF ≈ 1.32 V.
Set R2 = 10 kΩ, set R1 = 15 kΩ
Note that IFS must also follow Equation 3 in order to avoid saturating the motor. VM is the motor supply voltage,
and RL is the motor winding resistance.
VM (V)
IFS (A) ꢀ
RL (:) ꢁ 2 u RDS(ON) (:) ꢁ RSENSE (:)
(3)
8.2.1.2.2 Stepper Motor Speed
Next, the driving waveform needs to be planned. In order to command the correct speed, determine the
frequency of the input waveform.
If the target motor speed is too high, the motor will not spin. Make sure that the motor can support the target
speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
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v (rpm) u 360 (q / rot)
step (q / step) unm (steps / microstep) u 60 (s / min)
¦
ꢀVWHSV ꢁ Vꢂ
step
T
(4)
θstep can be found in the stepper motor data sheet or written on the motor itself.
The frequency ƒstep gives the frequency of input change on the DRV8881P. 1/ ƒstep = tSTEP on the diagram below.
120 rpm u 360q / rot
1.8q / step u1/ 2 steps / microstep u 60 s / min
¦
ꢀVWHSV ꢁ Vꢂ
ꢃꢄꢄ+]
step
(5)
Figure 25. Example 1/2 Stepping Operation
8.2.1.2.3 Decay Modes
The DRV8881 supports several different decay modes: slow decay, fast decay, mixed decay, and AutoTune
(DRV8881E only). The current through the motor windings is regulated using an adjustable fixed-time-off
scheme. This means that after any drive phase, when a motor winding current has hit the current chopping
threshold (ITRIP), the DRV8881 will place the winding in one of the decay modes for TOFF. After TOFF, a new
drive phase starts.
8.2.1.2.4 Sense Resistor
For optimal performance, it is important for the sense resistor to be:
•
•
•
•
Surface-mount
Low inductance
Rated for high enough power
Placed closely to the motor driver
The power dissipated by the sense resistor equals Irms 2 × R. For example, if the rms motor current is 1.4 A and a
250 mΩ sense resistor is used, the resistor will dissipate 1.4 A2 × 0.25 Ω = 0.49 W. The power quickly increases
with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be
added. It is always best to measure the actual sense resistor temperature in a final system, along with the power
MOSFETs, as those are often the hottest components.
30
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Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.
8.2.1.3 Application Curve
Figure 26. DRV8881P Inputs and Output Current Waveform
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8.2.2 Alternate Application
In this application, the DRV8881P will be operated in parallel mode in order to drive a single brushed-DC motor.
DRV8881PPWP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
GND
CPL
CPH
2
0.1 µF
TRQ0
TRQ1
PARA
AIN1
VM
0.1 µF
3
VCP
4
0.47 µF
V3P3
VM
5
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
100 m
6
AIN2
7
BIN1
BDC
8
BIN2
9
ADECAY
BDECAY
nFAULT
nSLEEP
TOFF
10
11
12
13
14
VM
+
GND
100 µF
0.1 µF
10 k
AVREF
BVREF
V3P3
R1
0.47 µF
R2
Figure 27. Typical Application Schematic
8.2.2.1 Design Requirements
Table 11 gives design input parameters for system design.
Table 11. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
EXAMPLE VALUE
VM
RL
24 V
6 Ω
Motor winding resistance
Motor winding inductance
Target maximum motor current
LL
4.1 mH
2 A
ITRIP
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Current Regulation
The maximum current (ITRIP) is set by the TRQ pins, the xVREF analog voltage, and the sense resistor value
(RSENSE). In parallel mode the winding current is set by AVREF only and BVREF is ignored. When starting a
brushed-DC motor, a large inrush current may occur because there is no back-EMF. Current regulation will act to
limit this inrush current and prevent high current on startup.
Example: If the desired regulation current is 2 A
Set RSENSE = 100 mΩ, assume TRQ = 100%.
AVREF would have to be 1.32 V.
Create a resistor divider from V3P3 (3.3 V) to set AVREF ≈ 1.32 V: Set R2 = 10 kΩ, set R1 = 15 kΩ
32
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8.2.2.3 Application Curves
Figure 28. DRV8881P Startup Current Waveform Without
Current Regulation
Figure 29. DRV8881P Startup Current Waveform Without
Current Regulation (Zoomed In)
Figure 30. DRV8881P Startup Current Waveform With 2-A
Current Regulation
Figure 31. DRV8881P Startup Current Waveform With 2-A
Current Regulation (Zoomed In)
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9 Power Supply Recommendations
The DRV8881 is designed to operate from an input voltage supply (VM) range between 6.5 V and 45 V. THe
device has an absolute maximum rating of 50 V. A 0.1 µF ceramic capacitor rated for VM must be placed at each
VM pin as close to the DRV8881 as possible. In addition, a bulk capacitor must be included on VM.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
±
GND
Local
IC Bypass
Bulk Capacitor
Capacitor
Figure 32. Setup of Motor Drive System With External Power Supply
34
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10 Layout
10.1 Layout Guidelines
Each VM terminal must be bypassed to GND using a low-ESR ceramic bypass capacitors with recommended
values of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a
thick trace or ground plane connection to the device GND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an
electrolytic.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.1 μF rated for VM
is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.47 μF rated for 16
V is recommended. Place this component as close to the pins as possible.
Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
The current sense resistors should be placed as close as possible to the device pins in order to minimize trace
inductance between the pin and resistor.
10.2 Layout Example
+
0.1 µF
CPL
CPH
GND
TRQ0
0.1 µF
VCP
TRQ1
VM
PARA
AIN1
0.47 µF
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
VM
AIN2
BIN1
BIN2
ADECAY
BDECAY
nFAULT
nSLEEP
TOFF
0.1 µF
GND
BVREF
AVREF
V3P3
0.1 µF
Figure 33. Layout Recommendation
版权 © 2015, Texas Instruments Incorporated
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ZHCSDY9A –JUNE 2015–REVISED JULY 2015
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
•
•
•
•
•
•
《PowerPAD™ 耐热增强型封装》，SLMA002
《PowerPAD™ 速成》，SLMA004
《电流再循环和衰减模式》，SLVA321
《计算电机驱动器的功耗》，SLVA504
《了解电机驱动器的额定电流》，SLVA505
《采用 DRV88xx 系列的高分辨率微步进驱动器》，SLVA416
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
36
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8881EPWP
DRV8881EPWPR
DRV8881ERHRR
DRV8881ERHRT
DRV8881PPWP
DRV8881PPWPR
DRV8881PRHRR
DRV8881PRHRT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
WQFN
PWP
PWP
RHR
RHR
PWP
PWP
RHR
RHR
28
28
28
28
28
28
28
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DRV8881E
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
DRV8881E
DRV8881E
DRV8881E
DRV8881P
DRV8881P
DRV8881P
DRV8881P
WQFN
250
250
RoHS & Green
RoHS & Green
HTSSOP
HTSSOP
WQFN
2000 RoHS & Green
3000 RoHS & Green
WQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8881EPWPR
DRV8881ERHRR
DRV8881ERHRT
DRV8881PPWPR
DRV8881PRHRR
DRV8881PRHRT
HTSSOP PWP
28
28
28
28
28
28
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
16.4
12.4
12.4
16.4
12.4
12.4
6.9
3.8
3.8
6.9
3.8
3.8
10.2
5.8
1.8
1.2
1.2
1.8
1.2
1.2
12.0
8.0
16.0
12.0
12.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
WQFN
WQFN
RHR
RHR
5.8
8.0
HTSSOP PWP
2000
3000
250
10.2
5.8
12.0
8.0
WQFN
WQFN
RHR
RHR
5.8
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8881EPWPR
DRV8881ERHRR
DRV8881ERHRT
DRV8881PPWPR
DRV8881PRHRR
DRV8881PRHRT
HTSSOP
WQFN
PWP
RHR
RHR
PWP
RHR
RHR
28
28
28
28
28
28
2000
3000
250
350.0
346.0
210.0
350.0
346.0
210.0
350.0
346.0
185.0
350.0
346.0
185.0
43.0
33.0
35.0
43.0
33.0
35.0
WQFN
HTSSOP
WQFN
2000
3000
250
WQFN
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DRV8881EPWP
DRV8881PPWP
PWP
PWP
HTSSOP
HTSSOP
28
28
50
530
530
10.2
10.2
3600
3600
3.5
3.5
250
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RHR 28
3.5 x 5.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4210249/B
www.ti.com
PACKAGE OUTLINE
RHR0028A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
0.5
0.3
5.6
5.4
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
2±0.1
2X 1.5
(0.2) TYP
EXPOSED
THERMAL PAD
11
14
24X 0.5
10
15
2X
4.5
4±0.1
SEE TERMINAL
DETAIL
1
24
0.3
28X
28
25
0.5
0.2
PIN 1 ID
(OPTIONAL)
0.1
C A
B
28X
0.3
0.05
4219075/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
SYMM
28X (0.6)
28X (0.25)
25
28
1
24
24X (0.5)
(0.66)
(5.3)
TYP
SYMM
(4)
(
0.2) TYP
VIA
15
10
11
14
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219075/A 11/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.55) TYP
28
25
28X (0.6)
28X (0.25)
1
24
24X (0.5)
SYMM
(1.32)
TYP
(5.3)
METAL
TYP
6X (1.12)
15
10
14
11
6X (0.89)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219075/A 11/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
PACKAGE OUTLINE
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
8.45
NOTE 3
14
15
0.30
0.19
28X
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
14
15
2X 0.2 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
5.18
4.48
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
28
3.1
2.4
4223582/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
(5.18)
(0.6)
26X (0.65)
SYMM
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
(
0.2) TYP
VIA
14
15
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4223582/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28X (0.45)
28
(R0.05) TYP
26X (0.65)
SYMM
(5.18)
BASED ON
0.125 THICK
STENCIL
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.47 X 5.79
3.10 X 5.18 (SHOWN)
2.83 X 4.73
0.125
0.15
0.175
2.62 X 4.38
4223582/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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