DRV8885RHRR [TI]
具有集成电流感应功能和 1/16 微步进的 37V、1.5A 双极步进电机驱动器 | RHR | 28 | -40 to 125;
| 型号： | DRV8885RHRR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电流感应功能和 1/16 微步进的 37V、1.5A 双极步进电机驱动器 | RHR | 28 | -40 to 125 电机 驱动 驱动器 |
| 文件： | 总46页 (文件大小：2821K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
DRV8885 具有集成电流检测功能的 1.5A 步进电机驱动器
1 特性
2 应用
1
•
脉宽调制 (PWM) 微步进电机驱动器
•
•
•
•
•
•
•
多功能打印机和扫描仪
激光束打印机
–
–
最高 1/16 微步进
3D 打印机
非循环和标准 ½ 步进模式
自动取款机和验钞机
视频安保摄像机
办公自动化设备
工厂自动化和机器人
•
集成电流检测功能
–
–
无需检测电阻
±6.25% 满量程电流精度
•
•
•
慢速衰减和混合衰减选项
8.0V 至 37V 的工作电源电压范围
3 说明
低 RDS(ON)：24V 和 25°C 条件下为 0.86Ω HS +
DRV8885 是一款面向工业设备应用的步进电机 应用。
此器件具有两个 N 沟道功率金属氧化物半导体场效应
晶体管 (MOSFET) H 桥驱动器、一个微步进分度器以
及集成电流检测功能。DRV8885 能够驱动高达 1.5A
的满量程输出电流或 1.0A rms 输出电流（采用适当的
印刷电路板 (PCB) 接地层进行散热，电压为 24V，TA
= 25°C）。
LS
•
高电流容量
–
–
每个桥的满量程为 1.5A
每个桥的均方根 (rms) 为 1.0A
•
•
•
•
固定的关断时间 PWM 斩波
简单的 STEP/DIR 接口
低电流休眠模式 (20μA)
小型封装和外形尺寸
DRV8885 集成了电流检测功能，消除了对两个外部检
测电阻的需求。
–
24 引脚散热薄型小外形尺寸 (HTSSOP)
PowerPAD™封装
STEP/DIR 引脚提供简单的控制接口。器件可配置为多
种步进模式，从全步进模式到 1/16 步进模式。凭借专
用的 nSLEEP 引脚，该器件可提供一种低功耗的休眠
模式，从而实现超低静态电流待机。
–
28 WQFN 封装
•
保护 特性
–
–
–
–
–
VM 欠压锁定 (UVLO)
电荷泵欠压 (CPUV)
过流保护 (OCP)
该器件内置以下保护功能：欠压、电荷泵故障、过流、
短路以及过热保护。故障状态通过 nFAULT 引脚指
示。
热关断 (TSD)
故障条件指示引脚 (nFAULT)
器件信息 (1)
器件型号
DRV8885
封装
HTSSOP (24)
WQFN (28)
封装尺寸（标称值）
7.80mm × 4.40mm
5.50mm × 3.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
微步进电流波形
8 to 37 V
Full-scale current
RMS current
DRV8885
STEP/DIR
1.5 A
1.5 A
M
Stepper
Motor
Driver
Step size
+
œ
Decay mode
Current Sense
AOUT
BOUT
1/16 µstep
Step Input
Copyright © 2016, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSD39
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 27
Power Supply Recommendations...................... 30
9.1 Bulk Capacitance ................................................... 30
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Indexer Timing Requirements................................... 8
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 器件和文档支持 ..................................................... 32
11.1 文档支持................................................................ 32
11.2 接收文档更新通知 ................................................. 32
11.3 社区资源................................................................ 32
11.4 商标....................................................................... 32
11.5 静电放电警告......................................................... 32
11.6 术语表 ................................................................... 32
12 机械、封装和可订购信息....................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (July 2018) to Revision C
Page
•
已更改 器件状态从“预告信息”更改为“生产数据”...................................................................................................................... 1
Changes from Revision A (April 2016) to Revision B
Page
•
•
•
•
已添加 WQFN 封装选项 ......................................................................................................................................................... 1
Deleted and internal indexer from the description of the ENABLE pin in the Pin Functions table......................................... 3
Changed until ENABLE is deasserted to until ENABLE is asserted in the Device Functional Modes section .................... 26
已添加 接收文档更新通知部分.............................................................................................................................................. 32
Changes from Original (October 2015) to Revision A
Page
•
•
•
•
•
Updated peak drive current based on OCP ........................................................................................................................... 4
Updated RPD and RPU values ................................................................................................................................................. 6
Fixed chopping current equation .......................................................................................................................................... 18
Added "Controlling RREF with a PWM Resource"............................................................................................................... 18
Fixed resistance values in tri-level input pin diagram........................................................................................................... 24
2
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
5 Pin Configuration and Functions
PWP PowerPAD™ Package
24-Pin HTSSOP
RHR Package
28-Pin WQFN With Exposed Thermal Pad
Top View
Top View
CPL
CPH
1
24
23
22
21
20
19
18
17
16
15
14
13
DECAY
TRQ
2
VCP
3
M1
VCP
VM
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
TRQ
VM
4
M0
M1
AOUT1
PGND
AOUT2
BOUT2
PGND
BOUT1
VM
5
DIR
AOUT1
PGND
AOUT2
BOUT2
PGND
BOUT1
VM
M0
6
STEP
ENABLE
nSLEEP
RREF
nFAULT
DVDD
AVDD
Thermal
Pad
DIR
7
Thermal
Pad
STEP
ENABLE
nSLEEP
RREF
nFAULT
NC
8
9
10
11
12
GND
GND
Not to scale
Not to scale
Pin Functions
PIN
NO.
HTSSOP WQFN
TYPE(1)
DESCRIPTION
NAME
AOUT1
AOUT2
AVDD
BOUT1
BOUT2
CPH
5
7
3
5
O
PWR
O
Winding A output. Connect to stepper motor winding.
13
10
8
12
8
Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.
Winding B output. Connect to stepper motor winding.
6
2
28
27
PWR
I
Charge pump switching node. Connect a X5R or X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL.
CPL
1
Decay-mode setting. Sets the decay mode (see the Decay Modes section). Decay mode can be adjusted during
operation.
DECAY
24
25
DIR
20
14
18
12
21
22
21
13
19
10
22
23
11
14
15
26
4
I
Direction input. Logic level sets the direction of stepping; internal pulldown resistor.
Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.
Enable driver input. Logic high to enable device outputs; logic low to disable; internal pulldown resistor.
Device ground. Connect to system ground.
DVDD
ENABLE
GND
M0
PWR
I
PWR
I
Microstepping mode-setting. Sets the step mode; tri-level pins; sets the step mode; internal pulldown resistor.
M1
NC
—
—
No connect. No internal connection
6
9
PGND
RREF
PWR
I
Power ground. Connect to system ground.
7
16
17
Current-limit analog input. Connect a resistor to ground to set full-scale regulation current.
(1) I = input, O = output, PWR = power, OD = open-drain
Copyright © 2015–2018, Texas Instruments Incorporated
3
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
Pin Functions (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
STEP
HTSSOP WQFN
19
23
3
20
24
1
I
I
Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor.
Current-scaling control. Scales the output current; tri-level pin.
TRQ
VCP
PWR
Charge pump output. Connect a X5R or X7R, 0.22-μF, 16-V ceramic capacitor to VM.
4
2
Power supply. Connect to motor supply voltage and bypass to GND with two 0.01-μF ceramic capacitors (one for
each pin) plus a bulk capacitor rated for VM.
VM
PWR
11
15
9
nFAULT
nSLEEP
16
OD
I
Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown
resistor.
17
18
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
0
MAX
40
UNIT
V
Power supply voltage (VM)
Power supply voltage ramp rate (VM)
Charge pump voltage (VCP, CPH)
Charge pump negative switching pin (CPL)
Internal regulator voltage (DVDD)
Internal regulator current output (DVDD)
Internal regulator voltage (AVDD)
2
V/µs
V
–0.3
–0.3
–0.3
0
VM + 7
VM
V
3.8
V
1
mA
V
–0.3
–0.3
0
5.7
Control pin voltage (STEP, DIR, ENABLE, nFAULT, M0, M1, DECAY, TRQ, nSLEEP)
Open drain output current (nFAULT)
5.7
V
10
mA
V
Current limit input pin voltage (RREF)
–0.3
–0.7
6.0
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2)
Operating junction temperature, TJ
VM + 0.7
2.3
V
A
–40
–65
150
150
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
V(ESD)
Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
MAX
UNIT
V
VM
Power supply voltage range
Logic level input voltage
Applied STEP signal (STEP)
DVDD external load current
Motor full scale current
37
VCC
ƒPWM
IDVDD
IFS
0
5.3
V
(1)
0
100
kHz
mA
A
(2)
0
1
0
1.5
1.0
Irms
Motor rms current
0
A
TA
Operating ambient temperature
–40
125
°C
(1) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load
(2) Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8885
(1)
THERMAL METRIC
PWP (HTSSOP)
RHR (WQFN)
28 PINS
33.6
UNIT
24 PINS
36.1
18.3
15.8
0.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
23.8
12.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
15.7
1.1
12.6
RθJC(bot)
3.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2015–2018, Texas Instruments Incorporated
5
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, DVDD, AVDD)
VVM
VM operating voltage
8
37
8
V
VM ≈ 8 to 35 V, ENABLE = 1,
nSLEEP = 1, No motor load
IVM
VM operating supply current
5
mA
nSLEEP = 0; TA = 25°C
20
40
IVMQ
VM sleep mode supply current
μA
(1)
nSLEEP = 0; TA = 125°C
tSLEEP
tWAKE
tON
Sleep time
nSLEEP = 0 to sleep-mode
nSLEEP = 1 to output transition
VM > UVLO to output transition
0- to 1-mA external load
No external load
50
0.85
0.85
3.3
200
1.5
1.5
3.6
5.5
μs
ms
ms
V
Wake-up time
Turn-on time
VDVDD
VAVDD
Internal regulator voltage
Internal regulator voltage
2.9
4.5
5.0
V
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage
VM > 8 V
VM + 5.5
V
LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, M1)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
0
1.6
100
–1
0.8
5.3
V
V
mV
μA
μA
kΩ
μs
VIN = 0 V
1
IIH
VIN = 5.0 V
100
RPD
tPD
To GND
100
1.1
STEP to current change
1.2
TRI-LEVEL INPUT (M0, TRQ)
VIL
VIZ
Tri-level input logic low voltage
0
0.65
V
V
Tri-level input Hi-Z voltage
Tri-level input logic high
voltage
VIH
1.5
5.3
V
IIL
IIZ
Tri-level input logic low current VIN = 0 V
–80
–5
μA
μA
Tri-level input Hi-Z current
VIN = 1.3 V
5
Tri-level input logic high
current
IIH
VIN = 5.0 V
155
μA
RPD
RPU
Tri-level pulldown resistance
Tri-level pullup resistance
To GND
18
30
32
60
50
90
kΩ
kΩ
To DVDD
QUAD-LEVEL INPUT (DECAY)
VI1
VI2
VI3
VI4
IO
Quad-level input voltage 1
5% resistor 5 kΩ to GND
5% resistor 15 kΩ to GND
5% resistor 45 kΩ to GND
5% resistor 135 kΩ to GND
To GND
0.07
0.24
0.71
2.12
14
0.11
0.32
0.97
2.90
22
0.13
0.40
1.20
3.76
30
V
V
Quad-level input voltage 2
Quad-level input voltage 3
Quad-level input voltage 4
Output current
V
V
μA
CONTROL OUTPUTS (nFAULT)
VOL
IOH
Output logic low voltage
Output logic high leakage
IO = 1 mA, RPULLUP = 4.7 kΩ
VO = 5.0 V, RPULLUP = 4.7 kΩ
0.5
+1
V
–1
μA
(1) Not tested in production; limits are based on characterization data
6
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON)
RDS(ON)
High-side FET on resistance
Low-side FET on resistance
Output rise time
VM = 24 V, I = 1 A, TA = 25°C
VM = 24 V, I = 1 A, TA = 25°C
440
420
100
100
200
0.7
490
460
mΩ
mΩ
ns
(2)
tRISE
(2)
tFALL
Output fall time
ns
(2)
tDEAD
Output dead time
ns
(2)
Vd
Body diode forward voltage
IOUT = 0.5 A
1.0
V
PWM CURRENT CONTROL (RREF)
ARREF
VRREF
tOFF
RREF transimpedance gain
RREF voltage
28.1
1.18
30
1.232
20
31.9
1.28
kAΩ
V
RREF = 18 to 132 kΩ
PWM off-time
μs
Equivalent capacitance on
RREF
CRREF
10
pF
µs
IRREF = 1.5 A, 63% to 100% current
setting
1.5
1.0
tBLANK
PWM blanking time
Current trip accuracy
IRREF = 1.5 A, 0% to 63% current
setting
IRREF = 1.0 A, 10% to 20% current
setting, 1% reference resistor
–25%
–12.5%
–6.25%
25%
12.5%
6.25%
IRREF = 1.0 A, 20% to 63% current
setting, 1% reference resistor
ΔITRIP
IRREF = 1.0 A, 71% to 100% current
setting, 1% reference resistor
PROTECTION CIRCUITS
VM falling; UVLO report
VM rising; UVLO recovery
Rising to falling threshold
VCP falling; CPUV report
7.8
8.0
VUVLO
VM UVLO
V
VUVLO,HYS
VCPUV
Undervoltage hysteresis
100
mV
V
Charge pump undervoltage
VM + 2.0
Overcurrent protection trip
level
IOCP
Current through any FET
2.3
A
tOCP
Overcurrent deglitch time
Overcurrent retry time
1.3
1
1.9
20
2.8
1.6
μs
tRETRY
ms
Thermal shutdown
temperature
(2)
TTSD
Die temperature TJ
Die temperature TJ
150
°C
°C
(2)
THYS
Thermal shutdown hysteresis
(2) Not tested in production; limits are based on characterization data
Copyright © 2015–2018, Texas Instruments Incorporated
7
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
6.6 Indexer Timing Requirements
TA = 25°C, over recommended operating conditions unless otherwise noted
NO.
MIN
MAX
UNIT
kHz
ns
(1)
1
2
3
4
5
ƒSTEP
Step frequency
500
tWH(STEP)
tWL(STEP)
tSU(DIR, Mx)
tH(DIR, Mx)
Pulse duration, STEP high
970
970
200
200
Pulse duration, STEP low
ns
Setup time, DIR or USMx to STEP rising
Hold time, DIR or USMx to STEP rising
ns
ns
(1) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load
1
3
2
STEP
DIR, Mx
5
4
Figure 1. Timing Diagram
8
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
6.7 Typical Characteristics
Over recommended operating conditions (unless otherwise noted)
6.4
6.2
6
6.2
6
5.8
5.6
5.4
5.2
5
5.8
T A = 125°C
T A = 85°C
5.6
T A = 25°C
T A = -40°C
5.4
5.2
5
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
(èC)
100
120
140
Supply Voltage VM (V)
Ambient Temperature T
A
D001
D002
Figure 2. Supply Current over VM
Figure 3. Supply Current over Temperature (VM = 24 V)
20
18
16
14
12
10
8
16
T A = 125°C
T A = 85°C
T A = 25°C
T A = -40°C
15
14
13
12
11
10
9
8
6
7
4
6
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
(èC)
100
120
140
Supply Voltage VM (V)
Ambient Temperature T
A
D003
D004
Figure 4. Sleep Current over VM
Figure 5. Sleep Current over Temperature (VM = 24 V)
650
600
550
500
450
400
350
300
630
TA = +125°C
600
570
540
510
480
450
420
390
360
330
TA = +85°C
TA = +25°C
TA = -40°C
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D005
D006
Figure 6. High-Side RDS(ON) over VM
Figure 7. High-Side RDS(ON) over Temperature (VM = 24 V)
Copyright © 2015–2018, Texas Instruments Incorporated
9
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
Typical Characteristics (continued)
Over recommended operating conditions (unless otherwise noted)
600
600
570
540
510
480
450
420
390
360
330
300
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
550
500
450
400
350
300
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D007
D008
Figure 8. Low-Side RDS(ON) over VM
Figure 9. Low-Side RDS(ON) over Temperature (VM = 24 V)
3.339
3.336
3.333
3.33
2
TRQ = 0
TRQ = Z
TRQ = 1
1
0.7
0.5
3.327
3.324
3.321
3.318
3.315
3.312
3.309
3.306
3.303
0.3
0.2
0.1
0.07
0.05
T A = 125°C
T A = 85°C
T A = 25°C
T A = -40°C
0.03
0.02
0.01
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
10
20
30
40 50 60 70
100
200
300
DVDD Load (mA)
R REF (kW)
D009
D010
Figure 10. DVDD Regulator over Load (VM = 24 V)
Figure 11. Full-Scale Current over RREF Selection
10
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
7 Detailed Description
7.1 Overview
The DRV8885 is an integrated motor driver solution for bipolar stepper motors. The device integrates two NMOS
H-bridges, integrated current sense and regulation circuitry, and a microstepping indexer. The DRV8885 can be
powered with a supply voltage between 8 and 37 V, and is capable of providing an output current up 2.3-A peak,
1.5-A full-scale, or 1.0-A rms. Actual full-scale and rms current will depend on ambient temperature, supply
voltage, and PCB ground plane size.
The DRV8885 integrates current sense functionality, which eliminates the need for high-power external sense
resistors. This integration does not dissipate the external sense resistor power, because the current sense
functionality is not implemented using a resistor-based architecture. This functionality helps improve component
cost, board size, PCB layout, and system power consumption.
A simple STEP/DIR interface allows easy interfacing to the controller circuit. The internal indexer is able to
execute high-accuracy microstepping without requiring the processor to control the current level. The indexer is
capable of full step and half step as well as microstepping to 1/4, 1/8, and 1/16. In addition to the standard half
stepping mode, a non-circular 1/2-stepping mode is available for increased torque output at higher motor rpm.
The current regulation is configurable with several decay modes of operation. The decay mode can be selected
as a fixed slow, slow/mixed, or mixed decay. The slow/mixed decay mode uses slow decay on increasing steps
and mixed decay on decreasing steps.
An adaptive blanking time feature automatically scales the minimum drive time with output current. This helps
alleviate zero-crossing distortion by limiting the drive time at low-current steps.
A torque DAC feature allows the controller to scale the output current without needing to scale the reference
resistor. The torque DAC is accessed using a digital input pin. This allows the controller to save power by
decreasing the current consumption when not high current is not required.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
Copyright © 2015–2018, Texas Instruments Incorporated
11
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
7.2 Functional Block Diagram
VM
+
0.01 µF
0.01 µF
bulk
VM
VM
VM
VM
Power
Adaptive
Blanking
0.22 µF
VCP
AOUT1
CPH
Charge Pump
0.022 µF
CPL
AIREF
+
-
+
Step
AVDD
Motor
5.0-V LDO
3.3-V LDO
VM
0.47 µF
DVDD
œ
1 mA
0.47 µF
+
œ
AOUT2
STEP
DIR
-
+
AIREF
IREF
PGND
Core Logic
ENABLE
nSLEEP
M[1:0]
AIREF
4
SINE DAC
VM
Control
Inputs
DVDD
BOUT1
DVDD
DECAY
TRQ
DVDD
BIREF
-
+
VM
DVDD
IREF
Analog
Input
RREF
BOUT2
PGND
RREF
Protection
Overcurrent
-
+
Output
BIREF
IREF
nFAULT
Undervoltage
Thermal
BIREF
4
SINE DAC
GND
PPAD
Copyright © 2016, Texas Instruments Incorporated
12
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
7.3 Feature Description
Table 1 lists the recommended external components for the DRV8885 device.
Table 1. External Components
COMPONENT
CVM
PIN 1
VM
PIN 2
GND
GND
VM
RECOMMENDED
Two 0.01-µF ceramic capacitors rated for VM
Bulk electrolytic capacitor rated for VM
16-V, 0.22-µF ceramic capacitor
0.022-µF X7R capacitor rated for VM
6.3-V, 0.47-µF ceramic capacitor
6.3-V, 0.47-µF ceramic capacitor
>4.7 kΩ
CVM
VM
CVCP
VCP
CPH
AVDD
DVDD
CSW
CPL
CAVDD
CDVDD
RnFAULT
GND
GND
nFAULT
(1)
VCC
Resistor to limit chopping current must be installed. See the Typical Application
section for value selection.
RREF
RREF
GND
(1) VCC is not a pin on the DRV8885, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled
up to DVDD
7.3.1 Stepper Motor Driver Current Ratings
Stepper motor drivers can be classified using three different numbers to describe the output current: peak, rms,
and full-scale.
7.3.1.1 Peak Current Rating
The peak current in a stepper driver is limited by the overcurrent protection trip threshold IOCP. The peak current
describes any transient duration current pulse, for example when charging capacitance, when the overall duty
cycle is very low. In general the minimum value of IOCP specifies the peak current rating of the stepper motor
driver. For the DRV8885, the peak current rating is 2.3 A per bridge.
7.3.1.2 RMS Current Rating
The rms (average) current is determined by the thermal considerations of the IC. The rms current is calculated
based on the RDS(ON), rise and fall time, PWM frequency, device quiescent current, and package thermal
performance in a typical system at 25°C. The real operating rms current may be higher or lower depending on
heatsinking and ambient temperature. For the DRV8885, the rms current rating is 1.0 A per bridge.
7.3.1.3 Full-Scale Current Rating
The full-scale current describes the top of the sinusoid current waveform while microstepping. Since the
sineusoid amplitude is related to the rms current, the full-scale current is also determined by the thermal
considerations of the IC. The full-scale current rating is approximately √2 × Irms. The full-scale current is set by
VREF, the sense resistor, and Torque DAC when configuring the DRV8885, see Current Regulation for details.
For the DRV8885, the full-scale current rating is 1.5 A per bridge.
Full-scale current
RMS current
AOUT
BOUT
Step Input
Figure 12. Full-Scale and rms Current
Copyright © 2015–2018, Texas Instruments Incorporated
13
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
7.3.2 PWM Motor Drivers
The DRV8885 contains drivers for two full H-bridges. Figure 13 shows a block diagram of the circuitry.
VM
AOUT1
Gate
Drive
AIREF
+
Step
œ
Motor
PWM Logic
+
VM
Device Logic
œ
AOUT2
+
œ
Gate
Drive
AIREF
œ
+
PGND
Copyright © 2016, Texas Instruments Incorporated
Figure 13. PWM Motor Driver Block Diagram
7.3.3 Microstepping Indexer
Built-in indexer logic in the DRV8885 allows a number of different stepping configurations. The Mx pins are used
to configure the stepping format as shown in Table 2.
Table 2. Microstepping Settings
M1
0
M0
0
STEP MODE
Full step (2-phase excitation) with 71% current
0
1
1/16 step
1
0
1/2 step
1
1
1/4 step
0
Z
1/8 step
1
Z
Non-circular 1/2 step
Table 3 shows the relative current and step directions for full-step through 1/16-step operation. The AOUT
current is the sine of the electrical angle; BOUT current is the cosine of the electrical angle. Positive current is
defined as current flowing from xOUT1 to xOUT2 while driving.
At each rising edge of the STEP input the indexer travels to the next state in the table. The direction is shown
with the DIR pin logic high. If the DIR pin is logic low, the sequence is reversed.
On power-up or when exiting sleep mode, keep the STEP pin logic low, otherwise the indexer will advance one
step.
14
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
Note that if the step mode is changed from full, ½, ¼, 1/8, or 1/16 to full, ½, ¼, 1/8, or 1/16 while stepping, the
indexer will advance to the next valid state for the new MODE setting at the rising edge of STEP. If the step
mode is changed from or to non-circular ½ step the indexer will go immediately to the valid state for that mode.
The home state is an electrical angle of 45°. This state is entered after power-up, after exiting logic undervoltage
lockout, or after exiting sleep mode. This is shown in the table below with cells outlined in red.
Table 3. Microstepping Relative Current Per Step (DIR = 1)
FULL STEP
1/2 STEP
1/4 STEP
1/8 STEP
1/16 STEP
ELECTRICAL
ANGLE
(DEGREES)
AOUT
BOUT
CURRENT (% CURRENT (%
FULL-SCALE) FULL-SCALE)
1
1
1
2
1
0.000°
5.625°
0%
10%
20%
29%
38%
47%
56%
63%
71%
77%
83%
88%
92%
96%
98%
100%
100%
100%
98%
96%
92%
88%
83%
77%
71%
63%
56%
47%
38%
29%
20%
10%
0%
100%
100%
98%
2
3
11.250°
16.875°
22.500°
28.125°
33.750°
39.375°
45.000°
50.625°
56.250°
61.875°
67.500°
73.125°
78.750°
84.375°
90.000°
95.625°
101.250°
106.875°
112.500°
118.125°
123.750°
129.375°
135.000°
140.625°
146.250°
151.875°
157.500°
163.125°
168.750°
174.375°
180.000°
185.625°
191.250°
196.875°
202.500°
208.125°
213.750°
219.375°
4
96%
2
3
3
5
92%
6
88%
4
7
83%
8
77%
1
2
3
4
5
5
9
71%
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
63%
6
56%
47%
4
7
38%
29%
8
20%
10%
5
9
0%
–10%
–20%
–29%
–38%
–47%
–56%
–63%
–71%
–77%
–83%
–88%
–92%
–96%
–98%
–100%
–100%
–100%
–98%
–96%
–92%
–88%
–83%
–77%
10
11
12
13
14
15
16
17
18
19
20
6
2
7
8
9
–10%
–20%
–29%
–38%
–47%
–56%
–63%
10
Copyright © 2015–2018, Texas Instruments Incorporated
15
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
BOUT
Table 3. Microstepping Relative Current Per Step (DIR = 1) (continued)
FULL STEP
1/2 STEP
1/4 STEP
1/8 STEP
1/16 STEP
ELECTRICAL
ANGLE
(DEGREES)
AOUT
CURRENT (% CURRENT (%
FULL-SCALE) FULL-SCALE)
3
6
11
21
22
23
24
25
26
27
28
29
30
31
32
1
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
225.000°
230.625°
236.250°
241.875°
247.500°
253.125°
258.750°
264.375°
270.000°
275.625°
281.250°
286.875°
292.500°
298.125°
303.750°
309.375°
315.000°
320.625°
326.250°
331.875°
337.500°
343.125°
348.750°
354.375°
360.000°
–71%
–77%
–83%
–88%
–92%
–96%
–98%
–100%
–100%
–100%
–98%
–96%
–92%
–88%
–83%
–77%
–71%
–63%
–56%
–47%
–38%
–29%
–20%
–10%
0%
–71%
–63%
–56%
–47%
–38%
–29%
–20%
–10%
0%
12
13
14
15
16
1
7
8
1
10%
20%
29%
38%
47%
56%
63%
71%
77%
83%
88%
92%
96%
98%
100%
100%
4
Non-circular 1/2–step operation is shown below. This stepping mode consumes more power than circular ½-step
operation, but provides a higher torque at high motor rpm.
Table 4. Non-Circular 1/2-Stepping Current
NON-CIRCULAR 1/2 STEP
AOUT CURRENT
(% FULL-SCALE)
BOUT CURRENT
(% FULL-SCALE)
ELECTRICAL ANGLE
(DEGREES)
1
2
3
4
5
6
7
8
0
100
100
0
0
100
100
100
0
45
90
–100
–100
–100
0
135
180
225
270
315
–100
–100
–100
100
16
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
7.3.4 Current Regulation
The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage,
inductance of the winding, and the magnitude of the back EMF present. Once the current hits the current
chopping threshold, the bridge enters a decay mode for a fixed, 20 μs, period of time to decrease the current.
After the off time expires, the bridge is re-enabled, starting another PWM cycle.
ITRIP
tBLANK
tDRIVE
tOFF
Figure 14. Current Chopping Waveform
The PWM chopping current is set by a comparator which looks at the voltage across current sense FETs in
parallel with the low-side drivers. The current sense FETs are biased with a reference current that is the output of
a current-mode sine-weighted DAC whose full-scale reference current is set by the current through the RREF
pin. An external resistor is placed from the RREF pin to GND in order to set the reference current. In addition,
the TRQ pin can further scale the reference current.
The chopping current is calculated as follows:
ARREF (kAW)
RREF (kW)
30 (kAW)
RREF (kW)
IFS (A) =
ì TRQ (%) =
ì TRQ (%)
(1)
Example: If a 30-kΩ resistor is connected to the RREF pin, the chopping current will be 1 A (TRQ at 100%)
The TRQ pin is the input to a DAC used to scale the output current. The current scalar value for different inputs
is shown below.
Table 5. Torque DAC Settings
TRQ
CURRENT SCALAR (TRQ)
0
Z
1
100%
75%
50%
Copyright © 2015–2018, Texas Instruments Incorporated
17
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
7.3.5 Controlling RREF With an MCU
In some cases, the full-scale output current may need to be changed on the fly between many different values,
depending on motor speed and loading. The RREF pin reference current can be adjusted in system by tying the
RREF resistor to a DAC output instead of GND.
In this mode of operation, as the DAC voltage increases, the reference current will decrease and therefore the
full-scale current will decrease as well. For proper operation, the output of the DAC should not rise above VRREF
.
MCU
DVDD
IREF
Analog Input
RREF
RREF
DAC
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Controlling RREF with a DAC
The chopping current as controlled by a DAC is calculated as follows:
ARREF (kAW) ì V
(V) œ VDAC (V)
[
]
ì TRQ (%)
RREF
IFS (A) =
VRREF (V) ì RREF (kW)
(2)
Example: If a 20-kΩ resistor is connected from the RREF pin to the DAC, and the DAC is outputting 0.74 V, the
chopping current will be 600 mA (TRQ at 100%)
RREF can also be adjusted using a PWM signal and low-pass filter.
MCU
AVDD
IREF
Analog Input
GPIO
R1
RREF
RREF
R2
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Controlling RREF with a PWM Resource
18
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
7.3.6 Decay Modes
The DRV8885 decay mode is selected by setting the quad-level DECAY pin to the voltage range in Table 6.
Table 6. Decay Mode Settings
DECAY
INCREASING STEPS
DECREASING STEPS
100 mV
Slow decay
Mixed decay: 30% fast
Can be tied to ground
300 mV, 15 kΩ to GND
1.0 V, 45 kΩ to GND
Mixed decay: 30% fast
Mixed decay: 60% fast
Mixed decay: 30% fast
Mixed decay: 60% fast
2.9 V
Can be tied to DVDD
Slow decay
Slow decay
Increasing and decreasing current are defined in the chart below. For the Slow/Mixed decay mode, the decay
mode is set as slow during increasing current steps and mixed decay during decreasing current steps. In full step
mode the decreasing steps decay mode is always used.
Increasing Decreasing
Increasing Decreasing
STEP Input
Decreasing
Increasing
Increasing Decreasing
STEP Input
Figure 17. Definition of Increasing and Decreasing Steps
Copyright © 2015–2018, Texas Instruments Incorporated
19
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
7.3.6.1 Mode 1: Slow Decay for Increasing and Decreasing Current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
Figure 18. Slow/Slow Decay Mode
During slow decay, both of the low side FETs of the H-bridge are turned on, allowing the current to be
recirculated.
Slow decay exhibits the least current ripple of the decay modes for a given tOFF. However on decreasing current
steps, slow decay will take a long time to settle to the new ITRIP level because the current decreases very slowly.
20
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
7.3.6.2 Mode 2: Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
ITRIP
tBLANK
tFAST
tBLANK
tDRIVE
tFAST
tDRIVE
tOFF
tOFF
Figure 19. Slow/Mixed Decay Mode
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of tOFF. In this mode,
mixed decay only occurs during decreasing current. Slow decay is used for increasing current.
This mode exhibits the same current ripple as slow decay for increasing current, since for increasing current, only
slow decay is used. For decreasing current, the ripple is larger than slow decay, but smaller than fast decay. On
decreasing current steps, mixed decay will settle to the new ITRIP level faster than slow decay.
Copyright © 2015–2018, Texas Instruments Incorporated
21
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
7.3.6.3 Mode 3: Mixed Decay for Increasing and Decreasing Current
ITRIP
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
tDRIVE
ITRIP
tBLANK
tDRIVE
tFAST
tBLANK
tDRIVE
tFAST
tOFF
tOFF
Figure 20. Mixed/Mixed Decay Mode
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of tOFF. In this mode,
mixed decay occurs for both increasing and decreasing current steps.
This mode exhibits ripple larger than slow decay, but smaller than fast decay. On decreasing current steps,
mixed decay will settle to the new ITRIP level faster than slow decay.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow
decay may not properly regulate current because no back-EMF is present across the motor windings. In this
state, motor current can rise very quickly, and requires an excessively large off-time. Increasing/decreasing
mixed decay mode allows the current level to stay in regulation when no back-EMF is present across the motor
windings.
22
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
7.3.7 Blanking Time
After the current is enabled in an H-bridge, the current sense comparator is ignored for a period of time (tBLANK
)
before enabling the current sense circuitry. Note that the blanking time also sets the minimum drive time of the
PWM. Table 7 shows the blanking time based on the sine table index and the torque DAC setting. Please note
that the torque DAC index is not the same as one step as given in Table 3.
Table 7. Adaptive Blanking
Time over Torque DAC and
Microsteps
tblank = 1.5 µs
tblank = 1.0 µs
TORQUE DAC (TRQ)
SINE INDEX
100%
100%
98%
96%
92%
88%
83%
77%
71%
63%
56%
47%
38%
29%
20%
10%
0%
75%
75%
50%
50%
16
15
14
13
12
11
10
9
73.5
49%
72%
48%
69%
46%
66%
44%
62.3%
57.8%
53.3%
47.3%
42%
41.5%
38.5%
35.5%
31.5%
28%
8
7
6
35.3
23.5%
19%
5
28.5
4
21.8%
15%
14.5%
10%
3
2
7.5%
0%
5%
1
0%
7.3.8 Charge Pump
A charge pump is integrated in order to supply a high-side NMOS gate drive voltage. The charge pump requires
a capacitor between the VM and VCP pins. Additionally a low ESR ceramic capacitor is required between pins
CPH and CPL.
VM
0.22 µF
VCP
VM
CPH
Charge
Pump
VM
0.022 µF
CPL
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Charge Pump Diagram
Copyright © 2015–2018, Texas Instruments Incorporated
23
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
7.3.9 LDO Voltage Regulator
An LDO regulator is integrated into the DRV8885. DVDD can be used to provide a reference voltage. For proper
operation, bypass DVDD to GND using a ceramic capacitor.
The DVDD output is nominally 3.3 V. When the DVDD LDO current load exceeds 1 mA, the output voltage will
drop significantly.
The AVDD pin also requires a bypass capacitor to GND. This LDO is for DRV8885 internal use only.
VM
+
œ
AVDD
DVDD
0.47 µF
0.47 µF
VM
+
œ
3.3 V
1 mA
max
Copyright © 2016, Texas Instruments Incorporated
Figure 22. LDO Diagram
If a digital input needs to be tied permanently high (that is, Mx, DECAY or TRQ), it is preferable to tie the input to
DVDD instead of an external regulator. This will save power when VM is not applied or in sleep mode: DVDD is
disabled and current will not be flowing through the input pulldown resistors. For reference, logic level inputs
have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 60 kΩ.
7.3.10 Logic and Multi-Level Pin Diagrams
Figure 23 gives the input structure for logic-level pins STEP, DIR, ENABLE, nSLEEP, M1:
DVDD
100 kΩ
Figure 23. Logic-level Input Pin Diagram
Tri-level logic pins M0 and TRQ have the following structure:
DVDD
+
DVDD
-
60 kΩ
32 kΩ
DVDD
+
-
Figure 24. Tri-level Input Pin Diagram
24
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
Quad-level logic pin DECAY has the following structure:
DVDD
+
t
DVDD
20 µA
DVDD
+
t
DVDD
+
t
Figure 25. Quad-level Input Pin Diagram
7.3.11 Protection Circuits
The DRV8885 is fully protected against undervoltage, charge pump undervoltage, overcurrent, and
overtemperature events.
7.3.11.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (VUVLO), all
FETs in the H-bridge will be disabled, the charge pump will be disabled, the logic will be reset, the DVDD
regulator is disabled, and the nFAULT pin will be driven low. Operation will resume when VM rises above the
UVLO threshold. The nFAULT pin will be released after operation has resumed. Decreasing VM below this
undervoltage threshold will reset the indexer position.
7.3.11.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the charge pump undervoltage lockout threshold voltage, all
FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Operation will resume when VCP
rises above the CPUV threshold. The nFAULT pin will be released after operation has resumed.
7.3.11.3 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than tOCP, all FETs in the H-bridge will be disabled and nFAULT will be
driven low.
The driver will be re-enabled after the OCP retry period (tRETRY) has passed. nFAULT becomes high again at
after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal
operation resumes and nFAULT remains deasserted.
7.3.11.4 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume. The nFAULT
pin will be released after operation has resumed.
Copyright © 2015–2018, Texas Instruments Incorporated
25
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
RECOVERY
Table 8. Fault Condition Summary
FAULT
CONDITION
ERROR
H-BRIDGE
CHARGE
PUMP
INDEXER
DVDD
REPORT
VM undervoltage
(UVLO)
VM < VUVLO
(max 7.8 V)
VM > VUVLO
(max 8.0 V)
nFAULT
nFAULT
nFAULT
nFAULT
Disabled
Disabled
Disabled
Disabled
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
VCP undervoltage
(CPUV)
VCP < VCPUV
(typ VM + 2.0 V)
VCP > VCPUV
(typ VM + 2.7 V)
IOUT > IOCP
(min 2.1 A)
Overcurrent (OCP)
tRETRY
Thermal Shutdown
(TSD)
TJ > TTSD
(min 150°C)
TJ < TTSD - THYS
(THYS typ 20°C)
7.4 Device Functional Modes
The DRV8885 is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled,
the H-bridge FETs are disabled Hi-Z, and the V3P3 regulator is disabled. Note that tSLEEP must elapse after a
falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8885 is brought out of sleep mode
automatically if nSLEEP is brought logic high. Note that tWAKE must elapse before the outputs change state after
wake-up.
TI recommends to keep the STEP pin logic low when coming out of nSLEEP or when applying power.
If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the internal logic will still be active.
A rising edge on STEP will advance the indexer, but the outputs will not change state until ENABLE is asserted.
Table 9. Functional Modes Summary
CONDITION
H-BRIDGE
CHARGE PUMP
INDEXER
V3P3
8 V < VM < 40 V
nSLEEP pin = 1
ENABLE pin = 1
Operating
Operating
Operating
Operating
Operating
8 V < VM < 40 V
nSLEEP pin = 1
ENABLE pin = 0
Disabled
Disabled
Disabled
Operating
Disabled
Operating
Disabled
Operating
Disabled
8 V < VM < 40
nSLEEP pin = 0
Sleep mode
VM undervoltage (UVLO)
VCP undervoltage (CPUV)
Overcurrent (OCP)
Disabled
Disabled
Disabled
Disabled
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Fault encountered
Thermal Shutdown (TSD)
26
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8885 is used in bipolar stepper control.
8.2 Typical Application
The following design procedure can be used to configure the DRV8885.
DRV8885PWP
24
23
22
21
20
19
18
17
16
15
14
13
1
DECAY
TRQ
CPL
CPH
2
0.022 µF
0.22 µF
3
M1
VCP
4
VM
M0
VM
5
0.01 µF
DIR
AOUT1
PGND
AOUT2
BOUT2
PGND
BOUT1
VM
6
Step
Motor
STEP
ENABLE
nSLEEP
RREF
nFAULT
DVDD
AVDD
7
8
+
œ
9
10
11
12
VM
+
30 kΩ
GND
100 µF
0.47 µF
0.01 µF
0.47 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Typical Application Schematic
8.2.1 Design Requirements
Table 10 gives design input parameters for system design.
Table 10. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
EXAMPLE VALUE
24 V
VM
RL
LL
Motor winding resistance
Motor winding inductance
Motor full step angle
2.6 Ω/phase
1.4 mH/phase
1.8°/step
θstep
nm
v
Target microstepping level
Target motor speed
1/8 step
120 rpm
Target full-scale current
IFS
1.0 A
Copyright © 2015–2018, Texas Instruments Incorporated
27
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Stepper Motor Speed
The first step in configuring the DRV8885 requires the desired motor speed and microstepping level. If the target
application requires a constant speed, then a square wave with frequency ƒstep must be applied to the STEP pin.
If the target motor speed is too high, the motor will not spin. Make sure that the motor can support the target
speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
v (rpm) ì 360 (è / rot)
step (è / step) ìnm (steps / microstep) ì 60 (s / min)
ƒstep (steps / s) =
q
(3)
θstep can be found in the stepper motor data sheet, or written on the motor itself.
For the DRV8885, the microstepping level is set by the Mx pins and can be any of the settings in the table below.
Higher microstepping will mean a smother motor motion and less audible noise, but will increase switching
losses and require a higher fstep to achieve the same motor speed.
Table 11. Microstepping Indexer Settings
M1
0
M0
0
STEP MODE
Full step (2-phase excitation) with 71% current
0
1
1/16 step
1
0
1/2 step
1
1
1/4 step
0
Z
1/8 step
1
Z
Non-circular 1/2 step
Example: Target 120 rpm at 1/8 microstep mode. The motor is 1.8°/step
120 rpm ì 360è / rot
ƒstep (steps / s) =
= 3.2 kHz
1.8è / step ì1/ 8 steps / microstep ì 60 s / min
(4)
8.2.2.2 Current Regulation
In a stepper motor, the full-scale current (IFS) is the maximum current driven through either winding. This quantity
will depend on the RREF resistor and the TRQ setting. During stepping, IFS defines the current chopping
threshold (ITRIP) for the maximum current step.
ARREF (kAW)
RREF (kW)
30 (kAW) ì TRQ%
RREF (kW)
IFS (A) =
=
(5)
Note that IFS must also follow Equation 6 in order to avoid saturating the motor. VM is the motor supply voltage,
and RL is the motor winding resistance.
VM (V)
IFS (A) <
RL (W) + 2 ì RDS(ON) (W)
(6)
8.2.2.3 Decay Modes
The DRV8885 supports three different decay modes: slow decay, slow/mixed and all mixed decay. The current
through the motor windings is regulated using an adjustable fixed-time-off scheme. This means that after any
drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8885 will place
the winding in one of the three decay modes for tOFF. After tOFF, a new drive phase starts.
The blanking time tBLANK defines the minimum drive time for the PWM current chopping. ITRIP is ignored during
tBLANK, so the winding current may overshoot the trip level.
28
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
8.2.3 Application Curves
Figure 27. Microstepping Using Slow Decay on Increasing
and Decreasing Steps; Current Loses Regulation on
Falling Steps
Figure 28. Microstepping Using Slow Decay on Increasing
Steps and Mixed 30% Fast Decay on Decreasing Steps
Figure 29. Microstepping Using Mixed 30% Fast Decay on
Increasing and Decreasing Steps
Figure 30. Microstepping Using Mixed 60% Fast Decay on
Increasing and Decreasing Steps
Copyright © 2015–2018, Texas Instruments Incorporated
29
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
9 Power Supply Recommendations
The DRV8885 is designed to operate from an input voltage supply (VM) range between 8 V and 35 V. A 0.01 µF
ceramic capacitor rated for VM must be placed at each VM pin as close to the DRV8885 as possible. In addition,
a bulk capacitor must be included on VM.
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
œ
GND
Local
IC Bypass
Bulk Capacitor
Capacitor
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Example Setup of Motor Drive System With External Power Supply
30
Copyright © 2015–2018, Texas Instruments Incorporated
DRV8885
www.ti.com.cn
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
10 Layout
10.1 Layout Guidelines
The VM terminal should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended
value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground plane connection to the device GND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an
electrolytic.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for
VM is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16
V is recommended. Place this component as close to the pins as possible.
Bypass AVDD and DVDD to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as
close to the pin as possible.
10.2 Layout Example
+
0.01 µF
CPL
CPH
DECAY
TRQ
VCP
M1
VM
M0
AOUT1
PGND
AOUT2
BOUT2
PGND
BOUT1
VM
DIR
STEP
ENABLE
nSLEEP
RREF
nFAULT
DVDD
AVDD
0.01 µF
GND
Figure 32. Layout Recommendation
版权 © 2015–2018, Texas Instruments Incorporated
31
DRV8885
ZHCSER7C –OCTOBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
德州仪器 (TI)，《计算电机驱动器的功耗》应用报告
德州仪器 (TI)，《电流再循环和衰减模式》应用报告
德州仪器 (TI)，《使用数模转换器 (DAC) 调整满量程电流》应用报告
德州仪器 (TI)，《DRV8885 评估模块 (EVM) 用户指南》
德州仪器 (TI)，《PowerPAD™ 速成》应用报告
德州仪器 (TI)，《PowerPAD™ 热增强型封装》应用报告
德州仪器 (TI)，《了解电机驱动器电流额定值》应用报告
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
32
版权 © 2015–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8885PWP
DRV8885PWPR
DRV8885RHRR
DRV8885RHRT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
WQFN
PWP
PWP
RHR
RHR
24
24
28
28
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DRV8885
Samples
Samples
Samples
Samples
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
DRV8885
DRV8885
DRV8885
WQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8885PWPR
DRV8885RHRR
DRV8885RHRT
HTSSOP PWP
24
28
28
2000
3000
250
330.0
330.0
180.0
16.4
12.4
12.4
6.95
3.8
8.3
5.8
5.8
1.6
1.2
1.2
8.0
8.0
8.0
16.0
12.0
12.0
Q1
Q1
Q1
WQFN
WQFN
RHR
RHR
3.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8885PWPR
DRV8885RHRR
DRV8885RHRT
HTSSOP
WQFN
PWP
RHR
RHR
24
28
28
2000
3000
250
350.0
367.0
210.0
350.0
367.0
185.0
43.0
35.0
35.0
WQFN
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DRV8885PWP
24
60
530
10.2
3600
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
PWP 24
4.4 x 7.6, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024B
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC SMALL OUTLINE
6.6
6.2
SEATING PLANE
C
TYP
PIN 1 ID
A
0.1 C
AREA
22X 0.65
24
1
2X
7.9
7.7
NOTE 3
7.15
12
13
0.30
24X
4.5
4.3
0.19
B
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X (0.2) MAX
NOTE 5
2X (0.95) MAX
NOTE 5
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
5.16
4.12
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
2.40
1.65
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0024B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.4)
24X (1.5)
SYMM
SEE DETAILS
1
24
24X (0.45)
(R0.05)
TYP
(7.8)
NOTE 9
(1.1)
TYP
SYMM
(5.16)
22X (0.65)
(
0.2) TYP
VIA
12
13
(1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-24
4222709/A 02/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.4)
BASED ON
0.125 THICK
STENCIL
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
(5.16)
SYMM
BASED ON
0.125 THICK
STENCIL
22X (0.65)
13
12
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.68 X 5.77
2.4 X 5.16 (SHOWN)
2.19 X 4.71
0.125
0.15
0.175
2.03 X 4.36
4222709/A 02/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RHR 28
3.5 x 5.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4210249/B
www.ti.com
PACKAGE OUTLINE
RHR0028A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
0.5
0.3
5.6
5.4
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
2±0.1
2X 1.5
(0.2) TYP
EXPOSED
THERMAL PAD
11
14
24X 0.5
10
15
2X
4.5
4±0.1
SEE TERMINAL
DETAIL
1
24
0.3
28X
28
25
0.5
0.2
PIN 1 ID
(OPTIONAL)
0.1
C A
B
28X
0.3
0.05
4219075/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
SYMM
28X (0.6)
28X (0.25)
25
28
1
24
24X (0.5)
(0.66)
(5.3)
TYP
SYMM
(4)
(
0.2) TYP
VIA
15
10
11
14
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219075/A 11/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.55) TYP
28
25
28X (0.6)
28X (0.25)
1
24
24X (0.5)
SYMM
(1.32)
TYP
(5.3)
METAL
TYP
6X (1.12)
15
10
14
11
6X (0.89)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219075/A 11/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明