DRV8886 [TI]

具有集成电流感应功能和 1/16 微步进的 37V、2A 双极步进电机驱动器;


型号：	DRV8886
厂家：	TEXAS INSTRUMENTS
描述：	具有集成电流感应功能和 1/16 微步进的 37V、2A 双极步进电机驱动器电机驱动驱动器
文件：	总47页 (文件大小：3073K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

DRV8886 集成电流检测功能的 2A 步进电机驱动器

1 特性

3 说明

•

脉宽调制 (PWM) 微步进电机驱动器

DRV8886 是一款适用于工业和消费类终端设备的步进

电机驱动器。该器件与两个 N 沟道功率金属氧化物半

导体场效应晶体管 (MOSFET) H 桥驱动器、一个微步

进分度器以及集成电流检测功能完全集成。DRV8886

能够驱动高达 2A 的满量程电流或 1.4A rms 输出电流

（电压为 24V 且 T_A= 25°C，取决于印刷电路板

(PCB) 设计）。

–

最高 1/16 微步进

非循环和标准 ½ 步进模式

•

集成电流检测功能

–

无需感测电阻

±6.25% 满量程电流精度

•

慢速衰减和混合衰减选项

8V 至 37V 工作电源电压范围

DRV8886 采用内部电流检测架构，无需使用两个外部

功率感测电阻，从而缩小 PCB 面积并削减系统成本。

DRV8886 使用内部固定关断时间 PWM 电流调节方

案，可在慢速和混合衰减选项之间进行调节。

低 R_DS(ON)：550mΩ HS + LS（在 24V 和 25℃ 条

件下）

•

高电流容量

–

每条桥臂的峰值电流为 3A

简易 STEP/DIR 接口允许外部控制器管理步进电机的

方向和步进速率。该器件可以配置为不同步进模式，范

围涵盖整步至 1/16 微步。凭借专用 nSLEEP 引脚，该

器件可提供一种低功耗休眠模式，从而实现超低静态待

机电流。

每条桥臂的满量程电流为 2A

每条桥臂的均方根 (rms) 电流为 1.4A

•

固定关断时间脉宽调制 (PWM) 电流调节

简单的 STEP/DIR 接口

低电流休眠模式 (20μA)

小型封装尺寸

该器件的保护功能包括：电源欠压、电荷泵故障、过

流、短路以及过热保护。故障状态通过 nFAULT 引脚

指示。

–

24 引脚散热薄型小外形尺寸 (HTSSOP)

PowerPAD™封装

–

28 WQFN 封装

器件信息 ⁽¹⁾

•

保护特性

器件型号

DRV8886

封装

HTSSOP (24)

WQFN⁽²⁾(28)

封装尺寸（标称值）

7.80mm × 4.40mm

5.50mm × 3.5mm

–

VM 欠压闭锁 (UVLO)

电荷泵欠压 (CPUV)

过流保护 (OCP)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

热关断 (TSD)

故障条件指示引脚 (nFAULT)

(2) 仅供预览。

简化原理图

2 应用

8 to 37 V

•

双极步进电机

多功能打印机和扫描仪

激光束打印机

DRV8886

STEP

DIR

3D 打印机

2 A

自动取款机和验钞机

视频安保摄像机

办公自动化设备

工厂自动化和机器人

Step Size

Stepper Motor

Driver

Decay Mode

nFAULT

Current Sense

1/16 µstep

2 A

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

English Data Sheet: SLVSDA4

DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

www.ti.com.cn

7.4 Device Functional Modes........................................ 27

Application and Implementation ........................ 28

8.1 Application Information............................................ 28

8.2 Typical Application .................................................. 28

Power Supply Recommendations...................... 31

9.1 Bulk Capacitance ................................................... 31

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Indexer Timing Requirements................................... 8

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 12

7.3 Feature Description................................................. 13

10 Layout................................................................... 32

10.1 Layout Guidelines ................................................. 32

10.2 Layout Example .................................................... 32

11 器件和文档支持 ..................................................... 33

11.1 文档支持................................................................ 33

11.2 接收文档更新通知 ................................................. 33

11.3 社区资源................................................................ 33

11.4 商标....................................................................... 33

11.5 静电放电警告......................................................... 33

11.6 术语表 ................................................................... 33

12 机械、封装和可订购信息....................................... 33

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (January 2017) to Revision A

Page

•

已添加 WQFN 封装选项 ......................................................................................................................................................... 1

已更改 the units of the High-Side and Low-Side R_DS(ON)axis labels from mΩ to Ω in the high-side and low-side

R_DS(ON)over VM and over temperature graphs ...................................................................................................................... 9

DRV8886

www.ti.com.cn

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

5 Pin Configuration and Functions

PWP PowerPAD™ Package

24-Pin HTSSOP

RHR Package

28-Pin WQFN With Exposed Thermal Pad

Top View

CPL

CPH

DECAY

TRQ

VCP

TRQ

AOUT1

PGND

AOUT2

BOUT2

PGND

BOUT1

DIR

AOUT1

PGND

AOUT2

BOUT2

PGND

BOUT1

STEP

ENABLE

nSLEEP

RREF

nFAULT

DVDD

AVDD

Thermal

Pad

DIR

Thermal

Pad

STEP

ENABLE

nSLEEP

RREF

nFAULT

GND

Not to scale

Pin Functions

NO.

HTSSOP WQFN

TYPE⁽¹⁾

DESCRIPTION

NAME

AOUT1

AOUT2

AVDD

BOUT1

BOUT2

CPH

PWR

Winding A output. Connect to stepper motor winding.

Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.

Winding B output. Connect to stepper motor winding.

PWR

Charge pump switching node. Connect a X5R or X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL.

CPL

Decay-mode setting. Sets the decay mode (see the Decay Modes section). Decay mode can be adjusted during

operation.

DECAY

DIR

Direction input. Logic level sets the direction of stepping; internal pulldown resistor.

Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.

Enable driver input. Logic high to enable device outputs; logic low to disable; internal pulldown resistor.

Device ground. Connect to system ground.

DVDD

ENABLE

GND

PWR

Microstepping mode-setting. Sets the step mode; tri-level pins; sets the step mode; internal pulldown resistor.

—

No connect. No internal connection

PGND

RREF

PWR

Power ground. Connect to system ground.

Current-limit analog input. Connect a resistor to ground to set full-scale regulation current.

(1) I = input, O = output, PWR = power, OD = open-drain

DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

www.ti.com.cn

Pin Functions (continued)

NO.

TYPE⁽¹⁾

DESCRIPTION

NAME

STEP

HTSSOP WQFN

Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor.

Current-scaling control. Scales the output current; tri-level pin.

TRQ

VCP

PWR

Charge pump output. Connect a X5R or X7R, 0.22-μF, 16-V ceramic capacitor to VM.

Power supply. Connect to motor supply voltage and bypass to GND with two 0.01-μF ceramic capacitors (one for

each pin) plus a bulk capacitor rated for VM.

PWR

nFAULT

nSLEEP

Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.

Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown

resistor.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

Power supply voltage (VM)

Power supply voltage ramp rate (VM)

V/µs

Charge pump voltage (VCP, CPH)

–0.3

VM + 7

Charge pump negative switching pin (CPL)

Internal regulator voltage (DVDD)

3.8

Internal regulator current output (DVDD)

Internal regulator voltage (AVDD)

–0.3

5.7

Control pin voltage (STEP, DIR, ENABLE, nFAULT, M0, M1, DECAY, TRQ, nSLEEP)

Open drain output current (nFAULT)

5.7

Current limit input pin voltage (RREF)

–0.3

–1.0

–3.0

6.0

Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)

Transient 100 ns phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)

Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2)

Operating junction temperature, T_J

VM + 1.0

VM + 3.0

–40

–65

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

DRV8886

www.ti.com.cn

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_VM

V_I

Power supply voltage (VM)

Input voltage (DECAY, DIR, ENABLE, M0, M1, nSLEEP, STEP,

TRQ)

5.3

ƒ_PWM

I_DVDD

I_FS

Applied STEP signal (STEP)

External load current (DVDD)

Motor full-scale current (xOUTx)

Motor RMS current (xOUTx)

Operating ambient temperature

100⁽¹⁾

1⁽²⁾

2⁽²⁾

kHz

I_rms

1.4⁽²⁾

T_A

–40

125

°C

(1) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load

(2) Power dissipation and thermal limits must be observed

6.4 Thermal Information

DRV8886

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

RHR (WQFN)

28 PINS

33.2

UNIT

24 PINS

33.8

18.0

7.7

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

23.1

12.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

0.3

ψ_JB

7.8

12.0

R_θJC(bot)

1.3

3.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

www.ti.com.cn

6.5 Electrical Characteristics

at T_A= -40 to 125°C, V_VM= 8 to 37 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES (VM, DVDD, AVDD)

VVM

VM operating voltage

ENABLE = 1, nSLEEP = 1, No motor

load

I_VM

VM operating supply current

nSLEEP = 0; T_A= 25°C

nSLEEP = 0; T_A= 125°C⁽¹⁾

nSLEEP = 0 to sleep-mode

nSLEEP = 1 to output transition

VM > UVLO to output transition

0- to 1-mA external load

No external load

I_VMQ

VM sleep mode supply current

μA

t_SLEEP

t_WAKE

t_ON

Sleep time

0.85

3.3

200

1.5

3.6

5.5

μs

Wake-up time

Turn-on time

V_DVDD

V_AVDD

Internal regulator voltage

2.9

4.5

CHARGE PUMP (VCP, CPH, CPL)

V_VCPVCP operating voltage

LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, M1)

VM + 5.5

V_IL

Input logic-low voltage

Input logic-high voltage

Input logic hysteresis

Input logic-low current

Input logic-high current

Pulldown resistance

Propagation delay

0.8

5.3

V_IH

V_HYS

I_IL

1.6

200

100

μA

kΩ

μs

VIN = 0 V

–1

I_IH

VIN = 5 V

100

R_PD

To GND

(1)

t_PD

STEP to current change

1.2

TRI-LEVEL INPUT (M0, TRQ)

V_IL

V_IZ

Tri-level input logic low voltage

0.65

1.25

Tri-level input Hi-Z voltage

0.95

1.1

Tri-level input logic high

voltage

V_IH

I_IL

1.5

5.3

Tri-level input logic low current VIN = 0 V

–90

μA

Tri-level input logic high

VIN = 5 V

I_IH

155

current

R_PD

R_PU

Tri-level pulldown resistance

Tri-level pullup resistance

VIN = Hi-Z, to GND

kΩ

VIN = Hi-Z, to DVDD

130

QUAD-LEVEL INPUT (DECAY)

V_I1

V_I2

V_I3

V_I4

I_O

Quad-level input voltage 1

Can set with 1% 5 kΩ to GND

Can set with 1% 15 kΩ to GND

Can set with 1% 44.2 kΩ to GND

Can set with 1% 133 kΩ to GND

To GND

0.24

0.71

2.12

0.14

0.46

1.24

5.3

Quad-level input voltage 2

Quad-level input voltage 3

Quad-level input voltage 4

Output current

27.25

μA

CONTROL OUTPUTS (nFAULT)

V_OL

I_OH

Output logic-low voltage

Output logic-high leakage

I_O= 1 mA, R_PULLUP= 4.7 kΩ

V_O= 5 V, R_PULLUP= 4.7 kΩ

0.5

–1

μA

(1) Specified by design and characterization data

DRV8886

www.ti.com.cn

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

Electrical Characteristics (continued)

at T_A= -40 to 125°C, V_VM= 8 to 37 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)

R_DS(ON)

High-side FET on resistance

Low-side FET on resistance

Output rise time

VM = 24 V, I = 1.4 A, T_A= 25°C

290

260

100

200

0.7

346

320

mΩ

R_DS(ON)

(1)

t_RISE

(1)

t_FALL

Output fall time

(1)

t_DEAD

Output dead time

(1)

V_d

Body diode forward voltage

I_OUT= 0.5 A

PWM CURRENT CONTROL (RREF)

A_RREF

V_RREF

t_OFF

RREF transimpedance gain

RREF voltage

28.1

1.18

1.232

31.9

1.28

kAΩ

RREF = 18 to 132 kΩ

PWM off-time

μs

Equivalent capacitance on

RREF

C_RREF

µs

I_RREF= 2.0 A, 63% to 100% current

setting

1.5

t_BLANK

PWM blanking time

Current trip accuracy

I_RREF= 2.0 A, 0% to 63% current

setting

I_RREF= 1.5 A, 10% to 20% current

setting, 1% reference resistor

–15%

–10%

15%

10%

I_RREF= 1.5 A, 20% to 63% current

setting, 1% reference resistor

ΔI_TRIP

I_RREF= 1.5 A, 71% to 100% current

setting, 1% reference resistor

–6.25%

6.25%

PROTECTION CIRCUITS

VM falling, UVLO report

VM rising, UVLO recovery

Rising to falling threshold

VCP falling; CPUV report

7.8

V_UVLO

VM UVLO

7.2

V_UVLO,HYS

V_CPUV

Undervoltage hysteresis

200

Charge pump undervoltage

VM + 2

Overcurrent protection trip

level

I_OCP

Current through any FET

(1)

t_OCP

Overcurrent deglitch time

Overcurrent retry time

1.3

1.9

2.8

1.6

μs

t_RETRY

Thermal shutdown

temperature

(1)

T_TSD

Die temperature T_J

150

°C

(1)

T_HYS

Thermal shutdown hysteresis

DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

www.ti.com.cn

6.6 Indexer Timing Requirements

at T_A= -40 to 125°C, V_VM= 8 to 37 V (unless otherwise noted)

NO.

MIN

MAX

UNIT

kHz

(1)

ƒ_STEP

Step frequency

500

t_WH(STEP)

t_WL(STEP)

t_{SU(DIR, Mx)}

t_{H(DIR, Mx)}

Pulse duration, STEP high

970

200

Pulse duration, STEP low

Setup time, DIR or USMx to STEP rising

Hold time, DIR or USMx to STEP rising

(1) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load.

STEP

DIR, Mx

图 1. Timing Diagram

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ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

6.7 Typical Characteristics

Over recommended operating conditions (unless otherwise noted)

6.8

6.6

6.4

6.2

T_A= -40°C

6.8

T_A= 25°C

T_A= 125°C

6.6

6.4

6.2

5.8

5.6

5.4

5.2

VM = 8 V

VM = 24 V

VM = 37 V

5.8

5.6

-40

-20

100 120 140

Supply Voltage (V)

Ambient Temperature (°C)

D001

D002

图 2. Supply Current over VM

图 3. Supply Current over Temperature

VM = 8 V

VM = 24 V

VM = 37 V

T_A= -40°C

T_A= 25°C

T_A= 125°C

-40

-20

100 120 140

Supply Voltage (V)

Ambient Temperature (°C)

D003

D0042

图 4. Sleep Current over VM

图 5. Sleep Current over Temperature

0.5

0.45

0.4

0.38

0.36

0.34

0.32

0.3

0.35

0.3

0.25

0.2

0.28

0.26

0.24

0.22

0.15

0.1

T_A= -40°C

T_A= 25°C

T_A= 125°C

VM = 8 V

VM = 24 V

VM = 37 V

0.05

-40

-20

100 120 140

Supply Voltage (V)

Ambient Temperature (°C)

D005

D006

图 6. High-Side R_DS(ON)over VM

图 7. High-Side R_DS(ON)over Temperature

DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

www.ti.com.cn

Typical Characteristics (接下页)

Over recommended operating conditions (unless otherwise noted)

0.5

0.42

0.4

0.45

0.4

0.38

0.36

0.34

0.32

0.3

0.35

0.3

0.25

0.2

0.28

0.26

0.24

0.22

0.2

0.15

0.1

T_A= -40°C

VM = 8 V

VM = 24 V

VM = 37 V

T_A= 25°C

0.05

T_A= 125°C

-40

-20

100 120 140

Supply Voltage (V)

Ambient Temperature (°C)

D007

D008

图 8. Low-Side R_DS(ON)over VM

图 9. Low-Side R_DS(ON)over Temperature

3.339

TRQ = 0

3.336

3.333

3.33

TRQ = Z

TRQ = 1

0.7

0.5

3.327

3.324

3.321

3.318

3.315

3.312

3.309

3.306

3.303

0.3

0.2

0.1

0.07

0.05

T _A= 125°C

T _A= 85°C

T _A= 25°C

T _A= -40°C

0.03

0.02

0.01

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

40 50 60 70

100

200

300

DVDD Load (mA)

R _REF(kW)

D009

D010

图 10. DVDD Regulator over Load (VM = 24 V)

图 11. Full-Scale Current over RREF Selection

DRV8886

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ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

7 Detailed Description

7.1 Overview

The DRV8886 device is an integrated motor-driver solution for bipolar stepper motors. The device integrates two

N-channel power MOSFET H-bridges, integrated current sense and regulation circuitry, and a microstepping

indexer. The DRV8886 device can be powered with a supply voltage from 8 to 37 V and is capable of providing

an output current up to 3-A peak, 2-A full-scale, or 1.4-A root mean square (rms). The actual full-scale and rms

current depends on the ambient temperature, supply voltage, and PCB thermal capability.

The DRV8886 device uses an integrated current-sense architecture which eliminates the need for two external

power sense resistors. This architecture removes the power dissipated in the sense resistors by using a current

mirror approach and using the internal power MOSFETs for current sensing. The current regulation set point is

adjusted with a standard low-power resistor connected to the RREF pin. This features reduces external

component cost, board PCB size, and system power consumption.

A simple STEP/DIR interface allows for an external controller to manage the direction and step rate of the

stepper motor. The internal indexer can execute high-accuracy microstepping without requiring the external

controller to manage the winding current level. The indexer is capable of full step, half step, and 1/4, 1/8, 1/16

microstepping. In addition to a standard half stepping mode, a non-circular half stepping mode is available for

increased torque output at higher motor RPM.

The current regulation is configurable between several decay modes. The decay mode can be selected as a

fixed slow, slow-mixed, or mixed decay current regulation scheme. The slow-mixed decay mode uses slow decay

on increasing steps and mixed decay on decreasing steps.

An adaptive blanking time feature automatically scales the minimum drive time with output current level. This

feature helps alleviate zero-crossing distortion by limiting the drive time at low-current steps.

A torque DAC feature allows the controller to scale the output current without needing to scale the RREF

reference resistor. The torque DAC is accessed using a digital input pin which allows the controller to save

system power by decreasing the motor current consumption when high output torque is not required.

A low-power sleep mode is included which allows the system to save power when not actively driving the motor.

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7.2 Functional Block Diagram

0.01 ꢀF

Bulk

0.22 ꢀF

Power

VCP

AOUT1

CPH

Charge

Pump

0.022 ꢀF

CPL

Current

Sense

Stepper

Motor

AVDD

Regulator

Gate

Drivers

0.47 ꢀF

DVDD

Regulator

AOUT2

PGND

0.47 ꢀF

GND

Current

Sense

Digital

Core

I_REF

STEP

SINE DAC

DIR

ENABLE

nSLEEP

BOUT1

Current

Sense

Control

Inputs

Gate

Drivers

Microstepping

Indexer

DVDD

BOUT2

Adaptive

Blanking

TRQ

Current

Sense

I_REF

PGND

VCC

DECAY

SINE DAC

DVDD

I_REF

Protection

R_PU

nFAULT

Fault Output

Overcurrent

RREF

Analog

Input

RREF

R_REF

Undervoltage

Overtemperature

PPAD

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7.3 Feature Description

表 1 lists the recommended external components for the DRV8886 device.

表 1. DRV8886 External Components

COMPONENT

C_VM1

PIN 1

PIN 2

GND

RECOMMENDED

Two X5R or X7R, 0.01-µF, VM-rated ceramic capacitors

Bulk, VM-rated capacitor

C_VM2

C_VCP

VCP

CPH

AVDD

DVDD

X5R or X7R, 0.22-µF, 16-V ceramic capacitor

X5R or X7R, 0.022-µF, VM-rated ceramic capacitor

X5R or X7R, 0.47-µF, 6.3-V ceramic capacitor

>4.7-kΩ resistor

C_SW

CPL

C_AVDD

C_DVDD

R_nFAULT

GND

nFAULT

(1)

VCC

Resistor to limit chopping current must be installed. See the Typical Application

section for value selection.

R_REF

RREF

GND

(1) VCC is not a pin on the DRV8886 device, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be

pulled up to DVDD

7.3.1 Stepper Motor Driver Current Ratings

Stepper motor drivers can be classified using three different numbers to describe the output current: peak, rms,

and full-scale.

7.3.1.1 Peak Current Rating

The peak current in a stepper driver is limited by the overcurrent protection trip threshold, I_OCP. The peak current

describes any transient duration current pulse, for example when charging capacitance, when the overall duty

cycle is very low. In general the minimum value of I_OCPspecifies the peak current rating of the stepper motor

driver. For the DRV8886 device, the peak current rating is 3 A per bridge.

7.3.1.2 rms Current Rating

The rms (average) current is determined by the thermal considerations of the device. The rms current is

calculated based on the R_DS(ON), rise and fall time, PWM frequency, device quiescent current, and package

thermal performance in a typical system at 25°C. The actual operating rms current may be higher or lower

depending on heatsinking and ambient temperature. For the DRV8886 device, the rms current rating is 1.4 A per

bridge.

7.3.1.3 Full-Scale Current Rating

The full-scale current describes the top of the sinusoid current waveform while microstepping. Because the

sinusoid amplitude is related to the rms current, the full-scale current is also determined by the thermal

considerations of the device. The full-scale current rating is approximately √2 × I_RMS. The full-scale current is set

by the RREF pin and the torque DAC when configuring the DRV8886 device, for details see the Current

Regulation section. For the DRV8886 device, the full-scale current rating is 2 A per bridge.

Full-scale current

RMS current

AOUT

BOUT

Step Input

图 12. Full-Scale and rms Current

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7.3.2 PWM Motor Drivers

The DRV8886 device has drivers for two full H-bridges to drive the two windings of a bipolar stepper motor. 图

13 shows a block diagram of the circuitry.

xOUT1

Current

Sense

Microstepping and

Current Regulation

Logic

Gate

Drivers

xOUT2

PGND

Current

Sense

图 13. PWM Motor Driver Block Diagram

7.3.3 Microstepping Indexer

Built-in indexer logic in the DRV8886 device allows a number of different step modes. The M1 and M0 pins are

used to configure the step mode as shown in 表 2.

表 2. Microstepping Settings

STEP MODE

Full step (2-phase excitation) with 71% current

1/16 step

1/2 step

1/4 step

1/8 step

Non-circular 1/2 step

表 3 shows the relative current and step directions for full-step through 1/16-step operation. The AOUT current is

the sine of the electrical angle and the BOUT current is the cosine of the electrical angle. Positive current is

defined as current flowing from the xOUT1 pin to the xOUT2 pin while driving.

At each rising edge of the STEP input the indexer travels to the next state in the table. The direction is shown

with the DIR pin logic high. If the DIR pin is logic low, the sequence is reversed.

On power-up or when exiting sleep mode, keep the STEP pin logic low, otherwise the indexer advances one

step.

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注

If the step mode is changed from full, 1/2, 1/4, 1/8, or 1/16 to full, 1/2, 1/4, 1/8, or 1/16

while stepping, the indexer advances to the next valid state for the new step mode setting

at the rising edge of STEP. If the step mode is changed from or to noncircular 1/2 step the

indexer goes immediately to the valid state for that mode.

The home state is an electrical angle of 45°. This state is entered after power-up, after exiting logic undervoltage

lockout, or after exiting sleep mode. 表 3 lists the home state in red.

表 3. Microstepping Relative Current Per Step (DIR = 1)

FULL STEP

1/2 STEP

1/4 STEP

1/8 STEP

1/16 STEP

ELECTRICAL

ANGLE

(DEGREES)

AOUT

BOUT

CURRENT (% CURRENT (%

FULL-SCALE) FULL-SCALE)

0.000°

5.625°

10%

20%

29%

38%

47%

56%

63%

71%

77%

83%

88%

92%

96%

98%

100%

98%

96%

92%

88%

83%

77%

71%

63%

56%

47%

38%

29%

20%

10%

100%

98%

11.250°

16.875°

22.500°

28.125°

33.750°

39.375°

45.000°

50.625°

56.250°

61.875°

67.500°

73.125°

78.750°

84.375°

90.000°

95.625°

101.250°

106.875°

112.500°

118.125°

123.750°

129.375°

135.000°

140.625°

146.250°

151.875°

157.500°

163.125°

168.750°

174.375°

180.000°

185.625°

191.250°

196.875°

202.500°

208.125°

96%

92%

88%

83%

77%

71%

63%

56%

47%

38%

29%

20%

10%

–10%

–20%

–29%

–38%

–47%

–56%

–63%

–71%

–77%

–83%

–88%

–92%

–96%

–98%

–100%

–98%

–96%

–92%

–88%

–10%

–20%

–29%

–38%

–47%

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BOUT

表 3. Microstepping Relative Current Per Step (DIR = 1) (接下页)

FULL STEP

1/2 STEP

1/4 STEP

1/8 STEP

1/16 STEP

ELECTRICAL

ANGLE

(DEGREES)

AOUT

CURRENT (% CURRENT (%

FULL-SCALE) FULL-SCALE)

213.750°

219.375°

225.000°

230.625°

236.250°

241.875°

247.500°

253.125°

258.750°

264.375°

270.000°

275.625°

281.250°

286.875°

292.500°

298.125°

303.750°

309.375°

315.000°

320.625°

326.250°

331.875°

337.500°

343.125°

348.750°

354.375°

360.000°

–56%

–63%

–71%

–77%

–83%

–88%

–92%

–96%

–98%

–100%

–98%

–96%

–92%

–88%

–83%

–77%

–71%

–63%

–56%

–47%

–38%

–29%

–20%

–10%

–83%

–77%

–71%

–63%

–56%

–47%

–38%

–29%

–20%

–10%

10%

20%

29%

38%

47%

56%

63%

71%

77%

83%

88%

92%

96%

98%

100%

表 4 shows the noncircular 1/2–step operation. This stepping mode consumes more power than circular 1/2-step

operation, but provides a higher torque at high motor rpm.

表 4. Non-Circular 1/2-Stepping Current

NON-CIRCULAR 1/2-STEP

AOUT CURRENT

(% FULL-SCALE)

BOUT CURRENT

(% FULL-SCALE)

ELECTRICAL ANGLE

(DEGREES)

100

–100

135

180

225

270

315

–100

100

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7.3.4 Current Regulation

The current through the motor windings is regulated by an adjustable, fixed-off-time PWM current-regulation

circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply

voltage, inductance of the winding, and the magnitude of the back EMF present. When the current hits the

current regulation threshold, the bridge enters a decay mode for a fixed 20 μs, period of time to decrease the

current. After the off time expires, the bridge is re-enabled, starting another PWM cycle.

I_TRIP

t_BLANK

t_DRIVE

t_OFF

图 14. Current Chopping Waveform

The PWM regulation current is set by a comparator which monitors the voltage across the current sense

MOSFETs in parallel with the low-side power MOSFETs. The current sense MOSFETs are biased with a

reference current that is the output of a current-mode sine-weighted DAC whose full-scale reference current is

set by the current through the RREF pin. An external resistor is placed from the RREF pin to GND to set the

reference current. In addition, the TRQ pin can further scale the reference current.

Use 公式 1 to calculate the full-scale regulation current.

A_RREF(kAW)

RREF (kW)

30 (kAW)

RREF (kW)

I_FS(A) =

ì TRQ (%) =

ì TRQ (%)

(1)

For example, if a 30-kΩ resistor is connected to the RREF pin, the full-scale regulation current is 1 A (TRQ at

100%).

The TRQ pin is the input to a DAC used to scale the output current. 表 5 lists the current scalar value for different

inputs.

表 5. Torque DAC Settings

TRQ

CURRENT SCALAR (TRQ)

100%

75%

50%

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7.3.5 Controlling RREF With an MCU DAC

In some cases, the full-scale output current may need to be changed between many different values, depending

on motor speed and loading. The reference current of the RREF pin can be adjusted in the system by tying the

RREF resistor to a DAC output instead of GND.

In this mode of operation, as the DAC voltage increases, the reference current decreases and therefore the full-

scale regulation current decreases as well. For proper operation, the output of the DAC should not rise above

V_RREF

DVDD

I_REF

Controller

DAC

RREF

Analog

Input

RREF

R_REF

图 15. Controlling RREF With a DAC Resource

Use 公式 2 to calculate the full-scale regulation current as controlled by a controller DAC.

A_RREF(kAW) ì V (V) œ V_DAC(V)

[

]

ì TRQ (%)

RREF

I_FS(A) =

V_RREF(V) ì RREF (kW)

(2)

For example, if a 20-kΩ resistor is connected from the RREF pin to the DAC, and the DAC outputs 0.74 V, the

chopping current is 600 mA (TRQ at 100%)

The RREF pin can also be adjusted using a PWM signal and low-pass filter.

DVDD

I_REF

Controller

RREF

Analog

PWM

Input

R_REF

图 16. Controlling RREF With a PWM Resource

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7.3.6 Decay Modes

The DRV8886 decay mode is selected by setting the quad-level DECAY pin to the voltage range listed in 表 6.

The decay mode setting can be modified during device operation.

表 6. Decay Mode Settings

DECAY

INCREASING STEPS

DECREASING STEPS

100 mV

Slow decay

Mixed decay: 30% fast

Can be tied to ground

300 mV, 15 kΩ to GND

1 V, 45 kΩ to GND

Mixed decay: 30% fast

Mixed decay: 60% fast

Mixed decay: 30% fast

Mixed decay: 60% fast

2.9 V

Can be tied to DVDD

Slow decay

图 17 defines increasing and decreasing current. For the slow-mixed decay mode, the decay mode is set as slow

during increasing current steps and mixed decay during decreasing current steps. In full step mode the

decreasing steps decay mode is always used. In noncircular 1/2-step mode the increasing step decay mode is

used after a level transition (0% to 100% and 0% to –100%). When the level transition is to a similar level (100%

to 100% and –100% to –100%), the decreasing step decay mode is used.

Increasing Decreasing

STEP Input

AOUT Current

Decreasing

Increasing

Increasing Decreasing

STEP Input

图 17. Definition of Increasing and Decreasing Steps

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7.3.6.1 Mode 1: Slow Decay for Increasing Current, Mixed Decay for Decreasing Current

I_TRIP

t_BLANK

t_DRIVE

t_OFF

t_BLANK

t_OFF

t_BLANK

t_DRIVE

I_TRIP

t_BLANK

t_FAST

t_BLANK

t_DRIVE

t_FAST

t_DRIVE

t_OFF

图 18. Slow-Mixed Decay Mode

Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of the t_OFFtime. In this

mode, mixed decay only occurs during decreasing current. Slow decay is used for increasing current.

This mode exhibits the same current ripple as slow decay for increasing current because for increasing current,

only slow decay is used. For decreasing current, the ripple is larger than slow decay, but smaller than fast decay.

On decreasing current steps, mixed decay will settle to the new I_TRIPlevel faster than slow decay.

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7.3.6.2 Mode 2: Mixed Decay for Increasing and Decreasing Current

I_TRIP

t_OFF

t_BLANK

t_OFF

t_BLANK

t_DRIVE

I_TRIP

t_BLANK

t_DRIVE

t_FAST

t_BLANK

t_DRIVE

t_FAST

t_OFF

图 19. Mixed-Mixed Decay Mode

Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of t_OFF. In this mode,

mixed decay occurs for both increasing and decreasing current steps.

This mode exhibits ripple larger than slow decay, but smaller than fast decay. On decreasing current steps,

mixed decay settles to the new I_TRIPlevel faster than slow decay.

In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow

decay may not properly regulate current because no back-EMF is present across the motor windings. In this

state, motor current can rise very quickly, and requires an excessively large off-time. Increasing or decreasing

mixed decay mode allows the current level to stay in regulation when no back-EMF is present across the motor

windings.

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7.3.6.3 Mode 3: Slow Decay for Increasing and Decreasing Current

I_TRIP

t_BLANK

t_DRIVE

t_OFF

t_BLANK

t_OFF

t_DRIVE

I_TRIP

t_BLANK

t_DRIVE

t_OFF

t_BLANK

t_DRIVE

t_OFF

t_BLANK

t_DRIVE

图 20. Slow-Slow Decay Mode

During slow decay, both of the low-side MOSFETs of the H-bridge are turned on, allowing the current to be

recirculated.

Slow decay exhibits the least current ripple of the decay modes for a given t_OFF. However, on decreasing current

steps, slow decay takes a long time to settle to the new I_TRIPlevel because the current decreases very slowly.

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7.3.7 Blanking Time

After the current is enabled in an H-bridge, the current sense comparator is ignored for a period of time (t_BLANK

)

before enabling the current-sense circuitry. The blanking time also sets the minimum drive time of the PWM. 表 7

shows the blanking time based on the sine table index and the torque DAC setting. The torque DAC index is not

the same as one step as given in 表 3.

表 7. Adaptive Blanking Time

over Torque DAC and

Microsteps

t_blank= 1.5 µs

t_blank= 1 µs

TORQUE DAC (TRQ)

SINE INDEX

100%

98%

96%

92%

88%

83%

77%

71%

63%

56%

47%

38%

29%

20%

10%

75%

50%

73.5

49%

72%

48%

69%

46%

66%

44%

62.3%

57.8%

53.3%

47.3%

42%

41.5%

38.5%

35.5%

31.5%

28%

35.3

23.5%

19%

28.5

21.8%

15%

14.5%

10%

7.5%

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7.3.8 Charge Pump

A charge pump is integrated to supply a high-side N-channel MOSFET gate-drive voltage. The charge pump

requires a capacitor between the VM and VCP pins to act as the storage capacitor. Additionally a ceramic

capacitor is required between the CPH and CPL pins to act as the flying capacitor.

0.22 …F

VCP

CPH

0.022 …F

Charge

Pump

Control

CPL

图 21. Charge Pump Block Diagram

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7.3.9 Linear Voltage Regulators

An linear voltage regulator is integrated into the DRV8886 device. The DVDD regulator can be used to provide a

reference voltage. For proper operation, bypass the DVDD pin to GND using a ceramic capacitor.

The DVDD output is nominally 3.3 V. When the DVDD LDO current load exceeds 1 mA, the output voltage drops

significantly.

The AVDD pin also requires a bypass capacitor to GND. This LDO is for DRV8886 internal use only.

DVDD

3.3-V, 1-mA

0.47 …F

AVDD

0.47 …F

图 22. Linear Voltage Regulator Block Diagram

If a digital input must be tied permanently high (that is, Mx, DECAY or TRQ), tying the input to the DVDD pin

instead of an external regulator is preferred. This method saves power when the VM pin is not applied or in sleep

mode: the DVDD regulator is disabled and current does not flow through the input pulldown resistors. For

reference, logic level inputs have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 60

kΩ.

7.3.10 Logic and Multi-Level Pin Diagrams

图 23 shows the input structure for the logic-level pins STEP, DIR, ENABLE, nSLEEP, and M1.

DVDD

100 kΩ

图 23. Logic-Level Input Pin Diagram

The tri-level logic pins, M0 and TRQ, have the structure shown in 图 24.

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DVDD

60 kΩ

32 kΩ

DVDD

图 24. Tri-Level Input Pin Diagram

The quad-level logic pin, DECAY, has the structure shown in 图 25.

DVDD

20 µA

DVDD

图 25. Quad-Level Input Pin Diagram

7.3.11 Protection Circuits

The DRV8886 device is fully protected against supply undervoltage, charge pump undervoltage, output

overcurrent, and device overtemperature events.

7.3.11.1 VM Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the VM undervoltage-lockout threshold voltage (V_UVLO), all

MOSFETs in the H-bridge are disabled, the charge pump is disabled, the logic is reset, and the nFAULT pin is

driven low. Operation resumes when the VM voltage rises above the V_UVLOthreshold. The nFAULT pin is

released after operation resumes. Decreasing the VM voltage below this undervoltage threshold resets the

indexer position.

7.3.11.2 VCP Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin falls below the charge-pump undervoltage-lockout threshold voltage

(V_CPUV), all MOSFETs in the H-bridge are disabled and the nFAULT pin is driven low. Operation resumes when

the VCP voltage rises above the V_CPUVthreshold. The nFAULT pin is released after operation resumes.

7.3.11.3 Overcurrent Protection (OCP)

An analog current-limit circuit on each MOSFET limits the current through the MOSFET by removing the gate

drive. If this analog current limit persists for longer than t_OCP, all MOSFETs in the H-bridge are disabled and the

nFAULT pinis driven low.

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The driver is re-enabled after the OCP retry period (t_RETRY) has passed. The nFAULT pin becomes high again at

after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal

operation resumes and nFAULT remains deasserted.

7.3.11.4 Thermal Shutdown (TSD)

If the die temperature exceeds T_TSDlevel, all MOSFETs in the H-bridge are disabled and the nFAULT pin is

driven low. When the die temperature falls below the T_TSDlevel, operation automatically resumes. The nFAULT

pin is released after operation resumes.

表 8. Fault Condition Summary

FAULT

CONDITION

ERROR H-BRIDGE CHARGE INDEXER

DVDD

AVDD

RECOVERY

REPORT

PUMP

VM undervoltage

(UVLO)

VM < V_UVLO

(max 7.8 V)

VM > V_UVLO

(max 8 V)

nFAULT

Disabled

Operating

Disabled

VCP undervoltage

(CPUV)

VCP < V_CPUV

(typ VM + 2 V)

VCP > V_CPUV

(typ VM + 2.7 V)

nFAULT

Operating Operating Operating Operating

I_OUT> I_OCP

(min 3 A)

Overcurrent (OCP)

t_RETRY

T_J< T_TSD

T_HYS

(T_HYStyp 20°C)

–

Thermal shutdown

(TSD)

T_J> T_TSD

(min 150°C)

nFAULT

Disabled

Operating Operating Operating Operating

7.4 Device Functional Modes

The DRV8886 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is

disabled, the H-bridge MOSFETs are disabled Hi-Z, and the regulators are disabled.

注

The t_SLEEPtime must elapse after a falling edge on the nSLEEP pin before the device is in

sleep mode. The DRV8886 device is brought out of sleep mode automatically if nSLEEP

is brought logic high.

The t_WAKEtime must elapse before the outputs change state after wake-up.

TI recommends to keep the STEP pin logic low when coming out of nSLEEP or when applying power.

If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the internal logic is still active. A

rising edge on STEP advances the indexer, but the outputs do not change state until the ENABLE pin is

asserted.

表 9 lists a summary of the functional modes.

表 9. Functional Modes Summary

CONDITION

H-BRIDGE

CHARGE PUMP

INDEXER

DVDD

AVDD

8 V < VM < 40 V

nSLEEP pin = 1

ENABLE pin = 1

Operating

8 V < VM < 40 V

nSLEEP pin = 1

ENABLE pin = 0

Disabled

Operating

Disabled

Operating

Disabled

Operating

Disabled

Operating

Disabled

8 V < VM < 40

nSLEEP pin = 0

Sleep mode

VM undervoltage (UVLO)

VCP undervoltage (CPUV)

Disabled

Operating

Disabled

Operating

Disabled

Operating

Fault encountered

Overcurrent (OCP)

Thermal Shutdown (TSD)

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8886 device is used in bipolar stepper control.

8.2 Typical Application

The following design procedure can be used to configure the DRV8886 device.

DRV8886PWP

DECAY

TRQ

CPL

CPH

0.022 ꢀF

0.22 ꢀF

VCP

0.01 ꢀF

DIR

AOUT1

PGND

AOUT2

BOUT2

PGND

BOUT1

Step

Motor

STEP

ENABLE

nSLEEP

RREF

nFAULT

30 kꢁ

DVDD

AVDD

GND

0.47 ꢀF

0.01 ꢀF

100 ꢀF

0.47 ꢀF

图 26. Typical Application Schematic

8.2.1 Design Requirements

表 10 lists the design input parameters for system design.

表 10. Design Parameters

DESIGN PARAMETER

Supply voltage

REFERENCE

EXAMPLE VALUE

24 V

R_L

L_L

Motor winding resistance

Motor winding inductance

Motor full step angle

2.6 Ω/phase

1.4 mH/phase

1.8°/step

θ_step

n_m

Target microstepping level

Target motor speed

1/8 step

120 rpm

Target full-scale current

I_FS

2 A

DRV8886

www.ti.com.cn

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

8.2.2 Detailed Design Procedure

8.2.2.1 Stepper Motor Speed

The first step in configuring the DRV8886 device requires the desired motor speed and microstepping level. If the

target application requires a constant speed, then a square wave with frequency ƒ_stepmust be applied to the

STEP pin.

If the target motor speed is too high, the motor does not spin. Make sure that the motor can support the target

speed.

Use 公式 3 to calculate ƒ_stepfor a desired motor speed (v), microstepping level (n_m), and motor full step angle

(θ_step).

v (rpm) ì 360 (è / rot)

_step(è / step) ìn_m(steps / microstep) ì 60 (s / min)

ƒ_step(steps / s) =

(3)

The value of θ_stepcan be found in the stepper motor data sheet, or written on the motor.

For the DRV8886 device, the microstepping level is set by the Mx pins and can be any of the settings listed in 表

11. Higher microstepping results in smoother motor motion and less audible noise, but increases switching

losses and requires a higher ƒ_stepto achieve the same motor speed.

表 11. Microstepping Indexer Settings

STEP MODE

Full step (2-phase excitation) with 71% current

1/16 step

1/2 step

1/4 step

1/8 step

Non-circular 1/2 step

For example, the motor is 1.8°/step for a target of 120 rpm at 1/8 microstep mode.

120 rpm ì 360è / rot

1.8è / step ì1/ 8 steps / microstep ì 60 s / min

ƒ_step(steps / s) =

= 3.2 kHz

(4)

8.2.2.2 Current Regulation

In a stepper motor, the full-scale current (I_FS) is the maximum current driven through either winding. This quantity

depends on the RREF resistor and the TRQ setting. During stepping, I_FSdefines the current chopping threshold

(I_TRIP) for the maximum current step.

A_RREF(kAW)

RREF (kW)

30 (kAW) ì TRQ%

RREF (kW)

I_FS(A) =

(5)

注

The I_FScurrent must also follow 公式 6 to avoid saturating the motor. VM is the motor

supply voltage, and R_Lis the motor winding resistance.

VM (V)

I_FS(A) <

R_L(W) + 2 ì R_DS(ON)(W)

(6)

8.2.2.3 Decay Modes

The DRV8886 device supports three different decay modes: slow decay, slow-mixed decay, and all mixed decay.

The current through the motor windings is regulated using an adjustable fixed-time-off scheme which means that

after any drive phase, when a motor winding current has hit the current chopping threshold (I_TRIP), the DRV8886

places the winding in one of the three decay modes for t_OFF. After t_OFF, a new drive phase starts.

The blanking time, t_BLANK, defines the minimum drive time for the PWM current chopping. I_TRIPis ignored during

t_BLANK, so the winding current may overshoot the trip level.

DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

www.ti.com.cn

8.2.3 Application Curves

图 27. 1/8 Microstepping With Slow-Slow Decay;

图 28. 1/8 Microstepping With Slow-Mixed Decay

Loss of Current Regulation on Falling Steps

图 29. 1/8 Microstepping With Mixed30-Mixed30 Decay

图 30. 1/8 Microstepping With Mixed60-Mixed60 Decay

DRV8886

www.ti.com.cn

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

9 Power Supply Recommendations

The DRV8886 device is designed to operate from an input voltage supply (VM) range from 8 V to 37 V. A 0.01-

µF ceramic capacitor rated for VM must be placed at each VM pin as close to the DRV8886 device as possible.

In addition, a bulk capacitor must be included on VM.

9.1 Bulk Capacitance

Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors, including:

•

The highest current required by the motor system

The power supply’s capacitance and ability to source current

The amount of parasitic inductance between the power supply and motor system

The acceptable voltage ripple

The type of motor used (brushed DC, brushless DC, stepper)

The motor braking method

The inductance between the power supply and motor drive system will limit the rate current can change from the

power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or

dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

remains stable and high current can be quickly supplied.

The data sheet generally provides a recommended value, but system-level testing is required to determine the

appropriate sized bulk capacitor.

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases

when the motor transfers energy to the supply.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

Motor

Driver

GND

Local

IC Bypass

Bulk Capacitor

Capacitor

图 31. Example Setup of Motor Drive System With External Power Supply

DRV8886

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

The VM pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value

of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or

ground plane connection to the device GND pin.

The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an

electrolytic capacitor.

A low-ESR ceramic capacitor must be placed between the CPL and CPH pins. A value of 0.022 µF rated for VM

is recommended. Place this component as close to the pins as possible.

A low-ESR ceramic capacitor must be placed between the VM and VCP pins. A value of 0.22 µF rated for 16 V

is recommended. Place this component as close to the pins as possible.

Bypass the AVDD and DVDD pins to ground with a low-ESR ceramic capacitor rated 6.3 V. Place this bypass

capacitor as close to the pin as possible.

10.2 Layout Example

0.01 µF

CPL

CPH

DECAY

TRQ

VCP

AOUT1

PGND

AOUT2

BOUT2

PGND

BOUT1

DIR

STEP

ENABLE

nSLEEP

RREF

nFAULT

DVDD

AVDD

0.01 µF

GND

图 32. Layout Recommendation

DRV8886

www.ti.com.cn

ZHCSFZ1A –JANUARY 2017–REVISED JULY 2018

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《计算电机驱动器的功耗》应用报告

德州仪器 (TI)，《电流再循环和衰减模式》应用报告

德州仪器 (TI)，《DRV8886 评估模块用户指南》

德州仪器 (TI)，《使用数模转换器 (DAC) 调整满量程电流》应用报告

德州仪器 (TI)，《工业电机驱动解决方案指南》

德州仪器 (TI)，《PowerPAD™ 速成》应用报告

德州仪器 (TI)，《PowerPAD™ 热增强型封装》应用报告

德州仪器 (TI)，《了解电机驱动器电流额定值》应用报告

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jun-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DRV8886PWP

DRV8886PWPR

DRV8886RHRR

DRV8886RHRT

ACTIVE

HTSSOP

WQFN

PWP

RHR

RoHS & Green

NIPDAU

Level-3-260C-168 HR

Level-1-260C-UNLIM

-40 to 125

DRV8886

Samples

2000 RoHS & Green

3000 RoHS & Green

NIPDAU

DRV8886

WQFN

250

RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jun-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DRV8886PWPR

DRV8886RHRR

DRV8886RHRT

HTSSOP PWP

2000

3000

250

330.0

180.0

16.4

12.4

6.95

3.8

8.3

5.8

1.6

1.2

8.0

16.0

12.0

WQFN

RHR

3.8

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DRV8886PWPR

DRV8886RHRR

DRV8886RHRT

HTSSOP

WQFN

PWP

RHR

2000

3000

250

350.0

367.0

210.0

350.0

367.0

185.0

43.0

35.0

WQFN

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

PWP HTSSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

DRV8886PWP

530

10.2

3600

3.5

Pack Materials-Page 3

GENERIC PACKAGE VIEW

PWP 24

4.4 x 7.6, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224742/B

www.ti.com

PACKAGE OUTLINE

PWP0024B

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

0.1 C

AREA

22X 0.65

7.9

7.7

NOTE 3

7.15

0.30

24X

4.5

4.3

0.19

0.1

C A

(0.15) TYP

SEE DETAIL A

4X (0.2) MAX

NOTE 5

2X (0.95) MAX

NOTE 5

EXPOSED

THERMAL PAD

0.25

GAGE PLANE

5.16

4.12

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

TYPICAL

(1)

2.40

1.65

4222709/A 02/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may not be present and may vary.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0024B

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(2.4)

24X (1.5)

SYMM

SEE DETAILS

24X (0.45)

(R0.05)

TYP

(7.8)

NOTE 9

(1.1)

TYP

SYMM

(5.16)

22X (0.65)

(

0.2) TYP

VIA

(1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-24

4222709/A 02/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0024B

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(2.4)

BASED ON

0.125 THICK

STENCIL

24X (1.5)

(R0.05) TYP

24X (0.45)

(5.16)

SYMM

BASED ON

0.125 THICK

STENCIL

22X (0.65)

SYMM

(5.8)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.68 X 5.77

2.4 X 5.16 (SHOWN)

2.19 X 4.71

0.125

0.15

0.175

2.03 X 4.36

4222709/A 02/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

RHR 28

3.5 x 5.5, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4210249/B

www.ti.com

PACKAGE OUTLINE

RHR0028A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.6

3.4

PIN 1 INDEX AREA

0.5

0.3

5.6

5.4

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

2±0.1

2X 1.5

(0.2) TYP

EXPOSED

THERMAL PAD

24X 0.5

4.5

4±0.1

SEE TERMINAL

DETAIL

0.3

28X

0.5

0.2

PIN 1 ID

(OPTIONAL)

0.1

C A

28X

0.3

0.05

4219075/A 11/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHR0028A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2)

SYMM

28X (0.6)

28X (0.25)

24X (0.5)

(0.66)

(5.3)

TYP

SYMM

(4)

(

0.2) TYP

VIA

(0.75) TYP

(3.3)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219075/A 11/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RHR0028A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.55) TYP

28X (0.6)

28X (0.25)

24X (0.5)

SYMM

(1.32)

TYP

(5.3)

METAL

TYP

6X (1.12)

6X (0.89)

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4219075/A 11/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DRV8886 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E