DS100BR210_14 [TI]

Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output De-Emphasis;


型号：	DS100BR210_14
厂家：	TEXAS INSTRUMENTS
描述：	Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output De-Emphasis
文件：	总39页 (文件大小：1757K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

April 9, 2012

DS100BR210

Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input

Equalization and Output De-Emphasis

General Description

Features

The DS100BR210 is an extremely low power, high perfor-

mance dual-channel repeater for serial links with data rates

up to 10.3 Gbps. The DS100BR210 is configured as two uni-

directional channels.

Two channel repeater for up to 10.3 Gbps

■

DS100BR210 : 2x unidirectional channels

DS100BR111 : 1x bidirectional lane

—

10G-KR bi-directional interface compatibility

■

The DS100BR210 inputs feature a powerful 4-stage continu-

ous time linear equalizer (CTLE) to provide a boost of up to

+36 dB at 5 GHz and open an input eye that is completely

closed due to inter-symbol interference (ISI) induced by the

interconnect mediums such as an FR-4 backplane or

AWG-30 cables. The transmitter features a programmable

output de-emphasis driver with up to -12 dB and allows am-

plitude voltage levels to be selected from 700 mVp-p to 1200

mVp-p to suit multiple application scenarios.

Allows for back-channel communication and training

—

Low 65mW/channel (typical) power consumption, with

option to power down unused channels

Advanced signal conditioning features

■

Receive equalization up to +36 dB

Transmit de-emphasis up to -12 dB

Transmit VOD control: 700 to 1200 mVp-p

< 0.3 UI of residual DJ at 10 Gbps

—

When configured as a 10G-KR repeater, the DS100BR210

allows the KR host and the end point to optimize the full link

by adjusting transmit and receive equalizer coefficients using

back-channel communication techniques specified by the

802.3ap standard.

Programmable via pin selection, EEPROM or SMBus

interface

■

Single supply operation selectable: 2.5V or 3.3v

■

Flow-thru pinout in 4mmx4mm 24-pin leadless LLP

package

The programmable settings can be applied via pin contol,

SMBus (I2C) protocol or an external EEPROM. When oper-

ating in the EEPROM mode, the configuration information is

automatically loaded on power up – This eliminates the need

for an external microprocessor or software driver.

>5kV HBM ESD rating

■

Industrial -40 to 85°C operating temperature range

Applications

Part of National's PowerWise family of energy efficient de-

vices, the DS100BR210 consumes just 65 mW/channel (typ-

ical), and allows the option to turn-off unused channels. This

ultra low power consumption eliminates the need for external

heat sinks and simplifies thermal management in active cable

applications.

High-speed active copper cable modules and FR-4

backplane in communication systems

■

10GE, 10G-KR, FC, SAS, SATA 3/6 Gbps (with OOB

detection), InfiniBand, CPRI, RXAUI and many others.

■

Typical Application

30175390

301753 SNLS348C

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Block Diagram - Detail View Of Channel (1 Of 2)

30175386

Pin Diagram

30175324

DS100BR210 Pin Diagram 24 lead

Note 1: The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through multiple (minimum of 4) vias to

ensure optimal electrical and thermal performance.

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Ordering Information

NSID

Qty

Spec

Package

SQA24A

DS100BR210SQ

DS100BR210SQE

Tape & Reel Supplied As 1,000 Units

Tape & Reel Supplied As 250 Units

NOPB

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Pin Descriptions

Pin Name

Pin Number I/O, Type

Pin Descriptions

Differential High Speed I/O's

INA+, INA- ,

INB+, INB-,

7, 8

11, 12

I, CML

O,CML

Inverting and non-inverting CML differential inputs to the

equalizer. A on-chip 50Ω termination resistor connects INx+ to

VDD and INx- to VDD when enabled.

OUTA+, OUTA-,

OUTB+, OUTB-,

24, 23

20, 19

Inverting and non-inverting 50Ω driver outputs with de-emphasis.

Compatible with AC coupled CML inputs.

Control Pins

ENSMB

I, LVCMOS

Float

System Management Bus (SMBus) enable pin

Tie HIGH = Register Access, SMBus Slave mode

FLOAT = SMBus Master read from External EEPROM

Tie LOW = External Pin Control Mode

ENSMB = 1 (SMBUS MODE)

SCL

I, LVCMOS

O, Open

Drain

ENSMB Master or Slave mode

SMBUS clock input pin is enabled. A clock input in Slave mode.

Can also be a clock output in Master mode.

SDA

I, LVCMOS, ENSMB Master or Slave mode

O, Open

Drain

The SMBus bidirectional SDA pin is enabled. Data input or open

drain (pull-down only) output.

AD0-AD3

10, 9, 2, 1

I, LVCMOS, ENSMB Master or Slave mode

Float

SMBus Slave Address Inputs. In SMBus mode, these pins are

(4-Levels)

the user set SMBus slave address inputs. There are 16

addresses supported by these pins.

Pins must be tied LOW or HIGH when used to define the device

SMBus address.

Note: Setting VOD_SEL = High in SMBus Mode will force the

Address = B0'h

READEN#

DONE#

I, LVCMOS

When using an External EEPROM, a transition from high to low

starts the load from the external EEPROM

IO, LVCMOS, EEPROM Download Status

Float

HIGH indicates Error / Still Loading

(4-Levels)

LOW indicates download complete. No Error.

ENSMB = 0 (PIN MODE)

EQA0, EQA1

EQB0, EQB1

10, 9

1, 2

I, LVCMOS, EQA/B ,0/1 control the level of equalization of each channel. The

Float

EQA/B pins are active only when ENSMB is de-asserted (LOW).

When ENSMB goes high the SMBus registers provide

independent control of each lane, and the EQB0/B1 pins are

converted to SMBUS AD2/AD3 inputs.

(4-Levels)

Table 3: Equalizer Settings

DEMA, DEMB

4, 5

IO, LVCMOS, DEMA/B controls the level of de-emphasis. The DEMA/B pins

Float

(4-Levels)

are only active when ENSMB is de-asserted (LOW). The default

SMBus setting is -3.5 dB. Each of the 4 A/B channels have the

same level unless controlled by the SMBus control registers.

When ENSMB goes high the SMBus registers provide

independent control of each lane and the DEM pins are

converted to SMBUS SCL and SDA pins.

Table 4: De-emphasis and Output Voltage Settings

TX_DIS

I, LVCMOS

DS100BR210

High = OUTA/B Disabled

Low = OUTA/B Enabled

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Pin Name

Pin Number I/O, Type

Pin Descriptions

VOD_SEL

I, LVCMOS, EQ Mode and VOD select.

Float

High = 10G-KR Mode (VOD = 1.1V/1.3V)

(4-Levels)

Float = (VOD = 1.0 V)

20K = (VOD = 1.2 V)

Low = (VOD = 700m V)

Note: Setting VOD_SEL = High in SMBus Mode will force the

SMBus Address = B0'h

VDD_SEL

MODE

I, Internal

Pull-up

Enables the 3.3V to 2.5V internal regulator

Low = 3.3 V Operation

Float = 2.5 V Operation

I, LVCMOS, Controls Device Mode of Operation

Float

(4-Levels)

High = Continuous Talk (no output IDLE)

Float = 10G-KR Mode, Slow OOB

20KΩ = eSATA Mode, Fast OOB, Auto Low Power on 100 uS of

inactivity. SD stays active.

Low = SAS Mode, Fast OOB

Status Output

LOS

O, Open

Drain

When HIGH, indicates Loss of Signal (Default is LOS on INA).

Can be modified via SMBus registers.

LOS Threshold Input

SD_TH

I, LVCMOS, The SD_TH pin controls LOS threshold setting;

Float

Assert (mV), Deassert (mV)

(4-Levels)

20K = 160 mV, 100 mV

Float = 180 mV, 110 mV (Default)

High = 190 mV, 130 mV

Low = 210 mV, 150 mV

Note: Using values less than the default level can extend the

time required to detect LOS and are not recommended.

Power

VDD

21, 22

Power

Power supply pins

2.5V mode connect to 2.5V

3.3V mode do not connect to any supply voltage. Should be used

to attach external decoupling to device, 100 - 200 nF recom-

mended.

NOTE: See Applications section for additional information.

VIN

Power

VIN = 3.3V +/-10% (input to internal LDO regulator)

NOTE: Must FLOAT for 2.5V operation. See Applications

section for additional information.

GND

DAP

Ground pad (DAP - die attach pad).

Notes:

LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not

guaranteed. Unless the "Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V

mode), or VIN (in 3.3V mode). For Additional information. Tables Table 2: 4-Level Control Pin Settings, Table 6: 4-Level

Input Voltage

Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.

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MM, STD - JESD22-A115-A

CDM, STD - JESD22-C101-D

Package Thermal Resistance

θJC

100 V

1250 V

Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

3.2°C/W

33.0°C/W

θJA, No Airflow, 4 layer JEDEC

For soldering specifications:

Supply Voltage (VDD)

Supply Voltage (VIN)

LVCMOS Input/Output Voltage

CML Input Voltage

-0.5V to +2.75V

-0.5V to +4.0V

-0.5V to (VDD+0.5)

-30 to +30 mA

125°C

See product folder at www.national.com

www.national.com/ms/MS/MS-SOLDERING.pdf

Min

Typ Max Units

2.375 2.5 2.625

CML Input Current

Supply Voltage (2.5V mode)

Supply Voltage (3.3V mode)

Ambient Temperature

°C

Junction Temperature

Storage Temperature

ESD Rating

3.0

-40

3.3 3.6

25 +85

3.6

-40°C to +125°C

SMBus (SDA, SCL)

HBM, STD - JESD22-A114F

> 5 kV

Symbol

Power Supply Current

IDD Supply Current

Parameter

Conditions

Min

Typ

Max

Units

TX_DIS = LOW, EQ = ON

VOD_SEL = Float ( 1000 mV)

Auto Low Power Mode

TX_DIS = LOW, MODE = 20K

VID CHA and CHB = 0.0V

VOD_SEL = Float (1000 mV)

TX_DIS = HIGH (BR210)

LVCMOS DC Specifications

V_IH

High Level Input

Voltage

2.0

VDD

0.7

V_IL

Low Level Input Voltage

GND

2.0

V_OH

High Level Output

Voltage

I_OH= -4.0 mA

(Note 5)

V_OL

I_IN

Low Level Output

Voltage

I_OL= 4.0 mA

0.4

+15

+80

Input Leakage Current Vinput = 0V or VDD

SCL and SDA

-15

VDD_SEL = Float

Vinput = 0V or VIN

VDD_SEL = Low

I_IN-P

Input Leakage Current Vinput = 0V or VDD - 0.05V

-160

4-Level Input

VDD_SEL = Float

(Note 3)

Vinput = 0V or VIN - 0.05V

VDD_SEL = Low

LOS and ENABLE / DISABLE Timing

T_{LOS_OFF}

T_{LOS_ON}

T_OFF

Input IDLE to Active

RX_LOS response time

(Note 13)

0.035

0.4

Input Active to IDLE

RX_LOS response time

TX Disable assert Time (Note 13)

TX_DIS = HIGH to

0.005

Output OFF

T_ON

TX Disable negateTime (Note 13)

TX_DIS = LOW to

Output ON

0.150

150

T_{LP_EXIT}

Auto Low Power Exit

ALP to Normal

Operation

(Note 13)

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

T_{LP_ENTER}

Auto Low Power Enter (Note 13)

Normal Operation to

Auto Low Power

100

800

CML RECEIVER INPUTS

V_TX

Source Transmit

Launch Signal Level

RX return loss

Default power-up conditions

ENSMB = 0 or 1

190

1600

RL_RX-IN

SDD11 @ 4.1 GHz

SDD11 @ 11.1 GHz

SCD11 @ 11.1 GHz

-12

-8

-10

HIGH SPEED TRANSMITTER OUTPUTS

V_OD1

Output Voltage

Differential Swing

OUT+ and OUT- AC coupled

and terminated by 50Ω to

GND

VOD_SEL = LOW (700 mV

setting)

500

800

950

650

1000

1150

- 3.5

- 6.0

- 9.0

800

1100

1350

mVp-p

DE = LOW

V_OD2

Output Voltage

Differential Swing

OUT+ and OUT- AC coupled

and terminated by 50Ω to

GND

VOD_SEL = FLOAT (1000

mV setting)

DE = LOW

V_OD3

Output Voltage

Differential Swing

OUT+ and OUT- AC coupled

and terminated by 50Ω to

GND

VOD_SEL = 20K (1200 mV

setting)

DE = LOW

V_{OD_DE1}

V_{OD_DE2}

V_{OD_DE3}

De-Emphasis Levels

OUT+ and OUT- AC coupled

and terminated by 50Ω to

GND

VOD_SEL = FLOAT (1000

mV setting)

DE = FLOAT

OUT+ and OUT- AC coupled

and terminated by 50Ω to

GND

VOD_SEL = FLOAT (1000

mV setting)

DE = 20K

OUT+ and OUT- AC coupled

and terminated by 50Ω to

GND

VOD_SEL = FLOAT (1000

mV setting)

DE = HIGH

V_CM-AC

V_CM-DC

V_IDLE

Output Common-Mode AC Common Mode Voltage

4.5

1.1

mV (RMS)

Voltage

DE = 0 dB, VOD <= 1000 mV

DC Common Mode Voltage

Output DC Common-

Mode Voltage

1.9

TX IDLE Output

Voltage

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

RL_TX-DIFF

TX return loss

SDD22 @ 4.1 GHz

SDD22 @ 11.1 GHz

SCC22 @ 2.5 GHz

SCC22 @ 11.1 GHz

Measured at DC operating

-13

-9

-22

-10

2.5

delta Z_M

Transmitter

Termination Mismatch point

(Note 6)

T_R/F

Transmitter Rise and

Fall Time

Measurement points at 20% -

80%

(Note 14)

T_PD

Propagation Delay

Measured at 50% crossing

EQ = 00

230

T_CCSK

Channel to Channel

Skew

T = 25°C, VDD = 2.5V

T_PPSK

Part to Part Skew

T = 25°C, VDD = 2.5V

T_{TX-IDLE-SET-TO-}Max time to transition to VIN = 1Vpp, 10 Gbps

6.5

idle after differential

signal

EQ = 00, DE = 0

IDLE

T_{TX-IDLE-TO-DIFF-}Max time to transition to VIN = 1Vpp, 10 Gbps

3.2

3.3

valid differential signal EQ = 00, DE = 0

DATA

after idle

T_{ENV_DISTORT}

Active OOB timing

distortion, input active

time vs. output active

time

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

OUTPUT JITTER SPECIFICATIONS: (Note 4)

R_J

Random Jitter

No Media

Source Amplitude = 700 mV,

PRBS15 pattern,

0.3

ps (RMS)

D_J1

Deterministic Jitter

0.09

10.3125 Gbps

VOD = Default, EQ =

minimum, DE = 0 dB

Equalization

D_JE1

Residual Deterministic 8 meter 30AWG Cable on

0.27

0.17

Jitter

Input

10.3125 Gbps

Source = 700 mV, PRBS15

pattern

EQ = 0F'h; See Figure 15

D_JE2

Residual Deterministic

Jitter

30" 4-mil FR4 on Inputs

Source = 700 mV, PRBS15

pattern

10.3125 Gbps

EQ = 16'h; See Figure 12

De-emphasis

D_JD1

Residual Deterministic 10” 4 mil stripline FR4 on

0.13

Jitter

10.3125 Gbps

Outputs

Source = 700 mV, PRBS15

pattern

EQ = Min, VOD = 1200 mV,

DE = 010'b

See Figure 17

Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage

to the device may occur, including inoperability and degradation of device

reliability and/or performance. Functional operation of the device and/or non-

degradation at the Absolute Maximum Ratings or other conditions beyond

those indicated in the Recommended Operating Conditions is not implied.

The Recommended Operating Conditions indicate conditions at which the

device is functional and the device should not be operated beyond such

conditions. Absolute Maximum Numbers are guaranteed for a junction

temperature range of -40°C to +125°C. Models are validated to Maximum

Operating Voltages only.

Note 4: Typical jitter reported is determined by jitter decomposition software

on the DSA8200 Oscilloscope.

Note 5: VOH only applies to the DONE# pin; LOS, SCL, and SDA are open-

drain outputs that have no internal pull-up capability. DONE# is a full

LVCMOS output with pull-up and pull-down capability

Note 6: Force +/- 100 uA on output, measure delta V on the Output and

calculate impedance. Mismatch is the percentage difference of OUTn+ and

OUTn- impedance driving the same logic state.

Note 3: Input is held to a maximum of 50 mV below VDD or VIN to simulate

the use of a 1K resistor on the input.

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Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SERIAL BUS INTERFACE DC SPECIFICATIONS: (Note 7)

V_IL

Data, Clock Input Low Voltage

Data, Clock Input High Voltage

0.8

3.6

V_IH

2.1

I_PULLUP

Current Through Pull-Up Resistor High Power Specification

or Current Source

V_DD

Nominal Bus Voltage

2.375

-200

3.6

+200

I_LEAK-Bus

C_I

Input Leakage Per Bus Segment (Note 8)

µA

Capacitance for SDA and SCL

(Note 8, Note 9, Note 12)

R_TERM

External Termination Resistance Pullup V_DD= 3.3V,

2000

1000

Ω

pull to V_DD= 2.5V ± 5% OR 3.3V ±

10%

(Note 8, Note 9, Note 10)

Pullup V_DD= 2.5V,

(Note 8, Note 9, Note 10)

SERIAL BUS INTERFACE TIMING SPECIFICATIONS

FSMB

Bus Operating Frequency

ENSMB = VDD (Slave Mode)

400

520

kHz

ENSMB = FLOAT (Master Mode)

(Note 7)

280

1.3

400

TBUF

Bus Free Time Between Stop and

Start Condition

µs

THD:STA

Hold time after (Repeated) Start

Condition. After this period, the first

clock is generated.

At I_PULLUP, Max

0.6

TSU:STA

Repeated Start Condition Setup

Time

TSU:STO

THD:DAT

TSU:DAT

T_LOW

Stop Condition Setup Time

Data Hold Time

0.6

µs

Data Setup Time

100

1.3

0.6

Clock Low Period

T_HIGH

t_F

Clock High Period

Clock/Data Fall Time

Clock/Data Rise Time

(Note 11)

300

t_R

(Note 11)

t_POR

Time in which a device must be

operational after power-on reset

(Note 11, Note 12)

500

Note 7: EEPROM interface requires 400 KHz capable EEPROM device.

Note 8: Recommended value.

Note 9: Recommended maximum capacitance load per bus segment is 400pF.

Note 10: Maximum termination voltage should be identical to the device supply voltage.

Note 11: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common

AC specifications for details.

Note 12: Guaranteed by Design and/or characterization. Parameter not tested in production.

Note 13: Parameter not tested in production.

Note 14: Default VOD used for testing. DE = -1.5 dB level used to compensate for fixture attenuation.

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Timing Diagrams

30175302

FIGURE 1. CML Output Transition Times

30175303

FIGURE 2. Propagation Delay Timing Diagram

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30175304

FIGURE 3. Idle Timing Diagram

30175301

FIGURE 4. SMBus Timing Parameters

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Functional Description

The DS100BR210 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the

details associated with high-speed design as well as providing a clean power supply. Refer to the information below and Revision

4 of the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues.

The control pins have been enhanced to have 4 different levels and provide a wider range of control settings. Refer to

Table 2: 4-Level Control Pin Settings

Pin Setting

Description

Tie pin to GND through a 1 KΩ resistor

Tie pin to ground through 20 KΩ resistor

Float the pin (no connection)

Float

Tie pin to VDD through a 1 KΩ resistor

Note: 4-Level IO pins require a 1K resistance to GND or VDD/VIN. It is possible to tie mulitple 4-level IO pins together with a single

resistor to GND or VDD/VIN. When multiple IOs are connected in parallel, the resistance to GND or VDD/VIN should be adjusted

to compensate. For 2 pins the optimal resistance is 500 Ohms, 3 pins = 330 Ohms, and 4 pins = 250 Ohms.

Note: For 2.5V mode the control pin logic 1 level is VDD (pins 21 and 22), in 3.3V mode the control pin logic 1 level is defined by

VIN (pin 15).

Table 3: Equalizer Settings

EQA1/

EQB1

EQA0/

EQB0

Level

EQ — 8 bits [7:0] dB Boost at 5 Ghz

Suggested Media

0000 0000 = 0x00

0000 0001 = 0x01

0000 0010 = 0x02

0000 0011 = 0x03

0000 0111 = 0x07

0001 0101 = 0x15

0000 1011 = 0x0B

0000 1111 = 0x0F

0101 0101 = 0x55

0001 1111 = 0x1F

2.5

6.5

FR4 < 5 inch trace

FR4 5 inch trace

FR4 10 inch trace

FR4 15 inch trace

FR4 20 inch trace

FR4 25 inch trace

7m 30AWG Cable

FR4 30 inch trace

Float

11.5

Float

8m 30 AWG Cable

FR4 35 inch trace

Float

0010 1111 = 0x2F

0011 1111 = 0x3F

1010 1010 = 0xAA

0111 1111 = 0x7F

1011 1111 = 0xBF

1111 1111 = 0xFF

10m 30 AWG Cable

10m - 12m, Cable

Float

Note: Settings are approximate and will change based on PCB material, trace dimensions, and driver waveform characteristics.

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Table 4: De-emphasis and Output Voltage Settings

SMBus Register VOD

Level

Level VOD_SEL DEMA/B

SMBus Register DEM Level

VOD (mV)

DEM (dB)

000

010

011

101

000

010

011

101

000

010

011

101

000

001

010

000

011

101

100

110

100

110

700

Float

- 3.5

- 6

700

- 9

Float

1000

1200

1100

1300

1100

1300

- 3.5

- 6

- 9

- 0

Float

- 3.5

- 6

- 9

Float

- 1.5

- 3.5

Note: When VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS100BR210 will support 10G-KR back-channel

communication using pin control.

Note: In SMBus Mode if VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS100BR210 AD0-AD3 pins are internally

forced to 0'h

Table 5: Signal Detect Threshold Level

SMBus REG bit

[3:2] and [1:0]

SD_TH

Assert Level (Typical)

De-assert Level (Typical)

210 mV

160 mV

180 mV

190 mV

150 mV

100 mV

110 mV

130 mV

20K to GND

Float (Default)

Note: VDD = 2.5V, 25°C, and 010101 pattern at 10 Gbps

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APPLICATIONS INFORMATION

rically for each side of a given differential pair. Whenever

differential vias are used the layout must also provide for a

low inductance path for the return currents as well. Route the

differential signals away from other signals and noise sources

on the printed circuit board. See AN-1187 for additional infor-

mation on LLP packages.

4-Level Input Configuration Guidelines

The 4-level input pins utilize a resistor divider to help set the

4 valid levels. There is an internal 30K pull-up and a 60K pull-

down connected to the package pin. These resistors, together

with the external resistor connection combine to achieve the

desired voltage level. Using the 1K pull-up, 1K pull-down, no

connect, and 20K pull-down provide the optimal voltage levels

for each of the four input states.

Different transmission line topologies can be used in various

combinations to achieve the optimal system performance.

Impedance discontinuities at vias can be minimized or elimi-

nated by increasing the swell around each hole and providing

for a low inductance return current path. When the via struc-

ture is associated with thick backplane PCB, further optimiza-

tion such as back drilling is often used to reduce the

detrimental high frequency effects of stubs on the signal path.

Table 6: 4-Level Input Voltage

Level

Setting

01K to GND

20K to GND

FLOAT

3.3V Mode

0.1 V

2.5V Mode

0.08 V

0.33 * V_IN

0.67 * V_IN

V_IN- 0.05V

0.33 * V_DD

0.67 * V_DD

V_IN- 0.04V

Power Supply Configuration Guidelines

The DS100BR210 can be configured for 2.5V operation or

3.3V operation. The lists below outline required connections

for each supply selection.

1K to V_DD/V_IN

•

Typical 4-Level Input Thresholds

3.3V Mode of Operation

1. Tie VDD_SEL = 0 with 1K resistor to GND.

Level 1 - 2 = 0.2 V_INor V_DD

Level 2 - 3 = 0.5 V_INor V_DD

Level 3 - 4 = 0.8 V_INor V_DD

—

2. Feed 3.3V supply into VIN pin. Local 1.0 uF decoupling

at VIN is recommended.

In order to minimize the startup current associated with the

integrated 2.5V regulator the 1K pull-up / pull-down resistors

are recommended. If several 4 level inputs require the same

setting, it is possible to combine two or more 1K resistors into

a single lower value resistor. As an example; combining two

inputs with a single 500Ω resistor is a good way to save board

space.

3. See information on VDD bypass below.

4. SDA and SCL pins should connect pull-up resistor to VIN

5. Any 4-Level input which requires a connection to "Logic

1" should use a 1K resistor to VIN

2.5V Mode of Operation

1. VDD_SEL = Float

10G-KR Configuration Guidelines

2. VIN = Float

When configured in "KR Mode", using eith the VOD_SEL pin

setting or SMBus register control, the DS100BR210 is de-

signed to operate transparently within a KR backplance chan-

nel environment. Installing a DS100 repeater within the KR

backplane channel splits the total channel attenuation into

two parts. Ideally the repeater can be placed near the middle

of the channel maximizing the signal to noise ratio across the

bidirectional interface.

3. Feed 2.5V supply into VDD pins.

4. See information on VDD bypass below.

5. SDA and SCL pins connect pull-up resistor to VDD for

2.5V uC SMBus IO

6. SDA and SCL pins connect pull-up resistor to 3.3V for

3.3V uC SMBus IO

Any 4-Level input which requires a connection to "Logic

1" should use a 1K resistor to VDD

In order to maximize the 10G-KR solution space, the 802.3ap

specification calls for an optimization of the transmit signal

conditioning coefficients based on feedback for the KR re-

ceiver. Setting the DS100BR210 active CTLE to compensate

for the channel loss from each of the KR transmitters will re-

duce the transmit and receive equalization settings required

on the KR physical layer devices. This central location keeps

a larger S/N raito at all points in the channel, extending the

available solution space and increasing the overall margin of

almost any channel.

Note: The DAP (bottom solder pad) is the GND connection.

Power Supply Bypass

Two approaches are recommended to ensure that the

DS100BR210 is provided with an adequate power supply.

First, the supply (VDD) and ground (GND) pins should be

connected to power planes routed on adjacent layers of the

printed circuit board. The layer thickness of the dielectric

should be minimized so that the V_DDand GND planes create

a low inductance supply with distributed capacitance. Sec-

ond, careful attention to supply bypassing through the proper

use of bypass capacitors is required. A 0.1 μF bypass capac-

itor should be connected to each V_DDpin such that the ca-

pacitor is placed as close as possible to the device. Smaller

body size capacitors can help facilitate proper component

placement.

PCB Layout Guidelines

The CML inputs and outputs have been optimized to work with

interconnects using a controlled differential impedance of 85

- 100Ω. It is preferable to route differential lines exclusively on

one layer of the board, particularly for the input traces. The

use of vias should be avoided if possible. If vias must be used,

they should be used sparingly and must be placed symmet-

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System Management Bus (SMBus) and Configuration

Registers

IDLE: If SCL and SDA are both High for a time exceeding

t_BUFfrom the last detected STOP condition or if they are High

for a total exceeding the maximum specification for t_HIGHthen

the bus will transfer to the IDLE state.

The System Management Bus interface is compatible to SM-

Bus 2.0 physical layer specification. ENSMB must be pulled

high to enable SMBus mode and allow access to the config-

uration registers.

SMBus TRANSACTIONS

The device supports WRITE and READ transactions. See

Write, Read Only), default value and function information.

The DS100BR210 has AD[3:0] inputs in SMBus mode. These

pins are the user set SMBus slave address inputs. When

pulled low the AD[3:0] = 0000'b, the device default address

byte is B0'h. Based on the SMBus 2.0 specification, this con-

figuration results in a 7-bit slave address of 1011000'b. The

LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1011

0000'b or B0'h. The device address byte can be set with the

use of the AD[3:0] inputs.

WRITING A REGISTER

To write a register, the following protocol is used (see SMBus

2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus

address, and a “0” indicating a WRITE.

Shown in the form of an expression:

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drive the 8-bit data byte.

6. The Device drives an ACK bit (“0”).

7. The Host drives a STOP condition.

Slave Address [7:4] = The DS100BR210 hardware address

(1011'b) + Address pin AD[3]

Slave Address [3:1] = Address pins AD[2:0]

Slave Address [0] = 0'b for a WRITE or 1'b for a READ

Slave Address Examples:

•

AD[3:0] = 0001'b, the device slave address byte is B2'h

The WRITE transaction is completed, the bus goes IDLE and

communication with other SMBus devices may now occur.

Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h

Slave Address [3:1] = 001'b

—

READING A REGISTER

Slave Address [0] = 0'b for a WRITE

To read a register, the following protocol is used (see SMBus

2.0 specification).

AD[3:0] = 0010'b, the device slave address byte is B4'h

Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h

Slave Address [3:1] = 010'b

—

1. The Host drives a START condition, the 7-bit SMBus

address, and a “0” indicating a WRITE.

Slave Address [0] = 0'b for a WRITE

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

AD[3:0] = 0100'b, the device slave address byte is B8'h

Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h

Slave Address [3:1] = 100'b

—

5. The Host drives a START condition.

Slave Address [0] = 0'b for a WRITE

6. The Host drives the 7-bit SMBus Address, and a “1”

indicating a READ.

AD[3:0] = 1000'b, the device slave address byte is C0'h

Slave Address [7:4] = 1011'b + 1'b = 1100'b or C'h

Slave Address [3:1] = 000'b

—

7. The Device drives an ACK bit “0”.

8. The Device drives the 8-bit data value (register contents).

Slave Address [0] = 0'b for a WRITE

9. The Host drives a NACK bit “1”indicating end of the

READ transfer.

TRANSFER OF DATA VIA THE SMBus

10. The Host drives a STOP condition.

During normal operation the data on SDA must be stable dur-

ing the time when SCL is High.

The READ transaction is completed, the bus goes IDLE and

communication with other SMBus devices may now occur.

There are three unique states for the SMBus:

Please see SMBus Register Map Table for more information.

START: A High-to-Low transition on SDA while SCL is High

indicates a message START condition.

STOP: A Low-to-High transition on SDA while SCL is High

indicates a message STOP condition.

30175305

FIGURE 5. Typical SMBus Write Operation

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EEPROM Modes in the DS100BR210

The DS100BR210 device supports reading directly from an external EEPROM device by implementing SMBus Master mode. When

using the SMBus master mode, the DS100 will read directly from specific location in the external EEPROM. When designing a

system for using the external EEPROM, the user needs to follow these specific guidelines.

•

Set the DS100BR210 into SMBus Master Mode

Float ENSMB (PIN 3)

—

•

The external EEPROM device must support 400 KHz operation

The external EEPROM device address byte must be 0xA0'h

Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.

Based on the SMBus 2.0 specification, a device can have a 7-bit slave address of 1010 000'b. The LSB is set to 0'b (for a

WRITE). The bit mapping for SMBus is listed below:

[7:5] = Reserved Bits from the SMBus specification

[4:1] = Usable SMBus Address Bits

[0] = Write Bit

—

•

The DS100BR210 device has AD[3:0] inputs in SMBus mode (pins 1, 2, 9, 10). These pins set SMBus slave address. When

the AD[3:0] = 0001'b, the device address byte is B2'h.

[7:5] = Default to 3b'101

[4:1] = Address of 4'b0001

[0] = Write Bit, 1'b0

—

The device address can be set with the use of the AD[3:0] input up to 16 different addresses. Use the example below to set

each of the SMBus addresses.

AD[3:0] = 0001'b, the device address byte is B2'h

AD[3:0] = 0010'b, the device address byte is B4'h

AD[3:0] = 0011'b, the device address byte is B6'h

AD[3:0] = 0100'b, the device address byte is B8'h

—

•

The master implementation in the DS100BR210, supports multiple devices reading from 1 EEPROM. When tying multiple

devices to the SDA and SCL pins, use these guidelines:

Use adjacent SMBus addresses for the 4 devices

—

Use a pull-up resistor on SDA; value = 4.7KΩ

Use a pull-up resistor on SCL: value = 4.7KΩ

Daisy-chain READEN# (pin 17) and DONE# (pin18) from one device to the next device in the sequence

1. Tie READEN# of the 1st device in the chain (U1) to GND

2. Tie DONE# of U1 to READEN# of U2

3. Tie DONE# of U2 to READEN# of U3

4. Tie DONE# of U3 to READEN# of U4

5. Optional: Tie DONE# of U4 to a LED to show each of the devices have been loaded successfully

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Master EEPROM Mode in the DS100BR210

Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR210 device. The first 3 bytes of the EEPROM

always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag

to enable/disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data

start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS100BR210 address

and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM.

There are 37 bytes of data size for each DS100BR210 device.

30175315

FIGURE 6. Typical EEPROM Data Set

The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the DS100BR210 or 40

bytes in total. The result of this calculation is placed immediately after the DS100BR210 data in the EEPROM which ends with

"5454". The CRC-8 in the DS100BR210 uses a polynomial = x⁸+ x²+ x + 1

In SMBus master mode the DS100BR210 reads its initial configuration from an external EEPROM upon power-up. Some of the

pins of the DS100BR210 perform the same functions in SMBus master and SMBus slave mode. Once the DS100BR210 has

finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and

can be further configured by an external controller over the SMBus. The connection to an external SMBus master is optional and

can be omitted for applications were additional security is desirable. There are two pins that provide unique functions in SMBus

master mode.

•

DONE#

READEN#

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When the DS100BR210 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the

READEN# pin goes low. When the DS100BR210 is finished reading its configuration from the external EEPROM, it drives the

DONE# pin low. In applications where there is more than one DS100BR210 on the same SMBus, bus contention can result if more

than one DS100BR210 tries to take control of the SMBus at the same time. The READEN# and DONE# pins prevent this bus

contention. The system should be designed so that the READEN# pin from one DS100BR210 in the system is driven low on power-

up. This DS100BR210 will take command of the SMBus on power-up and will read its initial configuration from the external

EEPROM. When it is finished reading its configuration, it will drive the DONE# pin low. This pin should be connected to the

READEN# pin of another DS100BR210. When this DS100BR210 senses its READEN# pin driven low, it will take command of the

SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin low. By connecting the

DONE# pin of each DS100BR210 to the READEN# pin of the next DS100BR210, each DS100BR210 can read its initial configu-

ration from the EEPROM without causing bus contention.

30175316

FIGURE 7. Typical multi-device EEPROM connection diagram

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Table 7: Multi-Device EEPROM Register Map Overview

Addr Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

BIt 0

CRC EN

Address

Map

EEPROM > Reserved

256 Bytes

COUNT[3]

COUNT[2]

COUNT[1]

COUNT[0]

Header

Reserved

EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3] EE Burst[2] EE Burst[1] EE Burst[0]

CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]

EE AD0 [7] EE AD0 [6] EE AD0 [5] EE AD0 [4] EE AD0 [3] EE AD0 [2] EE AD0 [1] EE AD0 [0]

CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]

EE AD1 [7] EE AD1 [6] EE AD1 [5] EE AD1 [4] EE AD1 [3] EE AD1 [2] EE AD1 [1] EE AD1 [0]

CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]

EE AD2 [7] EE AD2 [6] EE AD2 [5] EE AD2 [4] EE AD2 [3] EE AD2 [2] EE AD2 [1] EE AD2 [0]

CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]

EE AD3 [7] EE AD3 [6] EE AD3 [5] EE AD3 [4] EE AD3 [3] EE AD3 [2] EE AD3 [1] EE AD3 [0]

Device 0 3

Info

Device 1 5

Info

Device 2 7

Info

Device 3 9

Info

Device 0 11

Addr 3

RES

DRES

RES

Device 0 12

Addr 4

PDWN Inp PDWN OSC RES

eSATA CHA eSATA CHB Ovrd TX_DIS

Device 0 46

Addr 38

RES

Device 0 47

Addr 39

Device 1 48

Addr 3

RES

Device 1 49

Addr 4

PDWN Inp PDWN OSC RES

eSATA CHA eSATA CHB Ovrd TX_DIS

Device 1 83

Addr 38

RES

Device 1 84

Addr 39

Device 2 85

Addr 3

RES

Device 2 86

Addr 4

PDWN Inp PDWN OSC RES

eSATA CHA eSATA CHB Ovrd TX_DIS

Device 2 120 RES

Addr 38

RES

Device 2 121 RES

Addr 39

Device 3 122 RES

Addr 3

RES

Device 3 123 RES

Addr 4

PDWN Inp PDWN OSC RES

eSATA CHA eSATA CHB Ovrd TX_DIS

Device 3 157 RES

Addr 38

RES

Device 3 158 RES

Addr 39

•

CRC EN = 1; Address Map = 1

EEPROM > 256 Bytes = 0

COUNT[3:0] = 0011'b

Note: Multiple DS100BR210 devices may point at the same address space if they have identical programming values.

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Table 8: Single EEPROM Header + Register Map with Default Value

EEPROM

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

BIt 0

Address Byte

CRC EN

Address

Map

EEPROM > RES

256 Bytes

COUNT[3]

COUNT[2]

COUNT[1]

COUNT[0]

Description

Value

Present

Description 1 RES

RES

Value

Max

Description

Value

EEPROM

Burst size[7] Burst size[6] Burst size[5] Burst size[4] Burst size[3] Burst size[2] Burst size[1] Burst size[0]

Description 3 Reserved

Reserved

0x01 [6]

Reserved

0x01 [5]

Reserved

0x01 [4]

Reserved

0x01 [3]

Reserved

0x01 [2]

Reserved

0x01 [1]

Reserved

0x01 [0]

Value

0x01 [7]

Description 4 Ovrd_LOS LOS_Value PDWN Inp PWDN Osc Reserved

eSATA

Ovrd

Enable A

Enable B

TX_DIS

Value

0x02 [5]

0x02 [4]

0x02 [3]

0x02 [2]

0x02 [0]

0x04 [7]

0x04 [6]

0x04 [5]

Description 5 TX_DIS

CHA

TX_DIS

CHB

Reserved

EQ Stage 4 EQ Stage 4 Reserved

Overide

IDLE_th

Reserved

CHB

CHA

Value

0x04 [4]

0x04 [3]

0x04 [2]

0x04 [1]

0x04 [0]

0x06 [4]

0x08 [6]

0x08 [5]

Description 6 Ovrd_IDLE Reserved

Ovrd_Out

Mode

Reserved

Value

0x08 [4]

0x08 [3]

0x08 [2]

0x08 [1]

0x08 [0]

0x0B [6]

0x0B [5]

0x0B [4]

Description 7 Reserved

Reserved

0x0B [2]

Reserved

0x0B [1]

Reserved

0x0B [0]

Idle auto A

0x0E [5]

Idle sel A

0x0E [4]

Reserved

0x0E [3]

Reserved

0x0E [2]

Value

0x0B [3]

Description 8 CHA EQ[7] CHA EQ[6] CHA EQ[5] CHA EQ[4] CHA EQ[3] CHA EQ[2] CHA EQ[1] CHA EQ[0]

Value

0x0F [7]

0x0F [6]

0x0F [5]

0x0F [4]

0x0F [3]

0x0F [2]

0x0F [1]

0x0F [0]

Description 9 A Sel scp

A Out Mode Reserved

Reserved

0x10 [4]

Reserved

0x10 [3]

Reserved

0x10 [2]

Reserved

0x10 [1]

Reserved

0x10 [0]

Value

0x10 [7]

0x10 [6]

0x10 [5]

Description 1 DEMA[2]

DEMA[1]

0x11 [1]

DEMA[0]

0x11 [0]

CHA Slow IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0]

Value

0x11 [2]

0x12 [7]

0x12 [3]

0x12 [2]

0x12 [1]

0x12 [0]

Description 1 Idle auto B Idle sel B

Reserved

0x15 [3]

Reserved

0x15 [2]

CHB EQ[7] CHB EQ[6] CHB EQ[5] CHB EQ[4]

Value

0x15 [5]

0x15 [4]

0x16 [7]

0x16 [6]

0x16 [5]

0x16 [4]

Description 1 CHB EQ[3] CHB EQ[2] CHB EQ[1] CHB EQ[0] B Sel scp

B Out Mode Reserved

Reserved

0x17 [4]

Value

0x16 [3]

0x16 [2]

0x16 [1]

0x16 [0]

0x17 [7]

0x17 [6]

0x17 [5]

Description 1 Reserved

Reserved

0x17 [2]

Reserved

0x17 [1]

Reserved

0x17 [0]

CHB DEM[2] CHB DEM[1] CHB DEM[0] CHB Slow

Value

0x17 [3]

0x18 [2]

0x18 [1]

0x18 [0]

0x19 [7]

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Description

Value

IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0] Reserved

Reserved

0x19 [3]

0x19 [2]

0x19 [1]

0x19 [0]

Description 1 Reserved

Reserved

Value

Description 1 Reserved

Reserved

Value

Description 1 Reserved

Reserved

Value

Description 1 Reserved

Reserved

0x23 [4]

Reserved

0x23 [3]

Reserved

0x23 [2]

Reserved

Value

Description 1 Reserved

Reserved

A VOD[2]

0x25 [4]

Value

Description 2 A VOD[1]

A VOD[0]

0x25 [2]

Reserved

Value

0x25 [3]

Description 2 Reserved

Reserved

ovrd fst idle en hi idle th A en hi idle th B en fst idle A

Value

0x28 [6]

0x28 [5]

0x28 [4]

0x28 [3]

Description 2 en fst idle B Reserved

Reserved

0x28 [0]

Reserved

Value

0x28 [2]

0x28 [1]

Description 2 Reserved

Reserved

Value

Description 2 Reserved

Reserved

B VOD[2]

0x2D [4]

B VOD[1]

0x2D 3]

B VOD[0]

0x2D [2]

Reserved

Value

Description 2 Reserved

Reserved

Value

Description 2 Reserved

Reserved

Value

Description 2 Reserved

Reserved

Value

Description 2 Reserved

Reserved

Value

Description 2 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

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Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

Description 3 Reserved

Reserved

Value

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Below is an example of a 2 kbits (256 x 8-bit) EEPROM Register Dump in hex format for a multi-device DS100BR210 application.

Table 9: Multi DS100BR210 EEPROM Data

EEPROM

Address

(Hex)

EEPROM

Data

Comments

0x43

CRC_EN = 0, Address Map = 1, Device Count = 3 (Devices 0, 1, 2, and 3)

0x00

0x08

0x00

0x0B

0x00

0x30

0x00

0x30

0x00

0x0B

0x00

0x04

0x07

0x00

0x2F

0xED

0x40

0x02

0xFE

0xD4

0x00

0x2F

0xAD

0x40

0x02

0xFA

0xD4

0x01

0x80

0x5F

0x56

0x80

0x05

0xF5

0xA8

0x00

0x5F

0x5A

0x80

0x05

0xF5

0xA8

0x00

EEPROM Burst Size

CRC not used

Device 0 Address Location

CRC not used

Device 1 Address Location

CRC not used

Device 2 Address Location

CRC not used

Device 3 Address Location

Begin Device 0 and Device 3 - Address Offset 3

Default EQ CHA

Default EQ CHB

BR210 CHA VOD = 1000 mV

BR210 CHB VOD = 1000 mV

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EEPROM

Address

(Hex)

EEPROM

Data

Comments

0x54

0x00

0x04

0x07

0x00

0x2F

0xED

0x40

0x02

0xFE

0xD4

0x00

0x2F

0xAD

0x40

0x02

0xFA

0xD4

0x01

0x80

0x5F

0x56

0x80

0x05

0xF5

0xA8

0x00

0x5F

0x5A

0x80

0x05

0xF5

0xA8

0x00

0x54

End Device 0 and Device 3 - Address Offset 39

Begin Device 1 and Device 2 - Address Offset 3

Default EQ CHA

Default EQ CHB

BR210 CHA VOD = 1000 mV

BR210 CHB VOD = 1000 mV

End Device 1 and Device 2 - Address Offset 39

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TABLE 1. Table 10: SMBus Register Map

EEPROM

Name

Address

Bits Field

Type

Default

Description

Reg Bit

0x00

Device ID

Reserved

R/W

0x00

set bit to 0

6:3

I2C Address [3:0]

[6:3] SMBus strap observation

EEPROM reading

done

1: EEPROM Loading

0: EEPROM Done Loading

Reserved

Idle Control

RWSC

R/W

set bit to 0

0x01

Control 1

7:6

0x00

Yes

Control

[7]: Continuous talk ENABLE (Channel A)

[6]: Continuous talk ENABLE (Channel B)

5:3

Reserved

R/W

Set bits to 0

LOS Select

LOS Monitor Selection

1: Use LOS from CH B

0: Use LOS from CH A

1:0

Reserved

LOS override

R/W

Set bits to 00'b

Set bit to 0

0x02

Control 2

0x00

Set bit to 0

Yes

LOS pin override enable (1);

Use Normal Signal Detection (0)

LOS override

value

1: Normal Operation

0: Output LOS

PWDN Inputs

PWDN Oscillator

Reserved

Yes

1: PWDN

0: Normal Operation

Reserved

Yes

Set bit to 0

0x04

Control 3

7:6

eSATA Mode

Enable

R/W

0x00

[7] Channel A (1)

[6] Channel B (1)

TX_DIS Override

Enable

1: Override Use Reg 0x04[4:3]

0: Normal Operation - uses pin

TX_DIS Value

Channel A

1: TX Disabled

0: TX Enabled

TX_DIS Value

Channel B

Reserved

Set bit to 0

1:0

EQ CONTROL

[1]: Channel B - EQ Stage 4 ON/OFF

[0]: Channel A - EQ Stage 4 ON/OFF

0x05

0x06

CRC 1

CRC 2

7:0

CRC[7:0]

R/W

0x00

0x10

Slave Mode CRC Bits

Disable EEPROM R/W

CFG

Disable Master Mode EEPROM Configuration

6:5

Reserved

Set bits to 0

Set bit to 1

Yes

CRC Slave Mode

Disable

[1]: CRC Disable (No CRC Check)

[0]: CRC Check ENABLE

Note: With CRC check DISABLED register

updates take immediate effect on high speed

data path. With CRC check ENABLED

correct CRC value is loaded

2:1

Reserved

Set bits to 0

CRC Enable

Slave CRC Trigger

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0x07

Digital Reset

and Control

R/W

0x01

Reserved

Set bit to 0

Reset Regs

Self clearing reset for registers.

Writing a [1] will return register settings to

default values.

Reset SMBus

Master

Self clearing reset for SMBus master state

machine

4:0

Reserved

Set bits to '0001b

Set bit to 0

0x08

Pin Override 7

R/W

0x00

Override Idle

Threshold

Yes

[1]: Override by Channel - see Reg 0x13 and

0x19

[0]: SD_TH pin control

Reserved

Yes

Set bit to 0

Override IDLE

[1]: Force IDLE by Channel - see Reg 0x0E

and 0x15

[0]: Normal Operation

Reserved

Yes

Set bit to 0

[1]: Enable Output Mode control for individual

outputs. See register locations 0x10[6] and

0x17[6].

Override Out

Mode

[0]: Disable - Outputs are kept in the normal

mode of operation allowing VOD and DE ad-

justments.

Override DEM

Reserved

Yes

Set bit to 0

0x0C

CH A

R/W

0x00

Set bit to 0

Analog

Override 1

Set bit to 0

3:0

7:0

Set bits to 0000'b.

Set bits to 00'h.

0x0D

0x0E

CH A

Reserved

R/W

0x00

CH A

7:6

Reserved

Idle Auto

Set bits to 00'b.

Idle Control

Yes

Auto IDLE value when override bit is set (reg

0x08 [4] = 1)

Idle Select

Force IDLE value when override bit is set (reg

0x08 [4] = 1)

Reserved

Set bit to 0.

Set bits to 0.

2:0

7:0

Reserved

0x0F

0x10

CH A

EQ Setting

BOOST [7:0]

R/W

0x2F

0xED

Yes

EQ Boost Default to 24 dB

See EQ Table for Information

CH A

Sel_scp

[1]: Short Circuit Protection ON

[0]: Short Circuit Protection OFF

Control 1

Output Mode

[1]: Normal operation

[0]: 10G-KR operation

5:3

2:0

Reserved

Yes

Set bits to = 101'b

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0x11

CH A

Control 2

0x82

7:5

Reserved

DEM [2:0]

Set bits to = 100'b

Set bit to 0

R/W

Set bit to 0

2:0

Yes

De-Emphasis (Default = -3.5 dB)

000'b = -0.0 dB

001'b = -1.5 dB

010'b = -3.5 dB

011'b = -6.0 dB

100'b = -8.0 dB

101'b = -9.0 dB

110'b = -10.5 dB

111'b = -12.0 dB

0x12

CH A

Idle

Threshold

Slow OOB

Reserved

R/W

0x00

Yes

Slow OOB Enable (1); Disable (0)

Set bits to 000'b.

6:4

3:2

IDLE thA[1:0]

Assert Thresholds

Use only if register 0x08 [6] = 1

00 = 180 mV (Default)

01 = 160 mV

10 = 210 mV

11= 190 mV

1:0

IDLE thD[1:0]

Yes

De-assert Thresholds

Use only if register 0x08 [6] = 1

00 = 110 mV (Default)

01 = 100 mV

10 = 150 mV

11= 130 mV

0x13

CH B

Analog

Override 1

Reserved

R/W

0x00

Set bit to 0

3:0

7:0

Set bits to 0000'b.

Set bits to 00'h.

0x14

0x15

CH B

Reserved

R/W

0x00

CH B

Idle Control

7:6

Reserved

Idle Auto

Set bits to 00'b

Yes

Auto IDLE value when override bit is set (reg

0x08 [4] = 1)

Idle Select

Force IDLE value when override bit is set (reg

0x08 [4] = 1)

3:2

1:0

7:0

Reserved

Set bits to 00'b.

Reserved

0x16

0x17

CH B

EQ Setting

BOOST [7:0]

R/W

0x2F

0xED

Yes

EQ Boost Default to 24 dB

See EQ Table for Information

CH B

Control 1

Sel_scp

1 = Short Circuit Protection ON

0 = Short Circuit Protection OFF

Output Mode

[1]: Normal operation

[0]: 10G-KR operation

5:3

2:0

Reserved

Set bits to = 101'b

www.ti.com

0x18

CH B

Control 2

0x82

7:5

Reserved

DEM [2:0]

Set bits to = 100'b

Set bit to 0

R/W

Set bit to 0

2:0

Yes

De-Emphasis (Default = -3.5 dB)

000'b = -0.0 dB

001'b = -1.5 dB

010'b = -3.5 dB

011'b = -6.0 dB

100'b = -8.0 dB

101'b = -9.0 dB

110'b = -10.5 dB

111'b = -12.0 dB

0x19

CH B

Idle

Threshold

Slow OOB

Reserved

R/W

0x00

Yes

Slow OOB Enable (1); Disable (0)

Set bits to 000'b.

6:4

3:2

IDLE thA[1:0]

Assert Thresholds

Use only if register 0x08 [6] = 1

00 = 180 mV (Default)

01 = 160 mV

10 = 210 mV

11= 190 mV

1:0

IDLE thD[1:0]

Yes

De-assert Thresholds

Use only if register 0x08 [6] = 1

00 = 110 mV (Default)

01 = 100 mV

10 = 150 mV

11= 130 mV

0x23

0x25

Reserved

7:6

4:2

1:0

Reserved

R/W

0x00

Set bits to 00'b.

Set bits to 000'b.

Set bits to 00'b.

Set bits to 101'b.

Reserved

Yes

Reserved

CH A VOD 7:5

Control

Reserved

0xAD

4:2

VOD_CHA[2:0]

VOD Controls for CH A

(Default = 011'b)

000'b = 700 mV

001'b = 800 mV

010'b = 900 mV

011'b = 1000 mV

100'b = 1100 mV

101'b = 1200 mV

110'b = 1300 mV

1:0

Reserved

Set bits to 01'b.

0x28

Idle Control

Reserved

R/W

0x00

Override Fast Idle

Yes

5:4

en_high_idle_th

[1:0]

Enable high SD thresholds

[5]: CH A

[4]: CH B

3:2

1:0

en_fast_idle[1:0]

Reserved

Yes

Enable Fast IDLE

[3]: CH A

[2]: CH B

Set bits to 00'b.

www.ti.com

0x2D

CH B VOD

Control

R/W

0xAD

7:5

4:2

Reserved

Set bits to 101'b.

VOD_CHB[2:0]

Yes

VOD Controls for CH B

(Default = 011'b)

000'b = 700 mV

001'b = 800 mV

010'b = 900 mV

011'b = 1000 mV

100'b = 1100 mV

101'b = 1200 mV

110'b = 1300 mV

1:0

7:5

4:0

Reserved

Set bits to = 01'b

Read bits = 011'b

BR210 = 0 0110'b

0x51

Device

Information

Version[2:0]

Device ID[4:0]

0x66

www.ti.com

Typical DC Performance

Characteristics

The following data was collected at 25°C

100

3.3V Mode

2.5V Mode

700 800 900 1000 1100 1200 1300

OUTPUT VOLTAGE (mV)

30175393

FIGURE 8. Supply Current vs. Output Voltage Setting

VOD = 700 mV

Temp = 25°C

2.5V Mode

2.0

2.2

2.4

2.6

2.8

3.0

SUPPLY VOLTAGE (V)

30175394

FIGURE 9. Supply Current vs. Supply Voltage

1500

1400

1300

1200

1100

1000

900

800

700

600

500

VOD SETTING

30175395

FIGURE 10. Output Voltage vs. Output Voltage Setting

www.ti.com

Typical AC Performance Characteristics

NO MEDIA:

Device

Random Jitter (Rj)

Deterministic Jitter

(Dj)

Dj Component Breakdown Total Jitter (Tj @

1E-12)

DS100BR210 @

10.3125 Gbps

280 fs

9.8 ps

DDJ = 7.6 ps

DCD = 2.1 ps

DDPWS = 5.4 ps

PJ = 0.25 ps

13.7 ps

30175363

FIGURE 11. No Media; D3186 driving device directly

www.ti.com

The following lab setups were used to collect typical performance data on FR4 and Cable media.

30175371

FIGURE 12. Equalization Test Setup for FR4

EQUALIZATION RESULTS:

30175342

FIGURE 13. Equalization Performance with 10" of 4 mil FR4 using EQ settting 0x01

30175357

FIGURE 14. Equalization Performance with 30" of 4 mil FR4 using EQ settting 0x16

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30175372

FIGURE 15. Equalization Test Setup for Cables

CABLE TRANSMIT and RECEIVE RESULTS:

30175361

FIGURE 16. 8M 30AWG Cable Performance with 700mV Launch VOD and Rx EQ setting 0x0F

www.ti.com

30175370

FIGURE 17. De-Emphasis Test Setup

DE-EMPHASIS RESULTS:

30175339

FIGURE 18. De-Emphasis Performance with 5" of 4 mil FR4 using DE settting 0x01

30175338

FIGURE 19. 5" of 4 mil FR4 Without De-Emphasis

www.ti.com

30175341

FIGURE 20. De-Emphasis Performance with 10" of 4 mil FR4 using DE settting 0x02

30175340

FIGURE 21. 10" of 4 mil FR4 Without De-Emphasis

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Physical Dimensions inches (millimeters) unless otherwise noted

Order Number DS100BR210SQ (Tape and Reel 1000 units)

Order Number DS100BR210SQE (Tape and Reel 250 units)

NS Package Number SQA24A

(See AN-1187 for PCB Design and Assembly Recommendations)

www.ti.com

Notes

www.ti.com

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DS100BR210_14 [TI]

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