DS10CP152TMAX/NOPB [TI]
1.5Gbps 2x2 LVDS 交叉点开关 | D | 16 | -40 to 85;型号: | DS10CP152TMAX/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 1.5Gbps 2x2 LVDS 交叉点开关 | D | 16 | -40 to 85 开关 光电二极管 输出元件 |
文件: | 总17页 (文件大小:873K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS10CP152
www.ti.com
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
DS10CP152 1.5 Gbps 2X2 LVDS Crosspoint Switch
Check for Samples: DS10CP152
1
FEATURES
DESCRIPTION
The DS10CP152 is a 1.5 Gbps 2x2 LVDS crosspoint
switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board
backplanes and balanced cables. Fully differential
signal paths ensure exceptional signal integrity and
noise immunity. The non-blocking architecture allows
connections of any input to any output or outputs.
2
•
•
•
DC - 1.5 Gbps Low Jitter, Low Skew, Low
Power Operation
Pin Configurable, Fully Differential, Non-
Blocking Architecture
Wide Input Common Mode Voltage Range
Allows DC-Coupled Interface to LVDS, CML
and LVPECL Drivers
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower device return
losses, reduce component count and further minimize
board space.
•
On-chip 100Ω Input and Output Termination
Minimizes Insertion and Return Losses,
Reduces Component Count and Minimizes
Board Space
•
•
7 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small SOIC-16 Space Saving Package
APPLICATIONS
•
•
•
High-Speed Channel Select Applications
Clock and Data Buffering and Muxing
SD/HD SDI Routers
Typical Application
INPUT CARD
OUTPUT CARD
SD/HD
Reclocker +
Cable Driver
SD/HD
Adaptive Equalizer
BACKPLANES
DS10CP152
2 x 2 LVDS
DS10CP152
2 x 2 LVDS
Crosspoint Switch
Crosspoint Switch
SD/HD
Reclocker +
Cable Driver
SD/HD
Adaptive Equalizer
SD/HD
Reclocker +
Cable Driver
SD/HD
Adaptive Equalizer
DS10CP152
2 x 2 LVDS
DS10CP152
2 x 2 LVDS
Crosspoint Switch
Crosspoint Switch
SD/HD
Reclocker +
Cable Driver
SD/HD
Adaptive Equalizer
Large
(e.g. 128 x 128)
Crosspoint Switch
CROSSPOINT
CARD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS10CP152
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
SEL1 SEL0
EN0
IN0+
IN0-
OUT0+
OUT0-
EN1
2 x 2
IN1+
IN1-
OUT1+
OUT1-
Connection Diagram
DS10CP152 Pin Diagram
See Package Number D (R-PDSO-G16)
PIN DESCRIPTIONS
Pin
Number
Pin Name
I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-
3, 4,
6, 7
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
Inverting and non-inverting high speed LVDS output pins.
OUT0+, OUT0-,
OUT1+, OUT1-
14, 13,
11, 10
O, LVDS
SEL1, SEL0
EN0, EN1
NC
1, 2
16, 15
8, 9
5
I, LVCMOS
I, LVCMOS
NC
Switch configuration pins.
Output enable pins.
"NO CONNECT" pins.
Power supply pin.
Ground pin.
VDD
Power
GND
12
Power
2
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to +4V
1V
LVCMOS Input Voltage
LVDS Input Voltage
Differential Input Voltage |VID|
LVDS Output Voltage
LVDS Differential Output Voltage
LVDS Output Short Circuit Current Duration
Junction Temperature
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
−0.3V to (VCC + 0.3V)
0V to 1V
5 ms
+150°C
−65°C to +150°C
+260°C
Maximum Package Power Dissipation at 25°C
D Package
1.72W
Derate D Package
13.75 mW/°C above +25°C
Package Thermal Resistance
θJA
+72.7°C/W
+41.2°C/W
θJC
ESD Susceptibility
(3)
HBM
≥7 kV
≥250V
(4)
MM
(5)
CDM
≥1250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
1
Units
V
Supply Voltage (VCC
)
3.3
Receiver Differential Input Voltage (VID
)
V
Operating Free Air Temperature (TA)
−40
+25
+85
°C
Copyright © 2007–2013, Texas Instruments Incorporated
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
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DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
2.0
GND
40
VDD
0.8
V
V
VIN = 3.6V
VCC = 3.6V
175
±1
250
μA
IIL
Low Level Input Current
Input Clamp Voltage
VIN = GND
VCC = 3.6V
±10
μA
VCL
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
1
V
mV
mV
V
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
0
+100
−100
VCMR
0.05
VCC -
0.05
VIN = 3.6V or 0V
VCC = 3.6V or 0V
±1
±10
μA
IIN
Input Current
CIN
RIN
Input Capacitance
Any LVDS Input Pin to GND
Between IN+ and IN-
1.7
pF
Input Termination Resistor
100
Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
-35
350
1.2
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
1.05
-35
1.375
35
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
mV
(4)
IOS
Output Short Circuit Current
OUT to GND
-23
8
-55
55
mA
mA
pF
Ω
OUT to VCC
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
SUPPLY CURRENT
ICC
Supply Current
Outputs Powered Down Supply Current
EN0 = EN1 = H
EN0 = EN1 = L
58
25
70
30
mA
mA
ICCZ
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
4
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
tPHLD
tSKD1
tSKD2
tSKD3
Differential Propagation Delay Low to
High
440
400
40
650
650
120
60
ps
ps
ps
ps
ps
(3)
RL = 100Ω
Differential Propagation Delay High to
(3)
Low
Pulse Skew |tPLHD − tPHLD
|
(3) (4)
Channel to Channel Skew
25
(3)(5)
Part to Part Skew
45
190
(3)(6)
(3)
tLHT
tHLT
tON
Rise Time
170
170
5
350
350
20
ps
ps
μs
ns
ns
RL = 100Ω
(3)
Fall Time
Output Enable Time
Output Disable Time
tOFF
tSEL
3
12
Select Time
3
12
(3)
JITTER PERFORMANCE
tRJ1
tRJ2
VID = 350 mV
VCM = 1.2V
Clock (RZ)
135 MHz
0.5
0.5
0.5
0.5
9
1.2
1.2
1.2
1.2
38
ps
ps
311 MHz
503 MHz
750 MHz
270 Mbps
622 Mbps
1.06 Gbps
1.5 Gbps
270 Mbps
622 Mbps
1.06 Gbps
1.5 Gbps
(7)
Random Jitter (RMS Value)
tRJ3
tRJ4
tDJ1
tDJ2
tDJ3
tDJ4
tTJ1
tTJ2
tTJ3
tTJ4
ps
ps
VID = 350 mV
VCM = 1.2V
Clock (RZ)
ps
7
36
ps
Deterministic Jitter (Peak-to-Peak
Value )(8)
7
34
ps
9
35
ps
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.01
0.01
0.01
0.01
0.03
0.04
0.05
0.07
UIP-P
UIP-P
UIP-P
UIP-P
(9)
Total Jitter (Peak to Peak Value)
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(3) Specification is ensured by characterization and is not tested in production.
(4) tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(6) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
Copyright © 2007–2013, Texas Instruments Incorporated
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
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DC Test Circuits
V
OH
OUT+
OUT-
IN+
Power Supply
R
L
R
D
Power Supply
IN-
V
OL
Figure 1.
AC Test Circuits and Timing Diagrams
OUT+
OUT-
IN+
Signal Generator
R
L
R
D
IN-
Figure 2.
Figure 3.
Figure 4.
6
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Product Folder Links: DS10CP152
DS10CP152
www.ti.com
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The DS10CP152 is a 1.5 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board backplanes and balanced cables.
Table 1. Switch Configuration Truth Table
SEL1
SEL0
OUT1
IN0
OUT0
IN0
0
0
1
1
0
1
0
1
IN0
IN1
IN1
IN0
IN1
IN1
Table 2. Output Enable Truth Table
EN1
EN0
OUT1
OUT0
0
0
1
1
0
1
0
1
Disabled
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Input Interfacing
The DS10CP152 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS10CP152 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS10CP152 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS10CP152
Receiver
100W Differential T-Line
OUT+
OUT-
IN+
100W
IN-
Figure 5. Typical LVDS Driver DC-Coupled Interface to an DS10CP152 Input
CML3.3V or CML2.5V
Driver
V
CC
DS10CP152
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 6. Typical CML Driver DC-Coupled Interface to an DS10CP152 Input
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
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LVPECL
Driver
OUT+
LVDS
Receiver
100W Differential T-Line
IN+
IN-
100W
OUT-
150-250W
150-250W
Figure 7. Typical LVPECL Driver DC-Coupled Interface to an DS10CP152 Input
Output Interfacing
The DS10CP152 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
DS10CP152
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 8. Typical DS10CP152 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
8
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DS10CP152
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
Typical Performance Characteristics
Figure 9. A 270 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
Figure 10. A 622 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:500 ps / DIV
V:100 mV / DIV, H:200 ps / DIV
Figure 11. A 1.06 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
Figure 12. A 1.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
V:100 mV / DIV, H:100 ps / DIV
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS10CP152TMA/NOPB
DS10CP152TMAX/NOPB
ACTIVE
SOIC
SOIC
D
D
16
16
48
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
DS10CP152
TMA
ACTIVE
2500 RoHS & Green
SN
DS10CP152
TMA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS10CP152TMAX/NOPB SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
DS10CP152TMAX/NOPB
D
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS10CP152TMA/NOPB
D
16
48
495
8
4064
3.05
Pack Materials-Page 3
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SI9137LG
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SI9122E
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