DS10CP154ATSQ/NOPB [TI]
1.5Gbps 4x4 LVDS 交叉点开关 | RTA | 40 | -40 to 85;
| 型号： | DS10CP154ATSQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5Gbps 4x4 LVDS 交叉点开关 | RTA | 40 | -40 to 85 开关 输出元件 |
| 文件： | 总22页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS10CP154A
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SNLS306C –AUGUST 2008–REVISED APRIL 2013
DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint Switch
Check for Samples: DS10CP154A
1
FEATURES
DESCRIPTION
The DS10CP154A is
a 1.5 Gbps 4x4 LVDS
•
•
•
•
•
DC - 1.5 Gbps Low Jitter, Low Skew, Low
Power Operation
crosspoint switch optimized for high-speed signal
routing and switching over FR-4 printed circuit board
backplanes and balanced cables. Fully differential
signal paths ensure exceptional signal integrity and
noise immunity. The non-blocking architecture allows
connections of any input to any output or outputs.
The switch configuration can be accomplished via
external pins or the System Management Bus
(SMBus) interface. In addition, the SMBus circuitry
enables the loss of signal (LOS) monitors that can
inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
Pin and SMBus Configurable, Fully
Differential, Non-Blocking Architecture
Wide Input Common Mode Range Enables DC
Coupled Interface to CML or LVPECL Drivers
LOS Circuitry Detects Open Inputs Fault
Condition
On-chip 100 Ω Input and Output Termination
Minimizes Insertion and Return Losses,
Reduces Component Count and Minimizes
Board Space
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower return
losses, reduce component count and further minimize
board space.
•
•
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 6 mm x 6 mm WQFN-40 Space Saving
Package
APPLICATIONS
•
•
•
High-speed Channel Select Applications
Clock and Data Buffering and Muxing
SD / HD SDI Routers
Typical Application
INPUT CARD
OUTPUT CARD
SD / HD
Reclocker +
Cable Driver
SD / HD
Adaptive Equalizer
BACKPLANES
SD / HD
Reclocker +
Cable Driver
SD / HD
Adaptive Equalizer
DS10CP154
4x4 LVDS
DS10CP154
4x4 LVDS
Crosspoint Switch
Crosspoint Switch
SD / HD
SD / HD
Adaptive Equalizer
Reclocker +
Cable Driver
SD / HD
Reclocker +
Cable Driver
SD / HD
Adaptive Equalizer
DS10CP154
4x4 LVDS
Crosspoint Switch
CROSSPOINT
CARD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS10CP154A
SNLS306C –AUGUST 2008–REVISED APRIL 2013
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Block Diagram
S00 œ S31
8
IN0+
OUT0+
OUT0+
IN0-
IN1+
IN1-
OUT1+
OUT1-
4 X 4
IN2+
IN2-
OUT2+
OUT2-
IN3+
IN3-
OUT3+
OUT3-
System
Management Bus
PWDN
4
Connection Diagram
IN0+
1
2
30
29
28
27
26
25
24
23
22
21
VDD
IN0-
VDD
IN1+
IN1-
IN2+
IN2-
VDD
IN3+
IN3-
OUT0+
3
OUT0-
OUT1+
OUT1-
VDD
4
DAP
5
6
(GND)
7
OUT2+
OUT2-
OUT3+
OUT3-
8
9
10
Figure 1. WQFN Package
See Package Number RTA0040A
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PIN DESCRIPTIONS
Pin
Number
Pin Name
I/O, Type
I, LVDS
Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
EN_smb
17
I, LVCMOS
System Management Bus (SMBus) mode enable pin. The pin has an internal
20k pull down. When the pin is set to a [1], the device is in the SMBus mode.
All SMBus registers are reset when the pin is toggled.
S00/SCL,
S01/SDA
37,
36
I/O, LVCMOS
I/O, LVCMOS
I/O, LVCMOS
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the SMBus clock
input and data I/O pins respectively.
S10/ADDR0,
S11/ADDR1
35,
34
For EN_smb = [0], these pins select which LVDS input is routed to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the User-Set
SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
For EN_smb = [0], these pins select which LVDS input is routed to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the User-Set
SMBus Slave Address inputs.
S30, S31
PWDN
13, 14
38
For EN_smb = [0], these pins select which LVDS input is routed to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are non-functional
and should be tied to either logic [0] or [1].
I, LVCMOS
For EN_smb = [0], this is the power down pin. When the PWDN is set to a [0],
the device is in the power down mode. The SMBus circuitry can still be
accessed provided the EN_smb pin is set to a [1].
In the SMBus mode, the device is powered up by either setting the PWDN pin
to [1] OR by writing a [1] to the Control Register D[7] bit ( SoftPWDN). The
device will be powered down by setting the PWDN pin to [0] AND by writing a
[0] to the Control Register D[7] bit ( SoftPWDN).
NC
11, 12, 18,
19, 20, 31,
39, 40
No connect pins. May be left floating.
VDD
GND
3, 8,
15,25, 30
Power
Power supply pins.
16, DAP Power
Ground pin and pad (DAP - die attach pad).
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Absolute Maximum Ratings(1)(2)
Supply Voltage
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +4V
1.0V
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Voltage
Differential Input Voltage |VID|
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
0V to 1.0V
LVDS Differential Output Voltage
LVDS Output Short Circuit Current Duration
Junction Temperature
5 ms
+150°C
Storage Temperature Range
Lead Temperature Range
−65°C to +150°C
+260°C
Soldering (4 sec.)
Maximum Package Power Dissipation at
25°C
RTA0040A Package
4.65W
Derate RTA0040A Package
37.2 mW/°C above +25°C
+26.9°C/W
Package Thermal Resistance
θJA
θJC
+3.8°C/W
ESD Susceptibility
HBM(3)
MM(4)
CDM(5)
≥8 kV
≥250V
≥1250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
Units
V
Supply Voltage (VCC
)
3.3
Receiver Differential Input Voltage (VID
Operating Free Air Temperature (TA)
SMBus (SDA, SCL)
)
1.0
V
−40
+25
+85
3.6
°C
V
Electrical Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
LVCMOS DC SPECIFICATIONS
Test Conditions
Min
Typ
Max
Units
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
2.0
VDD
0.8
V
V
GND
VIN = 3.6V
VCC = 3.6V
0
175
0
±10
250
±10
−1.5
0.4
μA
μA
μA
V
EN_smb pin
40
IIL
Low Level Input Current
Input Clamp Voltage
VIN = GND, VCC = 3.6V
VCL
VOL
ICL = −18 mA, VCC = 0V
−0.9
Low Level Output Voltage
IOL= 4 mA
SDA pin
V
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
Typ
Max
Units
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
1
V
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
0
+100
mV
mV
−100
VCMR
VCC -
0.05
0.05
V
VIN = 3.6V or 0V
VCC = 3.6V or 0V
IIN
Input Current
±1
±10
μA
CIN
RIN
Input Capacitance
Any LVDS Input Pin to GND
Between IN+ and IN-
1.7
pF
Input Termination Resistor
100
Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
-35
350
1.2
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
1.05
-35
1.375
35
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
mV
IOS
Output Short Circuit Current(4)
OUT to GND
-25
7
-55
55
mA
mA
pF
Ω
OUT to VCC
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
SUPPLY CURRENT
ICC1
ICC2
ICC3
Supply Current
PWDN = 0
40
50
mA
mA
mA
Supply Current
Supply Current
PWDN = 1; Broadcast Mode (1:4)
PWDN = 1; Quad Buffer Mode (4:4)
103
115
125
140
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
AC Electrical Characteristics(1)(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
Typ
Max
Units
LVDS OUTPUT AC SPECIFICATIONS(3)
tPLHD
Differential Propagation Delay Low to
High
500
460
675
675
ps
ps
RL = 100Ω
tPHLD
Differential Propagation Delay High to
Low
(4)
tSKD1
tSKD2
tSKD3
tLHT
Pulse Skew |tPLHD − tPHLD
|
40
40
100
125
225
350
350
ps
ps
ps
ps
ps
Channel to Channel Skew(5)
Part to Part Skew(6)
Rise Time
50
145
145
RL = 100Ω
tHLT
Fall Time
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(3) Specification is ensured by characterization and is not tested in production.
(4) tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(6) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
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AC Electrical Characteristics(1)(2) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Power Up Time
Power Down Time
Test Conditions
Min
Typ
7
Max
Units
μs
tON
Time from PWDN = LH to OUTn active
20
25
tOFF
Time from PWDN = HL to OUTn
inactive
6
ns
tSEL
Select Time
Time from Sn = LH or HL to new signal
at OUTn
8
12
ns
JITTER PERFORMANCE(3)
tRJ1
VID = 350 mV
VCM = 1.2V
Clock (RZ)
135 MHz
311 MHz
503 MHz
750 MHz
270 Mbps
622 Mbps
1.06 Gbps
1.5 Gbps
270 mbps
622 Mbps
1.06Gbps
1.5 Gbps
1
0.5
2.0
1.2
ps
ps
tRJ2
tRJ3
tRJ4
tDJ1
tDJ2
tDJ3
tDJ4
tTJ1
tTJ2
tTJ3
tTJ4
Random Jitter
(RMS Value)(7)
0.5
1.0
ps
0.5
1.0
ps
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
7
30
ps
12
26
ps
Deterministic Jitter
(Peak to Peak Value)(8)
9
24
ps
12
28
ps
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.008
0.007
0.008
0.007
0.036
0.043
0.064
0.072
UIP-P
UIP-P
UIP-P
UIP-P
Total Jitter
(Peak to Peak Value)(9)
SMBus AC SPECIFICATIONS
fSMB SMBus Operating Frequency
tBUF
10
100
kHz
Bus free time between Stop and Start
Conditions
4.7
μs
tHD:SDA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0
μs
tSU:SDA
tSU:SDO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
Repeated Start Condition setup time.
Stop Condition setup time
Data hold time
4.7
4.0
300
250
25
μs
μs
ns
ns
ms
μs
μs
Data setup time
Detect clock low timeout
Clock low period
35
4.7
4.0
tHIGH
Clock high period
50
tPOR
Time in which a device must be
operational after power-on reset
500
ms
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DC Test Circuits
¼ DS10CP154
V
OH
IN+
IN-
OUT+
OUT-
Power Supply
Power Supply
R
L
R
D
V
OL
AC Test Circuits and Timing Diagrams
¼ DS10CP154
OUT+
OUT-
IN+
IN-
Signal Generator
R
L
R
D
FUNCTIONAL DESCRIPTION
The DS10CP154A is a 1.5 Gbps 4x4 LVDS digital crosspoint switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board backplanes and balanced cables. The DS10CP154A operates in
two modes: Pin Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with external pins. This is possible with two input select
pins per output (e.g. S00 and S01 pins for OUT0).
In the Pin Mode, feedback from the LOS (Loss Of Signal) monitor circuitry is not available (there is not an LOS
output pin).
When in the SMBus Mode, the full switch configuration and SoftPWDN can be programmed via the SMBus
interface. In addition, by using the SMBus interface, a user can obtain the feedback from the built-in LOS circuitry
which detects an open inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus clock (SCL) input and data (SDA) input pins
respectively; the S10, S11, S21 and S21 pins become the User-Set SMBus Slave Address input pins (ADDR0, 1,
2 and 3) while the S30 and S31 pins become non-functional (tieing these two pins to either H or L is
recommended if the device will function only in the SMBus mode).
In the SMBus Mode, the PWDN pin remains functional. How this pin functions in each mode is detailed in the
following sections.
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DS10CP154A OPERATION IN THE PIN MODE
Power Up
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In the Pin Mode, when the power is applied to the device power suppy pins, the DS10CP154A enters the Power
Up mode when the PWDN pin is set to logic H. When in the Power Down mode (PWDN pin is set to logic L), all
circuitry is shut down except the minimum required circuitry for the LOS and SMBus Slave operation.
Switch Configuration
In the Pin Mode, the DS10CP154A operates as a fully pin-configurable crosspoint switch. The following truth
tables illustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
Table 1. Input Select Pins Configuration for the Output OUT0
S01
0
S00
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
Table 2. Input Select Pins Configuration for the Output OUT1
S11
0
S10
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
Table 3. Input Select Pins Configuration for the Output OUT2
S21
0
S20
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
Table 4. Input Select Pins Configuration for the Output OUT3
S31
0
S30
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
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DS10CP154A OPERATION IN THE SMBUS MODE
The DS10CP154A operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to
a high (1). Under these conditions, the SCL pin is a clock input while the SDA pin is a serial data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS10CP154A has a 7-bit slave address. The three most significant
bits of the slave address are hard wired inside the DS10CP154A and are “101”. The four least significant bits of
the address are assigned to pins ADDR3-ADDR0 and are set by connecting these pins to GND for a low (0) or to
VCC for a high (1). The complete slave address is shown in the following table:
Table 5. DS10CP154A Slave Address
1
0
1
ADDR3
ADDR2
ADDR1
ADDR0
LSB
MSB
This slave address configuration allows up to sixteen DS10CP154A devices on a single SMBus bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition.
IDLE: If SCK and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if they
are high for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS10CP154A SMBus into the START condition, then a byte (8
bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify
NACK, after this the host holds the SCL line low, and waits for the receiver to raise the SDA line as an
ACKnowledge that the byte has been received.
Writing to a Register
To write a register, the following protocol is used (see SMBus 2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and communication with other SMBus devices may now
occur.
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Reading From a Register
To read a register, the following protocol is used (see SMBus 2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and communication with other SMBus devices may now
occur.
REGISTER DESCRIPTIONS
There are three data registers in the DS10CP154A accessible via the SMBus interface.
Table 6. DS10CP154A SMBus Data Registers
Address
(hex)
Name
Access
Description
0
3
4
Switch Configuration
R/W
R/W
RO
Switch Configuration Register
Control
LOS
Powerdown, LOS Enable and Pin Control Register
Loss Of Signal (LOS) Reporting Register
4
SCL
SDA
SMBus
Interface
EN_smb
Switch
Configuration
Register
LOS
Register
Control
Register
Switch Configuration Register
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch
Configuration Register mapping and associated truth table.
Bit
Default
Bit Name
Input Select 0
Access
R/W
Description
D[1:0]
D[3:2]
D[5:4]
D[7:6]
00
00
00
00
Selects which input is routed to the OUT0.
Selects which input is routed to the OUT1.
Selects which input is routed to the OUT2.
Selects which input is routed to the OUT3.
Input Select 1
Input Select 2
Input Select 3
R/W
R/W
R/W
10
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DS10CP154A
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SNLS306C –AUGUST 2008–REVISED APRIL 2013
Table 7. Switch Configuration Register Truth Table
D1
D0
0
Input Routed to the OUT0
0
0
1
1
IN0
IN1
IN2
IN3
1
0
1
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power
consumption based on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the
power down state).
Control Register
The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS
Circuitry Enable control via the SMBus. The following table shows the register mapping.
Bit
Default
1111
Bit Name
Access
Description
D[3:0]
PWDNn
R/W
Writing a [0] to the bit D[n] will power down the output
OUTn when either the PWDN pin OR the Control
Register bit D[7] (SoftPWDN) is set to a high [1].
D[4]
D[5]
D[6]
x
x
0
n/a
R/W
R/W
R/W
Undefined.
Undefined.
n/a
EN_LOS
Writing a [1] to the bit D[6] will enable the LOS circuitry
and receivers on all four inputs. The SmartPWDN
circuitry will not disable any of the inputs nor any
supporting LOS circuitry depending on the switch
configuration.
D[7]
0
SoftPWDN
R/W
Writing a [0] to the bit D[7] will place the device into
the power down mode. This pin is ORed together with
the PWDN pin.
Table 8. DS10CP154A Power Modes Truth Table
PWDN
SoftPWDN
PWDNn
DS25CP104 Power Mode
0
0
x
Power Down Mode. In this mode, all
circuitry is shut down except the minimum
required circuitry for the LOS and SMBus
Slave operation. The SMBus circuitry
allows enabling the LOS circuitry and
receivers on all inputs in this mode by
setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the
SmartPWDN circuitry will automatically
power down any unused I/O and logic
blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the
SmartPWDN circuitry indicates that that
particular output is needed for the
particular switch configuration and the
respective PWDNn bit has logic high [1].
An input will be enabled when the
SmartPWDN circuitry indicates that that
particular input is needed for the
particular switch configuration or the
EN_LOS bit is set to a [1].
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LOS Register
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the
register mapping.
Bit
Default
Bit Name
Access
Description
D[0]
0
0
0
0
LOS0
RO
Reading a [0] from the bit D[0] indicates an open inputs fault
condition on the IN0. A [1] indicates presence of a valid
signal.
D[1]
D[2]
LOS1
RO
RO
RO
RO
Reading a [0] from the bit D[1] indicates an open inputs fault
condition on the IN1. A [1] indicates presence of a valid
signal.
LOS2
Reading a [0] from the bit D[2] indicates an open inputs fault
condition on the IN2. A [1] indicates presence of a valid
signal.
D[3]
LOS3
Reading a [0] from the bit D[3] indicates an open inputs fault
condition on the IN3. A [1] indicates presence of a valid
signal.
D[7:4]
0000
Reserved
Reserved for future use. Returns undefined value when read.
INPUT INTERFACING
The DS10CP154A accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS10CP154A can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS10CP154A inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS10CP154
Receiver
100W Differential T-Line
OUT+
IN+
100W
IN-
OUT-
Figure 2. Typical LVDS Driver DC-Coupled Interface to DS10CP154A Input
CML3.3V or CML2.5V
Driver
V
CC
DS10CP154
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 3. Typical CML Driver DC-Coupled Interface to DS10CP154A Input
12
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SNLS306C –AUGUST 2008–REVISED APRIL 2013
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS10CP154A Input
OUTPUT INTERFACING
The DS10CP154A outputs signals that are compliant to the LVDS standard. Its outputs can be DC-coupled to
most common differential receivers. The following figure illustrates typical DC-coupled interface to common
differential receivers and assumes that the receivers have high impedance inputs. While most differential
receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to
check respective receiver's data sheet prior to implementing the suggested interface implementation.
DS10CP154
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 5. Typical DS10CP154A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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Product Folder Links: DS10CP154A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS10CP154ATSQ/NOPB
DS10CP154ATSQX/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
RTA
RTA
40
40
250
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
1CP154AS
1CP154AS
2500 RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS10CP154ATSQ/NOPB WQFN
RTA
RTA
40
40
250
178.0
330.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
DS10CP154ATSQX/
NOPB
WQFN
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS10CP154ATSQ/NOPB
DS10CP154ATSQX/NOPB
WQFN
WQFN
RTA
RTA
40
40
250
208.0
356.0
191.0
356.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RTA0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
0.5
0.3
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
(0.2) TYP
(0.1) TYP
4.6 0.1
EXPOSED
THERMAL PAD
20
11
36X 0.5
10
21
4X
4.5
SEE TERMINAL
DETAIL
1
30
0.3
40X
40
31
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
0.1
C A B
40X
0.05
4214989/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.6)
SYMM
40
31
40X (0.6)
40X (0.25)
1
30
36X (0.5)
SYMM
(5.8)
(0.74)
TYP
(
0.2) TYP
VIA
(1.31)
TYP
10
21
(R0.05) TYP
11
20
(0.74) TYP
(1.31 TYP)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214989/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.48) TYP
9X ( 1.28)
40
31
40X (0.6)
1
30
40X (0.25)
36X (0.5)
(1.48)
TYP
SYMM
(5.8)
METAL
TYP
10
21
(R0.05) TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4214989/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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