DS125BR800 [TI]
具有去加重功能的 2.5/5.0/8.0Gbps 8 通道 PCIe 转接驱动器;型号: | DS125BR800 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有去加重功能的 2.5/5.0/8.0Gbps 8 通道 PCIe 转接驱动器 PC 驱动 驱动器 |
文件: | 总59页 (文件大小:1260K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
DS125BR800 具有输入 CTLE 和输出去加重功能的低功耗 12.5Gbps 8 通
道中继器
1 特性
3 说明
1
•
广泛的产品系列,经实践检验的系统互操作性
DS125BR800 器件是一款超低功耗、高性能的多协议
中继器/转接驱动器,设计用于支持速率高达 12.5Gbps
的八通道 PCIe 3 代/2 代/1 代、10G-KR 以及其他高速
接口串行协议。接收器的连续时间线性均衡器 (CTLE)
可在 6.25GHz (12.5Gbps) 时为八个通道分别提供高达
+30dB 的增强功能,能够打开一个因码间干扰 (ISI)
(由 30in 以上电路板迹线或 8m 以上铜缆等互连介质
引起)而完全关闭的输入眼型状态,从而通过主机控制
器确保实现无错误端到端链接。发送器提供高达 -12dB
的去加重增强以及 700mV 至 1300mV 的输出电压幅
度控制,以便在互连通道内的实体布局方面实现最大限
度的灵活性。
–
–
–
–
–
DS125BR111:单通道中继器
DS125BR401:四通道中继器
DS125BR800:八通道中继器
DS125MB203:双端口 2:1/1:2 多路复用/开关
DS125DF410:具有 CDR 功能的四通道重定时
器
•
低功耗:每通道 65mW(典型值),可选择关闭不
使用的通道
•
•
支持 PCIe“非限制性”输出和 10G-KR 链路协商
高级信号调节 功能
–
频率为 6.25GHz 时,最高可支持 30dB 的接收
均衡功能
器件信息(1)
–
–
发送去加重功能高达 –12dB
器件型号
封装
封装尺寸(标称值)
发送输出电压控制:700mV 至 1300mV
DS125BR800
WQFN (54)
10.00mm x 5.50mm
•
可通过引脚选择、EEPROM 或 SMBus 接口进行编
程
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
•
•
•
单电源电压:2.5V 或 3.3V(可选)
工作温度范围为 -40°C 至 85°C
典型应用
3kV 人体放电模型 (HBM) 静电放电 (ESD) 额定电
压
8
TX
ASIC
or
PCIe EP
•
•
直通引脚分配:54 引脚超薄型四方扁平无引线
(WQFN) 封装(10mm × 5.5mm,0.5mm 间距)
Connector
8
RX
DS125BR800
支持的协议
–
sRIO,Infiniband,Interlaken,通用公共无线
接口 (CPRI),开放基站架构协议 (OBSAI)
8
RX
System Board
Root Complex
DS125BR800
Connector
–
其它私有接口高达 12.5Gbps
8
TX
2 应用
•
SAS/SATA(高达 6Gbps),光纤通道(高达
10GFC)
•
PCIe 1 代/2 代/3 代、10G-KR、10GbE、XAUI、
RXAUI
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNLS426
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 15
8.5 Programming........................................................... 15
8.6 Register Maps......................................................... 25
Application and Implementation ........................ 44
9.1 Application Information............................................ 44
9.2 Typical Application ................................................. 44
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
9
10 Power Supply Recommendations ..................... 48
10.1 3.3-V or 2.5-V Supply Mode Operation................. 48
10.2 Power Supply Bypassing ...................................... 49
11 Layout................................................................... 49
11.1 Layout Guidelines ................................................. 49
11.2 Layout Example .................................................... 50
12 器件和文档支持 ..................................................... 51
12.1 文档支持................................................................ 51
12.2 接收文档更新通知 ................................................. 51
12.3 商标....................................................................... 51
12.4 静电放电警告......................................................... 51
12.5 术语表 ................................................................... 51
13 机械、封装和可订购信息....................................... 51
7.6 Electrical Characteristics: Serial Management Bus
Interface .................................................................... 9
7.7 Timing Requirements................................................ 9
7.8 Typical Characteristics............................................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8
4 修订历史记录
Changes from Revision E (January 2015) to Revision F
Page
•
Changed 1/3 x VDD and 2/3 x VDD to 1/3 x VIN and 2/3 x VIN in the 3.3-V MODE column of the 4-Level Input Voltage
table ..................................................................................................................................................................................... 12
•
•
Changed VIN - 0.04 V to VDD - 0.04 V in the 2.5-V MODE column of the 4-Level Input Voltage table ............................... 12
添加了接收文档更新通知 部分.............................................................................................................................................. 51
Changes from Revision D (March 2013) to Revision E
Page
•
已添加引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、
布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 .................................................................................... 1
2
版权 © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
5 说明 (续)
在 10G-KR 和 PCIe 3 代模式下运行时,DS125BR800 允许主控制器和端点优化完整链路并协商发射均衡器系数。
这种链路协商协议的无缝管理可确保系统级互操作性和最小延迟。DS125BR800 拥有每通道 65mW(典型值)的
低功耗,可选择关闭不使用的通道,能够实现高效节能的系统设计。需要一个 3.3V 或 2.5V 单电源来为此器件供
电。
可通过引脚、软件(SMBus 或 I2C)轻松应用这些可编程设置,或者通过外部 EEPROM 加载这些设置。当运行在
EEPROM 模式下时,配置信息在加电时自动载入,这样就免除了对于外部微控制器或软件驱动程序的需要。
6 Pin Configuration and Functions
DS125BR800 NJY Package
54-Pin WQFN
Top View
SMBUS AND CONTROL
45
44
43
42
41
40
39
38
OUTB_0+
OUTB_0-
OUTB_1+
OUTB_1-
VDD
INB_0+
INB_0-
INB_1+
INB_1-
1
2
3
4
INB_2+
INB_2-
INB_3+
INB_3-
5
6
7
8
OUTB_2+
OUTB_2-
OUTB_3+
9
DAP = GND
OUTB_3-
VDD
VDD
37
36
35
34
33
32
31
10
11
12
13
14
15
16
17
INA_0+
INA_0-
INA_1+
OUTA_0+
OUTA_0-
OUTA_1+
OUTA_1-
OUTA_2+
OUTA_2-
OUTA_3+
OUTA_3-
INA_1-
VDD
INA_2+
INA_2-
30
29
28
INA_3+
INA_3-
18
Copyright © 2012–2018, Texas Instruments Incorporated
3
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Pin Functions(1)
PIN
TYPE
DESCRIPTION
NAME
NO.
DIFFERENTIAL HIGH SPEED I/O'S
INA_0+, INA_0-, INA_1+,
INA_1-, INA_2+, INA_2-
,INA_3+, INA_3-
I
Inverting and noninverting CML differential inputs to the equalizer. On-
chip, 50-Ω termination resistor connects INA_n+ to VDD and INA_n- to
VDD when enabled.
10, 11, 12, 13,
15, 16, 17, 18
AC coupling required on high-speed I/O
INB_0+, INB_0-, INB_1+,
INB_1-, INB_2+, INB_2-
,INB_3+, INB_3-,
I
Inverting and noninverting CML differential inputs to the equalizer. On-
chip, 50-Ω termination resistor connects INB_n+ to VDD and INB_n- to
VDD when enabled.
1, 2, 3, 4,
5, 6, 7, 8,
AC coupling required on high-speed I/O
OUTA_0+, OUTA_0-,
OUTA_1+, OUTA_1-,
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
O
O
Inverting and noninverting 50-Ω driver outputs with de-emphasis.
Compatible with AC-coupled CML inputs.
AC coupling required on high-speed I/O
35, 34, 33, 32,
31, 30, 29, 28
OUTB_0+, OUTB_0-,
OUTB_1+, OUTB_1-,
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-,
Inverting and noninverting 50-Ω driver outputs with de-emphasis.
Compatible with AC-coupled CML inputs.
AC coupling required on high-speed I/O
45, 44, 43, 42,
40, 39, 38, 37
CONTROL PINS — SHARED (LVCMOS)
ENSMB
I, 4-LEVEL,
LVCMOS
System Management Bus (SMBus) Enable pin
Tie 1 kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1 kΩ to GND = Pin Mode
48
ENSMB = 1 (SMBUS MODE)
AD0-AD3
I, 4-LEVEL,
LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
54, 53, 47, 46
There are 16 addresses supported by these pins. Pins must be tied LOW
or HIGH when used to define the device SMBus address.
READ_EN
26
I, 2-LEVEL,
LVCMOS
When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
SCL
I, 2-LEVEL,
LVCMOS,
Clock output when loading EEPROM configuration, reverting to SMBus
clock input when EEPROM load is complete (ALL_DONE = 0). External
50
O, OPEN Drain 2-kΩ to 5-kΩ pullup resistor to VDD (2.5-V Mode) or VIN (3.3-V Mode)
recommended as per SMBus interface standards.
SDA
I, 2-LEVEL,
LVCMOS,
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
open-drain output. External 2-kΩ to 5-kΩ pullup resistor to VDD (2.5-V
49
O, OPEN Drain Mode) or VIN (3.3-V Mode) recommended as per SMBus interface
standards.
ENSMB = 0 (PIN MODE)
DEMA0, DEMA1,
DEMB0, DEMB1
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver. The pins are only active when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
DEMA[1:0] pins and bank B is controlled with the DEMB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA
and DEMB[1:0] pins are converted to AD0, AD1 inputs.
49, 50,
53, 54
See Table 3.
EQA0, EQA1,
EQB0, EQB1
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.
The pins are active only when ENSMB is deasserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3
inputs. See Table 2.
20, 19,
46, 47
(1) LVCMOS inputs without the FLOAT conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V Mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
For 2.5-V Mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.
4
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Pin Functions(1) (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
MODE
SD_TH
MODE control pin selects operating modes.
Tie 1 kΩ to GND = PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6
Gbps)
FLOAT = AUTO Rate Select (for PCIe)
Tie 20 kΩ to GND = PCIe Gen-3 without De-emphasis
Tie 1 kΩ to VDD = PCIe Gen-3 with De-emphasis
See Table 6
I, 4-LEVEL,
LVCMOS
21
Controls the internal Signal Detect Threshold.
I, 4-LEVEL,
LVCMOS
For data rates above 8 Gbps the Signal Detect function should be
disabled to avoid potential for intermittent data loss. See Table 5 for
additional information.
26
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
PWDN
Tie High = Low power - power down
52
I, LVCMOS
I, FLOAT
Tie GND = Normal Operation
See Table 4.
RESERVED
RXDET
23
22
Float (leave pin open) = Normal Operation
The RXDET pin controls the receiver detect function. Depending on the
input level, a 50 Ω or >50-kΩ termination to the power rail is enabled.
See Table 4.
I, 4-LEVEL,
LVCMOS
VDD_SEL
Controls the internal regulator
FLOAT = 2.5-V mode
Tie GND = 3.3-V mode
25
27
I, LVCMOS
O, LVCMOS
OUTPUTS
ALL_DONE
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
POWER
GND
DAP
Power
Power
Ground pad (DAP - die attach pad)
VDD
Power supply pins CML/analog
2.5-V Mode, connect to 2.5-V supply
3.3-V mode, connect 0.1-µF cap to each VDD pin
See Power Supply Recommendations for proper power supply
decoupling.
9, 14, 36, 41, 51
VIN
In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating
24
Power
Copyright © 2012–2018, Texas Instruments Incorporated
5
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)(2)(3)
MIN
–0.5
–0.5
–0.5
–0.5
–30
MAX
UNIT
V
Supply voltage (VDD - 2.5-V mode)
Supply voltage (VIN - 3.3-V mode)
LVCMOS Input/Output Voltage
CML input voltage
2.75
4
4
V
V
VDD + 0.5
30
V
CML input current
mA
°C
°C
°C
Junction temperature
125
Lead temperature soldering (4 sec.)
Storage temperature, Tstg
260
–40
125
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are specified for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
(2) For soldering specifications: see product folder at Absolute Maximum Ratings for Soldering (SNOA549).
(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
7.2 ESD Ratings
VALUE
±3000
±1000
±200
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Machine model, STD - JESD22-A115-A
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
2.375
3
TYP
2.5
3.3
25
MAX
2.625
3.6
UNIT
Supply voltage (2.5-V mode)
Supply voltage (3.3-V mode)
Ambient temperature
V
V
–40
85
°C
SMBus (SDA, SCL)
3.6
V
Supply noise up to 50 MHz(1)
100
mVp-p
(1) Allowed supply noise (mVp-p sine wave) under typical conditions.
7.4 Thermal Information
DS125BR800
THERMAL METRIC(1)
NJY (WQFN)
54 PINS
26.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
10.8
4.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
4.3
RθJC(bot)
1.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
7.5 Electrical Characteristics(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
POWER
Power Dissipation
VDD = 2.5-V supply,
EQ Enabled,
500 700 mW
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0
PD
VIN = 3.3-V supply,
EQ Enabled,
660 900 mW
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0
LVCMOS / LVTTL DC SPECIFICATIONS
VIH25
VIH33
VIL
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
2.5 V-Mode
3.3 V-Mode
2
2
0
2
VDD
VIN
0.8
V
V
V
V
High Level Output Voltage
(ALL_DONE pin)
Ioh= –4 mA
VOH
VOL
Low Level Output Voltage
(ALL_DONE pin)
Iol= 4 mA
0.4
V
Input High Current (PWDN pin)
VIN = 3.6 V, LVCMOS = 3.6 V
–15
20
15
µA
µA
IIH
Input High Current with internal
resistors (4-level input pin)
150
Input Low Current (PWDN pin)
VIN = 3.6 V, LVCMOS = 0 V
–15
15
µA
µA
IIL
Input Low Current with internal
resistors (4-level input pin)
–160
–40
CML RECEIVER INPUTS (IN_n+, IN_n-)
RX Differential return loss
RLRX-DIFF
0.05 - 7.5 GHz
–15
-5
dB
dB
dB
Ω
7.5 - 15 GHz
RLRX-CM
ZRX-DC
RX Common mode return loss
0.05 - 5 GHz
–10
50
RX DC common mode impedance
RX DC differential mode impedance
Tested at VDD = 2.5 V
Tested at VDD = 2.5 V
Tested at pins
40
60
ZRX-DIFF-DC
80 100 120
1.2
Ω
Differential RX peak to peak voltage
(VID)
V
VRX-DIFF-DC
VRX-SIGNAL-DET- Signal detect assert level for active
SD_TH = float,
0101 pattern at 8 Gbps
180
110
mVp-p
mVp-p
data signal
DIFF-PP
VRX-IDLE-DET-
DIFF-PP
Signal detect de-assert level for
electrical idle
SD_TH = float,
0101 pattern at 8 Gbps
HIGH SPEED OUTPUTS
Output Voltage Differential Swing
Differential measurement with OUT_n+ and OUT_n-,
terminated by 50 Ω to GND,
0.8
1
1.2 Vp-p
VTX-DIFF-PP
AC-Coupled, VID = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0(4)
TX de-emphasis ratio
VOD = 1.0 Vp-p,
–3.5
dB
VTX-DE-
DEM0 = 0, DEM1 = R
PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6
Gbps)
RATIO_3.5
(1) Typical values represent most likely parametric norms at VDD = 2.5 V, TA = 25°C., and at the Recommended Operating Conditions at
the time of product characterization and are not guaranteed.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(3) Specified by device characterization.
(4) In PCIe Gen-3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The
output VOD level set by DEMA/B[1:0] in this MODE is dependent on the VID level and the frequency content. The DS125BR800
repeater is designed to be non-limiting in this MODE, so the TX-FIR (de-emphasis) is passed to the RX to support the handshake
negotiation link training.
Copyright © 2012–2018, Texas Instruments Incorporated
7
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Electrical Characteristics(1)(2)(3) (continued)
PARAMETER
TEST CONDITIONS
VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R
MIN TYP MAX UNIT
TX de-emphasis ratio
-6
dB
VTX-DE-RATIO_6
PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6
Gbps)
Deterministic Jitter
Random Jitter
VID = 800 mV, PRBS15 pattern, 8.0 Gbps, VOD =
1.0 V, EQ = 0x00, DE = 0 dB, (no input or output
trace loss)
0.05
0.3
UIpp
TTX-DJ
VID = 800 mV, 0101 pattern, 8.0 Gbps, VOD = 1.0
V, EQ = 0x00, DE = 0 dB, (no input or output trace
loss)
ps
RMS
TTX-RJ
TTX-RISE-FALL
TRF-MISMATCH
TX rise/fall time
20% to 80% of differential output voltage
20% to 80% of differential output voltage
0.05 - 7.5 GHz
35
45
0.01
–15
–5
ps
UI
dB
dB
dB
Ω
TX rise/fall mismatch
TX Differential return loss
0.1
RLTX-DIFF
7.5 - 15 GHz
RLTX-CM
TX Common mode return loss
DC differential TX impedance
TX AC common mode voltage
0.05 - 5 GHz
–10
100
ZTX-DIFF-DC
VOD = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0
100 mVp-p
VTX-CM-AC-PP
TX short circuit current limit
Total current the transmitter can supply when
shorted to VDD or GND
20
mA
ITX-SHORT
VTX-CM-DC-
ACTIVE-IDLE-
DELTA
Absolute delta of DC common mode
voltage during L0 and electrical idle
100 mV
VTX-CM-DC-LINE- Absolute delta of DC common mode
25 mV
voltgae between TX+ and TX-
DELTA
Max time to transition to differential
TTX-IDLE-DATA
VID = 1.0 Vp-p, 8 Gbps
VID = 1.0 Vp-p, 8 Gbps
3.5
6.2
ns
ns
DATA signal after IDLE
Max time to transition to IDLE after
TTX-DATA-IDLE
differential DATA signal
TPLHD/PHLD
TLSK
Differential Propagation Delay
Lane to lane skew
EQ = 00(5)
200
25
ps
ps
ps
T = 25°C, VDD = 2.5 V
T = 25°C, VDD = 2.5 V
TPPSK
Part to part propagation delay skew
40
EQUALIZATION
DJE1
Residual deterministic jitter at 12 Gbps 30in 5mils FR4, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB
0.18
0.11
0.07
0.25
0.33
UIpp
UIpp
UIpp
UIpp
UIpp
DJE2
DJE3
DJE4
DJE5
Residual deterministic jitter at 8 Gbps 30in 5mils FR4, VID = 0.6 Vp-p,
PRBS15,EQ = 0x07, DEM = 0 dB
Residual deterministic jitter at 5 Gbps 30in 5mils FR4, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB
Residual deterministic jitter at 12 Gbps 5m 30 awg cable, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB
Residual deterministic jitter at 5 Gbps 8m 30 awg cable, VID = 0.6 Vp-p,
PRBS15, EQ = 0x0F, DEM = 0 dB
DE-EMPHASIS — PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps)
DJD1
Residual deterministic jitter at 12 Gbps Input Channel: 20in 5mils FR4,
Output Channel: 10in 5mils FR4
VID = 0.6 Vp-p,
0.1
UIpp
PRBS15, EQ = 0x03,
VOD = 1.0 Vp-p, DEM = –3.5 dB
(5) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the longest propagation
delays.
8
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7.6 Electrical Characteristics: Serial Management Bus Interface
over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
0.8
3.6
V
V
VIH
2.1
4
IPULLUP
Current Through Pull-Up Resistor or
Current Source
High Power Specification
mA
VDD
Nominal Bus Voltage
2.375
–200
3.6
V
µA
µA
pF
Ω
(1)
ILEAK-Bus Input Leakage Per Bus Segment
ILEAK-Pin Input Leakage Per Device Pin
200
–15
(1) (2)
CI
Capacitance for SDA and SCL
10
RTERM
External Termination Resistance pull to
VDD = 2.5 V ± 5% or 3.3 V ± 10%
Pullup VDD = 3.3 V(1) (2) (3)
Pullup VDD = 2.5 V(1) (2) (3)
2000
1000
Ω
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400 pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
7.7 Timing Requirements
MIN
TYP
MAX UNIT
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
ENSMB = VDD (Slave Mode)
400 kHz
520 kHz
µs
FSMB
Bus Operating Frequency(1)
ENSMB = FLOAT (Master Mode)
280
1.3
400
TBUF
Bus Free Time Between Stop and Start Condition
Hold time after (Repeated) Start Condition. After this At IPULLUP, Max
period, the first clock is generated.
THD:STA
0.6
µs
TSU:STA Repeated Start Condition Setup Time
TSU:STO Stop Condition Setup Time
THD:DAT Data Hold Time
0.6
0.6
µs
µs
ns
ns
µs
0
TSU:DAT Data Setup Time
100
TLOW
THIGH
tF
Clock Low Period
1.3
(2)0.6
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
50
300
300
µs
ns
ns
(2)
(2)
tR
Time in which a device must be operational after
power-on reset
(2) (3)
tPOR
500
ms
(1) In Master Mode, a serial EEPROM with a minimum rating of 520 KHz is required.
(2) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(3) Specified by Design. Parameter not tested in production.
80%
80%
0V
20%
VOD = [Out+ - Out-]
20%
t
t
RISE
FALL
Figure 1. CML Output and Rise and FALL Transition Time
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+
IN
0V
-
t
t
PHLD
PLHD
+
OUT
0V
-
Figure 2. Propagation Delay Timing Diagram
+
0V
IN
DATA
-
t
t
IDLE-DATA
DATA-IDLE
DATA
+
0V
OUT
-
IDLE
IDLE
Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time
t
LOW
t
R
t
HIGH
SCL
SDA
t
t
t
t
SU:STA
F
HD:STA
HD:DAT
t
t
BUF
SU:STO
t
SU:DAT
ST
SP
SP
ST
Figure 4. SMBus Timing Parameters
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7.8 Typical Characteristics
640.0
1021
1019
1016
1013
1010
1007
VDD = 2.625V
620.0
T = 25°C
VDD = 2.5V
600.0
VDD = 2.375V
580.0
560.0
540.0
520.0
500.0
480.0
460.0
440.0
420.0
T = 25oC
2.375
2.5
2.625
0.8
0.9
1
1.1
1.2
1.3
VOD (Vp-p)
VDD (V)
Figure 5. Power Dissipation (PD) vs
Output Differential Voltage (VOD)
Figure 6. Output Differential Voltage (VOD = 1.0 Vp-p) vs
Supply Voltage (VDD)
1020
1018
1016
1014
V
DD
= 2.5 V
1012
-40
-15
10
TEMPERATURE (°C)
Figure 7. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Temperature
35
60
85
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8 Detailed Description
8.1 Overview
The DS125BR800 compensates for lossy printed-circuit board backplanes and balanced cables.
The DS125BR800 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and
SMBus Master Mode (ENSMB = float) to load register information from external EEPROM. Refer to SMBUS
Master Mode for more information.
8.2 Functional Block Diagram
VOD/DeEMPHASIS
VDD
CONTROL
DEMA/B
RATE
DET
Auto/Manual
RXDET
SMBus
EQ
INx_n+
INx_n-
OUTBUF
OUTx_n+
OUTx_n-
TX Idle Enable
IDLE
DET
EQA/B
SMBus
SMBus
Figure 8. Block Diagram - Detail View of Channel (1 of 8)
8.3 Feature Description
8.3.1 4-Level Input Configuration Guidelines
The 4-level input pins use a resistor divider to help set the 4 valid levels and provide a wider range of control
settings when ENSMB=0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the package pin.
These resistors, together with the external resistor connection combine to achieve the desired voltage level.
Using the 1-kΩ pullup, 1-kΩ pulldown, no connect, and 20-kΩ pulldown provide the optimal voltage levels for
each of the four input states.
Table 1. 4-Level Input Voltage
LEVEL
SETTING
3.3-V MODE
0.10 V
2.5-V MODE
0.08 V
0
R
Tie 1 kΩ to GND
Tie 20 kΩ to GND
Float (leave pin open)
Tie 1 kΩ to VDD
1/3 x VIN
1/3 x VDD
2/3 x VDD
VDD - 0.04 V
Float
1
2/3 x VIN
VIN - 0.05 V
•
•
•
Level 1 - 2 = 0.2 × VIN or VDD
Level 2 - 3 = 0.5 × VIN or VDD
Level 3 - 4 = 0.8 × VIN or VDD
To minimize the startup current associated with the integrated 2.5-V regulator the 1-kΩ pullup and pulldown
resistors are recommended. If several 4-level inputs require the same setting, it is possible to combine two or
more 1-kΩ resistors into a single lower value resistor. For example, combining two inputs with a single 500-Ω
resistor is a good way to save board space.
12
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8.3.2 PCIe Signal Integrity
When using the DS125BR800 in PCIe Gen-3 systems, there are specific signal integrity settings to ensure signal
integrity margin. The settings were achieved with completing extensive testing. Contact your field representative
for more information regarding the testing completed to achieve these settings.
For tuning the in the downstream direction (from CPU to EP).
•
•
•
EQ: use the guidelines outlined in Table 2.
De-Emphasis: use the guidelines outlined in Table 3.
VOD: use the guidelines outlined in Table 3.
For tuning in the upstream direction (from EP to CPU).
•
•
EQ: use the guidelines outlined in Table 2.
De-Emphasis:
–
–
For trace lengths < 15" set to -3.5 dB
For trace lengths > 15" set to -6 dB
•
VOD: set to 900 mV
Table 2. Equalizer Settings
EQA1
EQB1
EQA0
EQB
dB at
1.5 GHz
dB at
2.5 GHz
dB at
4 GHz
dB at
6 GHz
Suggested Use(1)
Level
EQ – 8 bits [7:0]
1
2
0
0
0000 0000 = 0x00
0000 0001 = 0x01
0000 0010 = 0x02
0000 0011 = 0x03
0000 0111 = 0x07
0001 0101 = 0x15
0000 1011 = 0x0B
0000 1111 = 0x0F
0101 0101 = 0x55
0001 1111 = 0x1F
0010 1111 = 0x2F
0011 1111 = 0x3F
1010 1010 = 0xAA
0111 1111 = 0x7F
1011 1111 = 0xBF
1111 1111 = 0xFF
2.5
3.8
3.5
5.4
3.8
6.7
3.1
6.7
FR4 < 5 inch trace
FR4 5-10 inch trace
FR4 10 inch trace
FR4 15-20 inch trace
FR4 20-30 inch trace
FR4 25-30 inch trace
FR4 25-30 inch trace
8m, 30awg cable
0
0
R
3
Float
5.0
7.0
8.4
8.4
4
0
1
5.9
8.0
9.3
9.1
5
R
0
R
7.4
10.3
10.2
12.4
13.8
12.6
16.2
18.3
19.8
20.5
22.2
24.4
25.8
12.8
13.9
15.3
16.7
17.5
20.3
22.8
24.2
26.4
27.8
30.2
31.6
13.7
16.2
15.9
17.0
20.7
21.8
23.6
24.7
28.0
29.2
30.9
31.9
6
R
6.9
7
R
Float
1
9.0
8
R
10.2
8.5
9
Float
Float
Float
Float
1
0
> 8m cable
10
11
12
13
14
15
16
R
11.7
13.2
14.4
14.4
16.0
17.6
18.7
Float
1
0
1
R
1
Float
1
1
(1) Cable and FR4 lengths are for reference only. FR4 lengths based on a 100 Ω differential stripline with 5-mil traces and 8-mil trace
separation. Optimal EQ setting should be determined via simulation and prototype verification.
Table 3. Output Voltage and De-Emphasis Settings
DEMA1
DEMB1
DEMA0
DEMB0
Inner Amplitude
Vp-p
Level
VOD Vp-p
DEM dB(1)
Suggested Use(2)
1
2
3
4
5
6
7
0
0
0
R
0.8
0.9
0.9
1.0
1.0
1.0
1.1
0
0
0.8
0.9
0.6
1.0
0.7
0.5
1.1
FR4 < 5 inch 4–mil trace
FR4 < 5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 < 5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 < 5 inch 4–mil trace
0
Float
1
- 3.5
0
0
R
R
R
0
- 3.5
- 6
0
R
Float
(1) The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are available in PCIe Gen-3 modes when MODE = 1 (tied to VIN)
(2) FR4 lengths are for reference only. FR4 lengths based on a 100 Ω differential stripline with 5-mil traces and 8-mil trace separation.
Optimal DEM settings should be determined via simulation and prototype verification.
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Table 3. Output Voltage and De-Emphasis Settings (continued)
DEMA1
DEMB1
DEMA0
DEMB0
Inner Amplitude
Vp-p
Level
VOD Vp-p
DEM dB(1)
Suggested Use(2)
8
R
Float
Float
Float
Float
1
1
0
1.1
1.1
1.2
1.2
1.2
1.3
1.3
1.3
1.3
- 3.5
- 6
0.7
0.6
1.2
0.8
0.6
1.3
0.9
0.7
0.5
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 < 5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 < 5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 20 inch 4–mil trace
9
10
11
12
13
14
15
16
R
0
Float
1
- 3.5
- 6
0
0
1
R
- 3.5
- 6
1
Float
1
1
- 9
Table 4. RX-Detect Settings
PWDN
(PIN 52)
RXDET
(PIN 22)
SMBus REG
bit [3:2]
Recommeded
Input Termination
Comments
Use
0
0
0
00
Hi-Z
X
Manual RX-Detect, input is high impedance mode
Tie 20 kΩ
to GND
01
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe Only
Auto RX-Detect, outputs test every 12 msec for 600
msec then stops; termination is Hi-Z until detection;
once detected input termination is 50 Ω.
Reset function by pulsing PWDN high for 5 µsec then
low again
0
Float
(Default)
10
11
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe Only
Auto RX-Detect, outputs test every 12 msec until
detection occurs; termination is Hi-Z until RX detection;
once detected input termination is 50 Ω.
0
1
1
50 Ω
All Others
X
Manual RX-Detect, input is 50 Ω.
X
High Impedance
Power down mode, input is Hi-Z, output drivers are
disabled.
Used to reset RX-Detect State Machine when held high
for 5 µsec.
8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
Unlike PCIe systems, SAS/SATA (up to 6 Gbps) systems use a low speed Out-Of-Band or OOB communications
sequence to detect and communicate between Controllers/Expanders and target drives. This communication
eliminates the need to detect for endpoints like PCIe. For SAS/SATA systems, it is recommended to tie the
RXDET pin high. This will ensure any OOB sequences sent from the Controller/Expander will reach the target
drive without any additional latency due to the termination detection sequence defined by PCIe.
Table 5. Signal Detect Threshold Level(1)
SMBus REG Bit
[3:2] and [1:0]
SD_TH
(PIN 26)
Assert Level (typ)
De-assert Level (typ)
0
10
01
00
11
210 mVp-p
160 mVp-p
180 mVp-p
190 mVp-p
150 mVp-p
100 mVp-p
110 mVp-p
130 mVp-p
R
F (default)
1
(1) VDD = 2.5 V, 25°C and 0101 pattern at 8 Gbps
8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
Signal detect bandwidth limitations combined with high levels of signal attenuation can result in intermittent data
loss above 8 Gbps. This data loss can be eliminated by disabling automatic detection and forcing the Signal
Detect function to be always "on". This programming requires SMBus control over the DS125BR800 to be
present. The Signal Detect function is controlled for each channel independently. The register programming
sequence is shown below:
1. Write register 0x06 = 0x18 //* Enable SMBus register programming
14
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2. Write registers 0x0D[1]= 1'b, 0x14[1] = 1'b, 0x1B[1] = 1'b, 0x22[1] = 1'b //* CH0 - CH3
3. Write registers 0x2A[1]= 1'b, 0x31[1] = 1'b, 0x38[1] = 1'b, 0x3F[1] = 1'b //* CH4 - CH7
Table 6. MODE Operation With Pin Control
MODE
(PIN 21)
SAS
SATA
CPRI
OBSAI
SRIO
(R)XAUI
Interlaken
Infiniband
Driver Characteristics
PCIe
10G-KR
10GbE
0
Limiting
X
X
X
X
X
R
F (default)
1
Transparent without DE
Automatic
X
Transparent with DE
X
NOTE: Automatic operation allows input to sense the incoming data-rate and utilize a "Transparent" output driver
for operation at or above 8 Gbps.
NOTE: SAS/SATA up to 6 Gbps.
8.3.2.2 MODE Operation with SMBus Registers
When in SMBus mode (Slave or Master), the MODE pin retains control of the output driver characteristics. In
order to override this control function, Register 0x08[2] must be written with a "1". Writing this bit enables MODE
control of each channel individually using the channel registers defined in Table 10.
8.4 Device Functional Modes
8.4.1 Pin Control Mode
When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side
independently. When de-emphasis is asserted VOD is automatically adjusted per Table 3. For PCIe applications,
the RXDET pins provides automatic and manual control for input termination (50 Ω or >50 kΩ). MODE setting is
also pin controllable with pin selections (PCIe Gen-1, PCIe Gen-2, auto detect, and PCIe Gen-3). The receiver
electrical idle detect threshold is also adjustable via the SD_TH pin.
8.4.2 SMBus Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx
and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (MODE,
RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit
is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is
driven low all registers are reset to their default state. If PWDN is asserted while ENSMB is high, the registers
retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most high speed
applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed
via the SMBus registers. Each input has a total of 256 possible equalization settings. 4-Level Input Configuration
Guidelines shows the 16 setting when the device is in pin mode. When using SMBus mode, the equalization,
VOD and de-Emphasis levels are set by registers.
8.5 Programming
8.5.1 SMBus Master Mode
The DS125BR800 devices support reading directly from an external EEPROM device by implementing SMBus
Master mode. When using the SMBus master mode, the DS125BR800 will read directly from specific location in
the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these
specific guidelines. For additional information, refer to SNLA228.
•
•
Set ENSMB = Float — enable the SMBUS master mode.
The external EEPROM device address byte must be 0xA0 and capable of 520 kHz operation at 2.5 V and 3.3
V supply.
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Programming (continued)
•
Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.
When tying multiple DS125BR800 devices to the SDA and SCL bus, use these guidelines to configure the
devices.
•
Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM.
Example below is for 4 device.
–
–
–
–
U1: AD[3:0] = 0000 = 0xB0,
U2: AD[3:0] = 0001 = 0xB2,
U3: AD[3:0] = 0010 = 0xB4,
U4: AD[3:0] = 0011 = 0xB6
•
•
Use a pull-up resistor on SDA and SCL; value = 2 kΩ
Daisy-chain READ_EN (pin 26) and ALL_DONE (pin 27) from one device to the next device in the sequence
so that they do not compete for the EEPROM at the same time.
1. Tie READ_EN of the 1st device in the chain (U1) to GND
2. Tie ALL_DONE of U1 to READ_EN of U2
3. Tie ALL_DONE of U2 to READ_EN of U3
4. Tie ALL_DONE of U3 to READ_EN of U4
5. Optional: Tie ALL_DONE output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS125BR800 device. The first 3
bytes of the EEPROM always contain a header common and necessary to control initialization of all devices
connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed
pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a
MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the
MAP bit is not present the configuration data start address is derived from the DS125BR800 address and the
configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the
EEPROM. There are 37 bytes of data size for each DS125BR800 device. For additional information on EEPROM
programming, refer to SNLA228.
spacer
:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
NOTE
The maximum EEPROM size supported is 8-kbits (1024 x 8 bits).
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Table 7. EEPROM Register Map - Single Device with Default Value
EEPROM Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
BIt 0
Description
0x00
CRC EN
Address Map
Present
EEPROM > 256
Bytes
DEVICE COUNT[3] DEVICE COUNT[2] DEVICE COUNT[1] DEVICE COUNT[0]
Default Value
0x00
0x00
0
0
0
0
0
0
0
0
Description
0x01
0x02
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Default Value
Description
Max EEPROM Burst Max EEPROM
size[7]
Max EEPROM
Burst size[5]
Max EEPROM
Burst size[4]
Max EEPROM
Burst size[3]
Max EEPROM
Burst size[2]
Max EEPROM
Burst size[1]
Max EEPROM Burst
size[0]
Burst size[6]
Default Value
0x00
0x00
00
0
0
0
0
0
0
0
0
Description
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
PWDN_ch7
0x01 [7]
0
PWDN_ch6
0x01 [6]
0
PWDN_ch5
0x01 [5]
0
PWDN_ch4
0x01 [4]
0
PWDN_ch3
0x01 [3]
0
PWDN_ch2
0x01 [2]
0
PWDN_ch1
0x01 [1]
0
PWDN_ch0
0x01 [0]
0
SMBus Register
Default Value
Description
lpbk_1
0x02 [5]
0
lpbk_0
0x02 [4]
0
PWDN_INPUTS
PWDN_OSC
0x02 [2]
0
Ovrd_PWDN
0x02 [0]
0
Reserved
0x04 [7]
0
Reserved
0x04 [6]
0
Reserved
0x04 [5]
0
SMBus Register
Default Value
0x02 [3]
0
Description
Reserved
0x04 [4]
0
Reserved
0x04 [3]
0
Reserved
0x04 [2]
0
Reserved
0x04 [1]
0
Reserved
0x04 [0]
0
rxdet_btb_en
Ovrd_idle_th
0x08 [6]
0
Ovrd_RES
0x08 [5]
0
SMBus Register
Default Value
0x06 [4]
1
04
Description
Ovrd_IDLE
0x08 [4]
0
Ovrd_RX_DET
Ovrd_MODE
0x08 [2]
0
Ovrd_RES
0x08 [1]
0
Ovrd_RES
0x08 [0]
0
rx_delay_sel_2
rx_delay_sel_1
rx_delay_sel_0
SMBus Register
Default Value
0x08 [3]
0
0x0B [6]
1
0x0B [5]
1
0x0B [4]
1
07
Description
RD_delay_sel_3
RD_delay_sel_2
RD_delay_sel_1
RD_delay_sel_0
ch0_Idle_auto
ch0_Idle_sel
0x0E [4]
0
ch0_RXDET_1
ch0_RXDET_0
SMBus Register
Default Value
0x0B [3]
0
0x0B [2]
0
0x0B [1]
0
0x0B [0]
0
0x0E [5]
0
0x0E [3]
0
0x0E [2]
0
00
Description
ch0_BST_7
0x0F [7]
0
ch0_BST_6
0x0F [6]
0
ch0_BST_5
0x0F [5]
1
ch0_BST_4
0x0F [4]
0
ch0_BST_3
0x0F [3]
1
ch0_BST_2
0x0F [2]
1
ch0_BST_1
0x0F [1]
1
ch0_BST_0
0x0F [0]
1
SMBus Register
Default Value
2F
Description
ch0_Sel_scp
0x10 [7]
1
ch0_Sel_mode
ch0_RES_2
0x10 [5]
1
ch0_RES_1
0x10 [4]
0
ch0_RES_0
0x10 [3]
1
ch0_VOD_2
0x10 [2]
1
ch0_VOD_1
0x10 [1]
0
ch0_VOD_0
0x10 [0]
1
SMBus Register
Default Value
0x10 [6]
0
AD
40
Description
ch0_DEM_2
0x11 [2]
0
ch0_DEM_1
0x11 [1]
1
ch0_DEM_0
0x11 [0]
0
ch0_Slow
0x12 [7]
0
ch0_idle_tha_1
ch0_idle_tha_0
ch0_idle_thd_1
ch0_idle_thd_0
SMBus Register
Default Value
0x12 [3]
0
0x12 [2]
0
0x12 [1]
0
0x12 [0]
0
Copyright © 2012–2018, Texas Instruments Incorporated
17
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
BIt 0
Table 7. EEPROM Register Map - Single Device with Default Value (continued)
EEPROM Address Byte
Description
Bit 7
ch1_Idle_auto
0x15 [5]
Bit 6
ch1_Idle_sel
0x15 [4]
0
Bit 5
ch1_RXDET_1
0x15 [3]
Bit 4
ch1_RXDET_0
0x15 [2]
Bit 3
ch1_BST_7
0x16 [7]
0
Bit 2
ch1_BST_6
0x16 [6]
0
Bit 1
ch1_BST_5
0x16 [5]
1
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
ch1_BST_4
SMBus Register
Default Value
0x16 [4]
0
02
FA
2F
00
2F
AD
40
02
FA
D4
09
0
0
0
Description
ch1_BST_3
0x16 [3]
1
ch1_BST_2
0x16 [2]
1
ch1_BST_1
0x16 [1]
1
ch1_BST_0
0x16 [0]
1
ch1_Sel_scp
0x17 [7]
1
ch1_Sel_mode
ch1_RES_2
0x17 [5]
1
ch1_RES_1
0x17 [4]
0
SMBus Register
Default Value
0x17 [6]
0
Description
ch1_RES_0
0x17 [3]
1
ch1_VOD_2
0x17 [2]
1
ch1_VOD_1
0x17 [1]
0
ch1_VOD_0
0x17 [0]
1
ch1_DEM_2
0x18 [2]
0
ch1_DEM_1
0x18 [1]
1
ch1_DEM_0
0x18 [0]
0
ch1_Slow
0x19 [7]
0
SMBus Register
Default Value
Description
ch1_idle_tha_1
ch1_idle_tha_0
ch1_idle_thd_1
ch1_idle_thd_0
ch2_Idle_auto
ch2_Idle_sel
0x1C [4]
0
ch2_RXDET_1
ch2_RXDET_0
SMBus Register
Default Value
0x19 [3]
0
0x19 [2]
0
0x19 [1]
0
0x19 [0]
0
0x1C [5]
0
0x1C [3]
0
0x1C [2]
0
Description
ch2_BST_7
0x1D [7]
0
ch2_BST_6
0x1D [6]
0
ch2_BST_5
0x1D [5]
1
ch2_BST_4
0x1D [4]
0
ch2_BST_3
0x1D [3]
1
ch2_BST_2
0x1D [2]
1
ch2_BST_1
0x1D [1]
1
ch2_BST_0
0x1D [0]
1
SMBus Register
Default Value
Description
ch2_Sel_scp
0x1E [7]
1
ch2_Sel_mode
ch2_RES_2
0x1E [5]
1
ch2_RES_1
0x1E [4]
0
ch2_RES_0
0x1E [3]
1
ch2_VOD_2
0x1E [2]
1
ch2_VOD_1
0x1E [1]
0
ch2_VOD_0
0x1E [0]
1
SMBus Register
Default Value
0x1E [6]
0
Description
ch2_DEM_2
0x1F [2]
0
ch2_DEM_1
0x1F [1]
1
ch2_DEM_0
0x1F [0]
0
ch2_Slow
0x20 [7]
0
ch2_idle_tha_1
ch2_idle_tha_0
ch2_idle_thd_1
ch2_idle_thd_0
SMBus Register
Default Value
0x20 [3]
0
0x20 [2]
0
0x20 [1]
0
0x20 [0]
0
Description
ch3_Idle_auto
ch3_Idle_sel
0x23 [4]
0
ch3_RXDET_1
ch3_RXDET_0
ch3_BST_7
0x24 [7]
0
ch3_BST_6
0x24 [6]
0
ch3_BST_5
0x24 [5]
1
ch3_BST_4
0x24 [4]
0
SMBus Register
Default Value
0x23 [5]
0
0x23 [3]
0
0x23 [2]
0
Description
ch3_BST_3
0x24 [3]
1
ch3_BST_2
0x24 [2]
1
ch3_BST_1
0x24 [1]
1
ch3_BST_0
0x24 [0]
1
ch3_Sel_scp
0x25 [7]
1
ch3_Sel_mode
ch3_RES_2
0x25 [5]
1
ch3_RES_1
0x25 [4]
0
SMBus Register
Default Value
0x25 [6]
0
Description
ch3_RES_0
0x25 [3]
1
ch3_VOD_2
0x25 [2]
1
ch3_VOD_1
0x25 [1]
0
ch3_VOD_0
0x25 [0]
1
ch3_DEM_2
0x26 [2]
0
ch3_DEM_1
0x26 [1]
1
ch3_DEM_0
0x26 [0]
0
ch3_Slow
0x27 [7]
0
SMBus Register
Default Value
Description
ch3_idle_tha_1
ch3_idle_tha_0
ch3_idle_thd_1
ch3_idle_thd_0
ovrd_fast_idle
en_high_idle_th_n
en_high_idle_th_s
en_fast_idle_n
SMBus Register
Default Value
0x27 [3]
0
0x27 [2]
0
0x27 [1]
0
0x27 [0]
0
0x28 [6]
0
0x28 [5]
0
0x28 [4]
0
0x28 [3]
1
18
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Table 7. EEPROM Register Map - Single Device with Default Value (continued)
EEPROM Address Byte
Bit 7
en_fast_idle_s
0x28 [2]
Bit 6
eqsd_mgain_n
0x28 [1]
Bit 5
eqsd_mgain_s
0x28 [0]
Bit 4
ch4_Idle_auto
0x2B [5]
0
Bit 3
ch4_Idle_sel
0x2B [4]
0
Bit 2
ch4_RXDET_1
0x2B [3]
Bit 1
ch4_RXDET_0
0x2B [2]
BIt 0
ch4_BST_7
Description
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
SMBus Register
Default Value
0x2C [7]
0
80
5F
5A
80
05
F5
A8
00
5F
5A
80
1
0
0
0
0
Description
ch4_BST_6
0x2C [6]
0
ch4_BST_5
0x2C [5]
1
ch4_BST_4
0x2C [4]
0
ch4_BST_3
0x2C [3]
1
ch4_BST_2
0x2C [2]
1
ch4_BST_1
0x2C [1]
1
ch4_BST_0
0x2C [0]
1
ch4_Sel_scp
0x2D [7]
1
SMBus Register
Default Value
Description
ch4_Sel_mode
ch4_RES_2
0x2D [5]
1
ch4_RES_1
0x2D [4]
0
ch4_RES_0
0x2D [3]
1
ch4_VOD_2
0x2D [2]
1
ch4_VOD_1
0x2D [1]
0
ch4_VOD_0
0x2D [0]
1
ch4_DEM_2
0x2E [2]
0
SMBus Register
Default Value
0x2D [6]
0
Description
ch4_DEM_1
0x2E [1]
1
ch4_DEM_0
0x2E [0]
0
ch4_Slow
0x2F [7]
0
ch4_idle_tha_1
ch4_idle_tha_0
ch4_idle_thd_1
ch4_idle_thd_0
ch5_Idle_auto
SMBus Register
Default Value
0x2F [3]
0
0x2F [2]
0
0x2F [1]
0
0x2F [0]
0
0x32 [5]
0
Description
ch5_Idle_sel
0x32 [4]
0
ch5_RXDET_1
ch5_RXDET_0
ch5_BST_7
0x33 [7]
0
ch5_BST_6
0x33 [6]
0
ch5_BST_5
0x33 [5]
1
ch5_BST_4
0x33 [4]
0
ch5_BST_3
0x33 [3]
1
SMBus Register
Default Value
0x32 [3]
0
0x32 [2]
0
Description
ch5_BST_2
0x33 [2]
1
ch5_BST_1
0x33 [1]
1
ch5_BST_0
0x33 [0]
1
ch5_Sel_scp
0x34 [7]
1
ch5_Sel_mode
ch5_RES_2
0x34 [5]
1
ch5_RES_1
0x34 [4]
0
ch5_RES_0
0x34 [3]
1
SMBus Register
Default Value
0x34 [6]
0
Description
ch5_VOD_2
0x34 [2]
1
ch5_VOD_1
0x34 [1]
0
ch5_VOD_0
0x34 [0]
1
ch5_DEM_2
0x35 [2]
0
ch5_DEM_1
0x35 [1]
1
ch5_DEM_0
0x35 [0]
0
ch5_Slow
0x36 [7]
0
ch5_idle_tha_1
SMBus Register
Default Value
0x36 [3]
0
Description
ch5_idle_tha_0
ch5_idle_thd_1
ch5_idle_thd_0
ch6_Idle_auto
ch6_Idle_sel
0x39 [4]
0
ch6_RXDET_1
ch6_RXDET_0
ch6_BST_7
0x3A [7]
0
SMBus Register
Default Value
0x36 [2]
0
0x36 [1]
0
0x36 [0]
0
0x39 [5]
0
0x39 [3]
0
0x39 [2]
0
Description
ch6_BST_6
0x3A [6]
0
ch6_BST_5
0x3A [5]
1
ch6_BST_4
0x3A [4]
0
ch6_BST_3
0x3A [3]
1
ch6_BST_2
0x3A [2]
1
ch6_BST_1
0x3A [1]
1
ch6_BST_0
0x3A [0]
1
ch6_Sel_scp
0x3B [7]
1
SMBus Register
Default Value
Description
ch6_Sel_mode
ch6_RES_2
0x3B [5]
1
ch6_RES_1
0x3B [4]
0
ch6_RES_0
0x3B [3]
1
ch6_VOD_2
0x3B [2]
1
ch6_VOD_1
0x3B [1]
0
ch6_VOD_0
0x3B [0]
1
ch6_DEM_2
0x3C [2]
0
SMBus Register
Default Value
0x3B [6]
0
Description
ch6_DEM_1
0x3C [1]
1
ch6_DEM_0
0x3C [0]
0
ch6_Slow
0x3D [7]
0
ch6_idle_tha_1
ch6_idle_tha_0
ch6_idle_thd_1
ch6_idle_thd_0
ch7_Idle_auto
SMBus Register
Default Value
0x3D [3]
0
0x3D [2]
0
0x3D [1]
0
0x3D [0]
0
0x40 [5]
0
Copyright © 2012–2018, Texas Instruments Incorporated
19
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
BIt 0
Table 7. EEPROM Register Map - Single Device with Default Value (continued)
EEPROM Address Byte
Description
Bit 7
ch7_Idle_sel
0x40 [4]
0
Bit 6
ch7_RXDET_1
0x40 [3]
Bit 5
ch7_RXDET_0
0x40 [2]
Bit 4
ch7_BST_7
0x41 [7]
0
Bit 3
ch7_BST_6
0x41 [6]
0
Bit 2
ch7_BST_5
0x41 [5]
1
Bit 1
ch7_BST_4
0x41 [4]
0
0x21
0x22
0x23
0x24
0x25
0x26
0x27
ch7_BST_3
SMBus Register
Default Value
0x41 [3]
1
05
F5
A8
00
00
54
54
0
0
Description
ch7_BST_2
0x41 [2]
1
ch7_BST_1
0x41 [1]
1
ch7_BST_0
0x41 [0]
1
ch7_Sel_scp
0x42 [7]
1
ch7_Sel_mode
ch7_RES_2
0x42 [5]
1
ch7_RES_1
0x42 [4]
0
ch7_RES_0
0x42 [3]
1
SMBus Register
Default Value
0x42 [6]
0
Description
ch7_VOD_2
0x42 [2]
1
ch7_VOD_1
0x42 [1]
0
ch7_VOD_0
0x42 [0]
1
ch7_DEM_2
0x43 [2]
0
ch7_DEM_1
0x43 [1]
1
ch7_DEM_0
0x43 [0]
0
ch7_Slow
0x44 [7]
0
ch7_idle_tha_1
SMBus Register
Default Value
0x44 [3]
0
Description
ch7_idle_tha_0
ch7_idle_thd_1
ch7_idle_thd_0
Reserved
0x47 [3]
0
Reserved
0x47 [2]
0
Reserved
0x47 [2]
0
Reserved
0x47 [0]
0
Reserved
0x48 [7]
0
SMBus Register
Default Value
0x44 [2]
0
0x44 [1]
0
0x44 [0]
0
Description
Reserved
0x48 [6]
0
Reserved
0x4C [7]
0
Reserved
0x4C [6]
0
Reserved
0x4C [5]
0
Reserved
0x4C [4]
0
Reserved
0x4C [3]
0
Reserved
0x4C [0]
0
Reserved
0x59 [0]
0
SMBus Register
Default Value
Description
Reserved
0x5A [7]
0
Reserved
0x5A [6]
1
Reserved
0x5A [5]
0
Reserved
0x5A [4]
1
Reserved
0x5A [3]
0
Reserved
0x5A [2]
1
Reserved
0x5A [1]
0
Reserved
0x5A [0]
0
SMBus Register
Default Value
Description
Reserved
0x5B [7]
0
Reserved
0x5B [6]
1
Reserved
0x5B [5]
0
Reserved
0x5B [4]
1
Reserved
0x5B [3]
0
Reserved
0x5B [2]
1
Reserved
0x5B [1]
0
Reserved
0x5B [0]
0
SMBus Register
Default Value
20
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Table 8. Example of EEPROM for Four Devices Using Two Address Maps
EEPROM Address
Address (Hex)
00
EEPROM Data
0x43
0x00
0x08
0x00
0x0B
0x00
0x0B
0x00
0x30
0x00
0x30
0x00
0x00
0x04
0x07
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x01
0x80
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x00
0x54
Comments
0
CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3
1
01
2
02
EEPROM Burst Size
CRC not used
3
03
4
04
Device 0 Address Location
CRC not used
5
05
6
06
Device 1 Address Location
CRC not used
7
07
8
08
Device 2 Address Location
CRC not used
9
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
0A
0B
0C
0D
0E
0F
10
Device 3 Address Location
Begin Device 0, 1 - Address Offset 3
EQ CHB0 = 00
11
VOD CHB0 = 1.0 V
DEM CHB0 = 0 (0 dB)
EQ CHB1 = 00
12
13
14
VOD CHB1 = 1.0 V
DEM CHB1 = 0 (0 dB)
15
16
17
EQ CHB2 = 00
18
VOD CHB2 = 1.0 V
DEM CHB2 = 0 (0 dB)
EQ CHB3 = 00
19
1A
1B
1C
1D
1E
1F
20
VOD CHB3 = 1.0 V
DEM CHB3 = 0 (0 dB)
EQ CHA0 = 00
VOD CHA0 = 1.0 V
DEM CHA0 = 0 (0 dB)
EQ CHA1 = 00
21
22
23
VOD CHA1 = 1.0 V
DEM CHA1 = 0 (0 dB)
24
25
26
EQ CHA2 = 00
27
VOD CHA2 = 1.0 V
DEM CHA2 = 0 (0 dB)
EQ CHA3 = 00
28
29
2A
2B
2C
2D
2E
VOD CHA3 = 1.0 V
DEM CHA3 = 0 (0 dB)
Copyright © 2012–2018, Texas Instruments Incorporated
21
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Table 8. Example of EEPROM for Four Devices Using Two Address Maps (continued)
EEPROM Address
Address (Hex)
EEPROM Data
0x54
0x00
0x00
0x04
0x07
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x01
0x80
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x00
0x54
0x54
Comments
End Device 0, 1 - Address Offset 39
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
Begin Device 2, 3 - Address Offset 3
EQ CHB0 = 00
VOD CHB0 = 1.0 V
DEM CHB0 = 0 (0 dB)
EQ CHB1 = 00
VOD CHB1 = 1.0 V
DEM CHB1 = 0 (0 dB)
EQ CHB2 = 00
VOD CHB2 = 1.0 V
DEM CHB2 = 0 (0 dB)
EQ CHB3 = 00
VOD CHB3 = 1.0 V
DEM CHB3 = 0 (0 dB)
EQ CHA0 = 00
VOD CHA0 = 1.0 V
DEM CHA0 = 0 (0 dB)
EQ CHA1 = 00
VOD CHA1 = 1.0 V
DEM CHA1 = 0 (0 dB)
EQ CHA2 = 00
VOD CHA2 = 1.0 V
DEM CHA2 = 0 (0 dB)
EQ CHA3 = 00
VOD CHA3 = 1.0 V
DEM CHA3 = 0 (0 dB)
End Device 2, 3 - Address Offset 39
NOTE: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all 8 channels
set to EQ = 00 (min boost), VOD = 1.0 V, DEM = 0 (0 dB) and multiple device can point to the same address
map. Maximum EEPROM size is 8kbits (1024 x 8-bits).
8.5.2 Transfer of Data Via the SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
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STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
8.5.3 System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ
to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS125BR800 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address
inputs. The AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS125BR800 has a 7-bit slave address.
The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the
AD[3:0] inputs. Table 9 shows the 16 addresses.
Table 9. Device Slave Address Bytes
AD[3:0] Settings
0000
Address Bytes (HEX)
B0
B2
B4
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
CA
CC
CE
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
The SDA, SCL pins are 3.3 V tolerant, but are not 5 V tolerant. External pull-up resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pull-up resistor and it depends on the Host that drives the bus.
8.5.4 SMBus Transactions
The device supports WRITE and READ transactions. See Table 10 for register address, type (Read/Write, Read
Only), default value and function information.
8.5.5 Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a "0" indicating a WRITE.
2. The Device (Slave) drives the ACK bit ("0").
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit ("0").
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit ("0").
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
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8.5.6 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a "0" indicating a WRITE.
2. The Device (Slave) drives the ACK bit ("0").
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit ("0").
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a "1" indicating a READ.
7. The Device drives an ACK bit "0".
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit "1"indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
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8.6 Register Maps
Table 10. SMBUS Slave Mode Register Map
Address
Register Name
Bit
7
Field
Type
R/W
R
Default
EEPROM Bit
Description
0x00
Device Address
Observation
Reserved
0x00
Set bit to 0.
6:3
Address Bit
AD[3:0]
Observation of AD[3:0] bit
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
2
EEPROM Read Done
Reserved
R
1: Device completed the read from external EEPROM.
Set bits to 0.
1:0
7:0
R/W
R/W
0x01
PWDN Channels
PWDN CHx
0x00
Yes
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
0x00 = all channels enabled
0xFF = all channels disabled
Note: override PWDN pin.
0x02
Override
PWDN Control
7:1
0
Reserved
R/W
0x00
Set bits to 0.
Override PWDN
Yes
Yes
1: Block PWDN pin control
0: Allow PWDN pin control
0x03
0x04
0x05
0x05
0x06
Reserved
7:0
7:0
7:0
7:0
7:5
4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register Enable
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x10
Set bits to 0
Set bits to 0
Set bits to 0
Reserved
Reserved
Reserved
Reserved
Slave Register Control
Set bits to 0.
Set bit to 1.
Yes
3
1 = Enable SMBus Register Control
0 = Disable SMBus Register Control
Note: In order to change VOD, DEM, and EQ of the channels in
slave mode, this bit must be set to 1.
2:0
7
Reserved
Set bits to 0.
0x07
Digital Reset and Control
Reserved
R/W
0x01
Set bit to 0.
6
Reset Registers
Reset SMBus Master
Reserved
Self clearing bit, set to 1 to reset the register to default values
Self clearing reset to SMBus master state machine
Set bits to 0 0001'b.
5
4:0
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7
Field
Type
Default
EEPROM Bit
Description
0x08
Override
Pin Control
Reserved
Override SD_TH
R/W
0x00
Set bit to 0.
6
Yes
1: Block SD_TH pin control
0: Allow SD_TH pin control
5
4
Reserved
Yes
Yes
Set bit to 0.
Override IDLE
1: IDLE control by registers
0: IDLE control by signal detect
3
2
Override RXDET
Override MODE
Yes
Yes
1: Block RXDET pin control
0: Allow RXDET pin control
1: Block MODE pin control
0: Allow MODE pin control
1
Reserved
Set bit to 0.
Set bit to 0.
Set bits to 0
0
Reserved
0x09
0x0A
Reserved
7:0
7:0
Reserved
R/W
R
0x00
0x00
Signal Detect Monitor
SD_TH Status
CH7 - CH0 Internal Signal Detector Indicator
[7]: CH7 - CHA_3
[6]: CH6 - CHA_2
[5]: CH5 - CHA_1
[4]: CH4 - CHA_0
[3]: CH3 - CHB_3
[2]: CH2 - CHB_2
[1]: CH1 - CHB_1
[0]: CH0 - CHB_0
0 = Signal detected at input (active data)
1 = Signal not detected at input (idle state)
NOTE: These bits only function when RATE pin = FLOAT
0x0B
Reserved
Reserved
7
Reserved
Reserved
Reserved
Reserved
SD Reset
R/W
R/W
R/W
R/W
0x00
0x70
0x00
0x00
Set bits to 0
6:0
7:0
7:3
2
Yes
Set bits to 111 0000'b
Set bits to 0
0x0C
0x0D
CH0 - CHB0
Signal Detect
Set bits to 0.
1: Force signal detect "off"
0: Normal operation
1
0
SD Preset
Reserved
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
26
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:6
5
Field
Type
Default
EEPROM Bit
Description
0x0E
CH0 - CHB0
IDLE, RXDET
Reserved
IDLE_AUTO
R/W
0x00
Set bits to 0.
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
Yes
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x0F
0x10
CH0 - CHB0
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IB0 EQ Control - total of 256 levels.
See Table 2.
CH0 - CHB0
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
Copyright © 2012–2018, Texas Instruments Incorporated
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x11
CH0 - CHB0
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH0 - CHB0.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit for MODE_DET CH0 - CHB0.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OB0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x12
CH0 - CHB0
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x13
0x14
Reserved
7:0
7:3
2
Reserved
Reserved
SD Reset
R/W
R/W
0x00
0x00
Set bits to 0
Set bits to 0.
CH1 - CHB1
Signal Detect
1: Force signal detect "off"
0: Normal operation
1
0
SD Preset
Reserved
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
28
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:6
5
Field
Type
Default
EEPROM Bit
Description
0x15
CH1 - CHB1
IDLE, RXDET
Reserved
IDLE_AUTO
R/W
0x00
Set bits to 0.
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
Yes
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x16
0x17
CH1 - CHB1
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IB1 EQ Control - total of 256 levels.
See Table 2.
CH1 - CHB1
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OB1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x18
CH1 - CHB1
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH1 - CHB1.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit forMODE_DET CH1 - CHB1.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OB1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x19
CH1 - CHB1
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x1A
0x1B
Reserved
7:0
7:3
2
Reserved
Reserved
SD Reset
R/W
R/W
0x00
0x00
Set bits to 0
Set bits to 0.
CH2 - CHB2
Signal Detect
1: Force signal detect "off"
0: Normal operation
1
0
SD Preset
Reserved
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
30
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ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:6
5
Field
Type
Default
EEPROM Bit
Description
0x1C
CH2 - CHB2
IDLE, RXDET
Reserved
IDLE_AUTO
R/W
0x00
Set bits to 0.
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
Yes
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x1D
0x1E
CH2 - CHB2
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IB2 EQ Control - total of 256 levels.
See Table 2.
CH2 - CHB2
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OB2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x1F
CH2 - CHB2
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH2 - CHB2.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit for MODE_DET CH2 - CHB2.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OB2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x20
CH2 - CHB2
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x21
0x22
Reserved
7:0
7:3
2
Reserved
Reserved
SD Reset
R/W
R/W
0x00
0x00
Set bits to 0
Set bits to 0.
CH3 - CHB3
Signal Detect
1: Force signal detect "off"
0: Normal operation
1
0
SD Preset
Reserved
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
32
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ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:6
5
Field
Type
Default
EEPROM Bit
Description
0x23
CH3 - CHB3
IDLE, RXDET
Reserved
IDLE_AUTO
R/W
0x00
Set bits to 0.
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
Yes
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x24
0x25
CH3 - CHB3
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IB3 EQ Control - total of 256 levels.
See Table 2.
CH3 - CHB3
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x26
CH3 - CHB3
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH3 - CHB3.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit for MODE_DET CH3 - CHB3.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OB3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x27
CH3 - CHB3
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x28
Signal Detect Control
7:6
5:4
Reserved
High IDLE
R/W
0x0C
Set bits to 0.
Yes
Yes
Yes
Enable higher range of Signal Detect Thresholds
[5]: CH0 - CH3
[4]: CH4 -CH7
3:2
1:0
7:0
Fast IDLE
Enable Fast OOB response
[3]: CH0 - CH3
[2]: CH4 -CH7
Reduced SD Gain
Reserved
Enable reduced Signal Detect Gain
[1]: CH0 - CH3
[0]: CH4 -CH7
0x29
34
Reserved
R/W
0x00
Set bits to 0
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:3
2
Field
Type
Default
EEPROM Bit
Description
0x2A
CH4 - CHA0
Signal Detect
Reserved
SD Reset
R/W
0x00
Set bits to 0.
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
Reserved
IDLE_AUTO
Set bit to 0.
Set bits to 0.
0x2B
CH4 - CHA0
7:6
5
R/W
0x00
IDLE, RXDET
Yes
Yes
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x2C
0x2D
CH4 - CHA0
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IA0 EQ Control - total of 256 levels.
See Table 2.
CH4 - CHA0
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OA0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
Copyright © 2012–2018, Texas Instruments Incorporated
35
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x2E
CH4 - CHA0
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH4 - CHA0.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit for MODE_DET CH4 - CHA0.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OA0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x2F
CH4 - CHA0
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x30
0x31
Reserved
7:0
7:3
2
Reserved
Reserved
SD Reset
R/W
R/W
0x00
0x00
Set bits to 0
Set bits to 0.
CH5 - CHA1
Signal Detect
1: Force signal detect "off"
0: Normal operation
1
0
SD Preset
Reserved
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
36
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:6
5
Field
Type
Default
EEPROM Bit
Description
0x32
CH5 - CHA1
IDLE, RXDET
Reserved
IDLE_AUTO
R/W
0x00
Set bits to 0.
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
Yes
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x33
0x34
CH5 - CHA1
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IA1 EQ Control - total of 256 levels.
See Table 2.
CH5 - CHA1
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OA1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
Copyright © 2012–2018, Texas Instruments Incorporated
37
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x35
CH5 - CHA1
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH5 - CHA1.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit for MODE_DET CH5 - CHA1.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OA1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x36
CH5 - CHA1
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x37
0x38
Reserved
7:0
7:3
2
Reserved
Reserved
SD Reset
R/W
R/W
0x00
0x00
Set bits to 0
Set bits to 0.
CH6 - CHA2
Signal Detect
1: Force signal detect "off"
0: Normal operation
1
0
SD Preset
Reserved
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
38
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:6
5
Field
Type
Default
EEPROM Bit
Description
0x39
CH6 - CHA2
IDLE, RXDET
Reserved
IDLE_AUTO
R/W
0x00
Set bits to 0.
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
Yes
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x3A
0x3B
CH6 - CHA2
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IA2 EQ Control - total of 256 levels.
See Table 2.
CH6 - CHA2
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OA2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
Copyright © 2012–2018, Texas Instruments Incorporated
39
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x3C
CH6 - CHA2
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH6 - CHA2.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit for MODE_DET CH6 - CHA2.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OA2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x3D
CH6 - CHA2
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x3E
0x3F
Reserved
7:0
7:3
2
Reserved
Reserved
SD Reset
R/W
R/W
0x00
0x00
Set bits to 0
Set bits to 0.
CH0 - CHB0
Signal Detect
1: Force signal detect "off"
0: Normal operation
1
0
SD Preset
Reserved
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
40
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:6
5
Field
Type
Default
EEPROM Bit
Description
0x40
CH7 - CHA3
IDLE, RXDET
Reserved
IDLE_AUTO
R/W
0x00
Set bits to 0.
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
RXDET
Yes
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination
is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z
until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x41
0x42
CH7 - CHA3
EQ
EQ Control
R/W
0x2F
0xAD
Yes
Yes
Yes
IA3 EQ Control - total of 256 levels.
See Table 2.
CH7 - CHA3
VOD
7
6
Short Circuit Protection R/W
MODE_SEL
1: Enable the short circuit protection
0: Disable the short circuit protection
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
2:0
Reserved
Yes
Yes
Set bits to default value - 101.
VOD Control
OA3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
Copyright © 2012–2018, Texas Instruments Incorporated
41
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
Field
Type
Default
EEPROM Bit
Description
0x43
CH7 - CHA3
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH7 - CHA3.
1: RX = detected
0: RX = not detected
6:5
MODE_DET STATUS
R
Observation bit for MODE_DET CH7 - CHA3.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
Yes
OA3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x44
CH7 - CHA3
IDLE Threshold
7:4
3:2
Reserved
IDLE tha
R/W
0x00
Set bits to 0.
Yes
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x45
0x46
0x47
Reserved
Reserved
Reserved
7:0
7:0
7:4
3:0
7:6
5:0
7:0
7:0
7:0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x38
0x00
Set bits to 0
Set bits to 0x38
Set bits to 0
Yes
Yes
Set bits to 0
0x48
Reserved
0x05
Set bits to 0
Set bits to 00 0101'b
Set bits to 0
0x49
0x4A
0x4B
Reserved
Reserved
Reserved
0x00
0x00
0x00
Set bits to 0
Set bits to 0
42
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit
7:3
2:1
0
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Default
EEPROM Bit
Description
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
010'b
0x4C
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VERSION
ID
0x00
Yes
Yes
0x4D
0x4E
0x4F
0x50
0x51
Reserved
Reserved
Reserved
Reserved
Device ID
7:0
7:0
7:0
7:0
7:5
4:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:1
0
0x00
0x00
0x00
0x00
0x45
00101'b
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x10
0x64
0x21
0x00
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0x10
Set bits to 0x64
Set bits to 0x21
Set bits to 0
Set bit to 0
Yes
Yes
Yes
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x54
0x54
0x00
0x00
0x00
0x00
0x00
0x00
Set bits to 0x54
Set bits to 0x54
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
Set bits to 0
Copyright © 2012–2018, Texas Instruments Incorporated
43
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS125BR800 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to Layout Guidelines and the LVDS Owner's Manual, SNLA187, for more detailed information on high speed
design tips to address signal integrity design issues.
9.2 Typical Application
8
TX
ASIC
or
Connector
PCIe EP
8
RX
DS125BR800
8
RX
System Board
DS125BR800
Root Complex
Connector
8
TX
Figure 9. Typical Application
9.2.1 Design Requirements
As with any high speed design, there are many factors which influence the overall performance. Below are a list
of critical areas for consideration and study during design.
•
•
•
•
•
Use 100 Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
The maximum body size for AC-coupling capacitors is 0402.
Back-drill connector vias and signal vias to minimize stub length.
Use Reference plane vias to ensure a low inductance path for the return current.
9.2.2 Detailed Design Procedure
The DS125BR800 is designed to be placed at a location where the input CTLE can help to compensate for a
portion of the overall channel attenuation. In order to optimize performance, the repeater requires tuning to
extend the reach of the cable or trace length while also recovering a solid eye opening. To tune the repeater, the
settings mentioned in Table 2 and Table 3 (for Pin Mode) are recommended as a default starting point for most
applications. Once these settings are configured, additional tuning of the EQ and, to a lesser extent, VOD may
be required to optimize the repeater performance for each specific application environment. Examples of the
repeater performance as a generic high speed datapath repeater are illustrated in the performance curves in the
next section.
44
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Typical Application (continued)
Pattern
Generator
VID = 1.0 Vp-p
TL
Lossy Channel
Scope
BW = 60 GHz
IN
DS125BR800
OUT
DE = 0 dB
PRBS15
Figure 10. Test Setup Connections Diagram
Pattern
Generator
VID = 1.0 Vp-p
Tl1
Lossy Channel
Tl2
Lossy Channel
Scope
BW = 60 GHz
IN
DS125BR800
OUT
DE = –6 dB
PRBS15
Figure 11. Test Setup Connections Diagram
9.2.3 Application Curves
DS125BR800 settings: EQ[1:0] = 0, F = 0x02, DEM[1:0] = 0, 1
DS125BR800 settings: EQ[1:0] = 0, F = 0x02, DEM[1:0] = 0, 1
Figure 12. TL = 10 inch 5–mil FR4 trace, 5 Gbps
Figure 13. TL = 10 inch 5–mil FR4 trace, 8 Gbps
DS125BR800 settings: EQ[1:0] = 0, R = 0x01, DEM[1:0] = 0, 1
DS125BR800 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = 0, 1
Figure 14. TL = 10 inch 5–mil FR4 trace, 12 Gbps
Figure 15. TL = 20 inch 5–mil FR4 trace, 5 Gbps
Copyright © 2012–2018, Texas Instruments Incorporated
45
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
Typical Application (continued)
DS125BR800 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = 0, 1
DS125BR800 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = 0, 1
Figure 16. TL = 20 inch 5–mil FR4 trace, 8 Gbps
Figure 17. TL = 20 inch 5–mil FR4 trace, 12 Gbps
DS125BR800 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
DS125BR800 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
Figure 18. TL = 30 inch 5–mil FR4 trace, 5 Gbps
Figure 19. TL = 30 inch 5–mil FR4 trace, 8 Gbps
DS125BR800 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
DS125BR800 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
Figure 21. TL1 = 5-meter 30-AWG 100 Ω Twin-axial Cable,
12 Gbps
Figure 20. TL = 30 inch 5–mil FR4 trace, 12 Gbps
46
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
Typical Application (continued)
DS125BR800 settings: EQ[1:0] = R, 1 = 0x0F, DEM[1:0] = 0, 1
Figure 22. TL1 = 8-meter 30-AWG 100 Ω Twin-axial Cable,
12 Gbps
DS125BR800 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = R, 0
Figure 23. TL1 = 20 inch 5–mil FR4 trace, TL2 = 10 inch
5–mil FR4 trace, 5 Gbps
DS125BR800 settings: EQ[1:0] = R, 1 = 0x0F, DEM[1:0] = R, 0
Figure 24. TL1 = 20 inch 5–mil FR4 trace, TL2 = 10 inch
5–mil FR4 trace, 8 Gbps
DS125BR800 settings: EQ[1:0] = R, 1 = 0x0F, DEM[1:0] = R, 0
Figure 25. TL1 = 20 inch 5–mil FR4 trace, TL2 = 10 inch
5–mil FR4 trace, 12 Gbps
Copyright © 2012–2018, Texas Instruments Incorporated
47
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
10 Power Supply Recommendations
10.1 3.3-V or 2.5-V Supply Mode Operation
The DS125BR800 has an optional internal voltage regulator to provide the 2.5-V supply to the device. In 3.3-V
mode operation, the VIN pin = 3.3 V is used to supply power to the device. The internal regulator will provide the
2.5 V to the VDD pins of the device and a 0.1-µF cap is needed at each of the 5 VDD pins for power supply de-
coupling (total capacitance should be ≤0.5 µF), and the VDD pins should be left open. The VDD_SEL pin must
be tied to GND to enable the internal regulator. In 2.5-V mode operation, the VIN pin should be left open and 2.5-
V supply must be applied to the 5 VDD pins to power the device. The VDD_SEL pin must be left open (no
connect) to disable the internal regulator.
The DS125BR800 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3-V
Mode operation, the VIN pin = 3.3 V is used to supply power to the device. The internal regulator will provide the
2.5 V to the VDD pins of the device and a 0.1-µF cap is needed at each of the 5 VDD pins for power supply
decoupling (total capacitance should be ≤0.5 µF), and the VDD pins should be left open. The VDD_SEL pin must
be tied to GND to enable the internal regulator. In 2.5-V Mode operation, the VIN pin should be left open and 2.5-
V supply must be applied to the 5 VDD pins to power the device. The VDD_SEL pin must be left open (no
connect) to disable the internal regulator.
3.3-V mode
2.5-V mode
VDD_SEL
VDD_SEL
open
open
Enable
Disable
3.3 V
Internal
voltage
regulator
Internal
voltage
regulator
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
VIN
VDD
VDD
VDD
VDD
VDD
VIN
VDD
VDD
VDD
VDD
VDD
2.5 V
2.5V
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Place 0.1 uF close to VDD Pin
Total capacitance should be ~ 0.5 uF
Place capcitors close to VDD Pin
Figure 26. 3.3-V or 2.5-V Supply Connection Diagram
48
Copyright © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
10.2 Power Supply Bypassing
Two approaches are recommended to ensure that the DS125BR800 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1-µF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS125BR800. Smaller
body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in
the range of 1 µF to 10 µF should be incorporated in the power supply bypassing design as well. These
capacitors can be either tantalum or an ultra-low ESR ceramic.
11 Layout
11.1 Layout Guidelines
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100 Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 for additional information on LLP packages.
Figure 27 depicts different transmission line topologies which can be used in various combinations to achieve the
optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by
increasing the swell around each hole and providing for a low inductance return current path. When the via
structure is associated with thick backplane PCB, further optimization such as back drilling is often used to
reduce the deterimential high frequency effects of stubs on the signal path.
版权 © 2012–2018, Texas Instruments Incorporated
49
DS125BR800
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
www.ti.com.cn
11.2 Layout Example
20 mils
EXTERNAL MICROSTRIP
100 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
15
1
2
12
10
11
9
8
6
5
4
3
18
16
14 13
7
17
54
53
52
19
20
21
22
23
24
25
26
27
51
50
49
BOTTOM OF PKG
GND
48
47
46
VDD
44
29
32
36 37
39 40 41 42
38
43
45
28
30 31
33 34
35
VDD
VDD
Figure 27. Typical Routing Options
50
版权 © 2012–2018, Texas Instruments Incorporated
DS125BR800
www.ti.com.cn
ZHCSD85F –AUGUST 2012–REVISED NOVEMBER 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
•
•
•
《焊接的绝对最大额定值》(SNOA549)
《LVDS 用户手册》(SNLA187)
《了解高速中继器和复用缓冲器的 EEPROM 编程》 (SNLA228)
12.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 商标
All trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2012–2018, Texas Instruments Incorporated
51
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS125BR800SQ/NOPB
DS125BR800SQE/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
NJY
NJY
54
54
2000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
DS125BR800SQ
DS125BR800SQ
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS125BR800SQ/NOPB WQFN
DS125BR800SQE/NOPB WQFN
NJY
NJY
54
54
2000
250
330.0
178.0
16.4
16.4
5.8
5.8
10.3
10.3
1.0
1.0
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS125BR800SQ/NOPB
DS125BR800SQE/NOPB
WQFN
WQFN
NJY
NJY
54
54
2000
250
356.0
208.0
356.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
3.51±0.1
(0.1)
SEE TERMINAL
DETAIL
19
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
46
0.3
54X
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
54X
0.1
C A
C
B
0.05
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54X (0.25)
SEE DETAILS
54
46
1
45
50X (0.5)
(7.5)
(9.8)
SYMM
(1.17)
TYP
2X
(1.16)
28
18
(
0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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