DS125BR820 [TI]

具有均衡功能的 12Gbps 8 通道线性转接驱动器;


型号：	DS125BR820
厂家：	TEXAS INSTRUMENTS
描述：	具有均衡功能的 12Gbps 8 通道线性转接驱动器驱动驱动器
文件：	总63页 (文件大小：10485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

DS125BR820 低功耗 12.5Gbps 8 通道线性中继器

1 特性

3 说明

•

每通道 70mW（典型值）的低功耗，可选择关闭不

使用的通道

DS125BR820 是一款超低功耗高性能中继器/转接驱动

器，专用于支持高速接口速率高达 12.5Gbps 的八个通

道，例如 40G-CR4、40G-KR4、SAS/SATA 和

PCIe。接收器的连续时间线性均衡器 (CTLE) 后接一

个线性输出驱动器，可在 6GHz (12Gbps) 时提供 3dB

至 10dB 的可编程高频增强功能。 CTLE 接收器能够

打开一个因码间干扰 (ISI)（由电路板迹线或铜质同轴

电缆等互连介质引起）而完全关闭的输入眼型状态。

可编程的均衡能够可在互连通道内的实体布局方面实现

最大限度的灵活性并提高通道的总体性能。

•

支持无缝链路协商

启用主 ASIC，从而在较长的距离上满足前端口眼

图波罩要求

•

高级可配置信号调节 I/O

–

6GHz 时，接收高达 10dB 的连续时间线性均衡

器 (CTLE)

–

线性输出驱动器

可变输出电压范围高达 1200mVp-p

•

可通过引脚选择 EEPROM 或 SMBus 接口进行编

程

当在 40G-CR4/KR4、SAS/SATA 和 PCIe 应用中运行

时，DS125BR820 保留发射信号特性，从而使得主机

控制器和端点能够协商发射均衡器系数。这个链路协

商协议的透明管理有助于实现系统级互用性并最大限度

缩短延迟。

•

单电源电压：2.5V 或 3.3V

-40°C 至 85°C 工作温度范围

10mm x 5.5mm 54 引脚超薄型四方扁平无引线

(WQFN) 封装内的直通引脚分配

可通过引脚控制、软件（SMBus 或 I2C）来轻松应用

相关可编程设置，或者通过外部 EEPROM 直接加载设

置。在 EEPROM 模式下，配置信息在加电时自动加

载，这样就免除了对于外部微控制器或软件驱动程序的

需要。

2 应用

•

前端口 40G-CR4/SR4/LR4 链路扩展

背板 40G-KR4 链路扩展

SAS/SATA/PCIe 链路扩展

其它速率高达 12.5Gbps 的专有高速接口

器件信息⁽¹⁾

简化功能框图

器件型号

封装

WQFN (54)

封装尺寸（标称值）

INB_0+

OUTB_0+

DS125BR820

10mm x 5.5mm

INB_0-

OUTB_0-

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

INB_3+

INB_3-

OUTB_3+

OUTB_3-

典型应用方框图

INA_0+

OUTA_0+

INA_0-

OUTA_0-

Line Card

INA_3+

INA_3-

OUTA_3+

OUTA_3-

2x40G

DS125BR820

Stacked QSFP+

40GbE Copper CR4 or

40GbE SR4/LR4 Optical

DS125BR820

AD0

2x40G

Address

straps

AD1

ASIC

(pull-up or

pull-down)

VDD

AD2

FPGA

8x10G

AD3

SMBus

Slave Mode⁽¹⁾

Stacked QSFP+

1xQSFP+ to 4xSFP+

Breakout

DS125BR820

SMBus

READ_EN

ENSMB

Slave Mode⁽¹⁾

SDA⁽²⁾

SCL⁽²⁾

DS125BR820

To system

SMBus

8x10G

VIN

2.5 V

Mode⁽³⁾

ALL_DONE

GND

VDD_SEL

2.5V

VDD

10ꢀF

1ꢀF

0.1ꢀF

(5x)

(1) Schematic requires different connections for SMBus Master Mode and Pin Mode

(2) SMBus signals need to be pulled up elsewhere in the system.

(3) Schematic requires different connections for 3.3 V mode

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNLS491

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 14

7.5 Signal Conditioning Settings................................... 15

7.6 Programming........................................................... 17

7.7 Register Maps......................................................... 25

Applications and Implementation ...................... 41

8.1 Application Information............................................ 41

8.2 Typical Applications ................................................ 42

Power Supply Recommendations...................... 53

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ...................................... 7

6.2 Handling Ratings ...................................................... 7

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information ................................................. 7

6.5 Electrical Characteristics........................................... 8

10 Layout................................................................... 54

10.1 Layout Guidelines ................................................. 54

10.2 Layout Example .................................................... 54

11 器件和文档支持 ..................................................... 55

11.1 商标....................................................................... 55

11.2 静电放电警告......................................................... 55

11.3 术语表 ................................................................... 55

12 机械封装和可订购信息 .......................................... 55

6.6 Electrical Characteristics — Serial Management Bus

Interface .................................................................. 10

6.7 Timing Requirements Serial Bus Interface ............. 10

6.8 Typical Characteristics............................................ 12

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 13

4 修订历史记录

Changes from Original (July 2014) to Revision A

Page

•

已添加完整版文档发布........................................................................................................................................................... 1

DS125BR820

www.ti.com.cn

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

5 Pin Configuration and Functions

WQFN

54-Lead

Top View

SMBUS AND CONTROL

OUTB_0+

INB_0+

INB_0-

INB_1+

INB_1-

OUTB_0-

OUTB_1+

OUTB_1-

VDD

INB_2+

INB_2-

OUTB_2+

OUTB_2-

OUTB_3+

OUTB_3-

VDD

INB_3+

INB_3-

VDD

DAP = GND

INA_0+

INA_0-

INA_1+

OUTA_0+

OUTA_0-

OUTA_1+

OUTA_1-

OUTA_2+

OUTA_2-

OUTA_3+

OUTA_3-

INA_1-

VDD

INA_2+

INA_2-

INA_3+

INA_3-

NOTE: Above 54-lead WQFN graphic is a TOP VIEW, looking down through the package.

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Pin Functions⁽¹⁾

PIN NAME

PIN NUMBER

I/O, TYPE

PIN DESCRIPTION

DIFFERENTIAL HIGH SPEED I/O

INB_0+, INB_0- ,

INB_1+, INB_1-,

INB_2+, INB_2-,

INB_3+, INB_3-

1, 2

3, 4

5, 6

7, 8

Inverting and non-inverting CML differential inputs to the equalizer.

On-chip 50 Ω termination resistor connects INB_n+ to VDD and INB_n-

to VDD depending on the state of RXDET. See Table 2.

AC coupling required on high-speed I/O

OUTB_0+, OUTB_0-,

OUTB_1+, OUTB_1-,

OUTB_2+, OUTB_2-,

OUTB_3+, OUTB_3-

45, 44

43, 42

41, 40

39, 38

Inverting and non-inverting 50 Ω driver outputs. Compatible with AC

coupled CML inputs.

AC coupling required on high-speed I/O

INA_0+, INA_0- ,

INA_1+, INA_1-,

INA_2+, INA_2-,

INA_3+, INA_3-

10, 11

12, 13

15, 16

17, 18

Inverting and non-inverting CML differential inputs to the equalizer.

On-chip 50 Ω termination resistor connects INA_n+ to VDD and INA_n-

to VDD depending on the state of RXDET. See Table 2.

AC coupling required on high-speed I/O

OUTA_0+, OUTA_0-,

OUTA_1+, OUTA_1-,

OUTA_2+, OUTA_2-,

OUTA_3+, OUTA_3-

35, 34

33, 32

31, 30

29, 28

Inverting and non-inverting 50 Ω driver outputs. Compatible with AC

coupled CML inputs.

AC coupling required on high-speed I/O

CONTROL PINS — SHARED (LVCMOS)

System Management Bus (SMBus) Enable Pin

Tie 1 kΩ to VDD = Register Access SMBus Slave Mode

FLOAT = Read External EEPROM (SMBus Master Mode)

Tie 1 kΩ to GND = Pin Mode

ENSMB

I, LVCMOS

I, LVCMOS,

ENSMB = 1 (SMBus SLAVE MODE)

In SMBus Slave Mode, this pin is the SMBus clock I/O. Clock input or

open drain output.

SCL

O, OPEN Drain External 2 kΩ to 5 kΩ pull-up resistor to VDD or VIN recommended as

per SMBus interface standards⁽²⁾

In both SMBus Modes, this pin is the SMBus data I/O. Data input or

I, LVCMOS,

open drain output.

SDA

O, OPEN Drain External 2 kΩ to 5 kΩ pull-up resistor to VDD or VIN recommended as

per SMBus interface standards⁽²⁾

SMBus Slave Address Inputs. In both SMBus Modes, these pins are the

user set SMBus slave address inputs.

External 1 kΩ pull-up or pull-down recommended.

AD0-AD3

54, 53, 47, 46

I, LVCMOS

Note: In Pin Mode, AD2 must be tied via external 1 kΩ to GND.

Reserved

For applications requiring Signal Detect status register read-back:

I, 4-LEVEL,

LVCMOS

● Leave Pin 21 floating.

RESERVED2

RESERVED3

● Write Reg 0x08[2] = 1 if Pin 21 is floating.

Otherwise, tie Pin 21 via external 1 kΩ to GND (External 1 kΩ to VDD is

also acceptable).

Reserved

I, 4-LEVEL,

LVCMOS

This input may be left floating, tied via 1 kΩ to VDD, or tied via 1 kΩ to

GND.

(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.

Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.

For 3.3 V mode operation, VIN pin input = 3.3 V and the logic "1" or "high" reference for the 4-level input is 3.3 V.

For 2.5 V mode operation, VDD pin output= 2.5 V and the logic "1" or "high" reference for the 4-level input is 2.5 V.

(2) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5 V mode or 3.3 V mode.

DS125BR820

www.ti.com.cn

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Pin Functions⁽¹⁾(continued)

PIN NAME

PIN NUMBER

I/O, TYPE

PIN DESCRIPTION

ENSMB = Float (SMBus MASTER MODE)

Clock output when loading EEPROM configuration, reverting to SMBus

clock input when EEPROM load is complete (ALL_DONE = 0).

I, LVCMOS,

SCL

SDA

O, OPEN Drain External 2 kΩ to 5 kΩ pull-up resistor to VDD or VIN recommended as

per SMBus interface standards⁽²⁾

In both SMBus Modes, this pin is the SMBus data I/O. Data input or

open drain output.

I, LVCMOS,

O, OPEN Drain External 2 kΩ to 5 kΩ pull-up resistor to VDD or VIN recommended as

per SMBus interface standards⁽²⁾

SMBus Slave Address Inputs. In both SMBus Modes, these pins are the

user set SMBus slave address inputs.

External 1 kΩ pull-up or pull-down recommended.

Note: In Pin Mode, AD2 must be tied via external 1 kΩ to GND.

A logic low on this pin starts the load from the external EEPROM⁽³⁾

Once EEPROM load is complete (ALL_DONE = 0), this pin functionality

remains as READ_EN. It does not revert to an SD_TH input.

AD0-AD3

54, 53, 47, 46

I, LVCMOS

READ_EN

I, LVCMOS

Reserved

For applications requiring Signal Detect status register read-back:

● Leave Pin 21 floating.

● Write Reg 0x08[2] = 1 if Pin 21 is floating.

Otherwise, tie Pin 21 via external 1 kΩ to GND (External 1 kΩ to VDD is

also acceptable).

I, 4-LEVEL,

LVCMOS

RESERVED2

Reserved

I, 4-LEVEL,

LVCMOS

RESERVED3

This input may be left floating, tied via 1 kΩ to VDD, or tied via 1 kΩ to

GND.

ENSMB = 0 (PIN MODE)

EQA and EQB pins control the level of equalization for the A-channels

and B-channels, respectively. The pins are defined as EQA and EQB

only when ENSMB is de-asserted (low). Each of the four A-channels

have the same level unless controlled by the SMBus control registers.

Likewise, each of the four B-channels have the same level unless

controlled by the SMBus control registers.

EQA

EQB

I, 4-LEVEL,

LVCMOS

When the device operates in Slave or Master Mode, the SMBus registers

independently control each lane, and the EQB pin is converted to an

AD3 input. See Table 4.

VODB[1:0] controls the output amplitude of the B-channels. The pins are

defined as VODB[1:0] only when ENSMB is de-asserted (low). Each of

the four B-channels have the same level unless controlled by the SMBus

control registers. When the device operates in Slave or Master Mode, the

SMBus registers provide independent control of each lane, and

VODB[1:0] pins are converted to AD0, AD1 inputs. See Table 5.

VODB0

VODB1

I, 4-LEVEL,

LVCMOS

VODA[1:0] controls the output amplitude of the A-channels. The pins are

defined as VODA[1:0] only when ENSMB is de-asserted (low). Each of

the four A-channels have the same level unless controlled by the SMBus

control registers. When the device operates in Slave or Master Mode, the

SMBus registers provide independent control of each lane and the

VODA[1:0] pins are converted to SCL and SDA. See Table 5.

VODA0

VODA1

I, 4-LEVEL,

LVCMOS

Reserved in Pin Mode (ENSMB = 0)

This input must be tied via external 1 kΩ to GND.

AD2

I, LVCMOS

Controls the internal Signal Detect Status Threshold value when in Pin

Mode and SMBus Slave Mode. This pin is to be used for system

debugging only. See Table 3 for more information.

For final designs, input can be left floating, tied via 1 kΩ to VDD, or tied

via 1 kΩ to GND.

I, 4-LEVEL,

LVCMOS

SD_TH

I, 4-LEVEL,

LVCMOS

Reserved

RESERVED2

RESERVED3

Tie via external 1 kΩ to GND (External 1 kΩ to VDD is also acceptable).

I, 4-LEVEL,

LVCMOS

Reserved

This input must be tied via external 1 kΩ to GND.

(3) When READ_EN is low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to an invalid

or blank hex file, the DS125BR820 hangs indefinitely in an unknown state. ALL_DONE pin remains high in this situation.

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Pin Functions⁽¹⁾(continued)

PIN NAME

PIN NUMBER

I/O, TYPE

PIN DESCRIPTION

CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS)

The RXDET pin controls the input enable function. Depending on the

input level, a 50 Ω or >50 kΩ termination to the power rail is enabled.

Pull up pin to VDD (2.5 V mode) or VIN (3.3 V mode) through 1 kΩ

resistor to provide a 50 Ω termination to the power rail for normal

operation.

I, 4-LEVEL,

LVCMOS

RXDET

See Table 2.

I, 4-LEVEL,

LVCMOS

Reserved

This input must be left floating.

RESERVED1

VDD_SEL

Controls the internal regulator

Float = 2.5 V mode

I, FLOAT

Tie to GND = 3.3 V mode

Tie High = Low power - Power Down

Tie to GND = Normal Operation

See Table 2.

PWDN

I, LVCMOS

O, LVCMOS

Valid Register Load Status Output

HIGH = External EEPROM load failed or incomplete

LOW = External EEPROM load passed

ALL_DONE

POWER

In 3.3 V mode, feed 3.3 V to VIN

In 2.5 V mode, leave floating.

VIN

Power

Power Supply for CML and Analog Pins

2.5 V mode, connect to 2.5 V

VDD

GND

9, 14, 36, 41, 51

DAP

Power

3.3 V mode, connect 0.1 µF cap to each VDD Pin and GND

See Power Supply Recommendations for proper power supply

decoupling .

Ground pad (DAP - die attach pad).

DS125BR820

www.ti.com.cn

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

-0.5

-30

MAX

+2.75

+4.0

UNIT

Supply Voltage (VDD to GND, 2.5 V Mode)

Supply Voltage (VIN to GND, 3.3 V Mode)

LVCMOS Input/Output Voltage

CML Input Voltage

+4.0

VDD + 0.5

+30

CML Input Current

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other

conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions

indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum

Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.

6.2 Handling Ratings

MIN

MAX

125

UNIT

°C

T_stg

Storage temperature range

-40

T_solder

Lead Temperature Range Soldering (4 sec.)⁽¹⁾

260

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

-4000

-1000

4000

pins⁽²⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽³⁾

1000

(1) For soldering specifications: See application note SNOA549.

(2) JEDEC document JEP155 states that 4000-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 1000-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.375

3.0

TYP

2.5

MAX

2.625

3.6

UNIT

Supply Voltage (2.5 V mode)⁽¹⁾

Supply Voltage (3.3 V mode)⁽¹⁾

Ambient Temperature

3.3

-40

+85

°C

SMBus (SDA, SCL)

3.6

Supply Noise up to 50 MHz⁽²⁾

100

mVp-p

(1) DC plus AC power should not exceed these limits.

(2) Allowed supply noise (mVp-p sine wave) under typical conditions.

6.4 Thermal Information

DS125BR820

WQFN

54 PINS

26.6

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJCtop

R_θJB

10.8

4.4

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

4.3

R_θJCbot

1.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

6.5 Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

EQ = Level 4, VOD = Level 6

RXDET = 1, PWDN = 0

Current Consumption, 2.5 V Mode

220

280

I_DD

EQ = Level 4, VOD = Level 6

RXDET = 1, PWDN = 0

Current Consumption, 3.3 V Mode

Power Down Current Consumption

PWDN = 1

V_DD

Integrated LDO Regulator

V_IN= 3.0 - 3.6 V

2.375

2.5

2.625

LVCMOS / LVTTL DC SPECIFICATIONS

V_IH25

V_IH33

V_IL

High Level Input Voltage

Low Level Input Voltage

2.5 V Supply Mode

3.3 V Supply Mode

1.7

V_DD

V_IN

0.7

High Level Output Voltage

(ALL_DONE pin)

V_OH

V_OL

I_IH

I_OH= −4mA

2.0

Low Level Output Voltage

(ALL_DONE pin)

I_OL= 4mA

0.4

+15

V_IN= 3.6 V,

LVCMOS = 3.6 V

Input High Current (PWDN pin)

Input Low Current (PWDN pin)

-15

µA

V_IN= 3.6 V,

LVCMOS = 0 V

I_IL

4-LEVEL INPUT DC SPECIFICATIONS

Input High Current with internal

resistors

V_IN= 3.6 V,

LVCMOS = 3.6 V

I_IH

+20

+150

-40

µA

(4–level input pin)

Input Low Current with internal

resistors

V_IN= 3.6 V,

LVCMOS = 0 V

I_IL

-160

(4–level input pin)

Voltage Threshold from Pin Mode

Level 0 to R

0.50

1.25

2.00

0.66

1.65

2.64

V_DD= 2.5 V (2.5 V supply mode)

Internal LDO Disabled

See Table 1 for details

Voltage Threshold from Pin Mode

Level R to F

Voltage Threshold from Pin Mode

Level F to 1

V_TH

Voltage Threshold from Pin Mode

Level 0 to R

V_IN= 3.3 V (3.3 V supply mode)

Internal LDO Enabled

See Table 1 for details.

Voltage Threshold from Pin Mode

Level R to F

Voltage Threshold from Pin Mode

Level F to 1

CML RECEIVER INPUTS (IN_n+, IN_n-)

Z_Rx-DIFF-DCRx DC differential mode impedance

Z_Rx-DC

Tested at VDD = 2.5 V

SDD11 10 MHz

100

120

Ω

Rx DC single ended impedance

Rx Differential Input return loss

Rx Common mode return loss

-19

-14

-8

RL_Rx-DIFF

SDD11 2 GHz

SDD11 6-11.1 GHz

SCC11 0.05 - 5 GHz

RL_Rx-CM

-10

Signal detect assert level for active

data signal

SD_TH = F (float),

1010 pattern at 12 Gbps

V_{Rx-ASSERT-DIFF-PP}

mVp-p

V_{Rx-DEASSERT-DIFF-}Signal detect de-assert for inactive

SD_TH = F (float),

1010 pattern at 12 Gbps

mVp-p

signal level

DS125BR820

www.ti.com.cn

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HIGH SPEED OUTPUTS

SDD22 10 MHz - 2 GHz

SDD22 5.5 GHz

-15

-12

-10

-8

RL_Tx-DIFF

Tx Differential return loss

SDD22 11.1 GHz

Ω

RL_Tx-CM

Tx Common mode return loss

DC differential Tx impedance

SCC22 50 MHz- 2.5 GHz

Z_Tx-DIFF-DC

100

Total current when output is

shorted to VDD or GND

I_Tx-SHORT

Transmitter short circuit current limit

V_{Tx-CM-DC-LINE-}

DELTA

Absolute delta of DC common mode

voltage between Tx+ and Tx-

Differential measurement with

OUT_n+ and OUT_n-,

AC-Coupled and terminated by

50 Ω to GND,

V_Tx-DIFF1-PP

V_Tx-DIFF2-PP

V_Tx-DIFF3-PP

Output Voltage Differential Swing

Inputs AC-Coupled,

Measured with 8T Pattern at 12

Gbps⁽¹⁾

615

mVp-p

VID = 600 mVp-p

VOD = Level 6⁽²⁾⁽³⁾

Differential measurement with

OUT_n+ and OUT_n-,

AC-Coupled and terminated by

50 Ω to GND,

Inputs AC-Coupled,

Measured with 8T Pattern at 12

Gbps⁽¹⁾

950

VID = 1000 mVp-p

VOD = Level 6⁽²⁾⁽³⁾

Differential measurement with

OUT_n+ and OUT_n-,

AC-Coupled and terminated by

50 Ω to GND,

Inputs AC-Coupled,

Measured with 8T Pattern at 12

Gbps⁽¹⁾

1100

VID = 1200 mVp-p

VOD = Level 6⁽²⁾⁽³⁾

T_PDEQ

Differential propagation delay

AC common mode voltage

Tx disable output voltage

OOB idle output voltage

EQ = Level 1 to Level 4

VOD = Level 6, 12 Gbps

Driver disabled via PWDN

VID = 0 mVp-p

V_Tx-CM-AC-P

V_DISABLE-OUT

V_OOB-IDLE

mV rms

mVp-p

-30

OOB pattern, EQ = Level 1

VOD = Level 6

V_OOB-OS-DELTA

V_OOB-CM-DELTA

T_{Tx-IDLE-SET-TO-}

OOB offset delta

mVp-p

OOB pattern, EQ = Level 1

VOD = Level 6

OOB common mode delta

Time to transition to idle after

differential signal

VID = 1.0 Vp-p, 1.5 Gbps

0.70

0.04

IDLE

T_{Tx-IDLE-TO-DIFF-}

DATA

Time to transition to valid differential

signal after idle

(1) 8T pattern is defined as a 1111111100000000'b pattern bit sequence.

(2) ATE measurements for production are tested at DC.

(3) In 40G-CR4/KR4/SAS/SATA/PCIe applications, the output VOD level is not fixed. It adjusts automatically based on the VID input

amplitude level. The output VOD level set by VODA/B[1:0] depends on the VID level and the frequency content. The DS125BR820

repeater is designed to be transparent in this mode, so the Tx-FIR (de-emphasis) is passed to the Rx to support the handshake

negotiation link training.

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Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Evaluation Module (EVM) Only,

FR4,

VID = 800 mVp-p, EQ = Level 1

PRBS15, 12 Gbps

RJ_ADD

Additive Random Jitter

0.36

ps rms

VOD = Level 6

All other channels active

(4)

EQUALIZATION

5” Differential Stripline, 5mil trace

width, FR4,

DJE1

Residual deterministic jitter at 6 Gbps VID = 800 mVp-p,

PRBS15, EQ = Level 2,

0.06

0.12

UIp-p

VOD = Level 6

5” Differential Stripline, 5mil trace

width, FR4,

Residual deterministic jitter at 12

Gbps

DJE2

VID = 800 mVp-p,

PRBS15, EQ = Level 2,

VOD = Level 6

(4) Additive random jitter is given in RMS value by the following equation: RJ_ADD= √[(Output Jitter)²- (Input Jitter)²]. Typical input jitter for

these measurements is 150 fs rms.

6.6 Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SERIAL BUS INTERFACE DC SPECIFICATIONS

V_IL

Data, Clock Input Low Voltage

Data, Clock Input High Voltage

Output Low Voltage

0.8

3.6

V_IH

2.1

V_OL

V_DD

I_IH-Pin

I_IL-Pin

C_I

SDA or SCL, I_OL= 1.25 mA

0.36

3.6

Nominal Bus Voltage

2.375

+20

-160

Input Leakage Per Device Pin

Capacitance for SDA and SCL

+150

-40

µA

Ω

See⁽¹⁾⁽²⁾

Pullup V_DD= 3.3 V^(1)(2)(3)

Pullup V_DD= 2.5 V^(1)(2)(3)

< 5

External Termination Resistance

pull to V_DD= 2.5 V ± 5% OR 3.3 V

± 10%

2000

R_TERM

1000

Ω

(1) Recommended value.

(2) Recommended maximum capacitance load per bus segment is 400 pF.

(3) Maximum termination voltage should be identical to the device supply voltage.

6.7 Timing Requirements Serial Bus Interface

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SERIAL BUS INTERFACE TIMING SPECIFICATIONS

F_SMB

ENSMB = VDD (Slave Mode)

400

520

kHz

Bus Operating Frequency

ENSMB = FLOAT (Master Mode)

280

400

Read operation

RPU = 4.7 kΩ, Cb < 50 pF

t_FALL

t_RISE

SCL or SDA Fall Time

SCL or SDA Rise Time

Read operation

RPU = 4.7 kΩ, Cb < 50 pF

140

t_F

Clock/Data Fall Time

Clock/Data Rise Time

See⁽¹⁾

300

t_R

1000

Time in which a device must be

operational after power-on reset

t_POR

See⁽¹⁾

500

(1) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1

SMBus common AC specifications for details.

DS125BR820

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80%

20%

80%

20%

VOD = [Out+ - Out-]

RISE

FALL

Figure 1. Output Rise And Fall Transition Time

PHLD

PLHD

OUT

Figure 2. Propagation Delay Timing Diagram

DATA

DATA-IDLE

IDLE-DATA

OUT

DATA

IDLE

Figure 3. Transmit Idle-Data and Data-Idle Response Time

LOW

HIGH

SCL

SDA

SU:STA

HD:STA

HD:DAT

BUF

SU:STO

SU:DAT

Figure 4. SMBus Timing Parameters

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6.8 Typical Characteristics

1.4

1.3

1.2

1.1

VID = 0.6Vpp

VID = 0.8Vpp

VID = 1.0Vpp

VID = 1.2Vpp

590

VDD = 2.5 V

570

550

530

510

490

470

450

430

410

390

370

350

0.9

0.8

0.7

0.6

2.325

2.5

2.675

VDD (V)

VOD Level

C003

C006

Test Conditions

Data Rate, Test Pattern 1.5625 Gbps, 1010 Pattern

EQ Level 4

VOD Level 6

EQ Level 1

VOD_DB 000'b

25°C

Figure 5. Typical Power Dissipation vs. VOD

Figure 6. Typical VOD vs. VDD

1.4

1.3

1.2

1.1

1.4

1.2

VID = 0.6Vpp

VID = 0.8Vpp

VID = 1.0Vpp

VID = 1.2Vpp

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

0.8

0.6

0.4

0.2

0.9

0.8

0.7

0.6

-40

-15

0.2

0.4

0.6

0.8

1.2

1.4

Temperature (C)

Input Differential Voltage (Vpp)

C001

C005

Test Conditions

Data Rate, Test Pattern 1.5625 Gbps, 1010 Pattern

EQ Level 1

VOD Level 6

EQ Level 1

VDD 2.5 V

25°C

VDD 2.5 V

Figure 7. Typical VOD vs. Temperature

Figure 8. Typical VOD vs. VID

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7 Detailed Description

7.1 Overview

The DS125BR820 provides linear equalization for lossy printed circuit board backplanes and balanced cables.

The DS125BR820 operates in three modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1)

and SMBus Master Mode (ENSMB = Float) to load register information from external EEPROM.

7.2 Functional Block Diagram

One channel of four A Channels

Term

RXDET

INA_n+

INA_n-

OUTA_n+

OUTA_n-

Pre-

driver

Driver

EN_SMB

EQA

VODA[1:0]

READ_EN

AD[3:0]

ALL_DONE

SCL

SDA

Internal voltage

regulator

Digital Core and SMBus Registers

PWDN

VDD_SEL

VIN

Term

RXDET

INB_n+

INB_n-

OUTB_n+

OUTB_n-

Pre-

driver

Driver

EN_SMB

EQB

VODB[1:0]

One channel of four B Channels

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Functional Block Diagram (continued)

7.2.1 Functional Datapath Blocks

In an increasing number of high speed applications, transparency between Tx and Rx endpoints is essential to

ensure high signal integrity. The DS125BR820 channel datapath uses one input gain stage equalization coupled

with a linear driver. This combination provides a high level of transparency, thereby achieving greater drive

distance in applications such as 40G-CR4, 40G-KR4, SAS, SATA, and PCIe that require Rx-Tx auto-negotiation

and link-training. Refer to the Typical Applications section for more application information regarding

recommended settings and placement.

7.3 Feature Description

The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of

control settings when ENSMB = 0. There is an internal 30 kΩ pull-up and a 60 kΩ pull-down connected to the

package pin. These resistors, together with the external resistor connection, combine to achieve the desired

voltage level. By using the 1 kΩ pull-down, 20 kΩ pull-down, no connect, and 1 kΩ pull-up, the optimal voltage

levels for each of the four input states are achieved as shown in Table 1.

Table 1. 4–Level Control Pin Settings

Resulting Pin Voltage

Level

Setting

3.3 V Mode

0.10 V

2.5 V Mode

0.08 V

Tie 1 kΩ to GND

Tie 20 kΩ to GND

Float (leave pin open)

Tie 1 kΩ to V_INor V_DD

1/3 x V_IN

2/3 x V_IN

V_IN- 0.05 V

1/3 x V_DD

2/3 x V_DD

V_DD- 0.04 V

Typical 4-Level Input Thresholds

•

Internal Threshold between 0 and R = 0.2 * V_INor V_DD

Internal Threshold between R and F = 0.5 * V_INor V_DD

Internal Threshold between F and 1 = 0.8 * V_INor V_DD

In order to minimize the startup current associated with the integrated 2.5 V regulator, the 1 kΩ pull-up / pull-

down resistors are recommended. If several four level inputs require the same setting, it is possible to combine

two or more 1 kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single

500 Ω resistor is a valid way to save board space.

7.4 Device Functional Modes

7.4.1 Pin Control Mode:

When in Pin Mode (ENSMB = 0), equalization and VOD (output amplitude) can be selected via pin control for

both the A-channels and B-channels per Table 4. The RXDET pin provides either automatic or manual control for

input termination (50 Ω or > 50 kΩ to VDD). The receiver electrical signal detect status threshold is adjustable via

the SD_TH pin. By setting signal-detect threshold level via the SD_TH pin, status information about a valid signal

detect assert/de-assert can be read back via SMBus registers. Pin control mode is ideal in situations where

neither MCU or EEPROM is available to access the device via SMBus SDA/SCL lines.

7.4.2 Slave SMBus Mode:

When in Slave SMBus Mode (ENSMB = 1), the VOD (output amplitude), equalization, and termination disable

features are all programmable on an individual channel basis, rather than in collective A-channel and B-channel

groups. Upon assertion of ENSMB, the EQx and VODx settings are controlled by SMBus immediately. It is

important to note that SMBus settings can only be changed from their defaults after asserting Register Enable by

setting Reg 0x06[3] = 1. The EQx and VODx pins are subsequently converted to AD0-AD3 SMBus address

inputs. The other external control pins (RXDET and SD_TH) remain active unless their respective registers are

written to and the appropriate override bit is set. If the user overrides a pin control, the input voltage level of that

control pin is ignored until ENSMB is driven low (Pin Mode). In the event that channels are powered down via the

PWDN pin, the state of all register settings are not affected.

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Device Functional Modes (continued)

Table 2. Rx Detect Settings

PWDN⁽¹⁾

(Pin 52)

RXDET

(Pin 22)

SMBus REG

Bit[3:2]

INPUT

TERMINATION

RECOMMENDED

USE

COMMENTS

Hi-Z

Manual Rx-Detect, input is Hi-Z

Auto Rx-Detect, outputs test every 12 ms for 600

ms then stops; termination is Hi-Z until Rx

detection; once detected input termination is 50 Ω

Reset function by pulsing PWDN high for 5 µs then

low again

Pre Detect: Hi-Z

Post Detect: 50 Ω

PCIe Only

Auto Rx-Detect, outputs test every 12 ms until

detection occurs; termination is Hi-Z until Rx

detection; once detected input termination is 50 Ω

Pre Detect: Hi-Z

Post Detect: 50 Ω

(Default)

40G-

CR4/SR4/LR4

SAS/SATA

Manual Rx-Detect, input is 50 Ω

For 40G-CR4/SR4/LR4/SAS/SATA applications, it

is required to use this setting.

50 Ω

Power Down mode, input is Hi-Z, output drivers

are disabled

Hi-Z

Used to reset Rx-Detect State Machine when held

high for 5 µs

(1) In SMBus Slave Mode, the Rx Detect State Machine can be manually reset in software by overriding the device PRSNT function. This is

accomplished by setting the Override PRSNT bit (Reg 0x02[7]) and then toggling the PRSNT value bit (Reg 0x02[6]). See Table 9 for

more information about resetting the Rx Detect State Machine.

Table 3. Signal Detect Status Threshold Level⁽¹⁾⁽²⁾

SD_TH

(Pin 26)

SMBus REG BIT[3:2]

and[1:0]

[3:2] ASSERT LEVEL

(mVp-p)

[1:0] DE-ASSERT LEVEL

(mVp-p)

Level

3 Gbps

12 Gbps

3 Gbps

12 Gbps

F (default)

(1) VDD = 2.5 V, 25°C, 11 00 11 00 pattern at 3 Gbps and 101010 pattern at 12 Gbps

(2) Signal detect status threshold sets the value at which a signal detect status is flagged via SMBus Reg 0x0A. Regardless of the threshold

level, the output always remains enabled unless manually powered down.

7.4.3 SMBus Master Mode

When in SMBus Master Mode (ENSMB = Float), the VOD (output amplitude), equalization, and termination

disable features for multiple devices can be loaded via external EEPROM. By asserting a Float condition on the

ENSMB pin, an external EEPROM writes register settings to each device in accordance with its SMBus slave

address. The settings programmable by external EEPROM provide only a subset of all the register bits available

via SMBus Slave Mode, and the bit-mapping between SMBus Slave Mode registers and Master SMBus registers

can be referenced in Table 6. Once the EEPROM successfully finishes loading each device's register settings,

the device reverts back to SMBus Slave Mode and releases SDA/SCL control to an external master MCU. If the

EEPROM fails to load settings to a particular device, for example due to an invalid or blank hex file, a time-out

occurs and the device hangs in an unknown state.

7.5 Signal Conditioning Settings

Equalization and VOD settings accessible via the pin controls are chosen to meet the needs of most high speed

applications. These settings can also be controlled via the SMBus registers. Each pin input has a total of four

possible voltage level settings. Table 4 and Table 5 show both the Pin Mode and SMBus Mode settings that are

used in order to program the equalization and VOD gain for each DS125BR820 channel.

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Signal Conditioning Settings (continued)

Table 4. Equalizer Settings⁽¹⁾⁽²⁾

EQUALIZATION BOOST RELATIVE TO DC

EQA⁽³⁾

EQB

dB at

1.5 GHz

dB at

2.5 GHz

dB at

4 GHz

dB at

5 GHz

dB at

6 GHz

Level

EQ – 8 bits[7:0]

xxxx xx00 = 0x00

xxxx xx01 = 0x01

xxxx xx10 = 0x02

xxxx xx11 = 0x03

2.1

4.0

5.5

6.8

2.5

5.1

7.0

8.3

2.7

6.4

8.3

9.5

2.9

6.8

8.6

9.6

3.0

7.4

8.9

9.8

(1) Optimal EQ setting should be determined via simulation and prototype verification.

(2) Equalization boost values are inclusive of package loss.

(3) To program EQ Level 1-4 correctly in Pin Mode, RESERVED3 and AD2 pins must be tied via 1 kΩ resistor to GND.

Table 5. Output Voltage Settings⁽¹⁾

VODA1

VODB1

VODA0

VODB0

VOD_DB - 3

bits[2:0]

Level

VOD - 3 bits[2:0]

VID Vp-p

VOD/VID Ratio⁽¹⁾

000'b

001'b

010'b

011'b

100'b

101'b

110'b

111'b

000'b

1.2

0.57⁽²⁾

0.65

0.71

0.77

0.83

0.90

1.00

1.04⁽²⁾⁽³⁾

(1) For 40G-CR4/KR4/SAS/SATA/PCIe operation, it is important to keep the output amplitude and dynamic range as large as possible.

When operating in Pin Mode, it is recommended to use VODA[1:0] = VODB[1:0] = Level 6. In SMBus Mode, it is also recommended to

use Level 6 (that is, VOD = 110'b and VOD_DB = 000'b).

(2) These VOD settings are only accessible via SMBus Modes.

(3) VOD = 111'b setting in SMBus Mode is not recommended.

DS125BR820

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7.6 Programming

The DS125BR820 device supports reading directly from an external EEPROM device by implementing SMBus

Master Mode. When using SMBus Master Mode, the DS125BR820 reads directly from specific location in the

external EEPROM. When designing a system for using the external EEPROM, the user must follow these

specific guidelines.

•

Maximum EEPROM size is 8K (1024 x 8-bit).

Set ENSMB = Float — enable the SMBus Master Mode.

The external EEPROM device address byte must be 0xA0 and capable of 1 MHz operation at 2.5 V and 3.3

V supply.

•

Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.

When tying multiple DS125BR820 devices to the SDA and SCL bus, use these guidelines to configure the

devices:

•

Use SMBus AD[3:0] address bits so that each device can load its configuration from the EEPROM. Example

below is for four devices. The first device in the sequence is conventionally address 0xB0, while subsequent

devices follow the address order listed below.

–

U1: AD[3:0] = 0000 = 0xB0,

U2: AD[3:0] = 0001 = 0xB2,

U3: AD[3:0] = 0010 = 0xB4,

U4: AD[3:0] = 0011 = 0xB6

•

Use a pull-up resistor on SDA and SCL; value = 2 kΩ to 5 kΩ

Daisy-chain READ_EN (Pin 26) and ALL_DONE (Pin 27) from one device to the next device in the sequence

so that they do not compete for the EEPROM at the same time.

1. Tie READ_EN of the first device in the chain (U1) to GND.

2. Tie ALL_DONE of U1 to READ_EN of U2.

3. Tie ALL_DONE of U2 to READ_EN of U3.

4. Tie ALL_DONE of U3 to READ_EN of U4.

5. Optional: Tie ALL_DONE output of U4 to a LED to show the devices have been loaded successfully.

Once the ALL_DONE status pin of the last device is flagged to indicate that all devices sharing the SMBus line

have been successfully programmed, control of the SMBus line is released by the repeater and the device

reverts back to SMBus Slave Mode. At this point, an external MCU can perform any additional Read or Write

operations.

Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS125BR820 device. The first

three bytes of the EEPROM always contain a base header common and necessary to control initialization of all

devices connected to the I2C bus. The CRC enable flag is used to enable or disable CRC checking. If CRC

checking is disabled, a fixed pattern (8’hA5) is written/read instead of the CRC byte from the CRC location to

simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration

data start address in the EEPROM. If the MAP bit is not present, the configuration data start address is assumed

to follow the base header directly. Lastly, one bit in the base header is used to indicate whether EEPROM size >

256 bytes. This bit ensures that EEPROM slot addresses are formatted properly as one byte (EEPROM ≤ 256

bytes) or two bytes (EEPROM > 256 bytes) for subsequent address map headers. There are 37 bytes of data for

each DS125BR820 device.

:2000000000001000000407002FAD4002FAD4002FAD4002FAD409805F5A8005F5A8005F5AD0

:200020008005F5A800005454000000000000000000000000000000000000000000000000F6

:20006000000000000000000000000000000000000000000000000000000000000000000080

:20008000000000000000000000000000000000000000000000000000000000000000000060

:2000A000000000000000000000000000000000000000000000000000000000000000000040

:2000C000000000000000000000000000000000000000000000000000000000000000000020

:2000E000000000000000000000000000000000000000000000000000000000000000000000

:200040000000000000000000000000000000000000000000000000000000000000000000A0

Note: The maximum EEPROM size supported is 8 kbits (1024 x 8 bits).

7.6.1 EEPROM Register Map for Single Device

A detailed EEPROM Register Map for a single device is shown in Table 6. For instances where multiple devices

are written to EEPROM, the device starting address definitions align starting with Table 6 Byte 0x03.

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Bit 0

Table 6. EEPROM Register Map - Single Device With Default Value

EEPROM Address Byte

Bit 7

CRC_EN

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

DEVICE

COUNT[1]

Address Map

Present

EEPROM > 256

Bytes

DEVICE

COUNT[0]

Description

0x00

Reserved

COUNT[3]

COUNT[2]

Default

0x00

Value

Description

Reserved

0x01

0x02

Default

Value

0x00

Max EEPROM

Burst size[7]

Max EEPROM

Burst size[6]

Max EEPROM

Burst size[5]

Max EEPROM

Burst size[4]

Max EEPROM

Burst size[3]

Max EEPROM

Burst size[2]

Max EEPROM

Burst size[1]

Max EEPROM

Burst size[0]

Description

Default

Value

Description

PWDN_CH7

0x01[7]

PWDN_CH6

0x01[6]

PWDN_CH5

0x01[5]

PWDN_CH4

0x01[4]

PWDN_CH3

0x01[3]

PWDN_CH2

0x01[2]

PWDN_CH1

0x01[1]

PWDN_CH0

0x01[0]

SMBus Register

Default

Value

0x03

0x04

0x05

0x06

0x07

0x08

0x00

Description

SMBus Register

Default

Reserved

0x02[5]

Reserved

0x02[4]

Reserved

0x02[3]

Reserved

0x02[2]

Ovrd_PWDN

0x02[0]

Reserved

0x04[7]

Reserved

0x04[6]

Reserved

0x04[5]

0x00

Value

Description

SMBus Register

Default

Reserved

0x04[4]

Reserved

0x04[3]

Reserved

0x04[2]

Reserved

0x04[1]

Reserved

0x04[0]

Reserved

0x06[4]

Ovrd_SD_TH

0x08[6]

Reserved

0x08[5]

0x04

Value

Description

SMBus Register

Default

Reserved

0x08[4]

Ovrd_RXDET

0x08[3]

Reserved

0x08[2]

Reserved

0x08[1]

Reserved

0x08[0]

Reserved

0x0B[6]

Reserved

0x0B[5]

Reserved

0x0B[4]

0x07

Value

Description

SMBus Register

Default

Reserved

0x0B[3]

Reserved

0x0B[2]

Reserved

0x0B[1]

Reserved

0x0B[0]

Reserved

0x0E[5]

Reserved

0x0E[4]

CH0_RXDET_1

0x0E[3]

CH0_RXDET_0

0x0E[2]

0x00

Value

Description

SMBus Register

Default

Reserved

0x0F[7]

Reserved

0x0F[6]

Reserved

0x0F[5]

Reserved

0x0F[4]

Reserved

0x0F[3]

Reserved

0x0F[2]

CH0_EQ_1

0x0F[1]

CH0_EQ_0

0x0F[0]

0x2F

Value

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Table 6. EEPROM Register Map - Single Device With Default Value (continued)

EEPROM Address Byte

Bit 7

CH0_SCP

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Description

Reserved

CH0_VOD_2

0x10[2]

CH0_VOD_1

0x10[1]

CH0_VOD_0

0x10[0]

SMBus Register

0x10[7]

0x10[6]

0x10[5]

0x10[4]

0x10[3]

0x09

Default

0xAD

Value

Description

CH0_VOD_DB_2 CH0_VOD_DB_1 CH0_VOD_DB_0 Reserved

CH0_THa_1

0x12[3]

CH0_THa_0

0x12[2]

CH0_THd_1

0x12[1]

CH0_THd_0

0x12[0]

SMBus Register

0x11[2]

0x11[1]

0x11[0]

0x12[7]

0x0A

Default

0x40

Value

Description

Reserved

0x15[5]

Reserved

0x15[4]

CH1_RXDET_1

0x15[3]

CH1_RXDET_0

0x15[2]

Reserved

0x16[7]

Reserved

0x16[6]

Reserved

0x16[5]

Reserved

0x16[4]

SMBus Register

0x0B

Default

0x02

Value

Description

Reserved

0x16[3]

Reserved

0x16[2]

CH1_EQ_1

0x16[1]

CH1_EQ_0

0x16[0]

CH1_SCP

0x17[7]

Reserved

0x17[6]

Reserved

0x17[5]

Reserved

0x17[4]

SMBus Register

0x0C

Default

0xFA

Value

Description

Reserved

0x17[3]

CH1_VOD_2

0x17[2]

CH1_VOD_1

0x17[1]

CH1_VOD_0

0x17[0]

CH1_VOD_DB_2 CH1_VOD_DB_1 CH1_VOD_DB_0 Reserved

SMBus Register

0x18[2]

0x18[1]

0x18[0]

0x19[7]

0x0D

Default

0xD4

Value

Description

CH1_THa_1

0x19[3]

CH1_THa_0

0x19[2]

CH1_THd_1

0x19[1]

CH1_THd_0

0x19[0]

Reserved

0x1C[5]

Reserved

0x1C[4]

CH2_RXDET_1

0x1C[3]

CH2_RXDET_0

0x1C[2]

SMBus Register

0x0E

Default

0x00

Value

Description

Reserved

0x1D[7]

Reserved

0x1D[6]

Reserved

0x1D[5]

Reserved

0x1D[4]

Reserved

0x1D[3]

Reserved

0x1D[2]

CH2_EQ_1

0x1D[1]

CH2_EQ_0

0x1D[0]

SMBus Register

0x0F

Default

0x2F

Value

Description

CH2_SCP

0x1E[7]

Reserved

0x1E[6]

Reserved

0x1E[5]

Reserved

0x1E[4]

Reserved

0x1E[3]

CH2_VOD_2

0x1E[2]

CH2_VOD_1

0x1E[1]

CH2_VOD_0

0x1E[0]

SMBus Register

0x10

Default

0xAD

Value

DS125BR820

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www.ti.com.cn

Bit 0

Table 6. EEPROM Register Map - Single Device With Default Value (continued)

EEPROM Address Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

CH2_THa_1

0x20[3]

Bit 2

CH2_THa_0

0x20[2]

Bit 1

CH2_THd_1

0x20[1]

Description

CH2_VOD_DB_2 CH2_VOD_DB_1 CH2_VOD_DB_0 Reserved

CH2_THd_0

SMBus Register

0x1F[2]

0x1F[1]

0x1F[0]

0x20[7]

0x20[0]

0x11

Default

0x40

Value

Description

Reserved

0x23[5]

Reserved

0x23[4]

CH3_RXDET_1

0x23[3]

CH3_RXDET_0

0x23[2]

Reserved

0x24[7]

Reserved

0x24[6]

Reserved

0x24[5]

Reserved

0x24[4]

SMBus Register

0x12

Default

0x02

Value

Description

Reserved

0x24[3]

Reserved

0x24[2]

CH3_EQ_1

0x24[1]

CH3_EQ_0

0x24[0]

CH3_SCP

0x25[7]

Reserved

0x25[6]

Reserved

0x25[5]

Reserved

0x25[4]

SMBus Register

0x13

Default

0xFA

Value

Description

Reserved

0x25[3]

CH3_VOD_2

0x25[2]

CH3_VOD_1

0x25[1]

CH3_VOD_0

0x25[0]

CH3_VOD_DB_2 CH3_VOD_DB_1 CH3_VOD_DB_0 Reserved

SMBus Register

0x26[2]

0x26[1]

0x26[0]

0x27[7]

0x14

Default

0xD4

Value

Description

CH3_THa_1

0x27[3]

CH3_THa_0

0x27[2]

CH3_THd_1

0x27[1]

CH3_THd_0

0x27[0]

Reserved

0x28[6]

hi_idle_SD CH0-3 hi_idle_SD CH4-7 fast_SD CH0-3

SMBus Register

0x28[5]

0x28[4]

0x28[3]

0x15

Default

0x09

Value

Description

fast_SD CH4-7

0x28[2]

lo_gain_SD CH0-3 lo_gain_SD CH4-7 Reserved

Reserved

0x2B[4]

CH4_RXDET_1

0x2B[3]

CH4_RXDET_0

0x2B[2]

Reserved

0x2C[7]

SMBus Register

0x28[1]

0x28[0]

0x2B[5]

0x16

Default

0x80

Value

Description

Reserved

0x2C[6]

Reserved

0x2C[5]

Reserved

0x2C[4]

Reserved

0x2C[3]

Reserved

0x2C[2]

CH4_EQ_1

0x2C[1]

CH4_EQ_0

0x2C[0]

CH4_SCP

0x2D[7]

SMBus Register

0x17

Default

0x5F

Value

Description

Reserved

0x2D[6]

Reserved

0x2D[5]

Reserved

0x2D[4]

Reserved

0x2D[3]

CH4_VOD_2

0x2D[2]

CH4_VOD_1

0x2D[1]

CH4_VOD_0

0x2D[0]

CH4_VOD_DB_2

0x2E[2]

SMBus Register

0x18

Default

0x5A

Value

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 6. EEPROM Register Map - Single Device With Default Value (continued)

EEPROM Address Byte

Bit 7

Bit 6

Bit 5

Bit 4

CH4_THa_1

0x2F[3]

Bit 3

CH4_THa_0

0x2F[2]

Bit 2

CH4_THd_1

0x2F[1]

Bit 1

CH4_THd_0

0x2F[0]

Bit 0

Reserved

Description

CH4_VOD_DB_1 CH4_VOD_DB_0 Reserved

SMBus Register

0x2E[1]

0x2E[0]

0x2F[7]

0x32[5]

0x19

Default

0x80

Value

Description

Reserved

0x32[4]

CH5_RXDET_1

0x32[3]

CH5_RXDET_0

0x32[2]

Reserved

0x33[7]

Reserved

0x33[6]

Reserved

0x33[5]

Reserved

0x33[4]

Reserved

0x33[3]

SMBus Register

0x1A

Default

0x05

Value

Description

Reserved

0x33[2]

CH5_EQ_1

0x33[1]

CH5_EQ_0

0x33[0]

CH5_SCP

0x34[7]

Reserved

0x34[6]

Reserved

0x34[5]

Reserved

0x34[4]

Reserved

0x34[3]

SMBus Register

0x1B

Default

0xF5

Value

Description

CH5_VOD_2

0x34[2]

CH5_VOD_1

0x34[1]

CH5_VOD_0

0x34[0]

CH5_VOD_DB_2 CH5_VOD_DB_1 CH5_VOD_DB_0 Reserved

CH5_THa_1

0x36[3]

SMBus Register

0x35[2]

0x35[1]

0x35[0]

0x36[7]

0x1C

Default

0xA8

Value

Description

CH5_THa_0

0x36[2]

CH5_THd_1

0x36[1]

CH5_THd_0

0x36[0]

Reserved

0x39[5]

Reserved

0x39[4]

CH6_RXDET_1

0x39[3]

CH6_RXDET_0

0x39[2]

Reserved

0x3A[7]

SMBus Register

0x1D

Default

0x00

Value

Description

Reserved

0x3A[6]

Reserved

0x3A[5]

Reserved

0x3A[4]

Reserved

0x3A[3]

Reserved

0x3A[2]

CH6_EQ_1

0x3A[1]

CH6_EQ_0

0x3A[0]

CH6_SCP

0x3B[7]

SMBus Register

0x1E

Default

0x5F

Value

Description

Reserved

0x3B[6]

Reserved

0x3B[5]

Reserved

0x3B[4]

Reserved

0x3B[3]

CH6_VOD_2

0x3B[2]

CH6_VOD_1

0x3B[1]

CH6_VOD_0

0x3B[0]

CH6_VOD_DB_2

0x3C[2]

SMBus Register

0x1F

Default

0x5A

Value

Description

CH6_VOD_DB_1 CH6_VOD_DB_0 Reserved

CH6_THa_1

0x3D[3]

CH6_THa_0

0x3D[2]

CH6_THd_1

0x3D[1]

CH6_THd_0

0x3D[0]

Reserved

0x40[5]

SMBus Register

0x3C[1]

0x3C[0]

0x3D[7]

0x20

Default

0x80

Value

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Bit 0

Table 6. EEPROM Register Map - Single Device With Default Value (continued)

EEPROM Address Byte

Bit 7

Reserved

Bit 6

CH7_RXDET_1

0x40[3]

Bit 5

CH7_RXDET_0

0x40[2]

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Description

Reserved

SMBus Register

0x40[4]

0x41[7]

0x41[6]

0x41[5]

0x41[4]

0x41[3]

0x21

Default

0x05

Value

Description

Reserved

0x41[2]

CH7_EQ_1

0x41[1]

CH7_EQ_0

0x41[0]

CH7_SCP

0x42[7]

Reserved

0x42[6]

Reserved

0x42[5]

Reserved

0x42[4]

Reserved

0x42[3]

SMBus Register

0x22

Default

0xF5

Value

Description

CH7_VOD_2

0x42[2]

CH7_VOD_1

0x42[1]

CH7_VOD_0

0x42[0]

CH7_VOD_DB_2 CH7_VOD_DB_1 CH7_VOD_DB_0 Reserved

CH7_THa_1

0x44[3]

SMBus Register

0x43[2]

0x43[1]

0x43[0]

0x44[7]

0x23

Default

0xA8

Value

Description

CH7_THa_0

0x44[2]

CH7_THd_1

0x44[1]

CH7_THd_0

0x44[0]

Reserved

0x47[3]

Reserved

0x47[2]

Reserved

0x47[1]

Reserved

0x47[0]

Reserved

0x48[7]

SMBus Register

0x24

Default

0x00

Value

Description

Reserved

0x48[6]

Reserved

0x4C[7]

Reserved

0x4C[6]

Reserved

0x4C[5]

Reserved

0x4C[4]

Reserved

0x4C[3]

Reserved

0x4C[0]

Reserved

0x59[0]

SMBus Register

0x25

Default

0x00

Value

Description

Reserved

0x5A[7]

Reserved

0x5A[6]

Reserved

0x5A[5]

Reserved

0x5A[4]

Reserved

0x5A[3]

Reserved

0x5A[2]

Reserved

0x5A[1]

Reserved

0x5A[0]

SMBus Register

0x26

Default

0x54

Value

Description

Reserved

0x5B[7]

Reserved

0x5B[6]

Reserved

0x5B[5]

Reserved

0x5B[4]

Reserved

0x5B[3]

Reserved

0x5B[2]

Reserved

0x5B[1]

Reserved

0x5B[0]

SMBus Register

0x27

Default

0x54

Value

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 7. Example Of EEPROM For Four Devices Using Two Address Maps

EEPROM

Address

Address (Hex)

EEPROM Data

Comments

0x43

0x00

0x10

0x00

0x0B

0x00

0x0B

0x00

0x30

0x00

0x30

0x00

0x04

0x07

0x00

0x01

0xAD

0x00

0x1A

0xD0

0x00

0x01

0xAD

0x00

0x1A

0xD0

0x09

0x80

0x07

0x5C

0x00

0x15

0xC0

0x00

0x07

0x5C

0x00

0x75

0xC0

0x00

0x54

CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3

EEPROM Burst Size

CRC not used

Device 0 Address Location

CRC not used

Device 1 Address Location

CRC not used

Device 2 Address Location

CRC not used

Device 3 Address Location

Begin Device 0, 1 - Address Offset 3

EQ CHB0 = 0x01

VOD CHB0 = 101'b

VOD_DB CHB0 = 000'b

EQ CHB1 = 0x01

VOD CHB1 = 101'b, VOD_DB CHB1 = 000'b

EQ CHB2 = 0x01

VOD CHB2 = 101'b

VOD_DB CHB2 = 000'b

EQ CHB3 = 0x01

VOD CHB3 = 101'b, VOD_DB CHB3 = 000'b

Signal Detect Status Threshold Control

EQ CHA0 = 0x03

VOD CHA0 = 110'b

VOD_DB CHA0 = 000'b

EQ CHA1 = 0x00

VOD CHA1 = 110'b, VOD_DB CHA1 = 000'b

EQ CHA2 = 0x03

VOD CHA2 = 110'b

VOD_DB CHA2 = 000'b

EQ CHA3 = 0x00

VOD CHA3 = 110'b, VOD_DB CHA3 = 000'b

DS125BR820

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www.ti.com.cn

Table 7. Example Of EEPROM For Four Devices Using Two Address Maps (continued)

EEPROM

Address

Address (Hex)

EEPROM Data

Comments

0x54

0x00

0x04

0x07

0x00

0x01

0xAB

0x00

0x1A

0xB0

0x00

0x01

0xAB

0x00

0x1A

0xB0

0x09

0x80

0x07

0x5C

0x00

0x15

0xA0

0x00

0x07

0x5C

0x00

0x15

0xA0

0x00

0x54

End Device 0, 1 - Address Offset 39

Begin Device 2, 3 - Address Offset 3

EQ CHB0 = 0x01

VOD CHB0 = 011'b

VOD_DB CHB0 = 000'b

EQ CHB1 = 0x01

VOD CHB1 = 011'b, VOD_DB CHB1 = 000'b

EQ CHB2 = 0x01

VOD CHB2 = 011'b

VOD_DB CHB2 = 000'b

EQ CHB3 = 0x01

VOD CHB3 = 011'b, VOD_DB CHB3 = 000'b

Signal Detect Status Threshold Control

EQ CHA0 = 0x03

VOD CHA0 = 110'b

VOD_DB CHA0 = 000'b

EQ CHA1 = 0x00

VOD CHA1 = 101'b, VOD_DB CHA1 = 000'b

EQ CHA2 = 0x03

VOD CHA2 = 110'b

VOD_DB CHA2 = 000'b

EQ CHA3 = 0x00

VOD CHA3 = 101'b, VOD_DB CHA3 = 000'b

End Device 2, 3 - Address Offset 39

Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. Multiple devices can point to the

same address map. Maximum EEPROM size is 8 kbits (1024 x 8-bits).

DS125BR820

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7.7 Register Maps

The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. Tie ENSMB = 1

kΩ to VDD (2.5 V mode) or VIN (3.3 V mode) to enable SMBus Slave Mode and allow access to the

configuration registers.

The DS125BR820 uses AD[3:0] inputs in both SMBus Modes. These AD[3:0] pins are the user set SMBus slave

address inputs and have internal pull-downs. Based on the SMBus 2.0 specification, the DS125BR820 has a 7-

bit slave address. The LSB is set to 0'b (for a WRITE). When AD[3:0] pins are left floating or pulled low, AD[3:0]

= 0000'b, and the device default address byte is 0xB0. The device supports up to 16 address bytes, as shown in

Table 8:

Table 8. Device Slave Address Bytes

Full Slave Address Byte

(7-Bit Address + Write Bit)

7-Bit Slave Address

(Hex)

AD[3:0] Settings

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

The SDA/SCL pins are 3.3 V tolerant, but are not 5V tolerant. An external pull-up resistor is required on the SDA

line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may

also require an external pull-up resistor and it depends on the Host that drives the bus.

7.7.1 Transfer Of Data Via The SMBus

During normal operation, the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.

STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding t_BUFfrom the last detected STOP condition or if they

are High for a total exceeding the maximum specification for t_HIGH, then the bus transfers to the IDLE state.

7.7.2 SMBus Transactions

The device supports WRITE and READ transactions. See Table 9 for register address, type (Read/Write, Read

Only), default value, and function information.

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7.7.3 Writing a Register

To write a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drive the 8-bit data byte.

6. The Device drives an ACK bit (“0”).

7. The Host drives a STOP condition.

The WRITE transaction is completed, the bus goes IDLE, and communication with other SMBus devices may

now occur.

7.7.4 Reading a Register

To read a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drives a START condition.

6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.

7. The Device drives an ACK bit “0”.

8. The Device drives the 8-bit data value (register contents).

9. The Host drives a NACK bit “1”indicating end of the READ transfer.

10. The Host drives a STOP condition.

The READ transaction is completed, the bus goes IDLE, and communication with other SMBus devices may now

occur.

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

7.7.5 Detailed Register Map

Table 9. SMBus Slave Mode Register Map

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

Description

Reserved

R/W

Set bit to 0

Observation of AD[3:0] bits

[6]: AD3

[5]: AD2

Address Bit

AD[3:0]

6:3

[4]: AD1

0x00

Observation

0x00

[3]: AD0

EEPROM

Read Done

1 = Device completed the read from external EEPROM

Reserved

R/W

Set bit to 0

Power Down per Channel

[7]: CH7 – CHA_3

[6]: CH6 – CHA_2

[5]: CH5 – CHA_1

[4]: CH4 – CHA_0

[3]: CH3 – CHB_3

[2]: CH2 – CHB_2

[1]: CH1 – CHB_1

PWDN

Channels

0x01

7:0

PWDN CHx

R/W

0x00

Yes

[0]: CH0 – CHB_0

0x00 = all channels enabled

0xFF = all channels disabled

Note: Override PWDN pin and enable register control

via Reg 0x02[0]

Override

PRSNT

1 = Override Automatic Rx Detect State Machine Reset

1 = Set Rx Detect State Machine Reset

0 = Clear Rx Detect State Machine Reset

PRSNT Value

Override

PWDN, PRSNT 5:2

0x02

R/W

0x00

Reserved

Yes

Set bits to 0

Set bit to 0

Override

PWDN

1 = Block PWDN pin control (Register control enabled)

0 = Allow PWDN pin control (Register control disabled)

0x03

0x04

0x05

Reserved

7:0

7:5

Reserved

R/W

0x00

Set bits to 0

Set bit to 1

Yes

1 = Enable SMBus Slave Mode Register Control

Note: In order to change VOD, VOD_DB, and EQ of

the channels in slave mode, this bit must be set to

Slave Register

Control

0x06

0x07

R/W

0x10

0x01

Enable

2:0

Reserved

Set bits to 0

Set bit to 0

Reset

Registers

1 = Self clearing reset for SMBus registers (register

settings return to default values)

Digital Reset

and Control

Reset SMBus

Master

1 = Self clearing reset to SMBus master state machine

4:0

Reserved

Set bits to 0 0001'b

Set bit to 0

Override

SD_TH

1 = Block SD_TH pin control (Register control enabled)

0 = Allow SD_TH pin control (Register control disabled)

Yes

Override

Pin Control

0x08

5:4

Reserved

R/W

0x00

Set bits to 0

Override

RXDET

1 = Block RXDET pin control (Register control enabled)

0 = Allow RXDET pin control (Register control disabled)

2:0

Reserved

Set bits to 0

DS125BR820

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www.ti.com.cn

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

Description

0x09

Reserved

7:0

Reserved

R/W

0x00

Set bits to 0

CH7 - CH0 Internal Signal Detect Indicator

[7]: CH7 – CHA_3

[6]: CH6 – CHA_2

[5]: CH5 – CHA_1

[4]: CH4 – CHA_0

[3]: CH3 – CHB_3

[2]: CH2 – CHB_2

[1]: CH1 – CHB_1

Signal Detect

Monitor

0x0A

7:0 SD_TH Status

0x00

[0]: CH0 – CHB_0

0 = Signal detected at input

1 = Signal not detected at input

Note: These bits only function when RESERVED2 pin =

FLOAT

Reserved

R/W

0x00

0x70

0x00

Set bit to 0

0x0B

Reserved

6:0

7:0

7:6

5:4

Yes

Set bits to 111 0000'b

Set bits to 0

0x0C

0x0D

Reserved

Set bits to 0

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH0 - CHB_0

RXDET

0x0E

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

Yes

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH0 - CHB_0

INB_0 EQ Control - total of four levels.

See Table 4.

0x0F

0x10

EQ Control

R/W

0x2F

0xAD

Yes

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTB_0 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH0 - CHB_0

VOD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

DS125BR820

www.ti.com.cn

Address

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Bit

Field

Type Default

Description

Observation bit for RXDET CH0 - CHB_0

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTB_0 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH0 - CHB_0

VOD_DB

0x11

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

CH0 - CHB_0

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x12

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x13

0x14

Reserved

7:0

7:6

5:4

Reserved

R/W

0x00

Set bits to 0

Yes

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH1 - CHB_1

RXDET

0x15

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH1 - CHB_1

INB_1 EQ Control - total of four levels.

See Table 4.

0x16

EQ Control

R/W

0x2F

Yes

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

Description

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTB_1 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH1 - CHB_1

VOD

0x17

R/W

0xAD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

Observation bit for RXDET CH1 - CHB_1

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTB_1 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH1 - CHB_1

VOD_DB

0x18

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

CH1 - CHB_1

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x19

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x1A

0x1B

Reserved

7:0

Reserved

R/W

0x00

Set bits to 0

DS125BR820

www.ti.com.cn

Address

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Bit

Field

Type Default

Description

7:6

5:4

Reserved

Set bits to 0

Yes

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH2 - CHB_2

RXDET

0x1C

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

Yes

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH2 - CHB_2

INB_2 EQ Control - total of four levels.

See Table 4.

0x1D

0x1E

EQ Control

R/W

0x2F

0xAD

Yes

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTB_2 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH2 - CHB_2

VOD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

Observation bit for RXDET CH2 - CHB_2

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTB_2 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH2 - CHB_2

VOD_DB

0x1F

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

Description

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

Yes

CH2 - CHB_2

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x20

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x21

0x22

Reserved

7:0

7:6

5:4

Reserved

R/W

0x00

Set bits to 0

Yes

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH3 - CHB_3

RXDET

0x23

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH3 - CHB_3

INB_3 EQ Control - total of four levels.

See Table 4.

0x24

0x25

EQ Control

R/W

0x2F

0xAD

Yes

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTB_3 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH3 - CHB_3

VOD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

DS125BR820

www.ti.com.cn

Address

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Bit

Field

Type Default

Description

Observation bit for RXDET CH3 - CHB_3

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTB_3 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH3 - CHB_3

VOD_DB

0x26

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

CH3 - CHB_3

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x27

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

Reserved

Set bit to 0

Set bit to 1

Yes

Enable Higher Range of Signal Detect Status

Thresholds

[5]: CH0 - CH3

High SD_TH

Status

5:4

[4]: CH4 - CH7

Signal Detect

Status Control

Enable Fast Signal Detect Status

[3]: CH0 - CH3

[2]: CH4 - CH7

Note: In Fast Signal Detect, assert/de-assert response

occurs after approximately 3-4 ns

0x28

R/W

0x4C

Fast Signal

Detect Status

3:2

1:0

Yes

Enable Reduced Signal Detect Status Gain

[1]: CH0 - CH3

[0]: CH4 - CH7

Reduced SD

Status Gain

0x29

0x2A

Reserved

7:0

Reserved

R/W

0x00

Set bits to 0

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

Description

7:6

5:4

Reserved

Set bits to 0

Yes

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH4 - CHA_0

RXDET

0x2B

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

Yes

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH4 - CHA_0

INA_0 EQ Control - total of four levels.

See Table 4.

0x2C

0x2D

EQ Control

R/W

0x2F

0xAD

Yes

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTA_0 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH4 - CHA_0

VOD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

Observation bit for RXDET CH4 - CHA_0

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTA_0 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH4 - CHA_0

VOD_DB

0x2E

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

DS125BR820

www.ti.com.cn

Address

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Bit

Field

Type Default

Description

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

Yes

CH4 - CHA_0

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x2F

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x30

0x31

Reserved

7:0

7:6

5:4

Reserved

R/W

0x00

Set bits to 0

Yes

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH5 - CHA_1

RXDET

0x32

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH5 - CHA_1

INA_1 EQ Control - total of four levels.

See Table 4.

0x33

0x34

EQ Control

R/W

0x2F

0xAD

Yes

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTA_1 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH5 - CHA_1

VOD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

Description

Observation bit for RXDET CH5 - CHA1

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTA_1 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH5 - CHA_1

VOD_DB

0x35

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

CH5 - CHA_1

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x36

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x37

0x38

Reserved

7:0

7:6

5:4

Reserved

R/W

0x00

Set bits to 0

Yes

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH6 - CHA_2

RXDET

0x39

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH6 - CHA_2

INA_2 EQ Control - total of four levels.

See Table 4.

0x3A

EQ Control

R/W

0x2F

Yes

DS125BR820

www.ti.com.cn

Address

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Bit

Field

Type Default

Description

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTA_2 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH6 - CHA_2

VOD

0x3B

R/W

0xAD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

Observation bit for RXDET CH6 - CHA_2

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTA_2 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH6 - CHA_2

VOD_DB

0x3C

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

CH6 - CHA_2

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x3D

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x3E

0x3F

Reserved

7:0

Reserved

R/W

0x00

Set bits to 0

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

Description

7:6

5:4

Reserved

Set bits to 0

Yes

00'b = Input is Hi-Z impedance

01'b = Auto Rx-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is Hi-Z until detection; once detected

input termination is 50 Ω

CH7 - CHA_3

RXDET

0x40

R/W

0x00

10'b = Auto Rx-Detect,

3:2

RXDET

Yes

outputs test every 12 ms until detection occurs;

termination is Hi-Z until detection; once detected input

termination is 50 Ω

11'b = Input is 50 Ω

Note: Override RXDET pin and enable register control

via Reg 0x08[3]

1:0

7:0

Reserved

Set bits to 0

CH7 - CHA_3

INA_3 EQ Control - total of four levels.

See Table 4.

0x41

0x42

EQ Control

R/W

0x2F

0xAD

Yes

Short Circuit

Protection

1 = Enable the short circuit protection

0 = Disable the short circuit protection

Yes

6:3

Reserved

Set bits to 0101'b

OUTA_3 VOD Control: VOD / VID Ratio

000'b = 0.57

001'b = 0.65

CH7 - CHA_3

VOD

010'b = 0.71

2:0

VOD Control

Yes

011'b = 0.77

100'b = 0.83

101'b = 0.90 (default)

110'b = 1.00 (recommended)

111'b = 1.04

Observation bit for RXDET CH7 - CHA_3

1 = Input 50 Ω terminated to VDD

0 = Input is Hi-Z

RXDET Status

6:5

4:3

Reserved

Set bits to 0

OUTA_3 VOD_DB Control

000'b = 0 dB (recommended)

001'b = –1.5 dB

010'b = –3.5 dB (default)

011'b = –5 dB

CH7 - CHA_3

VOD_DB

0x43

0x02

R/W

VOD_DB

Control

100'b = –6 dB

101'b = –8 dB

2:0

Yes

110'b = –9 dB

111'b = –12 dB

Note: Changing VOD_DB bits effectively lowers the

output VOD dynamic range by a factor of the

corresponding amount of dB reduction.

DS125BR820

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Address

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Bit

Field

Type Default

Description

Reserved

Yes

Set bit to 0

6:4

Set bits to 0

Status Assert threshold (1010 pattern 12 Gbps)

00'b = 50 mVp-p (default)

01'b = 40 mVp-p

10'b = 75 mVp-p

11'b = 58 mVp-p

Signal Detect

Status Assert

Threshold

3:2

1:0

Yes

CH7 - CHA_3

SD_TH

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x44

R/W

0x00

Status De-assert threshold (1010 pattern 12 Gbps)

00'b = 37 mVp-p (default)

01'b = 22 mVp-p

10'b = 55 mVp-p

11'b = 45 mVp-p

Signal Detect

Status

De-assert

Threshold

Yes

Note: Override SD_TH pin and enable register control

via Reg 0x08[6]

0x45

0x46

Reserved

7:0

7:4

3:0

7:6

5:0

7:0

7:3

2:1

Reserved

VERSION

R/W

0x00

0x38

Set bits to 0

Set bits to 0x38

Set bits to 0

Set bits to 00 0101'b

Set bits to 0

100'b

0x47

0x48

Reserved

R/W

0x00

0x05

Yes

R/W

0x49

0x4A

0x4B

Reserved

0x00

Yes

0x4C

Reserved

0x00

0x4D

0x4E

0x4F

0x50

Reserved

7:0

7:5

4:0

7:0

7:1

0x00

0x51

Device ID

0x85

0 0101'b

0x52

0x53

0x54

0x55

0x56

0x57

0x58

Reserved

R/W

0x00

0x10

0x64

0x21

Set bits to 0

Set bits to 0x10

Set bits to 0x64

Set bits to 0x21

Set bits to 0

Set bit to 0

0x59

Reserved

R/W

0x00

Yes

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

Reserved

7:0

R/W

0x54

0x00

Set bits to 0x54

Set bits to 0

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 9. SMBus Slave Mode Register Map (continued)

Name

EEPROM

Reg Bit

Address

Bit

Field

Type Default

R/W 0x00

Description

0x61

Reserved

7:0

Reserved

Set bits to 0

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Signal Integrity in 40G-CR4/KR4/SAS/SATA/PCIe Applications

In 40G-CR4/KR4/SAS/SATA/PCIe applications, specifications require Rx-Tx link training to establish and

optimize signal conditioning settings for data rates up to 12.5 Gbps. In link training, the Rx partner requests a

series of FIR coefficients from the Tx partner at speed. This polling sequence is designed to pre-condition the

signal path with an optimized link between the endpoints. Link training occurs at the following data-rates:

Table 10. Link Training Data-Rates

Protocol⁽¹⁾

40G-CR4

40G-KR4

SAS-3

Operating Data Rate (Gbps)

10.3125

12.0

PCIe Gen-3

8.0

(1) There is no link training with Tx FIR coefficients for the respective lower generation data rates.

The DS125BR820 works to extend the reach possible by using active linear equalization to the channel, boosting

attenuated signals so that they can be more easily recovered at the Rx. The repeater outputs are specially

designed to be transparent to Tx FIR signaling in order to pass information critical for optimal link training to the

Rx. Suggested settings for the A-channels and B-channels are given in Table 11 and Table 12. Further

adjustments to EQx and VODx settings may optimize signal margin on the link for different system applications:

Table 11. Suggested Device Settings in Pin Mode

Channel Settings

EQx

Pin Mode

Level 1

VODx[1:0]

Level 6 (1, 0)

Table 12. Suggested Device Settings in SMBus Modes

Channel Settings

SMBus Modes

0x00

EQx

VODx

110'b

VOD_DB

000'b

The SMBus Slave Mode code example in Table 13 may be used to program the DS125BR820 with the

recommended device settings.

Table 13. SMBus Example Sequence

0x06

Write Value

0x18

Comments

Set SMBus Slave Mode Register Enable.

0x0F

0x10

0x00

Set CHB_0 EQ to 0x00.

Set CHB_0 VOD to 110'b.

Set CHB_0 VOD_DB to 000'b.

Set CHB_1 EQ to 0x00.

Set CHB_1 VOD to 110'b.

0xAE

0x11

0x00

0x16

0x00

0x17

0xAE

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 13. SMBus Example Sequence (continued)

0x18

0x1D

0x1E

0x1F

0x24

0x25

0x26

0x2C

0x2D

0x2E

0x33

0x34

0x35

0x3A

0x3B

0x3C

0x41

0x42

0x43

Write Value

0x00

Comments

Set CHB_1 VOD_DB to 000'b.

Set CHB_2 EQ to 0x00.

0x00

0xAE

0x00

Set CHB_2 VOD to 110'b.

Set CHB_2 VOD_DB to 000'b.

Set CHB_3 EQ to 0x00.

0x00

0xAE

0x00

Set CHB_3 VOD to 110'b.

Set CHB_3 VOD_DB to 000'b.

Set CHA_0 EQ to 0x00.

0x00

0xAE

0x00

Set CHA_0 VOD to 110'b.

Set CHA_0 VOD_DB to 000'b.

Set CHA_1 EQ to 0x00.

0x00

0xAE

0x00

Set CHA_1 VOD to 110'b.

Set CHA_1 VOD_DB to 000'b.

Set CHA_2 EQ to 0x00.

0x00

0xAE

0x00

Set CHA_2 VOD to 110'b.

Set CHA_2 VOD_DB to 000'b.

Set CHA_3 EQ to 0x00.

0x00

0xAE

0x00

Set CHA_3 VOD to 110'b.

Set CHA_3 VOD_DB to 000'b.

8.1.2 Signal Integrity in 40G-SR4/LR4 Applications

In 40G-SR4/LR4 applications, the ideal device settings must be tuned. In particular, EQ and VOD settings must

be optimized in order to aid the link partners in meeting the nPPI eye mask test. While tuning the DS125BR820

contributes to signal quality improvement, it is equally important to ensure that the link partner ASIC Tx FIR

signal characteristics are optimized as well to facilitate error-free data transmission. Suggested settings for the A-

channels and B-channels in a 40G-SR4/LR4 environment can be referenced in Table 11 and Table 12.

8.1.3 Rx Detect Functionality in 40G-CR4/KR4/SAS/SATA Applications

Unlike PCIe systems, 40G-CR4/KR4/SAS/SATA systems use a low speed communications sequence to detect

and communicate device capabilities between host ASIC and link partners. This communication eliminates the

need to detect for endpoints like in a PCIe application. For 40G-CR4/KR4/SAS/SATA systems, it is

recommended to tie the RXDET pin high. This ensures any link-training sequences sent by the host ASIC can

reach the link partner receiver without any additional latency due to termination detection sequences.

8.2 Typical Applications

8.2.1 Generic High Speed Repeater

The DS125BR820 extends PCB and cable reach in multiple applications by using active linear equalization. The

high linearity of this device aids specifically in protocols requiring link training and can be used in line cards,

backplanes, motherboards, and active cable assemblies, thereby improving margin and overall eye performance.

The capability of the repeater can be explored across a range of data rates and ASIC-to-link-partner signaling, as

shown in the following two test setup connections.

Pattern

Generator

Scope

BW = 60 GHz

OUT

DS125BR820

= 1.0 Vp-p,

Lossy Channel

DE = 0 dB

PRBS15

Figure 9. Test Setup Connections Diagram

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Typical Applications (continued)

Pattern

Generator

Scope

BW = 60 GHz

TL1

Lossy Channel

TL2

Lossy Channel

OUT

DS125BR820

= 1.0 Vp-p,

DE = -6 dB

PRBS15

Figure 10. Test Setup Connections Diagram

8.2.1.1 Design Requirements

As with any high speed design, there are many factors which influence the overall performance. Below are a list

of critical areas for consideration and study during design.

•

Use 100 Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.

Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.

The maximum body size for AC-coupling capacitors is 0402.

Back-drill connector vias and signal vias to minimize stub length.

Use Reference plane vias to ensure a low inductance path for the return current.

8.2.1.2 Detailed Design Procedure

The DS125BR820 is designed to be placed at an offset location with respect to the overall channel attenuation.In

order to optimize performance, the repeater requires tuning to extend the reach of the cable or trace length while

also recovering a solid eye opening. To tune the repeater, the settings mentioned in Table 11 (for Pin Mode) and

Table 12 (for SMBus Modes) are recommended as a default starting point for most applications. Once these

settings are configured, additional tuning of the EQ and, to a lesser extent, VOD may be required to optimize the

repeater performance for each specific application environment.

Examples of the repeater performance as a generic high speed datapath repeater are illustrated in the

performance curves in the next section.

8.2.1.3 Application Performance Plots

No Repeater Used

TJ (1.0E-12) = 21.6 ps

DS125BR820 Settings: EQA = Level 2, VODA = Level 6

TJ (1.0E-12) = 13.6 ps

Figure 11. TL = 5 Inch 5–Mil FR4 Trace,

Figure 12. TL = 5 Inch 5–Mil FR4 Trace,

DS125BR820 CHA_0, 8 Gbps

No Repeater, 8 Gbps

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Applications (continued)

No Repeater Used

TJ (1.0E-12) = 43.7 ps

DS125BR820 Settings: EQA = Level 3, VODA = Level 6

TJ (1.0E-12) = 18.1 ps

Figure 14. TL= 10 Inch 5–Mil FR4 Trace,

Figure 13. TL = 10 Inch 5–Mil FR4 Trace,

No Repeater, 8 Gbps

DS125BR820 CHA_0, 8 Gbps

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

TJ (1.0E-12) = 35.5 ps

TJ (1.0E-12) = Not Available Due to Closed Eye

Figure 15. TL = 20 Inch 5–Mil FR4 Trace,

No Repeater, 8 Gbps

Figure 16. TL = 20 Inch 5–Mil FR4 Trace,

DS125BR820 CHA_0, 8 Gbps

No Repeater

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

TJ (1.0E-12) = 41.4 ps

TJ (1.0E-12) = Not Available Due to Closed Eye

Figure 17. TL = 5-Meter 30-AWG 100 Ω Twin-Axial Cable,

No Repeater, 8 Gbps

Figure 18. TL = 5-Meter 30-AWG 100 Ω Twin-Axial Cable,

DS125BR820 CHA_0, 8 Gbps

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Typical Applications (continued)

No Repeater Used

TJ (1.0E-12) = 24.3 ps

DS125BR820 Settings: EQA = Level 2, VODA = Level 6

TJ (1.0E-12) = 14.0 ps

Figure 20. TL = 5 Inch 5–Mil FR4 Trace,

Figure 19. TL = 5 Inch 5–Mil FR4 Trace,

No Repeater, 10.3125 Gbps

DS125BR820 CHA_0, 10.3125 Gbps

No Repeater Used

TJ (1.0E-12) = 50.6 ps

DS125BR820 Settings: EQA = Level 3, VODA = Level 6

TJ (1.0E-12) = 18.7 ps

Figure 21. TL = 10 Inch 5–Mil FR4 Trace,

No Repeater, 10.3125 Gbps

Figure 22. TL= 10 Inch 5–Mil FR4 Trace,

DS125BR820 CHA_0, 10.3125 Gbps

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

TJ (1.0E-12) = 49.1 ps

TJ (1.0E-12) = Not Available Due to Closed Eye

Figure 23. TL = 20 Inch 5–Mil FR4 Trace,

No Repeater, 10.3125 Gbps

Figure 24. TL = 20 Inch 5–Mil FR4 Trace,

DS125BR820 CHA_0, 10.3125 Gbps

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Applications (continued)

No Repeater

TJ (1.0E-12) = 26.1 ps

DS125BR820 Settings: EQA = Level 2, VODA = Level 6

TJ (1.0E-12) = 13.1 ps

Figure 26. TL = 5 Inch 5–Mil FR4 Trace,

Figure 25. TL = 5 Inch 5–Mil FR4 Trace,

No Repeater, 12 Gbps

DS125BR820 CHA_0, 12 Gbps

No Repeater

TJ (1.0E-12) = 56.6 ps

DS125BR820 Settings: EQA = Level 3, VODA = Level 6

TJ (1.0E-12) = 20.1 ps

Figure 27. TL = 10 Inch 5–Mil FR4 Trace,

No Repeater, 12 Gbps

Figure 28. TL = 10 Inch 5–Mil FR4 Trace,

DS125BR820 CHA_0, 12 Gbps

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

TJ (1.0E-12) = 33.0 ps

TJ (1.0E-12) = Not Available Due to Closed Eye

Figure 29. TL1 = 15 Inch 5–Mil FR4 Trace,

TL2 = 10 Inch 5–Mil FR4 Trace,

No Repeater, 8 Gbps

Figure 30. TL1 = 15 Inch 5–Mil FR4 Trace,

TL2 = 10 Inch 5–Mil FR4 Trace,

DS125BR820 CHA_0, 8 Gbps

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Typical Applications (continued)

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

TJ (1.0E-12) = 47.9 ps

Figure 32. TL1 = 15 Inch 5–Mil FR4 Trace,

TJ (1.0E-12) = Not Available Due to Closed Eye

Figure 31. TL1 = 15 Inch 5–Mil FR4 Trace,

TL2 = 10 Inch 5–Mil FR4 Trace,

No Repeater, 10.3125 Gbps

TL2 = 10 Inch 5–Mil FR4 Trace,

DS125BR820 CHA_0, 10.3125 Gbps

8.2.2 Front Port Applications (40G-CR4/SR4/LR4)

The DS125BR820 can be used in front port applications to extend the reach between the host ASIC and the

front-port cage. Front port applications typically include 40G-CR4/SR4/LR4. For 40GbE front port optical

protocols like 40G-SR4/LR4, the DS125BR820 is designed to support the front-port eye mask and jitter

requirements of applicable standards like nPPI. For 40GbE front port copper protocols like 40G-CR4, the

DS125BR820 is designed to provide channel equalization in a transparent fashion so as not to inhibit

IEEE802.3ba Clause 72 link training. In all of these front port cases, the DS125BR820 can also be used to

support eye mask and jitter requirements for SFF-8431 if the 40GbE QSFP+ port is intended to support 4x10G

SFP+ applications as well. Below is a typical example of the DS125BR820 used in a front port line-card

application.

Line Card

2x40G

DS125BR820

Stacked QSFP+

40GbE Copper CR4 or

40GbE SR4/LR4 Optical

DS125BR820

2x40G

ASIC

FPGA

8x10G

Stacked QSFP+

1xQSFP+ to 4xSFP+

Breakout

DS125BR820

8x10G

Figure 33. Typical Front-Port System Configuration

8.2.2.1 Design Requirements

As with any high speed design, there are many factors that influence the overall performance. Please reference

Design Requirements in the Generic High Speed Repeater application section for a list of critical areas for

consideration and study during design.

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Applications (continued)

8.2.2.2 Detailed Design Procedure

In front port applications, it is important to ensure that the placement of the DS125BR820 corresponds with the

direction of the data flow, since the device is unidirectional. For egress applications, the DS125BR820 should be

placed close to the connector cage, and for ingress applications, the DS125BR820 should be placed closer to

the switch ASIC. Once the DS125BR820 placement is decided on the signal path, the repeater must be tuned.

To tune the repeater, the settings mentioned in Table 11 (for Pin Mode) and Table 12 (for SMBus Modes) are

recommended as a default starting point for most applications. Once these settings are configured, additional

tuning of the EQ and, to a lesser extent, VOD may be required to optimize the repeater performance in order to

meet the link training requirements for 40G-CR4 and eye mask requirements for 40G-SR4/LR4.

An example of a test configuration used to evaluate the DS125BR820 in this application can be seen in

Figure 34. For more information about DS125BR820 front port applications, please refer to application note

SNLA226:

Molex zQSFP+^TM

Host Compliance Board

(HCB)

DS125BR820

QSFP+ Test Board

Huber+Suhner

2x8 MXP

connector

10G Transmitter Test Board

Agilent DCAx

Scope with

86108B PTB

FR4 Trace: 5inch to 15inch

DS125BR820

Huber+Suhner

2x1 Stacked

QSFP+

1x8 MXP

connector

~4 inch

~1 inch

FR4

~1 inch

FR4

9 inch

cable

9 inch

cable

10G

Transmitter

with FIR

Figure 34. 10 GbE Transmitter with DS125BR820 QSFP+ Test Board

8.2.2.3 Application Performance Plots

DS125BR820 Settings: EQA = Level 2, VODA = Level 6

Figure 35. nPPI Eye Mask Performance with 5 Inch 4-Mil

FR4 Input Trace, Test Pattern = PRBS-9, 10.3125 Gbps

DS125BR820 Settings: EQA = Level 2, VODA = Level 6

Figure 36. nPPI Jitter Performance with 5 Inch 4-Mil FR4

Input Trace, Test Pattern = PRBS-9, 10.3125 Gbps

DS125BR820

www.ti.com.cn

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Typical Applications (continued)

DS125BR820 Settings: EQA = Level 3, VODA = Level 6

Figure 37. nPPI Eye Mask Performance with 15 Inch 5-Mil

FR4 Input Trace, Test Pattern = PRBS-9, 10.3125 Gbps

DS125BR820 Settings: EQA = Level 3, VODA = Level 6

Figure 38. nPPI Jitter Performance with 15 Inch 5-Mil FR4

Input Trace, Test Pattern = PRBS-9, 10.3125 Gbps

8.2.3 PCIe Board Applications (PCIe Gen-3)

The DS125BR820 can be used to extend trace length on motherboards and line cards in PCIe Gen-3

applications. The high linearity of the DS125BR820 aids in the link training protocol required by PCIe Gen-3 at 8

Gbps in accordance with PCI-SIG standards. For PCIe Gen-3, preservation of the pre-cursor and post-cursor Tx

FIR presets (P1-P10) is crucial to successful signal transmission from motherboard system root complex to line

card ASIC or Embedded Processor. Below is a typical example of the DS125BR820 used in a PCIe application:

ASIC

PCIe EP

Connector

DS125BR820

System Board

Root Complex

DS125BR820

Connector

Figure 39. Typical PCIe Gen-3 Configuration Diagram

8.2.3.1 Design Requirements

As with any high speed design, there are many factors that influence the overall performance. Please reference

Design Requirements in the Generic High Speed Repeater application section for a list of critical areas for

consideration and study during design.

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Applications (continued)

8.2.3.2 Design Procedure

In PCIe Gen-3 applications, there is a large range of flexibility regarding the placement of the DS125BR820 in

the signal path due to the high linearity of the device. If the PCIe slot must also support lower speeds like PCIe

Gen-1 (2.5 Gbps) and Gen-2 (5.0 Gbps), it is recommended to place the DS125BR820 closer to the endpoint Rx.

Once the DS125BR820 is placed on the signal path, the repeater must be tuned. To tune the repeater, the

settings mentioned in Table 11 (for Pin Mode) and Table 12 (for SMBus Modes) are recommended as a default

starting point for most applications. Once these settings are configured, additional tuning of the EQ and, to a

lesser extent, VOD may be required to optimize the repeater performance to pass link training preset

requirements for PCIe Gen-3.

An example of a test configuration used to evaluate the DS125BR820 in this application can be seen in

Figure 40. For more information about DS125BR820 PCIe applications, please refer to application note

SNLA227:

PCIe Gen-3

Compliance

Lane Under

Test TX

Base Board Riser

Scope

Tektronix

DSA71604

PC Testing

Signal Test 3.2.0

Software

FR4 Trace

TL2

FR4 Trace

DS125BR820EVM

TL1

PCIe Gen 3.0 (x16 Lane)

^<v}Ávꢀ'}}ꢀ_ꢀ

Golden Graphics Card

TX: Front Side

RX: Back Side

PCIe Connector

Lane Under

Test RX

PCIe Gen-3 Preset

Configuration Control

PCIe Gen-3

Compliance

Base Board

(CBB)

Figure 40. Typical PCIe Gen-3 Add-In Card Test Diagram

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

Typical Applications (continued)

8.2.3.3 Application Performance Plots

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

Composite Eye Height: 50.39 mV

Minimum Eye Width: 49.87 ps

Overall SigTest Result: Fail

Composite Eye Height: 112.2 mV

Minimum Eye Width: 83.82 ps

Overall SigTest Result: Pass

Figure 41. PCIe Gen-3, Preset 7, Transition Eye

TL1 = 10 Inch 4-Mil FR4 Trace, No TL2

No Repeater, 8 Gbps

Figure 42. PCIe Gen-3, Preset 7, Transition Eye

TL1 = 10 Inch 4-Mil FR4 Trace, No TL2

DS125BR820, 8 Gbps

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

Composite Eye Height: 112.2 mV

Minimum Eye Width: 83.82 ps

Composite Eye Height: 50.39 mV

Minimum Eye Width: 49.87 ps

Overall SigTest Result: Fail

Overall SigTest Result: Pass

Figure 43. PCIe Gen-3, Preset 7, Non-Transition Eye

TL1 = 10 Inch 4-Mil FR4 Trace, No TL2

No Repeater, 8 Gbps

Figure 44. PCIe Gen-3, Preset 7, Non-Transition Eye

TL1 = 10 Inch 4-Mil FR4 Trace, No TL2

DS125BR820, 8 Gbps

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Applications (continued)

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

Composite Eye Height: 0.057 mV

Minimum Eye Width: 37.66 ps

Overall SigTest Result: Fail

Composite Eye Height: 77.26 mV

Minimum Eye Width: 78.24 ps

Overall SigTest Result: Pass

Figure 45. PCIe Gen-3, Preset 7, Transition Eye

Figure 46. PCIe Gen-3, Preset 7, Transition Eye

TL1 = 10 Inch 4-Mil FR4 Trace,

TL2 = 5 Inch 4-Mil FR4 Trace

No Repeater, 8 Gbps

TL1 = 10 Inch 4-Mil FR4 Trace,

TL2 = 5 Inch 4-Mil FR4 Trace

DS125BR820, 8 Gbps

No Repeater Used

DS125BR820 Settings: EQA = Level 4, VODA = Level 6

Composite Eye Height: 77.26 mV

Minimum Eye Width: 78.24 ps

Composite Eye Height: 0.057 mV

Minimum Eye Width: 37.66 ps

Overall SigTest Result: Fail

Overall SigTest Result: Pass

Figure 47. PCIe Gen-3, Preset 7, Non-Transition Eye

Figure 48. PCIe Gen-3, Preset 7, Non-Transition Eye

TL1 = 10 Inch 4-Mil FR4 Trace,

TL2 = 5 Inch 4-Mil FR4 Trace

No Repeater, 8 Gbps

TL2 = 5 Inch 4-Mil FR4 Trace

DS125BR820, 8 Gbps

DS125BR820

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ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

9 Power Supply Recommendations

Two approaches are recommended to ensure that the DS125BR820 is provided with an adequate power supply.

First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers

of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND

planes create a low inductance supply with distributed capacitance. Second, careful attention to supply

bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be

connected to each VDD pin such that the capacitor is placed as close as possible to the DS125BR820. Smaller

body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in

the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These

capacitors can be either tantalum or an ultra-low ESR ceramic.

The DS125BR820 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3 V

mode operation, the VIN pin = 3.3 V is used to supply power to the device. The internal regulator then provides

the 2.5 V to the VDD pins of the device and a 0.1 μF cap is needed at each of the five VDD pins for power

supply de-coupling (total capacitance should equal 0.5 μF). The VDD_SEL pin must be tied to GND to enable the

internal regulator. In 2.5 V mode operation, the VIN pin should be left open and 2.5 V supply must be applied to

the five VDD pins to power the device. The VDD_SEL pin must be left open (no connect) to disable the internal

regulator.

3.3 V mode

2.5 V mode

VDD_SEL

open

Enable

Disable

3.3 V

Internal

voltage

regulator

Internal

Capacitors can be

either tantalum or an

ultra-low ESR ceramic.

voltage

VIN

VDD

VIN

VDD

regulator

2.5 V

0.1 µF

Capacitors can be

either tantalum or an

ultra-low ESR ceramic.

0.1 µF

Place 0.1 µF close to VDD Pin

Place capacitors close to VDD Pin

Total capacitance should be 7 0.5 µF

Figure 49. 3.3 V or 2.5 V Supply Connection Diagram

DS125BR820

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

The CML inputs and outputs have been optimized to work with interconnects using a controlled differential

impedance of 100 Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly

for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used

sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias

are used the layout must also provide for a low inductance path for the return currents as well. Route the

differential signals away from other signals and noise sources on the printed circuit board. To minimize the

effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair and intra-pair spacing. See

AN-1187 “Leadless Leadframe Package (LLP) Application Report” (literature number SNOA401) for additional

information on QFN (WQFN) packages.

10.2 Layout Example

20 mils

EXTERNAL MICROSTRIP

100 mils

20 mils

INTERNAL STRIPLINE

VDD

14 13

BOTTOM OF PKG

GND

VDD

36 37

39 40 41 42

30 31

33 34

VDD

Figure 50. Typical Routing Options

The graphic shown above depicts different transmission line topologies which can be used in various

combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be

minimized or eliminated by increasing the swell around each hole and by providing for a low inductance return

current path. When the via structure is associated with a thick backplane PCB, further optimization such as back

drilling is often used to reduce the detrimental high frequency effects of stubs on the signal path.

DS125BR820

www.ti.com.cn

ZHCSCZ2A –JULY 2014–REVISED SEPTEMBER 2014

11 器件和文档支持

11.1 商标

All trademarks are the property of their respective owners.

11.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

12 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DS125BR820NJYR

DS125BR820NJYT

ACTIVE

WQFN

NJY

2000 RoHS & Green

250 RoHS & Green

Level-2-260C-1 YEAR

-40 to 85

125B820A0

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DS125BR820NJYR

DS125BR820NJYT

WQFN

NJY

2000

250

330.0

178.0

16.4

5.8

10.3

1.0

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DS125BR820NJYR

DS125BR820NJYT

WQFN

NJY

2000

250

356.0

208.0

356.0

191.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

NJY0054A

WQFN

SCALE 2.000

WQFN

5.6

5.4

PIN 1 INDEX AREA

0.5

0.3

0.2

10.1

9.9

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

2X 4

3.51±0.1

(0.1)

SEE TERMINAL

DETAIL

50X 0.5

7.5±0.1

8.5

0.3

54X

0.2

PIN 1 ID

(OPTIONAL)

0.5

0.3

54X

0.1

C A

0.05

4214993/A 07/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

NJY0054A

WQFN

(3.51)

SYMM

54X (0.6)

54X (0.25)

SEE DETAILS

50X (0.5)

(7.5)

(9.8)

SYMM

(1.17)

TYP

(1.16)

(

0.2) TYP

VIA

(1) TYP

(5.3)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214993/A 07/2013

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

NJY0054A

WQFN

SYMM

METAL

TYP

(0.855) TYP

54X (0.6)

54X (0.25)

50X (0.5)

(1.17)

TYP

SYMM

(9.8)

12X (0.97)

12X (1.51)

(5.3)

SOLDERPASTE EXAMPLE

BASED ON 0.125mm THICK STENCIL

EXPOSED PAD

67% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

4214993/A 07/2013

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DS125BR820 [TI]

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