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DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

DS125DF111 多协议双通道 9.8Gbps 至 12.5Gbps 重定时器

1 特性

3 说明

1

•

引脚兼容的重定时器系列

DS125DF111 是一款具有集成信号调节功能的双通道

（双向单信道）重定时器。 DS125DF111 的每条通道

包括一个输入连续时间线性均衡器 (CTLE)、时钟和数

据恢复 (CDR) 功能以及发送驱动器。

–

带有判决反馈均衡器 (DFE) 的

DS110DF111：8.5Gbps 至 11.3Gbps

–

带有 DFE 的 DS125DF111：9.8Gbps 至

12.5Gbps

DS125DF111 具有片上判决反馈均衡器 (DFE)，可延

长在有损且存在串扰的高速串行链路中的发送距离并提

高稳定性，从而实现比特误差率 (BER) < 1x10^-15。对

于要求较低的应用/互连，关闭 DFE 也能够获得相同的

BER 性能。 DS125DF111 和 DS110DF111 器件引脚

兼容。

•

具有自适应连续时间线性均衡器 (CTLE)：可在

6.25GHz 频率下提供最高 33dB 的升压

•

自调试 5 抽头 DFE

原始均衡和重定时数据环回

可调节的发送 V_OD：600 至 1300mVp-p

可设置的接收去加重驱动器：–12dB 至 0

低功耗：220mW/通道

DS125DF111 每条通道的特定串行数据速率均可独立

锁定在 9.8Gbps 到 12.5Gbps 范围内或者任何支持的

子速率上。这简化了系统设计并降低了总成本。

锁定传统支持的二分频/四分频/八分频数据速率

片上眼图监视器 (EOM)，伪随机二进制序列

(PRBS) 发生器

可编程发送去加重驱动器提供精确设置，从而符合

SFF-8431 输出眼图模板。利用完全自适应接收均衡

（CTLE 和 DFE），可以延长在因使用多个连接器而

受损的铜缆和背板上的发送距离。 CDR 功能可消除抖

动并恢复重定时高速串行数据，是前端口并行光学模块

应用的理想选择。

•

输入信号检测，时钟和数据恢复 (CDR) 锁定检测/

指示

•

3.3V 或 2.5V 单电源供电

SMBus、EEPROM 或基于引脚的配置

4mm x 4mm 24 引脚超薄四方扁平无引线 (WQFN)

封装

•

工作温度范围：–40°C 至 85°C

器件信息⁽¹⁾

器件型号

封装

WQFN (24)

封装尺寸（标称值）

2 应用

DS125DF111

4.0mm x 4.0mm

•

前端口光学互连

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

SFF-8431

10G/1G 以太网

CPRI

典型应用

DS125DF111

100nF

OUTA_P

OUTA_N

INA_P

INA_N

100nF

3.3V

INB_P

INB_N

OUTB_P

OUTB_N

2k:

25 MHz

REFCLK_IN

SDA

SCL

3.3V

LPF_REF_B

22nF

VIN

LPF_CP_B

LPF_REF_A

1ꢀF

GND

VDD

3.3V

LPF_CP_A

EN_SMB

TX_DIS

1k:

0.22ꢀF

(2x)

VODA/READ_EN

GND

DAP

ADDR0/LOCK

ADDR1/VODB/DONE#

1k:

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS450

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

7.4 Device Functional Modes........................................ 17

7.5 Programming........................................................... 18

7.6 Register Maps......................................................... 35

Application and Implementation ........................ 44

8.1 Application Information............................................ 44

8.2 Typical Application ................................................. 44

Power Supply Recommendations...................... 46

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration And Functions ........................ 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Timing Requirements................................................ 9

6.7 Typical Characteristics............................................ 11

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 12

7.3 Feature Description................................................. 12

8

9

10 Layout................................................................... 47

10.1 Layout Guidelines ................................................. 47

10.2 Layout Example .................................................... 47

11 器件和文档支持 ..................................................... 48

11.1 文档支持................................................................ 48

11.2 社区资源................................................................ 48

11.3 商标....................................................................... 48

11.4 静电放电警告......................................................... 48

11.5 Glossary................................................................ 48

12 机械、封装和可订购信息....................................... 48

7

4 修订历史记录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (January 2014) to Revision A

Page

•

已添加引脚配置和功能部分，处理额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，

布局部分，器件和文档支持部分以及机械、封装和可订购信息部分........................................................................................ 1

2

DS125DF111

www.ti.com.cn

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

5 Pin Configuration And Functions

RTW Package

24-Pin WQFN

Top View

OUTA+

OUTA-

24

23

22

21

20

19

7

INA+

INA-

8

VODA/READEN#

ADDR1/VODB/DONE#

INB+

9

VDD

4mm x 4mm, 0.5mm pitch

10

11

12

DAP = GND

OUTB+

OUTB-

INB-

TOP VIEW

Pin Functions

I/O TYPE

DESCRIPTION

NAME

NO.

HIGH SPEED DIFFERENTIAL I/OS

OUTA±

OUTB±

INA±

7, 8

O, CML

Inverting and non-inverting CML-compatible differential outputs.

Outputs require AC coupling

20, 19

24, 23

O, CML

I, CML

Inverting and non-inverting CML-compatible differential outputs.

Outputs require AC coupling

Inverting and non-inverting CML-compatible differential inputs. An on-

chip 100 Ω terminating resistor connects INA+ to INA-

Inputs require AC coupling. TI recommends 100 nF capacitors. Note that

for SFP+ applications, AC coupling is included as part of the SFP+

module.

INB±

11, 12

I, CML

Inverting and non-inverting CML-compatible differential inputs. An on-

chip 100 Ω terminating resistor connects INB+ to INB-

Inputs require AC coupling. TI recommends 100 nF capacitors. Note that

for SFP+ applications, AC coupling is included as part of the SFP+

module.

LOOP FILTER CONNECTION PIN

LPF_CP_A, LPF_REF_A 2, 1

I/O, analog

Loop filter connection, place a 22 nF ± 10% capacitor in series between

LPF_CP_A and LPF_REF_A

LPF_CP_B, LPF_REF_B 17, 18

Loop filter connection, place a 22 nF ± 10% capacitor in series between

LPF_CP_B and LPF_REF_B

REFERENCE CLOCK I/O

REFCLK_IN

14

I, LVCMOS

25 MHz ± 100 ppm clock from external Oscillator

3

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

Pin Functions (continued)

I/O TYPE

DESCRIPTION

NAME

INDICATOR PINS

LOCK

NO.

16

13

O, LVCMOS

LOCK VOH is referenced to V_INvoltage level. Note that this pin is shared

with strap input functions read at startup. The Address value loaded into

pin 16 (ADDR0) at startup changes the definition of the LOCK pin output.

See the Shared Register Definition in Table 7 for more details.

LOS/INT#

O, Open Drain

Output is driven LOW when a valid signal is present on INA. Output is

released when signal on INA is lost (LOS). This output can be redefined

as an INT# signal which will be driven LOW for any of the following

conditions.⁽¹⁾

1. The EOM check returns a value below the HEO/VEO interrupt

threshold.

2. CDR check returns lock/loss status.

3. Signal Detector returns detect/loss status.

SMBus MODE PINS

ENSMB

3

I, 4-Level

System Management Bus (SMBus) enable pin

HIGH = Register Access, SMBus Slave mode

FLOAT = SMBus Master read from External EEPROM

20 K to GND = Reserved

LOW = External Pin Control Mode. See section on Pin Mode Limitation

SDA

SCL

4

5

I, SMBus

O, Open Drain

Data Input / Open Drain Output

External pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant⁽¹⁾

I, SMBus

O, Open Drain

Clock input in SMBus slave mode. Can also be an open drain output in

SMBus master mode

Pin is 3.3 V LVCMOS Tolerant⁽¹⁾

TX_DIS

ADDR0

6

I, 4-Level

Disable the OUTB transmitter

HIGH = OUTA Enabled/OUTB Disabled

FLOAT = Reserved

20 K to GND = Reserved

LOW = OUTA/OUTB Enabled (normal operation)

16

I, LVCMOS

This pin sets the SMBus address for the retimer.

This pin is a strap input. The state is read on power-up to set the SMBus

address in SMBus control mode. The latched value of ADDR0 read at

startup will change the LOCK output definition. See the Shared Register

Definition in Table 7 for more details.⁽²⁾

ADDR1/DONE#

READEN#

10

9

IO, LVCMOS

I, LVCMOS

This pin sets the SMBus address for the retimer in SMBus Slave Mode.

DONE#. VOH is referenced to V_INvoltage level. DONE# goes low to

indicate that the SMBus master EEPROM read has been completed in

SMBus Master Mode⁽²⁾

Initiates SMBus master EEPROM read. When multiple DS125DF111 are

connected to a single EEPROM, the READEN# input can be daisy

chained to the DONE# output. In SMBus Slave Mode this pin should be

(3)

tied to Logic 0.

(4)

PIN CONTROL (ENSMB = LOW)

(3)

DEMA

DEMB

LPBK

4

5

6

I, 4-Level

Set CHA output de-emphasis level in pin control mode

(3)

Set CHB output de-emphasis level in pin control mode

HIGH = INA goes to OUTA, INB goes to OUTB

FLOAT = INB goes to OUTA and OUTB

20 K to GND = INA goes to OUTA and OUTB

LOW = INA goes to OUTB, INB goes to OUTA⁽³⁾

(3)

VODA

VODB

9

I, 4-Level

Set CHA output launch amplitude in pin control mode

Set CHB output launch amplitude in pin control mode⁽³⁾

.

10

(1) The LOS/INT# pin is an open drain output which requires external pull-up resistor (typically connected to 2.5 V or 3.3 V for system logic

compatibility) to achieve a HIGH level.

(2) This pin is shared with other functions.

(3) This pin is shared with other functions.

(4) When in pin control mode, the DS125DF111 device operates at 12.288, 9.8304, 6.144, 4.9152, 3.072, 2.4576, 1.536, or 1.2288 Gbps

and has limited VOD and De-Emphasis control. See Table 9.

4

DS125DF111

www.ti.com.cn

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

Pin Functions (continued)

I/O TYPE

DESCRIPTION

NAME

NO.

POWER

V_DD

21, 22

15

Power

V_DD= 2.5 V ± 5%. See Figure 12.

3.3-V supply mode: V_DD= 2.5 V is supplied the internal output regulator.

Pins only require de-coupling caps; no external supply is needed.

2.5-V supply mode: V_DDinput = 2.5 V ± 5%.

Regulator Input ⁽³⁾with Integrated Supply Mode Control. See Figure 12.

3.3-V supply mode: V_INinput = 3.3 V ± 10%.

V_IN

2.5-V Mode Operation: V_INSupply Input = 2.5 V ± 5%. Connect directly

to V_DDsupply pins.

DAP

PAD

GND reference

The exposed pad at the center of the package must be connected to

ground plane of the board with at least 4 vias to lower the ground

impedance and improve the thermal performance of the package

5

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN

–0.5

–30

MAX

UNIT

V

Supply Voltage (V_DD

)

2.75

Supply Voltage (V_IN

)

4

V

LVCMOS Input/Output Voltage

4-Level Input Voltage (2.5-V mode)

4-Level Input Voltage (3.3-V mode)

SMBus Input/Output Voltage

CML Input Voltage

4

V

2.75

V

4

V

V_DD+ 0.5

30

V

CML Input Current

mA

°C

Storage temperature, T_stg

–40

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions.

(2) Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For soldering specifications, see

product folder at SNOA549.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

±3000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101, all pins⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

2.375

3

NOM⁽¹⁾

2.5

MAX

2.625

3.6

UNIT

2.5 V Mode

3.3 V Mode

Supply Voltage

V

3.3

Ambient Temperature

–40

2.7

25

+85

°C

V

SMBus (SDA, SCL) Pull-up Supply Voltage

3.3

3.6

(1) Typical values represent the most likely parametric norm as determined at the time of design and characterization. Actual typical values

may vary over time and will also depend on the application and configuration.

6.4 Thermal Information

DS125DF111

THERMAL METRIC⁽¹⁾

RTW (WQFN)

UNIT

24 PINS

35

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

34

13.4

0.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

13.4

3.3

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

DS125DF111

www.ti.com.cn

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

6.5 Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

9.8

TYP⁽¹⁾

MAX

12.5

UNIT

Gbps

R_Baud

Input baud rate (primary VCO range) Full Rate: DS125DF111

R_Baud2

R_Baud4

R_Baud8

Divide by 2

Divide by 4

Divide by 8

Half Rate: DS125DF111

Quarter Rate: DS125DF111

Eighth Rate: DS125DF111

Slave Mode Clock Rate

Master Mode Clock Rate

± 100 ppm

4.9

6.25

2.45

1.225

100

3.125

1.5625

400

F_SDC

SMBus Clock Rate

kHz

280

400

25

520

REFCLK

Reference Clock Rate

MHz

DC_REFCLKReference Clock Duty Cycle

40%

50%

60%

POWER SUPPLY CURRENT

Average Supply Current, Default

Settings, CHA and CHB Locked

DFE Enabled

175

155

mA

Average Supply Current, CHA and

CHB Locked

Default Settings except DFE

Disabled

DS125DF111 Current Consumption

(Whole Device)

I_DD

Maximum Transient Supply Current

Default Settings: CHA and CHB

valid input signal detected

294

333

mA

CHA and CHB acquiring LOCK⁽²⁾

50 Hz to 100 Hz

100 Hz to 10 MHz

10 MHz to 3.0 GHz

100

40

mVp-p

NTps

Supply Noise Tolerance

10

LVCMOS (ADDR[1:0], READEN#, REFCLK_IN, DONE#, LOCK)

V_IH

High level input voltage

Low level input voltage

High level output voltage

Low level output voltage

Input leakage current

2.5 V or 3.3 V Supply Mode

I_OH= -3 mA

1.7

2

V_IN

0.7

V_IN

V

V_IL

V_OH1

V_OH2

V_OL

I_IN

I_OH= –100 µA

V_IN- 0.1

V

I_OL= 3 mA

0.4

15

V_INPUT= GND or V_IN

–15

µA

4-LEVEL INPUTS (ENSMB, DEMA, DEMB, LPBK, TX_DIS, VODA, VODB)

I_IH-R

I_IL-R

Input leakage current High

Input leakage current Low

V_INPUT= V_IN

80

µA

V_INPUT= GND

–160

OPEN DRAIN (LOS/INT#)

V_OL

Low level output voltage

I_OL= 3 mA

0.4

V

SIGNAL DETECT

Signal Detect:

ON Threshold Level

Default level to assert

Signal Detect, 12.5 Gbps, PRBS31

SDH

SDL

18

14

mVp-p

Signal Detect:

OFF Threshold Level

Default level to de-assert

Signal Detect, 12.5 Gbps, PRBS31

CML RX INPUTS

R_Rd

DC Input differential Resistance

80

100

–19

–13

-8

120

Ω

SDD11 10 MHz

RL_RX-IN

Input Return-Loss

SDD11 2.0 GHz

dB

SDD11 6.0 - 11.1 GHz

V_RX-

LAUNCH

Tx Launch amplitude of driver

Source Transmit Signal Level

1600

mVp-p

connected to DS125DF111 inputs⁽³⁾

(1) Typical values represent the most likely parametric norm as determined at the time of design and characterization. Actual typical values

may vary over time and will also depend on the application and configuration.

(2) Peak current only occurs during lock acquisition, limit is for power supply design not needed for thermal calculations.

(3) DS125DF111 equalizer is optimized to adapt to Tx Launch amplitudes between 600 - 1200 mV. Amplitudes above or below this range

will reduce the overall equalizer performance.

7

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

(4)

TRANSMIT JITTER SPECS

T_TJ

T_RJ

T_DJ

Total Jitter (@ BER = 1E-12)

Random Jitter

PRBS7, 9.8304 Gbps

7.5

0.33

3.6

ps

ps (RMS)

ps

PRBS7, 9.8304 Gbps

Deterministic Jitter

CLOCK AND DATA RECOVERY

Measured at 12.5 Gbps, 0.4 UI Sj

Injection

BW_{P LL}

J_TOL

PLL Bandwidth -3 dB

Total jitter tolerance

3.9

MHz

UI

Jitter per SFF-8431 Appendix D.11

Combination of Dj, Pj, and Rj

> 0.7

Best Lock Time 9.8304 Gbps

Adapt Mode 0 (Register 0x31[6:5])

CTLE Set - no Auto adapt

Disable HEO/VEO Lock Monitor -

(Register 0x3E[7])

HEO/VEO thresholds set to 0 -

(Register 0x6A[7:0])

Rate/Subrate limited to single divide

ratio. See Table 9

T_LOCK1

CDR Lock Time

1.3

ms

CDR Reset and Release - (Register

0x0A[3:2])

Signal Detect Preset and Release -

Before input signal is present

(Register 0x14[7:6])

Standards Based, 9.8304 Gbps,

Default settings⁽⁵⁾

T_LOCK2

CDR Lock Time

35

ms

°C

Lock Temperature Range

–40°C to 85°C operating range

TEMP_LOCKCDR Lock

125

(4) Rj and Dj Jitter decomposition as reported by TEK DSA8200 Sampling scope using a 80E09 Electrical sampling module, 80A06 Pattern

trigger, and 82A04 Phase Reference Module.

(5) The typical LOCK time can vary based on data-rate, input channel, and specific DS125DF111 settings.

8

DS125DF111

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ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

CML TX OUTPUTS

T_V_DIFF0Output differential voltage

Default setting, 8T pattern

400

550

675 mVp-p

mVp-p

Maximum setting, 8T

pattern

T_V_DIFF7Output differential voltage

1000

1200

Requires SMBus Control

Maximum setting, VOD and

DE

V_{OD_DE}

T_Rd

De-emphasis Level

Requires SMBus Control

Input: 9.8304 Gbps, 16T

pattern

–12

100

dB

DC Output Differential Resistance

Ω

Full Slew Rate (Channel

Reg 0x18[2] = 0), minimum

VOD

20% - 80%, See Figure 1.

Input: 9.8304 Gbps, 8T

Pattern

T_R/T_F

Output Rise/Fall Time

36

ps

Limited Slew Rate (Channel

Reg 0x18[2] = 1), minimum

VOD

20% - 80%, See Figure 1.

Input: 9.8304 Gbps, 8T

Pattern

T_RS/T_FS

Output Rise/Fall Time

50

ps

T_SDD22

Output differential mode return loss

SDD22 10 MHz - 2.0 GHz

–18

dB

SDD22

5.5 GHz

–11

SDD22 6

- 11.1

–9

GHz

Retimed Data: 9.8304

Gbps,

See Figure 2.

1.5UI +

200ps

T_PD

Propagation Delay

ps

Raw Data: 9.8304 Gbps,

See Figure 2.

T_PD-RAWPropagation Delay

200

SERIAL BUS INTERFACE CHARACTERISTICS⁽¹⁾See Figure 3.

Data, Clock Input Low Voltage

(SDA / SCL)

V_IL

0.8

3.6

V

Data, Clock Input High Voltage

(SDA / SCL)

V_IH

2.1

0

SDA or SCL, IOL = 1.25

mA

V_OL

T_R

Output Low Voltage

0.36

V

SDA, RPU = 4.7 K, Cb < 50

pF

SDA Rise Time, Read Operation

SDA Fall Time, Read Operation

140

60

ns

SDA, RPU = 4.7 K, Cb < 50

pF

T_F

T_SU;DAT

T_HD;DAT

C_IN

Setup Time, Read Operation

Hold Time, Read Operation

Input Capacitance

560

615

< 5

ns

pF

ns

SDA or SCL

T_R

SCL and SDA, Rise Time

300

T_F

1000

(1) EEPROM interface requires 520 kHz capable EEPROM device.

9

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

80%

0V

20%

V_OD(p-p) = (OUT+) ± (OUT-)

20%

t

RISE

FALL

Figure 1. Differential Output Edge Rate

+

IN

0V

-

t

PHLD

PLHD

+

OUT

0V

-

Figure 2. Differential Propagation Delay

t

LOW

t

R

t

HIGH

SCL

SDA

t

SU:STA

F

HD:STA

HD:DAT

t

BUF

SU:STO

t

SU:DAT

ST

SP

ST

Figure 3. SMBus Timing Diagram

10

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ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

6.7 Typical Characteristics

Frequency (MHz)

0

1000

2000

3000

4000

5000

0

-1

-2

-3

-4

-5

-6

-1.5

-3.5

-6

Test Conditions

Datarate: 10.3125 Gbps with a PRBS7 pattern

VOD Setting: 1000mV

Jitter Measurements

Rj (RMS): 315 fs

Dj: 3.74 ps

Tj (1E-12): 7.33 ps

Temperature: 25°C and VDD = 2.5V

Figure 5. Output Eye Diagram 10.3125 Gbps

Figure 4. De-Emphasis Gain vs. Frequency

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7 Detailed Description

7.1 Overview

The DS125DF111 is a low-power, multi-rate, 2-channel retimer. Both channels operate independently. Each

channel includes a Continuous Time Linear Equalizer (CTLE) which compensates for the presence of a

dispersive transmission channel between the source and the DS125DF111's input. Each channel includes an

independent Voltage-Controlled Oscillator (VCO) and Phase-Locked Loop (PLL) which produce a clean clock.

The clean clock produced by the VCO and the PLL is phase-locked to the incoming data clock, but the high-

frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially reduced

jitter. This clean clock is used to retime the incoming data, removing high-frequency jitter from the data stream

and producing a data output signal with reduced jitter. This provides the Clock and Data Recovery (CDR)

function of the retimer.

Each channel of the DS125DF111 features an output driver with settable differential output voltage and settable

output de-emphasis. The output de-emphasis compensates for dispersion in the transmission channel at the

output of the DS125DF111.

7.2 Functional Block Diagram

Eye

Monitor

LOS

LA

Channel

Status

and

LOCK

Control

Loopback OUT

SMBus

DFE

Raw

CTLE

IN

Retimed

+

OUT

CDR

Polarity

DE VOD

Signal

Detect

PRBS9

PRBS31

VCO

Loopback IN

Figure 6. 1 of 2 Channels, DS125DF111 Data Path Block Diagram

7.3 Feature Description

7.3.1 Device Data Path Operation

The data path operation of the DS125DF111 is shown in the data path block diagram of Figure 6. The functional

sections are as follows.

•

Input Channel Equalization

Clock and Data Recovery

PRBS Pattern Generator

Datapath Multiplexer and Output Driver

Reference Clock

Control Pins

Eye Opening Monitor

7.3.1.1 Input Channel Equalization

Physical transmission media comprising traces on printed circuit boards (PCBs) or copper cables exhibit a low-

pass frequency response characteristic. The magnitude of the high frequency loss varies with the length of the

transmission medium and with the loss of the materials which comprise it. This differential high frequency loss

and the frequency-dependent group delay of the transmission medium introduce inter-symbol interference in the

high-speed broadband signals propagating through the transmission medium.

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Feature Description (continued)

To make configuration of these settings easier, the DS125DF111 is designed to determine the correct settings

for the CTLE autonomously by automatically adapting these equalizations to the input transmission medium. The

automatic adaptation takes place when a signal is first detected at the input to the DS125DF111, immediately

after the DS125DF111 acquires phase lock.

The automatic adaptation is also triggered whenever the CDR circuitry is reset. The DS125DF111 uses its

internal eye monitor to generate a figure of merit for the adaptation. The DS125DF111 adjusts its CTLE boost

settings in a systematic way to optimize this figure of merit. When 8b/10b encoding is used and the input

channels has more than 15 dB of loss, the CTLE table and or adaption algorithm needs to be modified so as to

prevent CTLE mal-adaption. This scenario occurs when the CTLE boost is insufficient at lower settings to cause

regeneration of the high-frequency content of the K28.5 pattern. As boost is increased, the adaption Figure of

Merit (FOM) temporarily observes eye closure as the EQ boost begins to restore the high-frequency content. If

the FOM does not improve within the look-beyond counter depth, the CTLE will settle at a lower boost, which is

insufficient to equalize the signal and provide good BER. See Table 23 for additional information on CTLE

settings and gain levels.

The 5-tap DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the

DS125DF111. The DFE tap weights and polarities are adaptive and operate in conjunction with the CTLE to

achieve an acceptable BER with more severe channel impairments.

7.3.1.2 Clock and Data Recovery

The DS125DF111 performs its clock and data recovery function by detecting the bit transitions in the incoming

data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit

transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the

bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS125DF111 in a

system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the

system.

7.3.1.3 PRBS Pattern Generator

Each channel in the DS125DF111 can be configured to generate and output its own pseudo random bit

sequence (PRBS). The DS125DF111 pattern generators support the following PRBS sequences:

•

PRBS-9, 2⁹- 1

PRBS-31, 2³¹- 1

7.3.1.4 Datapath Multiplexer and Output Driver

The DS125DF111 datapath multiplexer is used to control which internal signal will be presented to the output

driver block. Inputs to this multiplexer include raw equalized data without clock recovery, retimed data, PRBS

patterns, and Loopback data from the other datapath.

The DS125DF111 output driver is used to control specific signal characteristics to enhance transmission quality.

The output driver is used to control the following signal features

•

Amplitude

De-Emphasis

Edge Rate

Polarity

The DS125DF111 is commonly used in applications where lossy transmission media exist both at the input and

the output of the DS125DF111. The CTLE compensates for lossy transmission media at the input to the

DS125DF111. The output de-emphasis compensates for the lossy transmission medium at the output of the

DS125DF111.

When there is a transition in the output data stream, the output differential voltage reaches its configured

maximum value within the configured rise/fall time of the output driver. Following this, the differential voltage

rapidly falls off until it reaches the configured VOD level minus the configured de-emphasis level. This

accentuates the high-frequency components of the output driver signal at the expense of the low frequency

components. The pre-distorted DS125DF111 output signal, with high-frequency components emphasized relative

to its low frequency components, exhibits less inter-symbol interference after traveling down a dispersive

transmission medium than an undistorted output signal.

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Feature Description (continued)

An idealized transmit waveform with analog de-emphasis applied is shown in Figure 7.

1

0.5

0

-0.5

-1

0

1

2

3

4

5

6

7

8

9

10

Figure 7. Idealized De-Emphasis Waveform

The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis.

The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The

DS125DF111 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user

is responsible for configuring these parameters. They can be set for each channel independently.

7.3.1.5 Reference Clock

A 25 MHz ±100 ppm reference clock is required for proper device operation. The DS125DF111 uses the

reference clock to determine when its VCO is properly phase-locked to the incoming data-rate. The

DS125DF111 does not include a crystal driver, so a stand-alone external oscillator is required.

The DS125DF111 is set to phase lock to a constrained set of data-rates, the digital circuitry in the device pre-

configures the VCO frequency. This enables the DS125DF111 to detect very quickly that a loss of lock has

occurred.

The phase noise of the reference clock is not critical. Any commercially-available 25 MHz oscillator (±100ppm

maximum) can provide an acceptable reference clock. The 25 MHz clock high level input voltage must match the

V_INlevel utilized on the DS125DF111.

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Feature Description (continued)

7.3.1.6 Control Pins

The 4-level input pins utilize a resistor divider to help set the 4 valid levels and provide a wider range of control

settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin.

These resistors, together with the external resistor connection combine to achieve the desired voltage level.

Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down provide the optimal voltage levels for each of

the four input states.

Table 1. 4-Level Inputs

LEVEL

SETTING

1 K to GND

20 K to GND

No connection

1 K to V_IN

VOLTAGE

0.1 V

0

R

0.33 * V_IN

0.67 * V_IN

V_IN- 0.05V

Float

1

In order to minimize the startup current associated with the integrated 2.5-V regulator the 1 K pull-up / pull-down

resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or

more 1 K resistors into a single lower value resistor. As an example; combining two inputs with a single 500 Ω

resistor is a good way to save board space.

7.3.1.6.1 Pin Mode Limitation

Using the control pins directly does limit the ability of the DS125DF111 CTLE to correctly adapt to high frequency

datarates in high loss input channel scenarios. For input channels with more than 15 dB of loss the CTLE

Adaption table and or adaption algorithm needs to be modified in the SMBus channel register so as to prevent

CTLE mal-adaption. This scenario occurs when the CTLE boost is insufficient at the lowest settings to cause

regeneration of the high-frequency content of the K28.5 pattern. As boost is increased, the adaption Figure of

Merit (FOM) temporarily observes eye closure as the EQ boost begins to restore the high-frequency content. If

the FOM does not improve within the look-beyond counter depth, the CTLE will settle at a lower boost, which is

insufficient to equalize the signal and provide good BER. See Table 23 for additional information on CTLE

settings and gain levels.

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7.3.1.7 Eye Opening Monitor

The DS125DF111’s Eye Opening Monitor (EOM) measures the internal data eye at the input of the CDR and can

be used for 2 functions:

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement

2. Full Eye Diagram Capture

The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement

is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from

channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to

convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

•

HEO [UI] = ch reg 0x27 ÷ 64

VEO [mV] = ch reg 0x28 x 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a

64 x 64 array, where each cell in the matrix consists of an 16-bit word. Users can manually adjust the vertical

scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal

scaling controlled by the state machine and is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out 4 16-bit words of junk data that should be

discarded followed by 4096 16-bit words that make up the 64 x 64 eye plot. The first actual word of the eye plot

from the retimer is for (X, Y) position (0,0). Each time the eye plot data is read out the voltage position is

incremented. Once the voltage position has incremented to position 63, the next read will cause the voltage

position to reset to 0 and the phase position to increment. This process will continue until the entire 64 x 64

matrix is read out. Figure 8 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In

this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users

can apply different algorithms to the output data to plot density or color gradients to the output data.

63

127 191

4095

63

64 128

4032

63

0

Phase Position

Figure 8. EOM Full Eye Capture Readout

To manually control the EOM vertical range, remove scaling control from the state machine then select the

desired range:

1. Channel Reg 0x2C[6] → 0

2. See Table 2

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Table 2. Eye Opening Monitor Vertical Range Settings

CHANNEL REG 0x11[7:6] VALUE

EOM VERTICAL RANGE [mV]

2’b00

2'b01

2'b10

2'b11

±100

±200

±300

±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over

equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit

error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

•

Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.

Or single byte reads. With single byte reads, the MSB are located in register 0x25 and the LSB are located in

register 0x26. In this mode, the device must be addressed each time a new byte is read.

To perform a full eye capture with the EOM, follow these steps within the desired channel register set:

Table 3. Eye Opening Monitor Full Eye Capture Instructions

REGISTER

STEP

VALUE

DESCRIPTION

[bits]

1

2

0x3E[7]

0

Disable lock EOM lock monitoring

Set the desired EOM vertical range

0x2C[6]

0x11[7:6]

0

2'b--

3

4

0x11[5]

0x24[7]

0

1

Power on the EOM

Enable fast EOM

Begin read out of the 64 x 64 array, discard first 4 words

Ch reg 0x24[0] is self clearing.

0x25 is the MSB of the 16-bit word

0x24[0]

0x25

0x26

5

1

0x26 is the LSB of the 16-bit word

0x25

0x26

6

7

Continue reading information until the 64 x 64 array is complete.

Return the EOM to its original state. Undo steps 1-4

0x3E[7]

0x2C[6]

0x11[5]

1

0

0x24[7,1]

7.4 Device Functional Modes

To select different programming device, the ENSMB pin selects the control modes. The DS125DF111device can

be programmed using external pin control, a SMBus controller, or through an EEPROM configuration load.

Table 4. ENSMB Control Description

ENSMB PIN

DESCRIPTION

READEN# terminal

Pull Low to initiate reading configuration data from

the EEPROM

High

SMBus Slave Mode

Tie Low to enable proper address strapping on

power up

Float

SMBus Master Mode

R

N/A

Low

Pin Mode Control

Shared with VODA terminal control function

7.4.1 Control Pin Mode

The 4-level input pins utilize a resistor divider to help set the 4 valid levels and provide a wider range of control

settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin.

These resistors, together with the external resistor connection combine to achieve the desired voltage level.

Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down provide the optimal voltage levels for each of

the four input states.

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Table 5. 4-Level Inputs

LEVEL

SETTING

1K to GND

20K to GND

No connection

1K to VIN

VOLTAGE

0

R

0.1 V

0.33 * VIN

0.67 * VIN

VIN - 0.05V

Float

1

Note: V_IN= 2.5V in 2.5V Mode and V_IN= 3.3V in 3.3V Mode

In order to minimize the startup current associated with the integrated 2.5-V regulator the 1K pull-up / pull-down

resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or

more 1K resistors into a single lower value resistor. As an example; combining two inputs with a single 500 Ohm

resistor is a good way to save board space.

7.4.2 SMBus Master Mode and SMBus Slave Mode

In SMBus master mode the DS125DF111 reads its initial configuration from an external EEPROM upon

powerup. The serial EEPROM must support a minimum frequency of 520 KHz. Once the DS125DF111 has

finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus

slave mode and can be further configured by an external controller over the SMBus. Two device pins initiate

reading the configuration from the external EEPROM and indicate when the configuration read is complete.

•

DONE#

READEN#

These pins are meant to work together. When the DS125DF111 is powered up in SMBus master mode, it reads

its configuration from the external EEPROM. This is triggered when the READEN# pin goes low. When the

DS125DF111 is finished reading its configuration from the external EEPROM, it drives its DONE# pin low. In this

mode, as the name suggests, the DS125DF111 acts as an SMBus master during the time it is reading its

configuration from the external EEPROM. After the DS125DF111 has finished reading its configuration from the

EEPROM, it releases control of the SMBus and becomes a SMBus slave. In applications where there is more

than one DS125DF111 on the same SMBus, bus contention can result if more than one DS125DF111 tries to

take command of the SMBus as the SMBus master at the same time. The READEN# and DONE# pins prevent

this bus contention.

In a system where the DS125DF111s are meant to operate in SMBus master mode, the READEN# pin of one

retimer should be wired to the DONE# pin of the next. The system should be designed so that the READEN# pin

of one (and only one) of the DS125DF111s in the system is driven low on power-up. This DS125DF111 will take

command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is

finished reading its configuration, it will set its DONE# pin low. This pin should be connected to the READEN#

pin of another DS125DF111. When this DS125DF111 senses its READEN# pin driven low, it will take command

of the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin

low. By connecting the DONE# pin of each DS125DF111 to the READEN# pin of the next DS125DF111, each

DS125DF111 can read its initial configuration from the EEPROM without causing bus contention.

7.5 Programming

7.5.1 SMBus Interface

7.5.1.1 Address Lines

In either SMBus Master or Slave mode the DS125DF111 must be assigned a SMBus address. A unique address

should be assigned to each device on the SMBus.

The SMBus address is latched into the DS125DF111 approximately 25 ms after power-up. The address is read

in from the state of the ADR[1:0] lines upon power-up. A floating address line input will be interpreted as a logic

0.

The DS125DF111 can be configured with any of 4 SMBus addresses. The SMBus addressing scheme uses the

least significant bit of the SMBus address as the Write/Read_N address bit. When an SMBus device is

addressed for writing, this bit is set to 0; for reading, to 1. Table 6 shows the write address setting for the

DS125DF111 versus the values latched in on the address line at power-up.

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Programming (continued)

7.5.1.2 Device Configuration in SMBus Slave Mode

The configurable settings of the DS125DF111 may be set independently for each channel at any time after

power up using the SMBus. A register write is accomplished when the controller sends a START condition on the

SMBus followed by the Write address of the DS125DF111 to be configured. See Table 6 for the mapping of the

address lines to the SMBus Write addresses. After sending the Write address of the DS125DF111, the controller

sends the register address byte followed by the register data byte. The DS125DF111 acknowledges each byte

written to the controller according to the data link protocol of the SMBus Version 2.0 Specification. See this

specification for additional information on the operation of the SMBus.

There are two types of device registers in the DS125DF111. These are the control/shared registers and the

channel registers. The control/shared registers control or allow observation of settings which affect the operation

of all channels of the DS125DF111. They are also used to select which channel of the device is to be the target

channel for reads from and writes to the channel registers.

The channel registers are used to set all the configuration settings of the DS125DF111. They provide

independent control for each channel of the DS125DF111 for all the settable device characteristics. Any registers

not described in the tables that follow should be treated as reserved. The user should not try to write new values

to these registers. The user-accessible registers described in the tables that follow provide a complete capability

for customizing the operation of the DS125DF111 on a channel-by-channel basis.

7.5.1.3 Bit Fields in the Register Set

Many of the registers in the DS125DF111 are divided into bit fields. This allows a single register to serve multiple

purposes, which may be unrelated. Often configuring the DS125DF111 requires writing a bit field that makes up

only part of a register value while leaving the remainder of the register value unchanged.

7.5.1.4 Writing To and Reading from the Control/Shared Registers

Any write operation targeting register 0xff writes to the control/shared register 0xff. This is the only register in the

DS125DF111 with an address of 0xff. Bit 2 of register 0xff is used to select either the control/shared register set

or a channel register set. If bit 2 of register 0xff is cleared (written with a 0), then all subsequent read and write

operations over the SMBus are directed to the control/shared register set. This situation persists until bit 2 of

register 0xff is set (written with a 1). There is a register with address 0x00 in the control/shared register set, and

there is also a register with address 0x00 in each channel register set. If you read the value in register 0x00

when bit 2 of register 0xff is cleared to 0, then the value returned by the DS125DF111 is the value in register

0x00 of the control/shared register set. If you read the value in register 0x00 when bit 2 of register 0xff is set to 1,

then the value returned by the DS125DF111 is the value in register 0x00 of the selected channel register set.

The channel register set is selected by bits 1:0 of register 0xff. If bit 3 of register 0xff is set to 1 and bit 2 of

register 0xff is also set to 1, then any write operation to any register address will write all the channel register

sets in the DS125DF111 simultaneously. This situation will persist until either bit 3 of register 0xff or bit 2 of

register 0xff is cleared.

Note that when you write to register 0xff, independent of the current settings in register 0xff, the write operation

ALWAYS targets the control/shared register 0xff. This channel select register, register 0xff, is unique in this

regard. Table 7 shows the control/shared register set.

Table 6. SMBus Write Address Assignment⁽¹⁾

ADDR1

ADDR0

SMBus WRITE ADDRESS

SMBus READ ADDRESS

0

1

0

1

0

1

0x30

0x32

0x34

0x36

0x31

0x33

0x35

0x37

(1) A floating ADDR[1:0] pin at power-up will be interpreted as a logic 0.

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Table 7. Control and Shared Register Space

DEFAULT

ADDRESS REGISTER

DEFAULT BIT

VALUE

(BINARY)

BITS

MODE

DESCRIPTION

(HEX)

VALUE

(HEX)

0x00

0x01

00

7:4

7:5

4:0

6

0000

R

SMBus Address Strap Observation <3:0>

Device Revision

011

61

0 0001

R

Device ID

0x04

0x05

0

R/W/SC

R/W

R

Self-Clearing Reset for Control/Shared Registers

Reset for SMBus Master Mode

Force EEPROM Configuration

Indicates EEPROM read complete

Indicates Channel A has interrupted

Indicates Channel B has interrupted

01

5

0

4

0

4

00

3

0

R

2

0

R

0x06

0x07

3:0

0000

R/W

Write to 0xA’h to observe SMBus Address strap in Reg 0x00[7:4]

Loopback:

1

0

R/W

Loopback Input of Channel B to output of Channel A

04

Loopback:

Loopback Input of Channel A to output of Channel B

0xff

Controls LOCK pin output (ADDR0 = 0 or Float)

00: Logical OR of Lock Status from CH A and CH B

01: Lock Status from Channel A

10: Lock Status from Channel B

11: Logical AND of Lock Status from CH A and CH B

Controls LOCK pin output (ADDR0 = 1)

7:6

00

R/W

00: Logical NOR of Lock Status from CH A and CH B

01: NOT Lock Status from Channel A

10: NOT Lock Status from Channel B

11: Logical NAND of Lock Status from CH A and CH B

00

Loss of Signal / Interrupt (LOS/INT) pin output

5

3

0

R/W

0: LOS

1: Interrupt

Selects Both Channels for Register Write. Register read from one

channel based on the selected channel in register 0xff bits 1:0. See

Table 8

0 = reads/writes directed to shared registers

2

0

R/W

1 = reads/writes directed to channel registers based on target

channel defined by register 0xff bits 1:0. See Table 8

1:0

Selects Target Channel for Register Reads and Writes. See Table 8

7.5.1.5 SMBus Strap Observation

Register 0x00, bits 7:4

In order to communicate with the DS125DF111 over the SMBus, it is necessary for the SMBus controller to know

the address of the DS125DF111. The address strap observation bits in control/shared register 0x00 are primarily

useful as a test of SMBus operation. In order to use the address strap observation bits of control/shared register

0x00, it is necessary first to set the diagnostic test control bits of control/shared register 0x06. This four bit field

should be written with a value of 0xa. When this value is written to bits 3:0 of control/shared register 0x06, then

the value of the SMBus address straps can be read in register 0x00, bits 7:4. The value read will be the same as

the value present on the ADDR line when the DS125DF111 powers up. For example, if a value of 0x0 is read

from control/shared register 0x00, bits 7:4, then at power-up the ADDR line was set to 0. The DS125DF111 is set

to a SMBus Write address of 0x30.

7.5.1.6 Interrupt Channel Flag Bits

Register 0x05, bits 3:2

The operation of these bits is described in the section on interrupt handling later in this data sheet.

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7.5.1.7 Control/Shared Register Reset

Register 0x04, bit 6

Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self clearing,

so it is cleared after it is written and the control/shared registers are reset to their factory default values.

7.5.1.8 Device Revision and Device ID

Register 0x01

Control/shared register 0x01 contains the device revision and device ID. The device ID will be different for the

different devices in the retimer family. This register is useful because it can be interrogated by software to

determine the device variant and revision installed in a particular system. The software might then configure the

device with appropriate settings depending upon the device variant and revision.

Table 8. Channel Select Register Values Mapped to Register Set Target

BROADCAST

CHANNEL

REGISTER

SELECTION

TARGETED

CHANNEL

REGISTER

SELECTION

SHARED/CHANNEL

REGISTER

REGISTER 0xFF

VALUE (HEX)

COMMENTS

SELECTION

0x00

0x04

0x05

Shared

Channel

N/A

No

N/A

A

All reads and writes target shared register set

All reads and writes target channel register set

No

B

All writes target all channel register sets, all reads

target Channel A register set

0x0c

0x0d

Channel

Yes

A

B

All writes target all channel register sets, all reads

target Channel B register set

7.5.1.9 Channel Select Register

Register 0xff, bits 3:0

Register 0xff, as described above, selects the channel or channels for channel register reads and writes. It is

worth describing the operation of this register again for clarity. If bit 3 of register 0xff is set, then any channel

register write applies to all channels. Channel register read operations always target only the channel specified in

bits 1:0 of register 0xff regardless of the state of bit 3 of register 0xff. Read and write operations target the

channel register sets only when bit 2 of register 0xff is set.

Bit 2 of register 0xff is the universal channel register enable. This bit must be set in order for any channel register

reads and writes to occur. If this bit is set, then read operations from or write operations to register 0x00, for

example, target channel register 0x00 for the selected channel rather than the control/shared register 0x00. In

order to access the control/shared registers again, bit 2 of register 0xff should be cleared. Then the

control/shared registers can again be accessed using the SMBus. Write operations to register 0xff always target

the register with address 0xff in the control/shared register set. There is no other register, and specifically, no

channel register, with address 0xff.

All eight bits of this register should always be set to the desired values whenever this register is written. The

register set target selected by each valid value written to the channel select register is shown in Table 8.

7.5.1.10 Resetting Individual Channels of the Retimer

Register 0x00, bit 2, and register 0x0a, bits 3:2

Bit 2 of channel register 0x00 is used to reset all the registers for the corresponding channel to their factory

default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the

DS125DF111 since it was powered-up.

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To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and

adaptation sequence for a particular channel, use channel register 0x0a. Set bits 2 and 3 of this register to

enable the reset override and force the CDR state machine into reset. These bits can be set in the same

operation. When both bits are subsequently cleared, the CDR state machine will resume normal operation. If a

signal is present at the input to the selected channel, the DS125DF111 will attempt to lock to it and will adapt its

CTLE and its DFE according to the currently configured adapt mode for the selected channel. The adapt mode is

configured by channel register 0x31, bits 6:5.

7.5.1.11 Rate and Subrate Setting

Each channel of the DS125DF111 will, by default operate at the primary datarates of 12.288 Gbps and 9.8304

Gbps. In addition to the primary rates, the DS125DF111 will operate at divide by 2/4/8 datarates using the default

settings. The device can be configured to operate with limited VCO divide ratios by selecting a RATE/SUBRATE

combination other than the default value of 0110'b. For example, selecting a RATE (Reg: 0x2F bits [7:6]) and

SUBRATE (Reg: 0x2F bits [5:4]) of 0000'b will limit the DS125DF111 to 1.2288 Gbps (Group 0 = 9.8304 / 8) and

12.288 Gbps (Group 1 = 12.288 / 1).

Table 9. Rate/Subrate VCO and Data-Rate Information

RATE

SUBRATE

GROUP 0 DIVIDE RATIOS⁽¹⁾

GROUP 1 DIVIDE RATIOS⁽¹⁾

00

8

1

00

01

1, 2, 4

1

00

10

1, 2, 4

00

11

1, 2, 4

01

00

2, 4

01

1, 4

01 (default)

10 (default)

1, 2, 4, 8

01

10

11

00

01

10

11

00

01

10

11

1

2

2, 4

1

2, 4

1

8

1

(1) The default datarates are Group 0 = 9.8304, 4.9152, 2.4576, 1.2288 Gbps and Group 1 =12.288, 6.144, 3.072, 1.536 Gbps.

The DS125DF111 is designed to lock to signals conforming to several different data transmission standards.

These standards may define a single data rate or multiple data rates. The rate and subrate settings of the

DS125DF111 are used to select which VCO divide ratios to enable. The DS125DF111 searches specific

datarates within these enabled VCO divide ratios starting with divide by 8 and working up to divide by 1.

To select datarates based on frequencies other than the VCO defaults a group of PPM Counter registers (0x60 -

0x64) need to be reprogrammed.

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Table 10. Group 0 VCO Frequency Programming Registers

GROUP 0

VCO (GHZ)

REGISTER 0x60[7:0]

REGISTER 0x61[7]

REGISTER 0x61[6:0]

REGISTER 0x64[7:4]

Frequency

Group 0 PPM Count [7:0]

Override Group 0 PPM

Group 0 PPM Count [14:8]

Group 0 PPM Delta[3:0]

Table 11. Group 1 VCO Frequency Programming Registers

GROUP 1

VCO (GHZ)

REGISTER 0x62[7:0]

REGISTER 0x63[7]

REGISTER 0x63[6:0]

REGISTER 0x64[3:0]

Frequency

Group 1 PPM Count [7:0]

Override Group 1 PPM

Group 1 PPM Count [14:8]

Group 1 PPM Delta[3:0]

Table 12. Programming Values for Common Data Rates

VCO GROUP 0 VCO GROUP 1

REGISTER 0x60

REGISTER 0x61 REGISTER 0x62

REGISTER 0x63

REGISTER 0x64

(GHz)

9.8304

12.288

0x26

0xC4

0x00

0x98

0x8C

0xB1

0xB2

0xB4

0xB5

0x70

0xC4

0x90

0x98

0x7A

0xBD

0xB1

0xB3

0xB4

0xB7

0xFF

0xCC

0xCD

0xDD

0xDE

9.95328

10.0

9.95328

10.3125

10.51875

11.0957

10.51875

10.70957

To set the VCO Registers for other datarates within the VCO range, the formulas shown can be used to populate

the Group 0/1 VCO programming registers.

Table 13. Group 0 VCO Programming Equations

PARAMETER

Reference Clock

VALUE or EQUATION

COMMENT

F0 = 25e6

F1

Internally the reference clock always

operates at 25 MHz

Desired Group 0 VCO Frequency

F1 is the frequency of the VCO which is

equal to the desired data rate. If the desired

data rate uses dividers, be sure to multiply

the data rate by the divide setting to get the

correct VCO frequency

Number of Reference Clocks

VCO Freq ÷ 32

N = 1024

F2 = F1 ÷ 32

F3 = F2 x N ÷ F0

F4

Counts of VCO Freq ÷ 32 required

Counts of VCO Freq ÷ 32 required rounded

Integer value only. Convert this value to

binary. Program the upper 7 bits to channel

register 0x61[6:0] and the lower 8 bits to ch

register 0x60[7:0]. Be sure to set channel

register 0x61[7] to 1 to enable the override

function for manual programming.

PPM error due to rounding

Err = 1e6 x (F4 – F3) ÷ F3

F5 = F4 ÷ 1000

VCO Freq ÷ 32 (1000 PPM tolerance)

Group 0 PPM Delta (Register 0x64[7:4])

Integer Value only, maximum value = 15.

Convert to Hex for register.

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Table 14. Group 1 VCO Programming Equations

PARAMETER

Reference Clock

VALUE or EQUATION

COMMENT

F0 = 25e6

F1

Internally the reference clock always

operates at 25 MHz

Desired Group 1 VCO Frequency

F1 is the frequency of the VCO which is

equal to the desired data rate. If the desired

data rate uses dividers, be sure to multiply

the data rate by the divide setting to get the

correct VCO frequency

Number of Reference Clocks

VCO Freq ÷ 32

N = 1024

F2 = F1 ÷ 32

F3 = F2 x N ÷ F0

F4

Counts of VCO Freq ÷ 32 required

Counts of VCO Freq ÷ 32 required rounded

Integer value only. Convert this value to

binary. Program the upper 7 bits to ch

register 0x63[6:0] and the lower 8 bits to ch

register 0x62[7:0]. Be sure to set channel

register 0x63[7] to 1 to enable the override

function for manual programming.

PPM error due to rounding

Err = 1e6 x (F4 – F3) ÷ F3

F5 = F4 ÷ 1000

VCO Freq ÷ 32 (1000 PPM tolerance)

Group 1 PPM Delta (Register 0x64[3:0])

Integer Value only, maximum value = 15.

Convert to Hex for register.

7.5.1.12 Overriding the CTLE Boost Setting

Register 0x03, Register 0x2D, bit 3, and Register 0x3a

To override the adaptive CTLE boost settings, channel register 0x03 is used in conjunction with override register

bit for the CTLE (0x2D[3]). If the override bit is set in 0x2D[3], CDR LOCK re-acquisition will fail in CTLE adapt

modes 1-3.

The current CTLE setting applied to the high-speed analog input can always be read back from register 0x52.

This readback register value is valid for adaptive CTLE settings or when the override mechanism is enabled and

the CTLE value from register 0x03 is being used.

When in divide by 4 or 8 VCO settings, CTLE channel register 0x3A comes into play. Divide by 4 and divide by 8

data-rates do not automatically adapt the CTLE setting, they use the value in register 0x3A as a settable CTLE

level.

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7.5.1.13 Overriding the Output Multiplexer

Register 0x09, bit 5 and Register 0x1e, bits 7:5

By default, the DS125DF111 output for each channel will be as shown in Table 15 and Table 16.

Table 15. Default Output Status Description

INPUT SIGNAL

CHANNEL STATUS

OUTPUT STATUS

STATUS

Absent

No Signal Detected

Not Locked

Mute

Present

Set by 0x1e[7:5]

Locked

Raw or Retimed, Set by 0x1e[7:5], 0x09[5]

Table 16. Output Multiplexer Override Settings,

Register 0x1e Bit 7:5

REGISTER

0x1E[7:5]

OUTPUT

COMMENTS

MULTIPLEXER

111

Mute

See Using the PRBS Generator for additional information

on PRBS generator usage.

100

PRBS Generator

001

000

Retimed Data

Raw Data

Default when the retimer is locked

Output of the CTLE + DFE, before retiming

This default behavior can be modified by register writes. Register 0x1e, bits 7:5, contain the output multiplexer

override value. The values of this three-bit field and the corresponding meanings of each are shown in Table 16.

When no signal is present at the input to the selected channel of the DS125DF111 the signal detect circuitry will

power down the channel. This includes the output driver which is therefore muted when no signal is present at

the input.

7.5.1.14 Overriding the VCO Divider Selection

Register 0x09, bit 2, and Register 0x18, bits 6:4

In normal operation, the DS125DF111 sets its VCO divider to the correct divide ratio, either 1, 2, 4, or 8

depending upon the bit rate of the signal at the channel input and the selected rate/subrate code. It is possible to

override the divider selection. This might be desired if the VCO is set to free run, for example, to output a PRBS

signal at a sub-harmonic of the actual VCO frequency.

In order to override the VCO divider settings, first set bit 2 of register 0x09. This is the VCO divider override

enable. Once this bit is set, the VCO divider setting is controlled by the value in register 0x18, bits 6:4. The valid

values for this three-bit field are 0x0 to 0x3. The mapping of the bit field values to the divider ratio is shown in

Table 17.

Table 17. Divider Ratio Map

BIT FIELD VALUE REG 18 [6:4]

DIVIDER RATIO

0

1

2

3

1

2

4

8

In order for the DS125DF111 to acquire LOCK, the override divider selection must be included in the Group 0

VCO list for the current Rate/Subrate setting.

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7.5.1.15 Using the Internal Eye Opening Monitor

Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register

0x26, Register 0x27, Register 0x28, Register 0x2a and Register 0x3e, bit 7

The DS125DF111 includes an internal eye opening monitor. The eye opening monitor is used by the retimer to

compute a figure of merit for automatic adaptation of the CTLE and the DFE. It can also be controlled and

queried through the SMBus by a system controller. Note that eye monitor is not equivalent to a pattern checker, it

is possible under very stressful input conditions that the adapted CTLE/DFE settings will incorrectly determine

the proper value of the incoming data pattern.

The eye opening monitor produces error hit counts for settable phase and voltage offsets of the comparator in

the retimer. This is similar to the way many Bit Error Rate Test Sets measure eye opening. At each phase and

amplitude offset setting, the eye opening monitor determines the nominal bit value (“0” or “1”) using its primary

comparator. This is the bit value that is resynchronized to the recovered clock and presented at the output of the

DS125DF111. The eye opening monitor also determines the bit value detected by the offset comparator. This

information yields an eye contour. Here's how this works.

If the offset comparator is offset in voltage by an amount larger than the vertical eye opening, for example, then

the offset comparator will always decide that the current bit has a bit value of “0”. When the bit is really a “1”, as

determined by the primary comparator, this is considered a bit error. The number of bit errors is counted for a

settable interval at each setting of the offset phase and voltage of the offset comparator. These error counts can

be read from registers 0x25 and 0x26 for sequential phase and voltage offsets. These error counts for all phase

and voltage offsets form a 64 X 64 point array. A surface or contour plot of the error hit count versus phase and

voltage offset produces an eye diagram, which can be plotted by external software.

The eye opening monitor works in two modes. In the first, only the horizontal and vertical eye openings are

measured. The eye opening monitor first sweeps its variable-phase clock through one unit interval with the

comparison voltage set to the mid-point of the signal. This determines the mid-point of the horizontal eye

opening. The eye opening monitor then sets its variable phase clock to the mid-point of the horizontal eye

opening and sweeps its comparison voltage. These two measurements determine the horizontal and vertical eye

openings. The horizontal eye opening value is read from register 0x27 and the vertical eye opening from register

0x28. Both values are single byte values.

The measurement of horizontal and vertical eye opening is very fast. The speed of this measurement makes it

useful for determining the adaptation figure of merit. In normal operation, the HEO and VEO are automatically

measured periodically to determine whether the DS125DF111 is still in lock. Reading registers 0x27 and 0x28

will yield the most-recently measured HEO and VEO values.

In normal operation, the eye monitor circuitry is powered down most of the time to save power. When the eye is

to be measured under external control, it must first be enabled by writing a 0 to bit 5 of register 0x11. The default

value of this bit is 1, which powers down the eye monitor except when it is powered-up periodically by the CDR

state machine and used to test CDR lock. The eye monitor must be powered up to measure the eye under

external SMBus control.

Bits 7:6 of register 0x11 are also used during eye monitor operation to set the EOM voltage range. This is

described below. A single write to register 0x11 can set both bit 5 and bits 7:6 in one operation.

Register 0x3e, bit 7, enables horizontal and vertical eye opening measurements as part of the lock validation

sequence. When this bit is set, the CDR state machine periodically uses the eye monitor circuitry to measure the

horizontal and vertical eye opening. If the eye openings are too small, according to the pre-determined

thresholds in register 0x6a, then the CDR state machine declares lock loss and begins the lock acquisition

process again. For SMBus acquisition of the internal eye, this lock monitoring function must be disabled. Prior to

overriding the EOM by writing a 1 to bit 0 of register 0x24, disable the lock monitoring function by writing a 0 to

bit 7 of register 0x3e.

Once the eye has been acquired, you can reinstate HEO and VEO lock monitoring by once again writing a 1 to

bit 7 of register 0x3e. Under external SMBus control, the eye opening monitor can be programmed to sweep

through all its 64 states of phase and voltage offset autonomously. This mode is initiated by setting register 0x24,

bit 7, the fast_eom mode bit.

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Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode. When the fast_eom bit is set, the eye

opening monitor operation is initiated by setting bit 0 of register 0x24, which is self-clearing. As soon as this bit is

set, the eye opening monitor begins to acquire eye data. The results of the eye opening monitor error counter are

stored in register 0x25 and 0x26. In this mode the eye opening monitor results can be obtained by repeated

multi-byte reads from register 0x25. It is not necessary to read from register 0x26 for a multi-byte read. As soon

as the eight most significant bits are read from register 0x25, the eight least significant bits for the current setting

are loaded into register 0x25 and they can be read immediately. As soon as the read of the eight most significant

bits has been initiated, the DS125DF111 sets its phase and voltage offsets to the next setting and starts its error

counter again. The result of this is that the data from the eye opening monitor is available as quickly as it can be

read over the SMBus with no further register writes required. The external controller just reads the data from the

DS125DF111 over the SMBus as fast as it can. When all the data has been read, the DS125DF111 clears the

eom_start bit.

If multi-byte reads are not used, meaning that the device is addressed each time a byte is read from it, then it is

necessary to read register 0x25 to get the MSB (the eight most significant bits) and register 0x26 to get the LSB

(the eight least significant bits) of the current eye monitor measurement. Again, as soon as the read of the MSB

has been initiated, the DS125DF111 sets its phase and voltage offsets to the next setting and starts its error

counter again. In this mode both registers 0x25 and 0x26 must be read in order to get the eye monitor data. The

eye monitor data for the next set of phase and voltage offsets will not be loaded into registers 0x25 and 0x26

until both registers have been read for the current set of phase and voltage offsets. In all eye opening monitor

modes, the amount of time during which the eye opening monitor accumulates eye opening data can be set by

the value of register 0x2a. In general, the greater this value the longer the accumulation time. When this value is

set to its maximum possible value of 0xff, the maximum number of samples acquired at each phase and

amplitude offset is approximately 218. Even with this setting, the eye opening monitor values can be read from

the SMBus with no delay. The eye opening monitor operation is sufficiently fast that the SMBus read operation

cannot outrun it.

The eye opening is measured at the input to the data comparator. At this point in the data path, a significant

amount of gain has been applied to the signal by the CTLE. In many cases, the vertical eye opening as

measured by the EOM will be on the order of 400 to 500 mV peak-to-peak. The secondary comparator, which is

used to measure the eye opening, has an adjustable voltage range from ±100 mV to ±400 mV. The EOM voltage

range is normally set by the CDR state machine during lock and adaptation, but the range can be overridden by

writing a two-bit code to bits 7:6 of register 0x11. The values of this code and the corresponding EOM voltage

ranges are shown in Table 18.

Table 18. EOM Voltage Range vs Reg 0x11 [7:6]

VALUE IN BITS 7:6 OF REGISTER 0x11

EOM VOLTAGE RESOLUTION (mv)

EOM VOLTAGE RANGE (± mV)

0x0

0x1

0x2

0x3

3.125

6.250

9.375

12.500

±100

±200

±300

±400

Note that the voltage ranges shown in Table 18 are the post CTLE voltage ranges of the signal at the input to the

data path comparator. These values are not directly equivalent to any observable voltage measurements at the

input to the DS125DF111. Note also that if the EOM voltage range is set too small the voltage sweep of the

secondary comparator may not be sufficient to capture the vertical eye opening. When this happens the eye

boundaries will be outside the vertical voltage range of the eye measurement.

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To summarize, the procedure for reading the eye monitor data from the DS125DF111is shown below.

1. Select the DS125DF111 channel to be used for the eye monitor measurement by writing the channel select

register, register 0xff, with the appropriate value as shown in Table 8. If the correct channel register set is

already selected, this step may be skipped.

2. Select the eye monitor voltage range by setting bits 7:6 of register 0x11 according to the values in Table 18.

The CDR state machine will have set this range during lock acquisition, but it may be necessary to change it

to capture the entire vertical eye extent.

3. Power up the eye monitor circuitry by clearing bit 5 of register 0x11. Normally the eye monitor circuitry is

powered up periodically by the CDR state machine. Clearing bit 5 of register 0x11 enables the eye monitor

circuitry unconditionally. This bit should be set again once the eye acquisition is complete. Clearing bit 5 and

setting bits 7:6 of register 0x11 as desired can be combined into a single register write if desired.

4. Clear bit 7 of register 0x22. This is the eye monitor override bit. It is cleared by default, so you may not need

to change it.

5. Set bit 7 of register 0x24. This is the fast eye monitor enable bit.

6. Set bit 1 of register 0x24. This initiates the automatic fast eye monitor measurement. This bit can be set at

the same time a bit 7 of register 0x24 if desired.

7. Read the data array from the DS125DF111. This can be accomplished in two ways.

–

If you are using multi-byte reads, address the DS125DF111 to read from register 0x25. Continue to read

from this register without addressing the device again until you have read all the data desired. The read

operation can be interrupted by addressing the device again and then resumed by reading once again

from register 0x25.

–

If you are not using multi-byte reads, then read the MSB for each phase and amplitude offset setting from

register 0x25 and the LSB for each setting from register 0x26. In this mode, you address the device each

time you want to read a new byte.

8. In either mode, the first four bytes do not contain valid data. These should be discarded.

9. Continue reading eye monitor data until you have read the entire 64X64 array.

10. Clear bit 7 of register 0x24. This disables fast eye monitor mode.

11. Set bit 5 of register 0x11. This will return control of the eye monitor circuitry to the CDR state machine.

12. Set bit 7 of register 0x3e. This re-enables the HEO and VEO lock monitoring.

7.5.1.16 Overriding the DFE Tap Weights and Polarities

Register 0x11, bits 3:0, Register 0x12, bit 7 and bits 4:0, Register 0x15, bit 7, Register 0x1e, bit 3, Register 0x20,

Register 0x21, Register 0x23, bit 6, Register 0x24, bit 2, Register 0x2f, bit 0, and Registers 0x71–0x75

For the DS125DF111 the DFE tap weights and polarities are normally set automatically by the adaptation

procedure. These values can be overridden by the user if desired.

Prior to overriding the DFE tap weights and polarities, the dfe_ov bit, bit 6 of register 0x23, should be set. This bit

is set by default. In order for the DFE tap weights and polarities to be applied to the input signal, bit 3 of register

0x1e, the dfe_PD bit, which powers down the DFE, should be cleared. This bit is cleared by default. It is not

necessary to change the default settings of these registers, but verify that they are set as described.

It is necessary to set bit 7 of register 0x15 to manually set the DFE tap weights. This bit is cleared by default.

Bits 4:0 of register 0x12 set the five-bit weight for DFE tap 1. The first DFE tap has a five-bit setting, while the

other taps are set using four bits. Often the first DFE tap has the largest effect in improving the bit error rate of

the system, which is why this tap has a five-bit weight setting.

The polarity of the tap weight for tap 1 is set using bit 7 of the same register, register 0x12. The polarity is set to

0 by default, which corresponds to a negative algebraic sign for the tap.

The other four taps are set using four-bit fields in registers 0x20 and 0x21. The polarities of these taps are set by

bits 3:0 in register 0x11. These tap polarities are all set to 0 by default.

As is the case for the CTLE settings, if changing the DFE tap weights or polarities causes the DS125DF111 to

lose lock, it may readapt its CTLE in order to reacquire lock. If this occurs, the CTLE settings may appear to

change spontaneously when the DFE tap weights are changed. The mechanism is the same as that described

above for the CTLE boost settings.

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When the DS125DF111 is set to adapt mode 2 or 3 using bits 6:5 of register 0x31, it will automatically adapt its

DFE whenever its CDR state machine is reset. This occurs when the user manually resets the CDR state

machine using bits 3:2 of register 0x0a, or when a signal is first presented at the input to the channel when the

channel is in an unlocked state.

Regardless of the adapt mode, DFE adaptation can be initiated under SMBus control. Because the DFE tap

weight registers are used by the DFE state machine during adaptation, they may be reset prior to adaptation,

which can cause the adaptation to fail. The DFE tap observation registers can be used to prevent this.

Prior to initiating DFE adaptation under SMBus control, write the starting values of the DFE tap settings into the

DFE tap weight registers, registers 0x11, 0x12, 0x20, and 0x21. The values can be read from the observation

registers, registers 0x71 through 0x75. For each DFE tap, read the current value in the observation register. Both

the polarities and the tap weights are contained in the observation registers. For each DFE tap, write the current

tap polarity and tap weight into the DFE tap register. Once all these values have been written, DFE adaptation

can be initiated and it will proceed normally. If the DS125DF111 fails to find a set of DFE tap weights producing a

better adaptation figure of merit than the starting tap weights, the starting tap weights will be retained and used.

CTLE adaptation can also be initiated manually. Setting and then clearing bit 0 of register 0x2f will initiate

adaptation of the CTLE. As with the DFE, if the DS125DF111 fails to find a set of CTLE settings that produce a

better adaptation figure of merit than the starting CTLE values, the starting CTLE values will be retained and

used.

7.5.1.17 Enabling Slow Rise/Fall Time on the Output Driver

Register 0x18, bit 2

Normally the rise and fall times of the output driver of the DS125DF111 are set by the slew rate of the output

transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence

the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For

example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by

a system.

Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.

Setting this bit will approximately double the nominal rise and fall times of the DS125DF111 output driver. This bit

is cleared by default.

7.5.1.18 Using the PRBS Generator

Register 0x1e, bits 7 and 4, Register 0x30, and Register 0x0d

Table 19. Programming Sequence 1: (Requires Valid and Locked Input Data Pattern)

REGISTER

STEP

REGISTER ADDRESS

REGISTER MASK

COMMENTS

DATA

0x0C

0x20

1

2

0xFF

0x09

0xFF (write bits[7:0])

0x20 (only write bit[5])

Enable Broadcast

Override Loopthru Select

Output MUX Select PRBS

Generator

3

0x1E

0x80

0xE0 (only write bits[7:5])

4

5

6

7

0x1E

0x30

0x0D

0x10

0x08

0x00

0x20

0x10

0x08

0x03

0x20

Power-up PRBS Generator

Power-up PRBS Clock

Select PRBS9 pattern (511 bits)

Enable PRBS Clock

Notes:

1. To select PRBS31 instead of PRBS9, change Register Data 0x30 = 0x02 with mask of 0x03 in Step 6.

2. To only select Channel A, change Register Data 0xFF = 0x04 in Step 1.

3. To only select Channel B, change Register Data 0xFF = 0x05 in Step 1.

4. It has been noted in product testing that some pattern analyzers use an alternate PRBS9 polarity.

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Table 20. Programming Sequence 2: (Free-Running VCO @ ~10.3 Gbps, No Input Data Required)

REGISTER

STEP

REGISTER ADDRESS

REGISTER MASK

COMMENTS

DATA

0x0C

0x04

0x80

0x04

0x80

0x12

0x00

1

2

3

4

5

6

7

0xFF

0x00

0x14

0x09

0x08

0x18

0xFF (write bits[7:0])

Enable Broadcast

0x04 (only write bit[2])

Reset Channel Registers

Preset Signal Detect

0x80 (only write bit[7])

0x04

0x80

0x1F

0x70

Override divider select

Override VCO cap count

Set VCO cap count to 12'h

Select divider select to 000'b

Override charge pump power

downs

8

0x09

0x08

9

0x1B

0x09

0x00

0x40

0x03

0x40

Disable both charge pumps

Override Loop-filter DAC

10

Set Loop-filter DAC override

value

11

12

13

14

15

16

0x1F

0x1E

0x30

0x09

0x1E

0x0D

0x12

0x10

0x08

0x20

0x80

0x20

0x1F

0x10

0x0F

0x20

0xE0

0x20

Enable PRBS Generator

Enable Digital Clock - set pattern

to PRBS9

Override Loopthru Select

Output MUX Select PRBS

Generator

PRBS Seed Load

Notes:

1. To select PRBS31 instead of PRBS9, change Register Data 0x30 = 0x0A in Step 13.

2. To achieve a data-rate of approximately 12.2 Gbps change Register Data 0x08 = 0x05 in Step 6.

3. To achieve a data-rate of approximately 9.8 Gbps change Register Data 0x08 = 0x16 in Step 6.

4. To only select Channel A, change Register Data 0xFF = 0x04 in Step 1.

5. To only select Channel B, change Register Data 0xFF = 0x05 in Step 1.

6. With a free running VCO the actual output frequency will change with temperature and voltage. BERT is not

recommended in this mode.

7.5.1.19 Inverting the Output Polarity

Register 0x1f, bit 7

In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes

necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals. The

DS125DF111 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of

register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility

in system design and board layout.

7.5.1.20 Figure of Merit Adaption

Register 0x2c, bits 5:4, Register 0x31, bits 6:5, Register 0x6b, Register 0x6c, Register 0x6d, and Register 0x6e,

bits 7 and 6

The default figure of merit for both the CTLE and DFE adaptation is simple. The horizontal and vertical eye

openings are measured for each CTLE boost setting or set of DFE tap weights and polarities. The vertical eye

opening is scaled to a constant reference vertical eye opening and the smaller of the horizontal or vertical eye

opening is taken as the figure of merit for that set of equalizer settings. The objective is to adapt the equalizer to

a point where the horizontal and vertical eye openings are both large and approximately equal in magnitude. This

usually provides optimum bit error rate performance for most transmission channels.

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Table 21. DS125DF111 Adaption Algorithm Settings, Register 0x31 Bits 6:5

ADAPT MODE

SETTING

<1:0>

REGISTER 0X31, BIT REGISTER 0x31, BIT 5

ADAPTION ALGORITHM

6 adapt_mode [1]

adapt_mode [0]

0

1

0

1

0

1

00

01

10

11

No Adaption

Adapt CTLE Until Optimum

Adapt CTLE Until Optimum the DFE, then CTLE Again (Default)

Adapt CTLE Until Lock, the DFE, the CTLE Again

In the DS125DF111 the CTLE figure of merit type is selected using the two-bit field in register 0x31, bits 6:5.

Table 22. DFE Figure of Merit Type Settings

VALUE IN BITS 5:4 OF

FIGURE OF MERIT TYPE

REGISTER 0x2C

0x0

0x1

Both HEO and VEO used

Only HEO used

0x2

Only VEO used

0x3 (Default)

Both HEO and VEO used

The DS125DF111 capability of adapting based on the following Figure Of Merit.

FOM = Minimum [ HEO, VEO ]

where

•

HEO = Horizontal Eye Opening

VEO = Vertical Eye Opening

FOM = Figure of Merit

7.5.1.21 Setting the Rate and Subrate for Lock Acquisition

Register 0x2f, bits 7:6 and bits 5:4

The rate and subrate settings, which constrain the data rate search can be set using channel register 0x2f. Bits

7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>.

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7.5.1.22 Setting the Adaption/Lock Mode

Register 0x31, bits 6:5, and Register 0x33, bits 7:4 and 3:0, Register 0x34, bits 3:0, Register 0x35, bits 4:0,

Register 0x3e, bit 7, and Register 0x6a

There are four adaptation modes available in the DS125DF111.

•

Mode 0: The user is responsible for setting the CTLE and DFE (for the DS125DF111) values. This mode is

used if the transmission channel response is fixed.

•

Mode 1: Only the CTLE is adapted to equalize the transmission channel. The DFE is enabled , but the tap

weights are all set to 0. This mode is primarily used for smoothly-varying high-loss transmission channels

such as cables and simple PCB traces.

•

Mode 2: In this mode, both the CTLE and the DFE are adapted to compensate for additional loss, reflections,

and crosstalk in the input transmission channel. The maximum DFE tap weights can be constrained using

register 0x34, bits 3:0, and register 0x35, bits 4:0.

Mode 3: In this mode, both the CTLE and DFE are adapted as in mode 2. However, in mode 3, more

emphasis is placed on the DFE setting. This mode may give better results for high crosstalk transmission

channels.

Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the

adaptation algorithm is shown in.

By default the DS125DF111 requires that the equalized internal eye exhibit horizontal and vertical eye openings

greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register

0x6a.

The DS125DF111 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye

opening falls below the threshold set in register 0x6a, the DS125DF111 will declare a loss of lock.

The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of

register 0x3e.

7.5.1.23 Initiating Adaption

Register 0x24, bit 2, and Register 0x2f, bit 0

When the DS125DF111 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is

selected using bits 6:5 in register 0x31, the DS125DF111 will also try to adapt its CTLE and DFE.

Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing

register 0x2f, bit 0. In the DS125DF111, DFE adaptation can be initiated by setting and then clearing bit 2 of

register 0x24. The Adaption for CTLE and DFE is also initiated by cycling the CDR reset bits in register 0x0a

[3:2].

7.5.1.24 Overriding the CTLE Settings Used for CTLE Adaption

Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x40-0x4f

The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined

boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation

process, the DS125DF111 attempts to phase lock to the equalized signal. If the phase lock succeeds, the

DS125DF111 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The

DS125DF111 computes a figure of merit for the eye opening and compares it to the previous best value of the

figure of merit. While the figure of merit continues to improve, the DS125DF111 continues to try additional values

of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of

merit starts to degrade, the DS125DF111 still continues to try additional CTLE settings for a pre-determined trial

count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE

boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in

register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by

default.

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The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers

0x40-0x4F. The default values for these settings are shown in Table 23. These values may be overridden by

setting the corresponding register values over the SMBus. If these values are overridden, then the next time the

CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the

adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost

settings to their defaults. So will power-cycling the DS125DF111.

Table 23. CTLE Settings for Adaption, Register 0x40-0x4F

REGISTER BITS 7:6

BITS 5:4

BITS 3:2

(STAGE 2)

BITS 1:0

(STAGE 3)

CTLE

BOOST

STRING

HEX

VALUE

GAIN (dB)

@ 6.25 GHz

ADAPTATION

INDEX

(HEX)

(STAGE 0) (STAGE 1)

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

0

1

2

1

3

2

1

2

1

3

2

3

0

1

0

1

2

3

1

2

1

2

3

0

1

0

1

2

1

2

1

2

0

1

2

1

0000

1000

2000

1100

3000

2100

1110

2200

2300

2111

1221

3111

2121

2211

3212

3321

00

40

80

50

C0

90

54

A0

B0

95

69

D5

99

A5

E6

F9

3

0

1

8

11

13

14

15

17

18

20

24

26

27

28

29

31

33

2

3

4

5

6

7

8

9

10

11

12

13

14

15

As an alternative to, or in conjunction with, writing the CTLE boost setting registers 0x40 through 0x4f, it is

possible to set the starting CTLE boost setting index. To override the default setting, which is 0, set bit 3 of

register 0x2f. When this bit is set, the starting index for adaptation comes from register 0x39, bits 4:0. This is the

index into the CTLE settings table in registers 0x40 through 0x4f. When this starting index is 0, which is the

default, CTLE adaptation starts at the first setting in the table, the one in register 0x40, and continues until the

optimum Figure of Merit (FOM) is reached.

Adjusting the starting index helps the DS125DF111 CTLE to correctly adapt to 8b/10b encoded high frequency

datarates in high loss input channel scenarios. For input channels with more than 15 dB of loss the CTLE

Adaption table and or adaption algorithm needs to be modified in the SMBus channel register so as to prevent

CTLE mal-adaption. This scenario occurs when the CTLE boost is insufficient at the lowest settings to cause

regeneration of the high-frequency content of the K28.5 pattern. As boost is increased, the adaption FOM

temporarily observes eye closure as the EQ boost begins to restore the high-frequency content. If the FOM does

not improve within the look-beyond counter depth, the CTLE will settle at a lower boost, which is insufficient to

equalize the signal and provide good BER.

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Table 24. VOD Settings

VODA/B

BIT 2, sel_vod[2]

BIT 1, sel_vod[1]

BIT 0, sel_vod[0]

OUTPUT VOD (mVppd)

(Pin 9 / Pin 10)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

600

700

R

800

900

F

1

1000

1100

1200

1300

7.5.1.25 Setting the Output Differential Voltage

Register 0x2d, bits 2:0

There are eight levels of output differential voltage available in the DS125DF111 SMBus register settings, from

0.6 V to 1.3 V in 0.1 V increments. The values in bits 2:0 of register 0x2d set the output VOD. The available VOD

settings and the corresponding values of this bit field are shown in Table 24. Not all VOD levels are available

using the VODA/B control pins when ENSMB = 0.

7.5.1.26 Setting the Output De-Emphasis Setting

Register 0x15, bits 2:0 and bit 6

Fifteen output de-emphasis settings are available in the DS125DF111, ranging from 0 dB to -12 dB. The de-

emphasis values come from register 0x15, bits 2:0 and register 0x15, bit 6, which is the de-emphasis range bit.

The available driver de-emphasis settings and the mapping to these bits are shown in Table 25.

Table 25. De-Emphasis Settings

DEMA/B

(Pin 4 / Pin 5)

REG 0X15 BIT [2],

drv_dem[2]

REG 0X15 BIT [1],

drv_dem[1]

REG 0X15 BIT [0],

drv_dem[0]

REG 0X15 BIT [6],

drv_dem_range

DE-EMPHASIS

SETTING (dB)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.0

-0.9

-1.5

-2.0

-2.8

-3.3

-3.5

-3.9

-4.5

-5.0

-5.6

-6.0

-7.5

-9.0

-12.0

R

F

1

7.5.1.27 CTLE Setting for Divide by 4 and Divide by 8 VCO Ranges

Register 0x3a, bits 7:0

In the DS125DF111 the default CTLE setting for lower speed signals is taken directly from register 0x3a and is

not automatically adapted. For long, high loss input channels this value may need to be increased from the

default (minimum) CTLE setting.

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7.6 Register Maps

7.6.1 Reading To and Writing from the Channel Registers

Each channel has a complete set of channel registers associated with it. The channel registers or the control/

shared registers are selected by channel select register 0xff. The settings in this register control the target for

subsequent register reads and writes until the contents of register 0xff are explicitly changed by a register write

to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register.

Table 26. Channel Register Definition

DEFAULT

VALUE

(HEX)

DEFAULT

VALUE

(BINARY)

ADDRESS

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

Reset Channel Registers to Defaults

(Self-clearing)

0x00

0x01

00

2

0

N

R/W/SC

R

4

0

CDR Lock Loss Interrupt

Signal Detect Loss Interrupt

CDR Status [7:0]

Bit[7] = Reserved

Bit[6] = Reserved

Bit[5] = Fail Lock Check

Bit[4] = Lock

0x02

00

7:0

00’h

N

R

Bit[3] = CDR Lock

Bit[2] = Reserved

Bit[1] = Reserved

Bit[0] = Reserved

7:6

5:4

3:2

00

Y

R/W

Used for setting CTLE value when Channel

Register 0x2D[3] is high. Read-back value

going to analog in Channel Register 0x52.

CTLE Boost Stage [0] <1:0> Bits [7:6]

CTLE Boost Stage [1] <1:0> Bits [5:4]

CTLE Boost Stage [2] <1:0> Bits [3:2]

CTLE Boost Stage [3] <1:0> Bits [1:0]

0x03

0x08

00

1:0

00

Y

R/W

7:5

4:0

7

000

00000

0

N

Y

R/W

Reserved

CDR Cap_DAC Start Group 0

Reserved

6

0

Reserved

Enable Override Output Mux

(Register 0x1E[7:5])

5

4:3

2

0

00

0

Y

0x09

00

Reserved

R/W

Enable Override Divider Select

(Register 0x18[6:4])

1:0

7:5

4

00

000

1

Y

Reserved

Enable CDR Reset Override (Register

0x0A[2])

0x0A

0x0B

10

0F

3

0

Y

2

0

Y

N

Y

CDR Reset Override Bit

Reserved

1:0

7:5

4:0

7:4

00

000

1111

0000

R/W

Reserved

CDR Cap_DAC Start Group 1

Status Control[3:0]

Single Bit Transition Detector – Lock

Qualification

1: Enables SBT

3

1

N

0x0C

08

R/W

0: Disables SBT

2

0

Y

N

Reserved

1:0

00

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Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

VALUE

(HEX)

DEFAULT

VALUE

(BINARY)

ADDRESS

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

7:6

00

N

Reserved

PRBS pattern shift Enable.

Use in conjunction with 0x1E[4] and 0x30[3] to

start PRBS.

0x0D

00

5

0

Y

R/W

Note: This bit must be set high last.

4:0

7:0

7:5

4:0

00000

1001 0011

0110 1001

001

N

Y

Reserved

0x0E

0x0F

93

69

R/W

0x10

3A

Y

R/W

Reserved

11010

Eye Opening Monitor Voltage Range <1:0>

00: 3.125 mV

7:6

00

Y

01: 6.250 mV

10: 9.375 mV

11: 12.500 mV

R/W

5

4

1

0

Y

N

Eye Opening Monitor Power Down

Reserved

0x11

20

DFE Tap 2 Polarity

(Use w/manual DFE override, 0x15[7])

3

2

1

0

7

0

1

Y

DFE Tap 3 Polarity

(Use w/manual DFE override, 0x15[7])

R/W

DFE Tap 4 Polarity

(Use w/manual DFE override, 0x15[7])

DFE Tap 5 Polarity

(Use w/manual DFE override, 0x15[7])

DFE Tap 1 Polarity

(Use w/manual DFE override, 0x15[7])

R/W

6

5

0

N

Y

N

Y

N

Y

N

Reserved

0x12

A0

1

DFE Select negative gm

DFE Tap 1 Weight <4:0>

R/W

4:0

7

00000

1

0

6

Reserved

5

0

R/W

4

1

Enable DC offset control

Reserved

0x13

90

3

0

2

0

CTLE Boost Stage 3, Bit 2 (Limiting Bit)

Enable DWDM Mode

1

0

Reserved

7

0

Force Signal Detect On

Force Signal Detect Off

Signal Detect – Assert Reference Levels

Signal Detect – De-assert Reference Levels

Reserved

6

0

0x14

00

5:4

3:2

1:0

00

R/W

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Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

ADDRESS

(HEX)

DEFAULT

VALUE

(BINARY)

VALUE

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

Enables manual DFE tap settings

Use with 0x11[3:0], 0x12[7], 0x12[4:0],

0x20[7:0], 0x21[7:0]

7

0

Y

R/W

6

5

4

3

0

1

0

Compress the range of de-emphasis to 0-6 dB

Y

R/W

Reserved

0x15

10

Reserved

Y

R/W

Driver Power-Down

Driver De-emphasis Setting<2:0>; 0dB - 12dB;

See Table 25

2:0

000

7:4

3:0

7:4

3:0

7

0111

1010

0010

0101

0

Y

N

0x16

0x17

7A

25

R/W

Reserved

VCO Divider Ratio <2:0>

(Enable from Register 0x09, Bit 2)

000: Full-Rate

6:4

100

Y

R/W

001: Divide by 2

010: Divide by 4

011: Divide by 8

0x18

40

100: Default value at power up

3

0

N

Y

N

Y

2

Enable slow rise/fall time edge rate

Reserved

1:0

7:6

5:0

7:4

3:0

7:2

1:0

7:5

4:2

1:0

7

00

0x19

0x1A

0x1B

37

00

03

R/W

Reserved

110111

0000

000000

11

001

00

0x1C

0x1D

24

00

Y

R/W

Reserved

0

Y

N

6:0

000000

Selects PFD MUX for Loopback

000: Raw Data

7:5

111

0

Y

R/W

001: Re-timed Data

100: PRBS Generator

111: Mute

0x1E

0x1F

E1

55

Enable the PRBS serializer, used with

0x1E[7:5], 0x30[3:0], 0x0D[5]

4

N

Y

R/W

3

2:1

0

Disable the DFE function (Disable = 1)

00

Reserved

1

Reserved

7

0

1

Invert the polarity of the driver

Reserved

Y

N

6

R/W

5:0

010101

Reserved

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www.ti.com.cn

Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

VALUE

(HEX)

DEFAULT

VALUE

(BINARY)

ADDRESS

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

DFE Tap 5 Weight <3:0>

(Use w/manual DFE override, 0x15[7])

7:4

3:0

7:4

3:0

0000

Y

0x20

0x21

00

R/W

DFE Tap 4 Weight <3:0>

(Use w/manual DFE override, 0x15[7])

DFE Tap 3 Weight <3:0>

(Use w/manual DFE override, 0x15[7])

R/W

DFE Tap 2 Weight <3:0>

(Use w/manual DFE override, 0x15[7])

7

6

0

Y

N

Y

N

Eye Monitor override

0x22

0x23

00

40

0

Reserved

5:0

7

00000

Reserved

0

R/W

R

Eye Monitor Get HEO VEO override

DFE Override

6

1

5:0

7

000000

Eye Monitor VDAC

0

Enable Fast Eye Opening Monitor Mode

DFE Error - No Lock

6

5

R

Get HEO VEO Error - No hits at crossing

Get HEO VEO Error - Vertical Eye not visible

Reserved

4

R

3

R/W

R/W/SC

0x24

00

2

Start DFE Adaptation (Self- Clearing)

Start Get HEO VEO Measurement (Self-

Clearing)

1

0

N

R/W/SC

Start Eye Opening Monitor Counter

(Self-Clearing)

0x25

0x26

00

7:0

00’h

N

R

Eye Opening Monitor Count <15:8>

Eye Opening Monitor Count <7:0>

HEO Value <7:0>

(Measured in 0-63 phase settings)

0x27

0x28

00

7:0

00’h

N

R

7:0

7

00’h

0

R

VEO Value <7:0>

Reserved

R/W

Eye Opening Monitor Voltage Range Setting

0x29

00

6:5

00

N

R

<1:0>

See 0x11[7:6]

4:0

7:0

7:6

5:4

3:0

7

00000

30’h

00

R/W

Reserved

0x2A

0x2B

30

00

Y

N

Y

N

Y

Eye Opening Monitor Timer Threshold <7:0>

Reserved

00

R/W

Reserved

0000

0

Minimum hits for HEO-VEO hit counter

Reserved

6

1

Scale VEO based on Eye Monitor Vrange

DFE Adaptation Figure of Merit Type <1:0>

00: Not Valid

01: State Machine uses only HEO

10: State Machine uses only VEO

11: State Machine uses both HEO and VEO

0x2C

72

5:4

3:0

11

Y

Determines number of DFE settings to look-

beyond current best Figure of Merit (FOM)

0010

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Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

ADDRESS

(HEX)

DEFAULT

VALUE

(BINARY)

VALUE

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

7

6

1

0

Enable Driver Short Circuit protection

Enable FAST signal detect

Increase the Assert and De-assert reference

thresholds

5

4

0

Set high (1) to decrease the signal detect gain

Set high (1) to override the EQ setting going to

3

0

the analog

from 0x03[7:0]

0x2D

80

Y

R/W

Output Driver VOD [2:0]

000: 600 mV

001: 700 mV

010: 800 mV

2:0

000

011: 900 mV

100: 1000 mV

101: 1100 mV

110: 1200 mV

111: 1300 mV

7:6

5

00

0

N

Y

N

Y

N

0x2E

00

4:3

2

00

0

R/W

Reserved

1:0

7:6

5:4

00

01

10

RATE <1:0>

SUBRATE <1:0>

CTLE Adaptation Index Override

0: CTLE adaption will start at Reg_0x40 +

Reg_0x39[3:0]. So this may be used to

preclude lower CTLE settings.

1: CTLE will not adapt and will use the CTLE

setting of Reg_0x40 + Reg_0x39[3:0] for

scalar divide ratios of 1 or 2. Divide ratios of 4

& 8 will take CTLE settings from 0x3A unless

0x55[0] is high, which will revert to the setting

in Reg_0x40 + Reg_0x39[3:0].

3

0

Y

R/W

0x2F

66

2

1

Enable PPM Check - for Lock qualifier

Enable FLD Check - for Lock qualifier

Start CTLE Adaptation

0

N

R

R/W

R

7:6

5

00

0

4

0

R

Goes High if Interrupt from CDR Goes High

Enable PRBS digital CLK

Reserved

0x30

00

3

0

Y

N

Y

2

0

R/W

1:0

00

PRBS Pattern[1:0]

39

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

VALUE

(HEX)

DEFAULT

VALUE

(BINARY)

ADDRESS

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

7

0

Reserved

Adaptation Mode <1:0>

00: No adaption

01: Adapt only CTLE till optimal

6:5

10

Y

R/W

10: Adapt CTLE till optimal, then DFE, then

CTLE again

11: Adapt CTLE till LOCK, then DFE, then

CTLE till optimal

0x31

40

CTLE Adaptation Figure of Merit Type <1:0>

00: SM uses both HEO and VEO

01: SM uses only HEO

4:3

00

R/W

10: SM uses only VEO

11: SM uses both HEO and VEO

2:0

7:4

000

N

Y

Reserved

HEO Interrupt Threshold <3:0>

Compares HEO value,

Reg_0x27[7:0] vs. threshold of

Reg_0x32[7:4]*4

0001

R/W

0x32

11

VEO Interrupt Threshold <3:0>

Compares VEO value,

Reg_0x28[7:0] vs. threshold of

Reg_0x32[3:0]*4

3:0

7:4

0001

1000

Y

HEO Threshold for CTLE Adaptation Handoff

to DFE Adaptation

Compares HEO value,

R/W

Reg_0x27[7:0] vs. threshold of

Reg_0x33[7:4]*2

0x33

88

VEO Threshold for CTLE Adaptation Handoff

to DFE Adaptation

3:0

1000

Y

N

Y

R/W

R

Compares HEO value,

Reg_0x27[7:0] vs. threshold of

Reg_0x33[3:0]*2

7

6

0

PPM Error Ready

Low power disable

Lock Counter

0x34

0x35

3F

1F

4:5

11

R/W

Maximum DFE Tap Absolute Value for Taps

2–5 <3:0>

3:0

7:6

5

1111

00

Get PPM Error from PPM count - clears when

done

0

Y

R/W

Maximum DFE Tap Absolute Value for Tap 1

<4:0>

4:0

1 1111

7

6

0

Reserved

Enable HEO/VEO Interrupt

Reserved

5:4

3

11

0

Y

N

Y

N

0x36

31

Reserved

2

0

Cap DAC range override enable

Cap DAC range[1:0]

CTLE Status

1:0

7:0

01

00'h

0x37

0x38

00

R

DFE Status

40

DS125DF111

www.ti.com.cn

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

ADDRESS

(HEX)

DEFAULT

VALUE

(BINARY)

VALUE

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

7

0

N

Reserved

6:5

00

0x39

00

R/W

Y

Start Index for CTLE Adaptation <4:0>

(Enable from Register 0x2f, Bit 3)

4:0

7:6

5:4

3:2

1:0

0 0000

00

Fixed CTLE Stage 0 Boost Setting for Divide

Ratios 4 and 8 <1:0>

R/W

Fixed CTLE Stage 1 Boost Setting for Divide

Ratios 4 and 8 <1:0>

00

0x3A

00

Y

Fixed CTLE Stage 2 Boost Setting for Divide

Ratios 4 and 8 <1:0>

00

Fixed CTLE Stage 3 Boost Setting for Divide

Ratios 4 and 8 <1:0>

00

0x3B

0x3C

00

7:0

7

00'h

N

Y

N

R

PPM Count MSB

PPM Count LSB

0

0x3D

00

80

00

R/W

Reserved

6:0

000000

Enable HEO/VEO lock monitoring once

SBT/FLD declare lock. Once the lock and

adaptation processes are complete, HEO/VEO

monitoring is performed once per the interval

determined by Reg_0x69[3:0].

7

1

Y

0x3E

R/W

6:0

7

0000000

0

N

Y

N

Y

N

Y

N

Y

Reserved

0x3F

R/W

Reserved

6:0

0000000

0x40 - 0x4F

CTLE Settings for Adaptation Table 20

7

6

5

4

0

Reserved

0x50

00

R/W

Slicer Sign Bit

Slicer adjustment in 5mV steps. Maximum

adjustment value is 50mV or 0x50[3:0] = A’h

3:0

0000

Y

0x51

0x52

0x53

00

7:0

7

00’h

0

Y

N

R/W

R

Reserved

CTLE Boost setting readback register.

Reserved

R/W

Signal Detect observation bit.

EQ Limiting (CTLE Stage 3[2]) observation bit.

Reserved

6

0

0x54

00

5:2

1

0000

0

N

R

CDR Lock Interrupt

Signal Detect Interrupt

Reserved

0

7

0

N

Y

6:5

00

Reserved

Allows observation of the alternate HEO/VEO

Figure of Merit

0x55

00

4

0

N

R/W

In Reg_0x27 and Reg_0x28

3:1

0

Y

Reserved

Enables Adaption in the lower divide ratios

41

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

VALUE

(HEX)

DEFAULT

VALUE

(BINARY)

ADDRESS

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

7:4

0000

N

Reserved

CDR Lock Interrupt Enable Bit.

[1]: Enable CDR LOCK Interrupt (Register

0x54[1])

[0]: Default

3

2

1

0

Y

Signal Detect Interrupt Enable Bit.

[1]: Enable Signal Detect Interrupt (Register

0x54[0])

0

0x56

00

R/W

[0]: Default

CDR Loss of Lock Interrupt Enable Bit.

[1]: Enable CDR LOSS of LOCK Interrupt

(Register 0x01[4])

[0]: Default

Signal Loss Interrupt Enable Bit.

[1]: Enable Signal Loss Interrupt (Register

0x01[0])

Y

[0]: Default

Group 0 (Rate/Subrate defined) PPM counter

<7:0> LSBs

0x60

0x61

0x62

0x63

26

B1

70

7:0

7

26’h

1

R/W

Override standard Group 0 tie cells for PPM

count and tolerance with Channel Registers

0x60, 0x61, and 0x64

Y

Group 0 (Rate/Subrate defined) PPM counter

<14:8> MSBs

6:0

7:0

011 0001

70’h

Group 1 (Rate/Subrate defined) PPM counter

<7:0> LSBs

Override standard Group 1 tie cells for PPM

count and tolerance with Channel Registers

0x62, 0x63, and 0x64

7

1

BD

Group 1 (Rate/Subrate defined) PPM counter

<14:8> MSBs

6:0

011 1101

7:4

3:0

7:0

7:6

5

1111

00'h

00

Group 0 PPM Delta

Group 1 PPM Delta

Reserved

0x64

FF

Y

R/W

0x65

0x66

00

N

Y

N

R/W

Reserved

0x67

0x68

00

0

R/W

Reserved

4:0

7:0

7:4

00000

00'h

0000

Reserved

HEO/VEO interval while monitoring lock.

Monitoring will take place 1 out of the

indicated count intervals (default h'A). Interval

time is determined 0x2B[5:4], which is 6.5ms

by default.

0x69

0A

R/W

3:0

1010

Y

7:4

3:0

0100

Vertical Eye Opening Lock Threshold <3:0>

Horizontal Eye Opening Lock Threshold <3:0>

0x6A

0x6B

44

40

N

Y

R/W

Adaptation Figure of Merit Term A<7:0>

FoM = Min [(HEO - B)*A, (VEO - C)*(1-A)]

FoM = Min [(HEO - 0x6C) * (0x6B)/127, (VEO

- 0x6D) * (128 - 0x6B)/127]

7:0

40’h

42

DS125DF111

www.ti.com.cn

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

Register Maps (continued)

Table 26. Channel Register Definition (continued)

DEFAULT

ADDRESS

(HEX)

DEFAULT

VALUE

(BINARY)

VALUE

(HEX)

BITS

EEPROM

MODE

DESCRIPTION

Adaptation Figure of Merit Term B<7:0>

FoM = Min [(HEO - B)*A, (VEO - C)*(1-A)]

FoM = Min [(HEO - 0x6C) * (0x6B)/127, (VEO

- 0x6D) * (128 - 0x6B)/127]

0x6C

00

7:0

0x0

Y

R/W

Adaptation Figure of Merit Term C<7:0>

FoM = Min [(HEO - B)*A, (VEO - C)*(1-A)]

FoM = Min [(HEO - 0x6C) * (0x6B)/127, (VEO

- 0x6D) * (128 - 0x6B)/127]

0x6D

0x6E

7:0

Y

R/W

Enable Alternate Figure of Merit for CTLE

Adaptation

7

6

0

Y

00

Enable Alternate Figure of Merit for DFE

Adaptation

5:0

7:0

7:3

2:0

7:6

5

000000

00'h

00000

011

00

N

Reserved

0x6F

0x70

00

03

R/W

Reserved

N

CTLE Adaptation Look-Beyond Count <2:0>

Reserved

R/W

R

0x71

0x72

0x73

0x74

0x75

00

0

N

DFE Tap 1 Polarity (Read Only)

DFE Tap 1 Weight (Read Only) <4:0>

Reserved

4:0

7:5

4

0 0000

000

0

R

R/W

R

N

DFE Tap 2 Polarity (Read Only)

DFE Tap 2 Weight (Read Only) <3:0>

Reserved

3:0

7:5

4

0000

000

0

R

R/W

R

DFE Tap 3 Polarity (Read Only)

DFE Tap 3 Weight (Read Only) <3:0>

Reserved

3:0

7:5

4

0000

000

0

R

R/W

R

DFE Tap 4 Polarity (Read Only)

DFE Tap 4 Weight (Read Only) <3:0>

Reserved

3:0

7:5

4

0000

000

0

R

R/W

R

DFE Tap 5 Polarity (Read Only)

DFE Tap 5 Weight (Read Only) <3:0>

3:0

0000

R

43

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS125DF111 is a 2 channel retimer that support many different data rates and application spaces.

8.2 Typical Application

Figure 9 shows a typical implementation for the DS125DF111 in a back plane application. The DS125DF111 can

also be used for front port applications. The DS125DF111 supports data rates for CPRI, Infiniband, Ethernet,

Interlaken and other custom data rates.

Line Card

Switch Fabric

Retimer with

DFE

Optical

Retimer with

DFE

QSFP

SFP

10G

ASIC

FPGA

10G

Retimer with

DFE

Passive

Copper

Cable

Retimer with

DFE

QSFP

SFP

Back

Plane

Figure 9. Typical Application

8.2.1 Design Requirements

This section lists some critical areas for high speed printed circuit board design consideration and study.

•

Utilize 100-Ω differential impedance traces.

Back-drill connector vias and signal vias to minimize stub length.

Use reference plane vias to ensure a low inductance path for the return current.

Place AC-Coupling capacitors for the transmitter links near the receiver for that channel.

The maximum body size for AC-coupling capacitors is 0402.

44

DS125DF111

www.ti.com.cn

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

Typical Application (continued)

8.2.2 Detailed Design Procedure

To begin the design process determine the following:

•

Select a reference clock frequency and routing scheme.

Plan out channel connectivity. Be sure to note any desired polarity inversion routing in the board schematics.

Ensure that each device has a unique SMBus address if the control bus is shared with other devices or

components.

•

Use the IBIS-AMI model for simple channel simulations before PCB layout is complete.

Initialization Sequence: Channel Register Configurations repeated for all desired channels:

•

CDR reset

Adapt Mode Configuration

Data rate selection

Output driver VOD and De-Emphasis Optional Interrupt enable

Optional Reference clock loop through enable

CDR reset release

8.2.3 Application Curves

8.2.3.1 SFF-8431 Testing

Testing for Receiver Jitter Tolerance based on SFF-8431 section D11.

•

Datarate: 10.3125 Gbps

PRBS15 Pattern

Output Amplitude: 700 mV

Periodic Jitter: 70 mUI at 20 MHz

ISI Jitter: 10" 4-mil FR4 differential microstrip + Limiting Amplifier

Random Jitter noise source: Agilent 346B

The SFF-8431 specification combines deterministic, random, and periodic jitter components. The combination of

these jitter components has been measured and calibrated to ensure adequate levels of individual jitter

components and total jitter.

Figure 10. SFF-8431 Rx Input Jitter Profile

Figure 11. SFF-8431 Output Jitter Eye Mask

The SFF-8431 specification defines a transmit eye mask to ensure robust signal reception across the host -

module interface.

45

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

9 Power Supply Recommendations

The DS125DF111 has an optional internal voltage regulator to provide the 2.5-V supply. In 3.3-V mode

operation, the V_INpin = 3.3 V is used as the power supply input to the device. The internal regulator provides 2.5

V to the V_DDpins of the device. A 0.22-uF cap is needed at each of the 2 V_DDpins for power supply de-coupling

(total capacitance should be ≤ 0.5 µF). These local decoupling capacitors should be the only connection to the

DS125DF111 V_DDnet as the internal regulator is not designed to supply power to additional devices. In 2.5-V

mode operation, the V_INpin should be connected to directly to the 2.5-V supply, a voltage less than 2.9 V will

disable the internal regulator allowing an external supply to power the DS125DF111.

3.3V mode

2.5V mode

VIN > 2.9V

VIN < 2.9V

Enable

Disable

3.3V

Internal

voltage

Internal

Capacitors can be

either tantalum or an

ultra-low ESR ceramic.

voltage

VIN

VDD

VIN

VDD

2.5V

regulator

2.5V

0.22 uF

Capacitors can be

either tantalum or an

ultra-low ESR ceramic.

0.22 uF

Place 0.22 uF capacitors close to VDD Pins

Place 0.22 uF capcitors close to VDD Pins

Total capacitance should be 7 0.5 uF

Figure 12. DS125DF111 Power Supply and Regulator Connections

46

DS125DF111

www.ti.com.cn

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

10 Layout

10.1 Layout Guidelines

The high speed inputs and outputs have been optimized to work with interconnects using a controlled differential

impedance of 100Ω. Vias should be used sparingly and must be placed symmetrically for each side of a given

differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for

the return currents as well. Route the differential signals away from other signals and noise sources on the

printed circuit board.

Figure 13 highlights good high-speed layout techniques.

1. Maintain differential pair symmetry to minimize any signal conversion to common mode.

2. Isolate Tx - Rx differential pairs with a minimum of 5x inter-pair to intra-pair spacing ratio.

3. Decoupling should be placed as close as possible to the DS125DF111

4. Use differential vias which incorporate reference plane current returns and relief to minimize impedance

disruption.

5. Use a back-drill technique to minimize via stubs.

6. Keep Loop Filter capacitors as close as possible to the DS125DF111.

10.2 Layout Example

Coupling Caps

Loop Filter

Channel A

5

1

6

5

4

3

2

24

23

22

21

20

19

7

8

Reference

Plane Relief

Coupling Caps

Reference

Plane Relief

V_DD

GND

BOTTOM OF PKG

9

25

10

11

12

V_DD

DECOUPLING

Coupling Caps

7

5

15 16 17

13 14

18

V_IN

7

Reference

Plane Relief

DECOUPLING

Coupling Caps

Loop Filter Channel B

V_IN

Figure 13. DS125DF111 Typical Layout

47

DS125DF111

ZHCSDZ7A –JANUARY 2014–REVISED JUNE 2015

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

《焊接相关的最大绝对额定值》，SNOA549

11.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

48

PACKAGE OUTLINE

RTW0024A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

4.1

3.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.1) TYP

EXPOSED

THERMAL PAD

7

12

20X 0.5

6

13

2X

25

2.5

2.6 0.1

1

18

0.3

24X

0.2

24

19

PIN 1 ID

(OPTIONAL)

0.1

C A B

C

0.05

0.5

0.3

24X

4222815/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.6)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(1.05)

SYMM

25

(3.8)

20X (0.5)

(R0.05)

TYP

6

13

(

0.2) TYP

VIA

7

12

(1.05)

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222815/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.15)

(0.675) TYP

19

(R0.05) TYP

24

24X (0.6)

1

18

24X (0.25)

(0.675)

TYP

SYMM

20X (0.5)

25

(3.8)

6

13

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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型号：	DS125DF111SQ
厂家：	TEXAS INSTRUMENTS
描述：	9.8-12.5 Gbps 低功耗多速率双通道重定时器 \| RTW \| 24 \| -40 to 85
文件：	总56页 (文件大小：1186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS125DF111SQ [TI]

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