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DS125DF1610

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

DS125DF1610 9.8 至 12.5Gbps 16 通道重定时器

1 特性

3 说明

1

•

引脚兼容系列

DS125DF1610 是一款具有集成信号调节功能的十六通

道多速率重定时器。该器件包含完全自适应性连续时

间线性均衡器 (CTLE)、判决反馈均衡器 (DFE)、时钟

和数据恢复 (CDR) 锁定检测以及发送 FIR 滤波器，可

延长在有损且存在串扰的高速串行链路中的发送距离并

–

DS150DF1610：12.5 到 15G

DS125DF1610：9.8 到 12.5G

DS110DF1610：8.5 到 11.3G

•

4x4 模拟交叉点开关（每个四通道）

提高稳定性，从而实现比特误差率 (BER) < 1×10^-15

。

完全自适应性连续时间线性均衡器 (CTLE)

自调谐判决反馈均衡器 (DFE)，可选配连续调节装

置

DS125DF1610 每个通道的串行数据速率均可独立锁定

在 9.8 到 12.5Gbps 范围内，并且可进行 2 分频、4 分

频和 8 分频。与输入数据流同步或异步的简单外部振

荡器 (±100ppm) 可用作基准时钟。集成的 4x4 交叉点

开关可在 DS125DF1610 的每个四通道内实现无阻塞

路由或广播。

•

可配置的可变增益放大器 (VGA)

可调发送 V_OD

可调 3 抽头发送有限脉冲响应 (FIR) 滤波器

接收输入上的片上交流耦合

锁定传统支持的二分频/四分频/八分频数据速率

可编程的发送 FIR 滤波器可控制前体、主抽头和后

体，从而实现发送均衡。利用完全自适应接收均衡

（CTLE 和 DFE），可以延长在因使用多个连接器而

受损的铜缆和背板上的发送距离。

片上眼图监视器 (EOM)，伪随机二进制序列

(PRBS) 校验器，图案信号发生器

•

支持 JTAG 边界扫描

可编程的输出极性反转

输入信号检测，CDR 锁定检测

单路 2.5V ±5% 电源

配备的非破坏性任务模式眼图监视器可从内部对接收器

进行链路监视。内置的 PRBS 发生器和校验器对内部

诊断功能进行了补充，以完成独立 BERT 测量。内置

JTAG 支持制造测试。

基于 SMBus 的寄存器配置

可选 EEPROM 配置

15mm × 15mm 196 引脚 FCBGA 封装

工作温度范围：–40°C 至 +85°C

器件信息 ⁽¹⁾

部件号

封装

封装尺寸标称值

DS125DF1610

FCBGA (196)

15.00mm x 15.00mm

2 应用

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

•

SFF-8431

CPRI

简化电路原理图

DS125DF1610

10G/40G 以太网

背板

100nF

RX_0A_P

TX_0A_P

RX_0A_N

TX_0A_N

.

100nF

2.5V or 3.3V

RX_7B_P

RX_7B_N

TX_7B_P

TX_7B_N

__________

2kW

100nF

TDI_IO

INTERR_IO

_________

TDO_IO

TRST_IO

TMS_IO

TCK_IO

RESET_IO

SDA_IO

SCL_IO

1ꢀF

25 MHz

CLK_MON_P

CLK_MON_N

EN_SMB

READ_EN

ADDR0

REF_CLK_P

REF_CLK_N

2.5V

22ꢀF

(1x)

0.1ꢀF

(8x)

VDD

GND

ADDR1

1kW

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS482

DS125DF1610

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

www.ti.com.cn

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 8

6.1 Absolute Maximum Ratings ..................................... 8

6.2 Handling Ratings ...................................................... 8

6.3 Recommended Operating Conditions....................... 8

6.4 Thermal Information ................................................. 8

6.5 Additional Thermal Information ................................ 8

6.6 Electrical Characteristics........................................... 9

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 13

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 24

7.5 Programming........................................................... 26

8

9

Application and Implementation ........................ 69

8.1 Application Information............................................ 69

8.2 Typical Applications ................................................ 70

8.3 Initialization Setup................................................... 73

Power Supply Recommendations...................... 75

9.1 Power Supply Filtering............................................ 75

10 Layout................................................................... 75

10.1 Layout Guidelines ................................................. 75

10.2 Layout Example .................................................... 76

11 器件和文档支持 ..................................................... 77

11.1 器件支持 ............................................................... 77

11.2 文档支持 ............................................................... 77

11.3 接收文档更新通知 ................................................. 77

11.4 社区资源................................................................ 77

11.5 商标....................................................................... 77

11.6 静电放电警告......................................................... 77

11.7 Glossary................................................................ 77

12 机械、封装和可订购信息....................................... 77

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (December 2015) to Revision B

Page

•

已更改最低温度为 -20°C 至 -40°C......................................................................................................................................... 1

Changed the minimum temperature from -20°C to -40°C ..................................................................................................... 8

Changes from Original (April 2014) to Revision A

Page

•

已添加完整的数据表 .............................................................................................................................................................. 1

2

DS125DF1610

www.ti.com.cn

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

5 Pin Configuration and Functions

Plastic Ball Grid Array

196 Balls

Bottom View

P

TX_6B_N

GND

N

TX_6B_P

GND

M

GND

L

K

TX_4B_N

GND

J

TX_4B_P

GND

H

GND

G

F

TX_3A_N

GND

E

TX_3A_P

GND

D

GND

C

GND

B

TX_1A_N

GND

A

GND

TX_1A_P

01

02

01

02

TX_5B_N

GND

TX_5B_P

GND

TX_4A_N

GND

TX_4A_P

GND

TX_2A_N

GND

TX_2A_P

GND

TX_7A_N

GND

TX_7A_P

GND

TX_5A_N

GND

TX_5A_P

GND

TX_2B_N

GND

TX_2B_P

GND

TX_0B_N

GND

TX_0B_P

GND

03

04

05

06

07

08

09

10

11

12

13

14

03

04

05

06

07

08

09

10

11

12

13

14

TX_6A_N

GND

TX_6A_P

TX_3B_N

GND

TX_3B_P

TX_1B_N

ADDR1

TCK_IO

TDI_IO

N/C

TX_1B_P

GND

ALL_DON

E

READ_E

N

TX_7B_N

GND

TX_7B_P

GND

VDD

TX_0A_N

ADDR0

TMS_IO

N/C

TX_0A_P

GND

N/C

SCL_IO

N/C

VDD

GND

VDD

GND

VDD

GND

N/C

REF_CLK

_P

CLK_MO

N_P

N/C

SDA_IO

GND

VDD

GND

VDD

TDO_IO

TRST_IO

N/C

REF_CLK

_N

INTERR#

_IO

RESET#_

IO

CLK_MO

N_N

EN_SMB

GND

VDD

GND

VDD

GND

VDD

GND

RX_7B_N

GND

N/C

GND

N/C

GND

VDD

GND

VDD

GND

VDD

N/C

GND

RX_0A_P

GND

RX_7B_P

GND

VDD

GND

VDD

GND

RX_0A_N

GND

RX_6A_N

GND

RX_6A_P

GND

RX_3B_N

GND

RX_3B_P

GND

RX_1B_N

GND

RX_1B_P

GND

RX_7A_N

GND

RX_7A_P

GND

RX_5A_N

GND

RX_5A_P

GND

RX_2B_N

GND

RX_2B_P

GND

RX_0B_N

GND

RX_0B_P

GND

RX_5B_N

GND

RX_5B_P

GND

RX_4A_N

GND

RX_4A_P

GND

RX_2A_N

GND

RX_2A_P

GND

RX_6B_N

RX_6B_P

RX_4B_N

RX_4B_P

RX_3A_N

RX_3A_P

RX_1A_N

RX_1A_P

P

N

M

L

K

J

H

G

F

E

D

C

B

A

(TOP VIEW)

3

DS125DF1610

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

www.ti.com.cn

Pin Functions

DS110DF1610,

DS150DF1610

DS125DF1610

PIN NAME

I/O

DESCRIPTION

PIN NAME

HIGH SPEED DIFFERENTIAL I/O

RX_1A_P

RX_1A_N

RX_0_0P

RX_0_0N

A14

B14

I, CML

O, CML

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_0B_P

Rx_0B_N

RX_0_1P

RX_0_1N

A12

B12

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_0A_P

RX_0A_N

RX_0_2P

RX_0_2N

A10

B10

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_2A_P

RX_2A_N

RX_0_3P

RX_0_3N

C13

D13

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_1B_P

RX_1B_N

RX_0_4P

RX_0_4N

C11

D11

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_3A_P

RX_3A_N

RX_0_5P

RX_0_5N

E14

F14

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_2B_P

RX_2B_N

RX_0_6P

RX_0_6N

E12

F12

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_4A_P

RX_4A_N

RX_0_7P

RX_0_7N

G13

H13

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_3B_P

RX_3B_N

RX_1_0P

RX_1_0N

G11

H11

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_4B_P

Rx_4B_N

RX_1_1P

RX_1_1N

J14

K14

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_5A_P

RX_5A_N

RX_1_2P

RX_1_2N

J12

K12

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_5B_P

RX_5B_N

RX_1_3P

RX_1_3N

L13

M13

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_6A_P

RX_6A_N

RX_1_4P

RX_1_4N

L11

M11

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_6B_P

RX_6B_N

RX_1_5P

RX_1_5N

N14

P14

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_7A_P

RX_7A_N

RX_1_6P

RX_1_6N

N12

P12

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

RX_7B_P

RX_7B_N

RX_1_7P

RX_1_7N

N10

P10

Inverting and non-inverting CML-compatible, AC coupled

differential inputs. An on-chip 100 Ohm differential termination

resistor connects these inputs.

TX_1A_P

TX_1A_N

TX_0_0P

TX_0_0N

A1

B1

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_0B_P

TX_0B_N

TX_0_1P

TX_0_1N

A3

B3

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_0A_P

TX_0A_N

TX_0_2P

TX_0_2N

A5

B5

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

4

DS125DF1610

www.ti.com.cn

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Pin Functions (continued)

DS110DF1610,

DS125DF1610

PIN NAME

DS150DF1610

PIN NAME

I/O

DESCRIPTION

TX_2A_P

TX_2A_N

TX_0_3P

TX_0_3N

C2

D2

O, CML

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_1B_P

TX_1B_N

TX_0_4P

TX_0_4N

C4

D4

O, CML

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_3A_P

TX_3A_N

TX_0_5P

TX_0_5N

E1

F1

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_2B_P

TX_2B_N

TX_0_6P

TX_0_6N

E3

F3

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_4A_P

TX_4A_N

TX_0_7P

TX_0_7N

G2

H2

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_3B_P

TX_3B_N

TX_1_0P

TX_1_0N

G4

H4

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_4B_P

TX_4B_N

TX_1_1P

TX_1_1N

J1

K1

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_5A_P

TX_5A_N

TX_1_2P

TX_1_2N

J3

K3

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_5B_P

TX_5B_N

TX_1_3P

TX_1_3N

L2

M2

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_6A_P

TX_6A_N

TX_1_4P

TX_1_4N

L4

M4

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_6B_P

TX_6B_N

TX_1_5P

TX_1_5N

N1

P1

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_7A_P

TX_7A_N

TX_1_6P

TX_1_6N

N3

P3

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

TX_7B_P

TX_7B_N

TX_1_7P

TX_1_7N

N5

P5

Inverting and non-inverting CML-compatible differential

outputs. Driver presents an output impedance of 100 ohms

between these outputs when switching.

CLOCK PINS

REF_CLK_P

REF_CLK_N

P7

P8

I, LVDS/

LVCMOS

Inverting and non-inverting

CML-compatible differential inputs for 25 MHz, 125 MHz, or

312.5 MHz clock. These differential signals are typically AC

coupled with 1 µF capacitors

When configured for single-ended input operation, apply

LVCMOS ref clock to REF_CLK_P and float REF_CLK_N.

Single-ended signals should be DC coupled.

CLK_MON_P

CLK_MON_N

A7

A8

O, LVDS

Inverting and non-inverting

CML-compatible differential outputs to monitor system

differential clock.

When daisy chaining to another retimer the output frequency

should be set to 25 MHz.

SMBUS INTERFACE

SDA_IO

M7

I/O,

Data Input / Open Drain Output

Open Drain External pull-up resistor is required, typically in the 2kΩ to 5kΩ

range. Pull-up value should be selected according to system

implementation.

Pin is 3.3 V LVCMOS tolerant.

5

DS125DF1610

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

www.ti.com.cn

Pin Functions (continued)

DS110DF1610,

DS150DF1610

DS125DF1610

PIN NAME

I/O

DESCRIPTION

PIN NAME

SCL_IO

L6

I/O,

Clock input/output

Open Drain

External pull-up resistor is required, typically in the 2kΩ to 5kΩ

range. Pull-up value should be selected according to system

implementation.

Pin is 3.3 V LVCMOS tolerant

EEPROM configuration (SMBus Master mode)

JTAG INTERFACE⁽¹⁾

TMS_IO

B7

C7

C8

D6

D7

I, LVCMOS JTAG Test Mode Select, internal pull-up

O, LVCMOS JTAG Test Data Out

TDO_IO

TRST_IO

I, LVCMOS JTAG Test Reset, internal pull-up

I, LVCMOS JTAG Test clock, internal pull-up

I, LVCMOS JTAG Test Data Input, internal pull-up

TCK_IO

TDI_IO

OTHER PINS

RESET_IO

L8

I, LVCMOS Resets registers and state machines on rising edge. Pulse

LOW for minimum of 10µs to perform reset. Pin should be

pulled HIGH during power on.

INTERR_IO

ADDR0

M8

B6

D5

G5

O, Open

Drain

Active Low interrupt signal. Pin goes low when an interrupt

event occurs. Interrupts must be enabled via SMBus.

I, LVCMOS 4 level input strap pin for SMBus address code LSB. Standard

LVCMOS output.

ADDR1

I, LVCMOS 4 level input strap pin for SMBus address code MSB.

Standard LVCMOS output.

READ_EN

I, LVCMOS Tie LOW for SMBus slave mode normal operation. Pin has

internal pull down.

In SMBus slave mode, tie HIGH to force SMBus address =

0x30.

ALL_DONE

EN_SMB

L5

O, LVCMOS EEPROM load status. Pin goes LOW when EEPROM load is

complete.

N8

I, LVCMOS Connect to GND through ≤1kΩ resistor for SMBus slave

operation.

Connect to VDD through ≤1kΩ resistor for EEPROM

configuration

POWER

VDD

E5, E7, E9,

E10, F5, F6,

Power

VDD = 2.5 V +/- 5%

F8, F10, G7,

G9, H6, H8,

J5, J7, J9,

J10, K5, K6,

K8, K10

(1) Refer to the DS125DF1610 Programming Guide for additional information

6

DS125DF1610

www.ti.com.cn

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Pin Functions (continued)

DS110DF1610,

DS125DF1610

PIN NAME

DS150DF1610

PIN NAME

I/O

DESCRIPTION

GND

A2, A4, A6,

A9, A11, A13,

B2, B4, B9,

B11, B13,

Power

Ground reference

C1, C3, C5,

C10, C12,

C14, D1, D3,

D10, D12,

D14, E2, E4,

E6, E8, E11,

E13, F2, F4,

F7, F9, F11,

F13, G1, G3,

G6, G8, G10,

G12, G14,

H1, H3, H5,

H7, H9, H10,

H12, H14, J2,

J4, J6, J8,

J11, J13, K2,

K4, K7, K9,

K11, K13, L1,

L3, L10, L12,

L14, M1, M3,

M5, M10,

M12, M14,

N2, N4, N6,

N9, N11,

N13, P2, P4,

P6, P9, P11,

P13

N/C

B8, C6, C9,

D8, D9, L7,

L9, M6, M9,

N7

No Connect, leave floating

7

DS125DF1610

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

–30

-40

MAX

2.75

UNIT

V

Supply Voltage (VDD)

LVCMOS Input/Output Voltage

Open Drain I/O Supply Voltage

CML Input Voltage

2.75

V

4.0

V

(VDD + 0.5)

30

V

CML Input Current

mA

°C

Storage temperature range, T_stg

150

(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications

6.2 Handling Ratings

VALUE

±4,000

±1,000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

2.375

–40

TYP

2.5

25

MAX

2.625

85

UNIT

V

Supply Voltage

Ambient Temperature

°C

V

SMBus (SDA, SCL), INTERR_IO

Maximum Continuous Junction Temperature while Device is Operational

2.5

3.6

115

°C

6.4 Thermal Information

DS125DF1610

FCBGA ABB

(196) PINS

THERMAL METRIC^{(1) (2)}

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

18.2

0.7

5.3

0.8

5.3

N/A

R_θJC(top)

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Thermal model available upon request

6.5 Additional Thermal Information

BOARD

θ_JC(°C / W)

θ_JA(°C / W)

ψ_JT(°C / W)

ψ_JB(°C / W)

JEDEC 4 layer board, no airflow

8x6 inches 10 layer, no airflow

8x6 inches 20 layer, no airflow

8x6 inches 30 layer, no airflow

0.7

18.2

7.2

0.8

0.3

5.3

3.2

6.4

6.3

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6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

SYMBOL

PARAMETER

CONDITIONS

Full Rate

MIN

9.8

TYP

MAX

12.5

UNIT

Gbps

Half Rate

4.9

6.25

R_baud

Input Data Rate

Quarter Rate

Eighth Rate

2.45

1.225

3.125

1.5625

POWER SUPPLY

CTLE only, 800mVp-p

VOD, per channel,

CDR locked

175

325

mW

CDR Locking with CTLE

only, 800mVp-p VOD,

per channel

Power Consumption per

Active Channel

CTLE and DFE, 800mVp-

p VOD, per channel,

CDR locked

W

200

350

323

mW

CDR Locking with CTLE

and DFE, 800mVp-p VOD

535.5

PRBS Checker

100

105

mW

PRBS Generator

Device Static Power

Consumption

Power Applied to Device,

No Signals Present

W_STATIC

325

1325

mW

50 Hz to 100 Hz

100 Hz to 10 MHz

10 MHz to 5.0 GHz

100

40

Power Supply Noise

Tolerance

NT_PS

mV_PP

10

LVCMOS

V _IH

High level input voltage

Low level input voltage

High level output voltage

Low level output voltage

1.75

GND

2

VDD

0.7

V

V_IL

V_OH

IOH = 4mA

IOL = -4mA

V_OL

0.4

30

Vinput = VDD,

Open Drain terminals

µA

Vinput = VDD,

JTAG terminals, Ref_CLK

terminals

25

75

µA

Input High Leakage

current

I_IH

Vinput = VDD,

ADDR, READ_EN,

ALL_DONE terminals,

EN_SMB terminal

µA

Vinput = 0V,

Open drain terminals

-15

-45

µA

Vinput = 0V,

JTAG terminals, Ref_CLK

terminals

Input Low Leakage

current

I_IL

Vinput = 0V,

ADDR, READ_EN,

ALL_DONE terminals,

EN_SMB terminal

-120

µA

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Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

SYMBOL

RX INPUTS

R_RD

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

DC Input Resistance

80

100

120

Ω

Differential voltage seen

at the high speed input

terminals

V_RX-IN

Input Differential Voltage

1600

mV_PP

(1)

Default setting

1T pattern, 12.5 Gbps

110

24

Signal Detect Assert

Threshold

V_SDAT

mV_PP

Default setting

PRBS-31, 12.5 Gbps

Default setting

1T pattern, 12.5 Gbps

70

Signal Detect De-Assert

Threshold

V_SDDT

mV_PP

Default setting

PRBS-31, 12.5 Gbps

21

VDD - (V_RX-

_IN/ 4)

V_cm-RX

Input common mode

Internal coupling cap

V_RX-IN/ 4

V

TX OUTPUTS

drv_sel_vod[5:0] = 31,

DEM, FIR = default

725

350

935

470

50

1135

595

V_OD

Output Differential Voltage

mV_PP

drv_sel_vod[5:0] = 15,

DEM, FIR = default

Step Size for drv_sel_vod Default DEM, and FIR

ΔV_OD

mV_PP

Control

settings

Change in Output

Differential Voltage due to

Change in Temperature

and Voltage

ΔV_ODVT

<15

Output Differential

Resistance

T_Rd

t_r, t_f

I_OS

100

35

Ω

ps

20% - 80% using 8T

Pattern, fir_sel_edge =

default

Output Rise/Fall Time

Output Short Circuit

Current

Differential Driver Output

Pin Short to GND

-16

mA

(1) Parameter is not tested at final production

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Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

RETIMER JITTER SPECS

PRBS-15 pattern,

measured to 1e-12

10.3125 Gbps

J_TJ

Total Output Jitter

0.08

UI

PRBS-15 pattern,

measured to 1e-12

10.3125 Gbps

J_RJ

Output Random Jitter

3.6

0.03

<1

mUI_RMS

PRBS-15

10.3125 Gbps

J_DJ

Output Deterministic Jitter

UI

Data Rate = 9.8 Gbps,

Peaking Frequency =

1 - 3 MHz

J_PEAK

Jitter Peaking

dB

Data Rate = 12.5 Gbps

Peaking Frequency =

3 - 8 MHz

<1

Data Rate = 9.8 Gbps

Data Rate = 12.5 Gbps

5

BW_PLL

PLL Bandwidth at -3 dB

Input Jitter Tolerance

MHz

UI

10

Jitter per SFF-8431

Appendix D.11

Combination of D_JP_Jand

R_J

J_TOL

>0.7

RETIMER TIMING SPECS

No Cross Point

3UI + 220ps

3UI + 230ps

Propagation Delay from

Rx inputs to Tx outputs

t_D

ps

Cross Point enabled

Channel To Channel

Skew

t_SK

<80

RECOMMENDED REFERENCE CLOCK SPECS

25

Input Reference Clock

Frequency

REF_f

125

MHz

PPM

312.5

Reference Clock PPM

Tolerance

REF_PPM

REF_f= 25 MHz⁽²⁾

-100

40%

100

Input Reference Clock

Duty Cycle

REF_IDC

REF_f= 25 MHz⁽²⁾

Intrinsic Duty Cycle

50%

±1%

60%

Intrinsic Reference Clock Distortion of the reference

Duty Cycle Distortion

REF_ODC

REF_VID

REF_VIH

clock output from the

CLK_MON pins

Reference Clock Input

Differential Voltage

Differential mode⁽²⁾

200

1200

mV_PP

Single-ended mode.

Signal DC coupled to

REF_CLK_P,

Reference Clock Signle-

Ended Input High

Threshold

1.75

0.7

V

REF_CLK_N is float

Single-ended mode.

Signal DC coupled to

REF_CLK_P,

Reference Clock Single-

Ended Input Low

Threshold

REF_VIL

V

REF_CLK_N is float

(2) Parameter is specified by design and not tested at final production

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Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)

V_IH

V_IL

C_IN

Input High Level Voltage

Input Low Level Voltage

Input Pin Capacitance

SDA and SCL

1.75

3.6

0.8

V

SDA and SCL

GND

<5

pF

SDA or SCL

IOL = 1.25 mA

V_OL

I_IN

Low Level Output Voltage

Input Current

0.4

15

V

SDA or SCL, V_INPUT

V_IN, V_DD, GND

=

-15

µA

ns

SDA Rise Time Read

Operation

SDA, pullup resistor = 1

kΩ, Cb = 50pF

T_R

T_F

150

4.5

SDA Fall Time Read

Operation

SDA, pullup resistor = 1

kΩ, Cb = 50pF

RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SLAVE MODE)

f_SCL

SCL Clock Frequency

Data Hold Time

10

100

0.75

100

400

kHz

ns

t_HD:DAT

t_SU:DAT

Data Setup Time

ns

RECOMMENDED SMBus SWITCHING CHARACTERISTICS (MASTER MODE)

F_SCL

SCL Clock Frequency

SCL Low Period

400

1.25

0.6

kHz

µs

T_LOW

T_HIGH

T_HD:STA

SCL High Period

µs

Hold Time Start Operation

µs

Setup Time Start

Operation

T_SU:STA

0.6

µs

T_HD:DAT

T_SD:DAT

Data Hold Time

Data Setup Time

0.9

0.1

µs

Stop Condition Setup

Time

T_SU:STO

T_BUF

0.6

1.3

µs

Bus Free Time between

Stop-Start

T_R

T_F

SCL and SDA Rise Time

SCL and SDA Fall Time

300

ns

RECOMMENDED JTAG SWITCHING CHARACTERISTICS

t_TCK

TCK Clock Period

100

50

ns

TDI, TMI Setup Time to

TCK

t_SU

TDI, TMS Hold Time to

TCK

t_HD

50

ns

t_DLY

TCK Falling Edge to TDO

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7 Detailed Description

7.1 Overview

The DS125DF1610 is a multi-rate, 16-channel retimer with integrated 4x4 cross point switches and receiver AC

coupling capacitors. There is 1 cross point switch per 4 channels (quad). Each channel in the DS125DF1610

operates independently even if the cross point switch routing is enabled. All channels include a Continuous Time

Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), Variable Gain Amplifier (VGA), Clock and Data

Recovery circuit (CDR) and a differential driver with a 3-tap transmit Finite Impulse Response (FIR) filter. Each

channel also has its own Eye Opening Monitor (EOM) and configurable Pseudo-Random Bit Sequence (PRBS)

pattern checker and pattern generator that can be used for debug purposes.

The DS125DF1610 also supports JTAG boundary scan. The DS125DF1610 is configurable through a single

SMBus port. The DS125DF1610 can also act as an SMBus master to configure itself from an EEPROM.

The sections below describe the functionality of the various circuits and features within the DS125DF1610. For

more information about how to program or operate these features please consult the DS125DF1610

Programming Guide.

7.2 Functional Block Diagram

Quad 0 -- 1 of 4 Quads

EQ

CrossPoint

DFE

CDR

Driver

RX_0A+

RX_0A-

TX_0A+

TX_0A-

TX_0B+

TX_0B-

RX_0B+

RX_0B-

EQ

DFE

CDR

Driver

RX_1A+

RX_1A-

TX_1A+

TX_1A-

RX_1B+

RX_1B-

TX_1B+

TX_1B-

Figure 1. DS125DF1610 Simplified Cross Point Diagram

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Functional Block Diagram (continued)

Retimer/CDR

EQ

Driver

Cross Point

VGA/DFE

FIR Filter

IN+

IN-

OUT+

OUT-

100ꢀ

100W

Eye

Opening

Monitor

PRBS

Check

Patt.

Gen

Signal

Detect

VCO

Digital Core

REFCLK_IN

SMBus

1.2V

Regulator

2V

Regulator

2.5V

Figure 2. DS125DF1610 Simplified Data Path Diagram

7.3 Feature Description

7.3.1 Device Data Path Operation

The DS125DF1610 data path consists of several key blocks as shown in Figure 2. These key circuits are:

•

AC-coupled Receiver with Signal Detect

CTLE

Cross Point Switch

DFE with VGA

CDR

Differential Driver with FIR Filter

7.3.2 AC-Coupled Receiver with Signal Detect

The differential receiver for each DS125DF1610 channel contains on chip AC coupling capacitors. The minimum

bandwidth for this AC coupled receiver is 16kHz. The receiver also contains a signal detect circuit.

The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high

speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to

automatically power on or off the rest of the high speed data path depending on if a signal is present. The signal

detect block can be manually controlled in the SMBus channel registers. This can be useful if it is desired

manually force channels to be disabled. For information on how to manually operate the signal detect circuit

please see the DS125DF1610 Programming Guide and channel register 0x14 information.

7.3.3 CTLE

The CTLE in the DS125DF1610 is a fully adaptive equalizer with adjustable bandwidth and optional limiting

stage. The CTLE adapts according to a Figure of Merit (FOM) calculation during the lock acquisition process.

Once the CDR has locked and the CTLE has been adapted, the CTLE boost level will be frozen until a manual

re-adapt command is issued or until the CDR re-enters the lock acquisition state. The CTLE is typically re-

adapted by resetting the CDR, set and then clear channel register 0x0A[3:2].

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Feature Description (continued)

The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-

boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost

combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel

registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost

settings. Users also have the option of limiting the EQ table length to any value between a minimum value of 1

and a maximum value of 32.

CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost

combinations that sum to the same number will have approximately the same boost level, but will result in a

different shape for the EQ transfer function (boost curve). The boost levels can be set between 0 dB and 31 dB.

The CTLE bandwidth can be adjusted through SMBus control to 3 different levels:

Table 1. CTLE Bandwidth Settings

CTLE BANDWIDTH SETTING

Full Rate (default)

Mid Rate

BANDWDITH (GHz) (TYP)

9

7

5

Half Rate

The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather

than a linear stage. This is useful in some applications, but it should not be typically used in combination with the

DFE.

7.3.4 Cross Point Switch

Each quad has a 4x4 non-blocking analog cross point switch. This allows for full switching or broadcasting of

data between any input within the quad to any output within the quad. Since the cross point switch is an analog

implementation, all of the channels are allowed to operate asynchronously. The analog implementation also

minimizes added latency through the device.

As shown in Figure 3, the cross point switch connections for each quad are located between CTLE and DFE in

each channel.

The cross point switch consists of 4 sets of MUXs and buffers. In each channel there is a local buffer and a multi-

drive buffer. The local buffer transmits data from the CTLE to the DFE of the same channel. The multi drive

buffer transmits data from the CTLE to the DFE(s) of other channels within the quad. Each channel has two

MUXs:

1. Data path mux – Selects whether to get data from the local buffer or from the other channel’s multi-driver

buffer

2. Control bus mux – Selects where the signal detect and EQ control bus should be connected. This setting

should mirror the data path mux setting. Note, when an EQ is connected to another channel’s CDR the EQ

becomes associated with that CDR’s register set. For example, if the cross point was configured to do point

to point switching from the inputs of channel 0 to the output of channel 1 and the inputs of channel 1 to the

outputs of channel 0, the EQ physically located at the pins for inputs of channel 0 would be accessible

through the register set of channel 1.

A simplified diagram of the cross point switch is shown in Figure 3.

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Local

Buffer

Data and Control

Bus Muxs

VGA, DFE, CDR,

CH A TX

CH A RX

CH B RX

CTLE

Multi-Point

Buffer

2

Local

Buffer

Data and Control

Bus Muxs

VGA, DFE, CDR,

CH B TX

Multi-Point

Buffer

2

Local

Buffer

Data and Control

Bus Muxs

CH C RX

CH D RX

VGA, DFE, CDR,

CH C TX

Multi-Point

Buffer

2

Local

Buffer

Data and Control

Bus Muxs

VGA, DFE, CDR,

CH D TX

Multi-Point

Buffer

2

Figure 3. Cross Point Switch Diagram

Table 2. Cross Point Switch Channel Map

QUAD

Ch A

TX/RX_0A

Ch B

Ch C

Ch D

0

1

2

3

TX/RX_0B

TX/RX_2B

TX/RX_4B

TX/RX_6B

TX/RX_1A

TX/RX_3A

TX/RX_5A

TX/RX_7A

TX/RX_1B

TX/RX_3B

TX/RX_5B

TX/RX_7B

TX/RX_2A

TX/RX_4A

TX/RX_6A

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In a typical point-to-point switching application users must configure the following for each channel:

1. Control bus mux setting (ch reg 0x9B)

2. Data path mux setting (ch reg 0x96)

3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)

4. Cross point enable bit (ch reg 0x96)

5. Perform a CDR reset and reset release (ch reg 0x0A)

Note, when using the cross point switch the local and multi-drive buffer should both be enabled regardless of the

desired configuration.

The cross point switch can also be used to replicate data or perform a broadcast function. The options for this

type of configuration include:

•

1:2 – any channel input to any 2 channels output

1:3 – any channel input to any 3 channels output

1:4 – any channel input to all 4 channels output

When the cross point switch is configured to replicate/broadcast data a master must be assigned during the

cross point configuration. The master channel will have control over the CTLE adaption. All of the slave channels

will be able to adapt their own DFE, but will not have control to adapt the CTLE. In this type of configuration there

must be 1 channel assigned as a master. All other channels in the broadcast network must be assigned as

slaves. There cannot be more than one master channel in a broadcast network. In a broadcast configuration, the

straight through path connecting the broadcasting input to its own output needs to be enabled and set to have

master control.

In a typical data replication/broadcast application users must configure the following for each channel:

1. Control bus mux setting (ch reg 0x9B)

2. Data path mux setting (ch reg 0x96)

3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)

4. Master/Slave assignment (ch reg 0x96) -- master/slave bit set to master, master function assigned by mux

setting

5. Cross point enable bit (ch reg 0x96)

6. Perform a CDR reset and reset release (ch reg 0x0A)

7.3.5 DFE with VGA

A 5-tap DFE with a VGA can be enabled within the data path of each channel to assist with reducing the effects

of cross talk, reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled,

regardless of the selected adapt mode. Once the DFE has been enabled it can be configured to adapt only

during lock acquisition or to adapt continuously. The DFE can also be manually configured to specified tap

polarities and tap weights. However, when the DFE is configured manually the DFE auto-adaption should be

disabled.

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity

bit.

Table 3. DFE Tap Weights

DFE Parameter

Tap 1 Weight Range

Tap 2-5 Weight Range

Tap Weight Step Size

Polarity

VALUE (mV) (TYP)

0 - 224

0 - 112

7

+ (positive): Signal is attenuated by the tap weight, register bit = 0

- (negative): Signal is boosted by the tap weight, register bit = 1

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The VGA is located within the DFE block. The VGA has 2-bit control and allows for 3 levels of boost. The VGA

can be used to assist in the recovery of extremely small signals. Note that the default VGA should be used for

most applications.

Table 4. VGA Boost Settings

VGA BOOST Setting (CH REG 0x8E[1:0])

BOOST (dB) (TYP)

00 (default)

0

6

01

10

11

6

12

7.3.6 Clock and Data Recovery

The CDR block consists of a Phase Locked Loop (PLL), reference clock based PPM counter, Input and Output

Data Multiplexers (mux) and circuits to monitor single bit transitions and detect false locking. The CDR sampling

position is fixed at the 0.5UI location for each bit.

By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output

to the FIR filter and differential driver. Users can configure the CDR data to route the recovered clock and data to

the PRBS checker. Users also have the option of configuring the output of the CDR to send raw non-retimed

data, or data from the pattern generator.

The CDR requires the following in order to be properly configured:

•

Input reference clock with proper reference clock divider setting to run the PPM counter.

Expected data rates must be programmed into the CDR either through the rate/sub-rate 表 18 or entered

manually with the corrected divider settings.

7.3.7 Reference Clock

The reference clock is not part of the CDR’s PLL. The reference clock is connected only to the PPM counter for

each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed

values in the rate/sub-rate 表 18 or the manually entered data rates.

The reference clock can be set to any of the 3 allowable frequencies independent of the data rate of the high

speed channel. The input reference clock can be single-ended or differential for the 25 MHz or 125 MHz settings.

If the 312.5 MHz setting is used, the input signaling type should be differential. The reference clock can be output

through the CLK_MON pins for observation or daisy chaining the reference clock to the next device. If the

CLK_MON port is used for daisy chaining then the output frequency should be set to 25 MHz.

If the reference clock port is configured to operate in single-ended mode, the 2.5V LVCMOS clock signal should

be applied to the REF_CLK_P pin. In this configuration the REF_CLK_N pin should be floated (N/C). In this case

the LVCMOS clock signal should be DC coupled into the REF_CLK_P pin. If the reference clock port is

configured for differential mode, it is recommended to AC couple the clock signal into the DS125DF1610 device.

Configuring the reference clock frequency is done in share register 0x02[6:5]. Configuring the reference clock

input port for single-ended or differential mode operation is done in share register 0x0B[4]. Enabling or disabling

the CLK_MON port is done in share reg 0x0A[0]. Selecting the CLK_MON outputs to transmit the divided (25

MHz) or undivided (input frequency) clock frequency is done in share register 0x04[7].

Table 5. REF_CLK and CLK_MON Configurations

INPUT FREQUENCE

INPUT CONFIGURATION

DEFAULT CLK_MON

FREQUENCY

RECOMMENDED CLK_MON

OUTPUT FREQUENCY FOR

DAISY CHAINING

25 MHz

125 MHz

312.5 MHz

Single-ended or Differential

Differential

25 MHz

125 MHz

312.5 MHz

25 MHz

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7.3.8 Differential Driver with FIR Filter

The DS125DF1610 uses a 3-tap FIR filter to assist with transmit equalization. The FIR filter consists of a pre

cursor tap, a main cursor tap and a post cursor tap. Each tap has a polarity bit and 64 available levels. By

default, the main cursor tap is set to a positive polarity, while the pre cursor and post cursor taps are set to a

negative polarity. Users can invert the polarity of all 3 FIR taps to invert the polarity of the output data.

The DS125DF1610 output driver can be manually powered off through SMBus register control.

7.3.9 Setting the Output V_OD

The output differential voltage (V_OD) of the driver is controlled by manipulating the drv_sel_vod bits, DEM bits,

and FIR main cursor tap. The Table 6 below shows various settings for V_ODsettings ranging from 150mV_PPto

1200 mV_PP. Using the FIR, DEM and drv_sel_vod bits is the recommended method for configuring the output

V_ODfor the best signal integrity.

Table 6. Typical V_ODSettings

V_OD(mV_PP

)

DEM SETTING

drv_sel_vod

SETTING

FIR

PRE

0

MAIN

56

52

49

45

54

56

52

46

42

56

46

40

50

52

50

52

51

55

56

57

POST

-4

-3

-2

-1

-3

-2

-1

-2

-3

1200

1150

1100

1050

1000

950

900

850

800

750

700

650

600

550

500

450

400

350

300

250

200

150

0

2

3

31

25

21

19

17

15

13

12

10

8

0

6

0

4

0

7.3.10 Output Driver Polarity Inversion

In some applications it may be necessary to invert the polarity of the data transmitted from the retimer. To invert

the polarity of the data read back the FIR polarity settings for the pre, main and post cursor taps and then invert

these bits.

7.3.11 Driver Output Rise/Fall Time

In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic

interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory

compliance. In others, it can reduce the crosstalk in the system.

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The DS125DF1610 can be configured to operate with a nominal rise/fall time corresponding to the maximum

slew rate of the output drivers into the load capacitance. Alternatively, the DS125DF1610 can be configured to

operate with a slightly greater rise/fall time if desired. By default the DS125DF1610 is configured to use the

fastest edge rate.

Table 7. Differential Driver Edge Rate Settings

EDGE RATE SETTING (CH REG 0x8E[4:2])

20-80 TYPICAL EDGE RATE (ps) (TYP)

111 (Default)

110

35

40

45

50

55

60

65

70

101

100

011

010

001

000

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7.3.12 Debug Features

7.3.12.1 Pattern Generator

Each channel in the DS125DF1610 can be configured to generate a 16-bit user defined data pattern or a pseudo

random bit sequence (PRBS). The user defined pattern can also be set to automatically invert every other 16-bit

symbol for DC balancing purposes. The DS125DF1610 pattern generator supports the following PRBS

sequences:

•

PRBS – 2⁷- 1

PRBS – 2⁹- 1

PRBS – 2¹⁵- 1

PRBS – 2³¹- 1

7.3.12.2 Pattern Checker

The pattern checker can be manually set to look for specific PRBS sequences and polarities or it can be set to

automatically detect the incoming pattern and polarity.

The pattern checker consists of a 47-bit word counter and an 11-bit error counter. The pattern checker uses 32-

bit words.

In order to read out the bit and error counters, the pattern checker must first be frozen. Continuous operation with

simultaneous read out of the bit and error counters is not supported in this implementation.

7.3.12.3 Eye Opening Monitor

The DS125DF1610’s Eye Opening Monitor (EOM) measures the internal data eye at the input of the CDR and

can be used for 2 functions:

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement

2. Full Eye Diagram Capture

The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement

is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from

channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to

convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

•

HEO [UI] = ch reg 0x27 ÷ 64

VEO [mV] = ch reg 0x28 x 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a

64 x 64 array, where each cell in the matrix consists of an 16-bit word. Users can manually adjust the vertical

scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal

scaling controlled by the state machine and is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out 4 16-bit words of junk data that should be

discarded followed by 4096 16-bit words that make up the 64 x 64 eye plot. The first actual word of the eye plot

from the retimer is for (X, Y) position (0,0). Each time the eye plot data is read out the voltage position is

incremented. Once the voltage position has incremented to position 63, the next read will cause the voltage

position to reset to 0 and the phase position to increment. This process will continue until the entire 64 x 64

matrix is read out. Figure 4 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In

this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users

can apply different algorithms to the output data to plot density or color gradients to the output data.

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63

127 191

4095

63

64 128

4032

63

0

Phase Position

Figure 4. EOM Full Eye Capture Readout

To manually control the EOM vertical range, remove scaling control from the state machine then select the

desired range:

1. Channel Reg 0x2C[6] → 0

2. See Table 8

Table 8. Eye Opening Monitor Vertical Range Settings

CH REG 0x11[7:6] VALUE

EOM VERTICAL RANGE [mV]

2’b00

2'b01

2'b10

2'b11

±100

±200

±300

±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over

equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit

error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

•

Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.

Or single byte reads. With single byte reads, the MSB are located in register 0x25 and the LSB are located in

register 0x26. In this mode, the device must be addressed each time a new byte is read.

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To perform a full eye capture with the EOM, follow these steps within the desired channel register set:

Table 9. Eye Opening Monitor Full Eye Capture Instructions

REGISTER

STEP

VALUE

DESCRIPTION

[bits]

1

2

0x67[5]

0

Disable lock EOM lock monitoring

Set the desired EOM vertical range

0x2C[6]

0x11[7:6]

0

2'b--

3

4

0x11[5]

0x24[7]

0

1

Power on the EOM

Enable fast EOM

Begin read out of the 64 x 64 array, discard first 4 words

Ch reg 0x24[0] is self clearing.

0x25 is the MSB of the 16-bit word

0x24[0]

0x25

0x26

5

1

0x26 is the LSB of the 16-bit word

0x25

0x26

6

7

Continue reading information until the 64 x 64 array is complete.

Return the EOM to its original state. Undo steps 1-4

0x67[5]

0x2C[6]

0x11[5]

1

0

0x24[7,1]

7.3.13 Interrupt Signals

The DS125DF1610 can be configured to report different events as interrupt signals. These interrupt signals do

not impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits

in the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that

interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once

the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The

DS125DF1610 will report the occurrence of an interrupt through the INTERR_IO pin. The INTERR_IO pin is an

open drain output that will pull the line low when an interrupt signal is triggered.

Note that all available interrupts are disabled by default. Users must activate the various interrupts before they

can be used.

The interrupts available in the DS125DF1610 are:

•

CDR loss of lock

CDR locked

Signal detect loss

Signal detected

PRBS pattern checker bit error detected

HEO/VEO threshold violation

When an interrupt occurs, share register 0x08 and 0x09 report which channel generated the interrupt request.

Users can then select the channel(s) that generated the interrupt request and service the interrupt by reading the

appropriate interrupt status bits in the corresponding channel registers.

7.3.14 Other Features

7.3.14.1 Lock Sequencer

A channel will temporarily consume a higher amount of power while its CDR is attempting to lock, compared to

when the CDR is locked. In order to reduce the impact of a power consumption spike when data is transmitted to

a DS125DF1610, the internal lock sequencer will limit the number of active channels that are simultaneously

allowed to attempt to lock.

The lock sequencer grants tokens to various channels that have detected a signal at the input to the CTLE. Once

a channel has achieved CDR lock, it returns its token to the lock sequencer. The lock sequencer will distribute

any available tokens on a first come first serve basis to any channel that is allowed to attempt lock and that has

detected a valid signal.

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The lock sequencer is configurable in the share registers. Users can control which channels are allowed to

attempt lock when a signal is present by configuring share registers 0x0F and 0x10. Users can also limit the

number of channels that are allowed to simultaneously attempt to lock by configuring share register 0x05.

7.3.14.2 RESET_IO Pin

The RESET_IO pin in the DS125DF1610 emulates a power on reset (POR). This type of reset re-initializes the

entire device including the SMBus address strap settings and restores both share and channel register defaults.

The RESET_IO pin triggers a reset on the rising edge of the signal. It is not recommended to hold the

RESET_IO terminal at a logic LOW state for an extended period of time. RESET_IO should be held at logic

HIGH during power on. After power on, the RESET_IO terminal should be pulsed low for a minimum of 10 µs to

perform a reset. After power on, the RESET_IO terminal can be held low longer than 10µs, but the device will

only be in a partial reset state for the during this time. Note, reset and partial reset states are not sleep or power

down states.

7.4 Device Functional Modes

7.4.1 SMBus Master Mode

SMBus master mode allows the DS125DF1610 to program itself by reading directly from an external EEPROM.

When using the SMBus master mode, the DS125DF1610 will read directly from specific location in the external

EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific

guidelines:

•

Maximum EEPROM size is 2048 Bytes

Minimum EEPROM size for a single DS125DF1610 with individual channel configuration is 1417 Bytes (3

base header bytes + 3 address map bytes + 16 x 88 channel register bytes + 3 share register bytes; bytes

are defined to be 8-bits)

•

Set ENSMB = VDD through 1kΩ resistor, enable SMBus master mode

The external EEPROM device address byte must be 0xA0

The external EEPROM device must support 400kHz operation at 2.5V supply

Set the SMBus address of the DS125DF1610 by configuring the ADDR0 and ADDR1 terminals.

When loading multiple DS125DF1610 devices from the same EEPROM, use these guidelines to configure the

devices:

•

Configure the SMBus addresses for each DS125DF1610 to be sequential. The first device in the sequence

must have an address of 0x30.

Daisy chain READEN and ALL_DONE from one device to the next device in the sequence so that they do not

compete for the EEPROM at the same time.

All DS125DF1610 devices sharing the same EEPROM must be configured with the common channel bit set

to 1. With common channel configuration enabled, each DS125DF1610 device will configure all 16 channels

with the same settings.

When loading a single DS125DF1610 from an EEPROM, use these guidelines to configure the device:

•

Set the common channel bit to 0 to allow for individual channel configuration. Or set the common channel bit

to 1 to load the same configuration settings to all channels.

•

When configuring individual channels, a 2048 Byte EEPROM must be used.

If there are multiple DS125DF1610 devices on a PCB that require individual channel configuration, then each

device must have its own EEPROM.

7.4.2 SMBus Slave Mode

7.4.2.1 SDA and SDC

In both SMBus master and SMBus slave mode, the DS125DF1610 is configured using the SMBus. The SMBus

consists of two lines, the SDA or serial data line and the SCL or serial clock line. In the DS125DF1610 these pins

are 3.3V tolerant. The SDA and SCL lines are both open-drain. They require a pull-up resistor to a supply

voltage, which may be either 2.5V or 3.3V. A pull-up resistor in the 2kΩ to 5kΩ range will provide reliable SMBus

operation.

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Device Functional Modes (continued)

7.4.2.2 SMBus Address Configuration

In either SMBus mode the DS125DF1610 must be assigned a unique SMBus address.

The DS125DF1610 can be configured to respond to one of the sixteen SMBus addresses listed in the Table 10

below. GPIO1 and GPIO0 are configured to be four level inputs immediately after the device powers on. Logic 0

can be set by tying the pin to ground through a ≤1kΩ resistor. Logic R is set by tying the pin to ground through a

20kΩ resistor. Logic F is set by floating the pin. Logic 1 is set by tying the pin to VCC = 2.5V through a ≤1kΩ

resistor.

Table 10. SMBus Address Configuration

ADDR1(GPIO1) (pin D5)

ADDR0(GPIO0) (pin B6)

7-BIT ADDRESS

7’h18

8-BIT WRITE ADDRESS

0

R

F

1

0x30

0x32

0x34

0x36

0x38

0x3A

0x3C

0x3E

0x40

0x42

0x44

0x46

0x48

0x4A

0x4C

0x4E

7’h19

0

7’h1A

7’h1B

7’h1C

7’h1D

7’h1E

7’h1F

0

R

F

1

0

R

F

1

0

7’h20

R

F

1

7’h21

7’h22

7’h23

0

7’h24

1

R

F

1

7’h25

1

7’h26

1

7’h27

When an SMBus device is addressed for reading or writing a bit is appended to the address a the least

significant bit space. This bit is set to 0 for a write or to 1 for a read.

7.4.3 Device Configuration in SMBus Slave Mode

The configurable settings of the DS125DF1610 may be set independently for each channel at any time after

power up using the SMBus. A register write is accomplished when the controller sends a START condition on the

SMBus followed by the Write address of the DS125DF1610 to be configured. After sending the Write address of

the DS125DF1610, the controller sends the register address byte followed by the register data byte. The

DS125DF1610 acknowledges each byte written to the controller according to the data link protocol of the SMBus

Version 2.0 Specification. See this specification for additional information on the operation of the SMBus.

There are 3 types of device registers in the DS125DF1610. These are the global registers, shared registers and

the channel registers. The global registers are programmed to access the various channel registers or the shared

registers. The shared registers control or allow observation of settings which affect the operation of all channels

of the DS125DF1610 at the greater device level.

The channel registers are used to set all the configuration settings of the DS125DF1610. They provide

independent control for each channel of the DS125DF1610 for all the settable device characteristics. Any

registers not described in the tables that follow should be treated as reserved. The user should not try to write

new values to these registers. The user-accessible registers described in the tables that follow provide a

complete capability for customizing the operation of the DS125DF1610 on a channel-by-channel basis.

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7.5 Programming

7.5.1 Bit Fields in the Register Set

Many of the registers in the DS125DF1610 are divided into bit fields. This allows a single register to serve

multiple purposes, which may be unrelated. Often configuring the DS125DF1610 requires writing a bit field that

makes up only part of a register value while leaving the remainder of the register value unchanged.

The procedure for accomplishing this is to read in the current value of the register to be written, modify only the

desired bits in this value, and write the modified value back to the register. Of course, if the entire register is to

be changed, rather than just a bit field within the register, it is not necessary to read in the current value of the

register first. In all the register configuration procedures described in the following sections, this procedure should

be kept in mind. In some cases, the entire register is to be modified. When only a part of the register is to be

changed, however, the procedure described above should be used.

Most register bits can be read or written to. However, some register bits are constrained to specific interface

instructions. Register bits can have the following interface constraints:

•

R - Read only

RW - Read/Write

RWSC - Read/Write, self clearing

W - Write only

7.5.2 Writing to and Reading from the Global/Shared/Channel Registers

Global registers can be accessed from the shared register page and also the channel register pages. There are

three global registers in the DS125DF1610:

1. Register 0xFC

2. Register 0xFD

3. Register 0xFF

Registers 0xFC and 0xFD are used to select the channel registers to be written to. To select a channel write a 1

to its corresponding bit in these global registers. Note more than one channel may be written to by setting

multiple bits in registers 0xFC and 0xFD. However, when performing an SMBus read transaction only one

channel can be selected at a time. If multiple channels are selected when attempting to perform an SMBus read,

the device will return 0x00.

Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read-

modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a

single channel in the 0xFC or 0xFD registers. This type of configuration allows for the reading of a single

channel's register information and then writing to all channels with the modified value.

Table 11. Channel Select Global Registers

GLOBAL

REGISTER

BIT

DESCRIPTION

CDR/TX PIN ASSIGNMENT

7

6

5

4

3

2

1

0

Channel 15– Quad 3 Channel 3 – Cross Point Ch D

Channel 14– Quad 3 Channel 2 – Cross Point Ch C

Channel 13– Quad 3 Channel 1 – Cross Point Ch B

Channel 12– Quad 3 Channel 0 – Cross Point Ch A

Channel 11– Quad 2 Channel 3 – Cross Point Ch D

Channel 10– Quad 2 Channel 2 – Cross Point Ch C

Channel 9– Quad 2 Channel 1 – Cross Point Ch B

Channel 8– Quad 2 Channel 0 – Cross Point Ch A

TX_7B

TX_7A

TX_6B

TX_6A

TX_5B

TX_5A

TX_4B

TX_4A

0xFD

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Programming (continued)

Table 11. Channel Select Global Registers (continued)

GLOBAL

REGISTER

BIT

DESCRIPTION

CDR/TX PIN ASSIGNMENT

7

6

5

4

3

2

1

0

Channel 7– Quad 1 Channel 3 – Cross Point Ch D

Channel 6– Quad 1 Channel 2 – Cross Point Ch C

Channel 5– Quad 1 Channel 1 – Cross Point Ch B

Channel 4– Quad 1 Channel 0 – Cross Point Ch A

Channel 3– Quad 0 Channel 3 – Cross Point Ch D

Channel 2– Quad 0 Channel 2 – Cross Point Ch C

Channel 1– Quad 0 Channel 1 – Cross Point Ch B

Channel 0 – Quad 0 Channel 0 – Cross Point Ch A

TX_3B

TX_3A

TX_2B

TX_2A

TX_1B

TX_1A

TX_0B

TX_0A

0xFC

Table 12. Shared-Channel Select Global Register

GLOBAL REGISTER

BIT

DESCRIPTION

0xFF

7:2

These bits are not used and default to 0

1: Broadcast write to all channels, 0xFF[0] must be set to 1.

0: Normal operation, select channel register as defined in 0xFC and 0xFD

1

0

1: Select Channel Registers

0: Select Share Registers

Table 13. Shared Registers

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

SMBus Address

Strapped 7-bit addres is 0x18 +

SMBus_Addr[3:0]

0

7

6

0

1

0

1

0

R

N

Y

N

Y

SMBus_Addr3

SMBus_Addr2

SMBus_Addr1

SMBus_Addr0

RESERVED

Version2

5

R

4

R

3

R

2:0

7

R

1

R

Device version

6

R

Version1

5

R

Version0

4

R

Device_ID4

Device_ID3

Device_ID2

Device_ID1

Device_ID0

RESERVED

REFCLK_SEL1

REFCLK_SEL0

Device ID code for

DS125DF1610

3

R

2

R

1

R

0

R

2

7

RW

6

Sets the REFCLK input

frequency

00: 25 MHz

5

01: 125 MHz

10: 312.5MHz

11: Reserved

4:0

7:3

2

0

RW

R

N

Y

N

RESERVED

3

R

1:0

R

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Table 13. Shared Registers (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

4

7

0

RW

N

SEL_REF_CLK_DIG_OUT_AN 1: Selects the divided clock

A

0: Selects the undivided clock

1: Resets share registers

6

5

0

RWSC

N

RST_SMB_REGS

RST_SMB_MAS

1: Resets SMBus Master

controller

4

3

0

RW

N

RESERVED

MR_DIS_LOCK_SEQR

1: Disables the lock sequencer

circuit

0: Normal operation, lock

sequencer is enabled

2

1

0

7

6

5

4

0

1

0

1

RW

R

N

RESERVED

5

RESERVED

CRC_EN

1: Slave CRC Trigger

RESERVED

EEPROM_READ_DONE

This bit is set to 1 when read

from EEPROM is done

3

2

1

0

RW

R

N

LIMIT_CONC_LOCKS3

LIMIT_CONC_LOCKS2

LIMIT_CONC_LOCKS1

LIMIT_CONC_LOCKS0

RESERVED

INT_Q1C3

Sets max number of channels

that can lock at any given time,

defaults to 8 channels.

1

0

6

7

8

7:0

7

Interrupt from quad 1, ch 3

Interrupt from quad 1, ch 2

Interrupt from quad 1, ch 1

Interrupt from quad 1, ch 0

Interrupt from quad 0, ch 3

Interrupt from quad 0, ch 2

Interrupt from quad 0, ch 1

Interrupt from quad 0, ch 0

Interrupt from quad 3, ch 3

Interrupt from quad 3, ch 2

Interrupt from quad 3, ch 1

Interrupt from quad 3, ch 0

Interrupt from quad 2, ch 3

Interrupt from quad 2, ch 2

Interrupt from quad 2, ch 1

Interrupt from quad 2, ch 0

6

R

INT_Q1C2

5

R

INT_Q1C1

4

R

INT_Q1C0

3

R

INT_Q0C3

2

R

INT_Q0C2

1

R

INT_Q0C1

0

R

INT_Q0C0

9

7

R

INT_Q3C3

6

R

INT_Q3C2

5

R

INT_Q3C1

4

R

INT_Q3C0

3

R

INT_Q2C3

2

R

INT_Q2C2

1

R

INT_Q2C1

0

R

INT_Q2C0

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Table 13. Shared Registers (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

A

7

0

RW

N

SEL_CLK_FROM_DIG

1: selects ref clk from digital to

transmit out

0: selects ref clk from analog

loop chain to transmit out. All

channels’ analog blocks must

have ref clk loop through

enabled to transmit ref clk out

of device

6

5

0

RW

N

SEL_REFCLK_TX_VCM1

SEL_REFCLK_TX_VCM0

Sets the output common-mode

voltage:

00: 800mV

01: 1000mV

10: 1200mV

11: Tracks VCC, bias at 1.2V

4

3

0

RW

N

SEL_REFCLK_TX_VOD1

SEL_REFCLK_TX_VOD0

Sets the output differential

peak-to-peak voltage:

00: 400mV

01: 533mV

10: 667mV

11: 800mV

2

1

0

RW

N

RESERVED

SEL_REFCLK_TX_SCP

1:disable

0:Ref-clk TX short-circuit

protection

0

1

RW

Y

DIS_REFCLK_OUT

1: Disable REFCLK_OUT (TRI-

STATE)

0: Enable REFCLK_OUT

B

7

6

0

RW

R

N

RESERVED

REFCLK_DET

This bit is set to 1 when refclk

has been detected

5

4

0

RW

N

RESERVED

REFCLK_SINGLE_END

1: Reference clock input port

configured as single-ended

input

0: Normal operation, reference

clock input port configured as

differential input

3:0

7:3

2

0

RW

R

N

RESERVED

C

D

RESERVED

SAR_ADC_RST

SAR_ADC_EN

RESERVED

Resets SAR ADC

Enables SAR ADC

1

0

7

SAR_ADC_OUT7

SAR_ADC_OUT6

SAR_ADC_OUT5

SAR_ADC_OUT4

SAR_ADC_OUT3

SAR_ADC_OUT2

SAR_ADC_OUT1

SAR_ADC_OUT0

RESERVED

10-bit SAR ADC Output[7:0]

6

5

4

3

2

1

0

E

7:2

1

SAR_ADC_OUT9

SAR_ADC_OUT8

10-bit SAR ADC Output[9:8]

0

R

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Table 13. Shared Registers (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

7

Mode

RW

R

EEPROM

Field Name

EN_CH_LOCK15

Description

F

1

0

Y

N

1: Allows channel to lock

0: Channel not allowed to lock

6

EN_CH_LOCK14

EN_CH_LOCK13

EN_CH_LOCK12

EN_CH_LOCK11

EN_CH_LOCK10

EN_CH_LOCK9

EN_CH_LOCK8

EN_CH_LOCK7

EN_CH_LOCK6

EN_CH_LOCK5

EN_CH_LOCK4

EN_CH_LOCK3

EN_CH_LOCK2

EN_CH_LOCK1

EN_CH_LOCK0

EEPRM_LOAD_STATUS

1: Allows channel to lock

0: Channel not allowed to lock

5

1: Allows channel to lock

0: Channel not allowed to lock

4

1: Allows channel to lock

0: Channel not allowed to lock

3

1: Allows channel to lock

0: Channel not allowed to lock

2

1: Allows channel to lock

0: Channel not allowed to lock

1

1: Allows channel to lock

0: Channel not allowed to lock

0

1: Allows channel to lock

0: Channel not allowed to lock

10

7

1: Allows channel to lock

0: Channel not allowed to lock

6

1: Allows channel to lock

0: Channel not allowed to lock

5

1: Allows channel to lock

0: Channel not allowed to lock

4

1: Allows channel to lock

0: Channel not allowed to lock

3

1: Allows channel to lock

0: Channel not allowed to lock

2

1: Allows channel to lock

0: Channel not allowed to lock

1

1: Allows channel to lock

0: Channel not allowed to lock

0

1: Allows channel to lock

0: Channel not allowed to lock

11

7:6

11: Not valid

10: EEPROM load completed

successfully

01: EEPROM load failed after

64 attempts

00: EEPROM load in progress

5

4

3

2

1

0

R

N

EEPRM_ATMPT5

EEPRM_ATMPT4

EEPRM_ATMPT3

EEPRM_ATMPT2

EEPRM_ATMPT1

EEPRM_ATMPT0

Number of attempts made to

load EEPROM image

30

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Table 13. Shared Registers (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

7

Mode

RW

EEPROM

Field Name

Description

FC

0

N

Channel 7– Quad 1 Channel 3 1: Enables SMBus access

to channel 7

6

Channel 6– Quad 1 Channel 2 1: Enables SMBus access

to channel 6

5

Channel 5– Quad 1 Channel 1 1: Enables SMBus access

to channel 5

4

Channel 4– Quad 1 Channel 0 1: Enables SMBus access

to channel 4

3

Channel 3– Quad 0 Channel 3 1: Enables SMBus access

to channel 3

2

Channel 2– Quad 0 Channel 2 1: Enables SMBus access

to channel 2

1

Channel 1– Quad 0 Channel 1 1: Enables SMBus access

to channel 1

0

Channel 0– Quad 0 Channel 0 1: Enables SMBus access

to channel 0

FD

7

Channel 15– Quad 3 Channel 3 1: Enables SMBus access

to channel 15

6

Channel 14– Quad 3 Channel 2 1: Enables SMBus access

to channel 14

5

Channel 13– Quad 3 Channel 1 1: Enables SMBus access

to channel 13

4

Channel 12– Quad 3 Channel 0 1: Enables SMBus access

to channel 12

3

Channel 11– Quad 2 Channel 3 1: Enables SMBus access

to channel 11

2

Channel 10– Quad 2 Channel 2 1: Enables SMBus access

to channel 10

1

Channel 9– Quad 2 Channel 1 1: Enables SMBus access

to channel 9

0

Channel 8– Quad 2 Channel 0 1: Enables SMBus access

to channel 8

FE

7

6

0

1

0

R

N

VENDOR_ID7

VENDOR_ID6

VENDOR_ID5

VENDOR_ID4

VENDOR_ID3

VENDOR_ID2

VENDOR_ID1

VENDOR_ID0

RESERVED

5

R

4

R

3

R

2

R

1

R

0

R

FF

7:2

1

RW

WRITE_ALL_CH

1: Write to all channels as if

they are the same, but only

allows to read back from a

single channel specified in

0xFC and 0xFD.

Note: EN_CH_SMB must be

set to 1, or else this function is

invalid.

0

RW

N

EN_CH_SMB

1: Enables SMBus access to

the channels specified in 0xFC

and 0xFD.

0: Enables SMBus access to

the shared registers

31

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Table 14. Channel Registers, 0 to 1F

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

CLK_CORE_DIS

Description

0

7

0

RW

N

1: Disables the primary digital

clock, resets all state machines

0: Normal operation

6:4

3

0

RW

N

RESERVED

RST_CORE

1: Reset core state machine

0: Normal Operation

2

1

0

RW

N

RST_REGS

RST_VCO

1: Resets channel registers,

restores default values

0: Normal Operation

1: Resets PPM counter, EOM

counter, FLD counter, SBT

counter

0: Normal Operation

0

7

0

RW

R

N

RST_REFCLK

SIG_DET

1: Reset PPM counter

0: Normal Operation

1

1: Signal is present on high speed

inputs

0: No signal is detected on high

speed inputs

6

5

0

R

N

POL_INV_DET

1: PRBS checker detected polarity

inversion 0: No pattern inversion

detected

CDR_LOCK_LOSS_INT

1: indicates loss of CDR lock after

having acquired it.

Bit clears on read.

4

3

2

1

0

R

N

PRBS_SEQ_DET3

PRBS_SEQ_DET2

PRBS_SEQ_DET1

PRBS_SEQ_DET0

SIG_DET_LOSS_INT

1: Indicates if the PRBS-31

sequence is locked

1: Indicates if the PRBS-15

sequence is locked

1: Indicates if the PRBS-9

sequence is locked

1: Indicates if the PRBS-7

sequence is locked

Loss of signal indicator.

Bit is set once signal is acquired

and then lost.

2

3

7:0

0

R

N

MULTI_PURP_STATUS

Register configured by setting

channel register 0x0C[7:4]

7

6

0

RW

Y

N

Y

N

EQ_BST0[1]

EQ_BST0[0]

EQ_BST1[1]

EQ_BST1[0]

EQ_BST2[1]

EQ_BST2[0]

EQ_BST3[1]

EQ_BST3[0]

RESERVED

This register can be used to force

an EQ boost setting if used in

conjuntion with channel register

0x2D[3]

0

5

0

4

3

0

2

0

1

0

4

7:4

3

0

2:0

7:0

0x01

5

6

7

32

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 14. Channel Registers, 0 to 1F (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

8

7

6

5

4

3

2

1

0

7

0

1

0

RW

Y

RESERVED

9

DIVSEL_VCO_CAP_OV

SET_CP_LVL_LPF_OV

BYPASS_PFD_OV

Enable bit to override cap_cnt with

value in register 0x0B[4:0]

6

5

0

RW

Y

Enable bit to override lpf_dac_val

with value in register 0x1F[4:0]

Enable bit to override

sel_retimed_loopthru and

sel_raw_loopthru with values in

reg 0x1E[7:5]

4

0

RW

Y

EN_FD_PD_VCO_PDIQ_OV

Enable bit to override en_fd,

pd_pd, pd_vco, pd_pdiq with reg

0x1E[0], reg 0x1E[2], reg 0x1C[0],

reg 0x1C[1]

3

2

0

RW

Y

EN_PD_CP_OV

DIVSEL_OV

Enable bit to override pd_fd_cp

and pd_pd_cp with value in reg

0x1B[1:0]

Enable bit to override divsel with

value in reg 0x18[6:4]

1: Override enable

0: Normal operation

1

0

7

6

0

1

RW

Y

EN_FLD_OV

Enable to override pd_fld with

value in reg 0x1E[1]

PFD_LOCK_

MODE_SM

Enable FD in lock state

A

SBT_EN

Enable bit to override sbt_en with

value in reg 0x1D[7]

EN_IDAC_PD_CP_OV

EN_IDAC_FD_CP_OV

Enable bit to overridephase

detector charge pump settings

with reg 0x1C[7:5]

Enable bit to override frequency

detector charge pump settings

with reg 0x1C[4:2]

5

0

RW

Y

DAC_LPF_HIGH_

PHASE_OV

DAC_LPF_LOW_

PHASE_OV

Enable bit to override loop filter

comparator trip voltage with reg

0x16[7:0]

4

3

2

1

0

1

0

RW

Y

N

EN150_LPF_OV

CDR_RESET_OV

CDR_RESET_SM

CDR_LOCK_OV

CDR_LOCK

Enable bit to override en150_lpf

with value in reg 0x1F[6]

Enable bit to override CDR reset

with reg 0x0A[2]

1: CDR is put into reset

0: normal CDR operation

Enable CDR lock signal override

with reg 0x0A[0]

CDR lock signal override bit

33

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Table 14. Channel Registers, 0 to 1F (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

B

7

6

0

1

0

1

0

RW

Y

N

RESERVED

5

4

3

2

1

0

C

7:4

STATUS_CONTROL

These bits repurpose channel

register 0x02 to report different

status signals

3

1

RW

Y

SINGLE_BIT_LIMIT_CHECK_ON

1: Normal operation, device

checks for single bit transitions as

a gate to achieving CDR lock

2

1

0

RW

N

Y

RESERVED

EN_IDAC_FD_CP3

Frequency detector charge pump

setting bit 3 (MSB)

LSB located in channel register

0x1C

0

RW

Y

EN_IDAC_PD_CP3

DES_PD

Phase detector charge pump

setting bit 3 (MSB)

LSB located in channel register

0x1C

D

7

1

RW

N

1: Deserializer is powered down

0: Deserializer is enabled

6

5

4

0

1

RW

N

Y

RESERVED

DRV_SEL_VOD4

DRV_SEL_VOD3

Used in conjunction with 0x2D[2:0]

to control the VOD levels of the

high speed drivers

3

0

1

RW

Y

N

Y

FIR_RLOAD_MAX

FIR_SEL_NEG_GM

RESERVED

2

1:0

7:0

0

E

0x93

0x69

0x3A

RESERVED

F

RESERVED

10

RESERVED

34

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 14. Channel Registers, 0 to 1F (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

11

7

6

0

RW

Y

EOM_SEL_VRANGE1

Manually set the EOM vertical

range, used with channel register

0x2C[6]

00: ±100 mV

01: ±200 mV

10: ±300 mV

11: ±400 mV

5

4

3

1

0

RW

Y

N

Y

EOM_PD

1: Normal operation

RESERVED

DFE_TAP2_POL

Bit forces DFE tap 2 polarity

1: Negative, boosts by the

specified tap weight

0: Positive, attenuates by the

specified tap weight

2

1

0

7

0

1

RW

Y

DFE_TAP3_POL

DFE_TAP4_POL

DFE_TAP5_POL

DFE_TAP1_POL

Bit forces DFE tap 3 polarity

1: Negative, boosts by the

specified tap weight

0: Positive, attenuates by the

specified tap weight

Bit forces DFE tap 4 polarity

1: Negative, boosts by the

specified tap weight

0: Positive, attenuates by the

specified tap weight

Bit forces DFE tap 5 polarity

1: Negative, boosts by the

specified tap weight

0: Positive, attenuates by the

specified tap weight

12

Bit forces DFE tap 1 polarity

1: Negative, boosts by the

specified tap weight

0: Positive, attenuates by the

specified tap weight

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

RW

N

Y

N

Y

SD_SEL_MUTEZ

DFE_SEL_NEG_GM

DFE_WT1[4]

DFE_WT1[3]

DFE_WT1[2]

DFE_WT1[1]

DFE_WT1[0]

RESERVED

Bits force DFE tap 1 weight,

manual DFE operation required to

take effect

13

RESERVED

EQ_EN_DC_OFF

RESERVED

1: Normal operation

EQ_LIMIT_EN

1: Configures the final stage of the

equalizer to be a limiting stage.

0: Normal operation, final stage of

the equalizer is configured to be a

linear stage.

1

0

RW

N

RESERVED

35

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Table 14. Channel Registers, 0 to 1F (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

EQ_SD_PRESET

Description

14

7

0

RW

Y

1: Forces signal detect HIGH, and

force enables the channel. Should

not be set if bit 6 is set.

0: Normal Operation.

6

0

RW

Y

EQ_SD_RESET

1: Forces signal detect LOW and

force disables the channel. Should

not be set if bit 7 is set.

0: Normal Operation.

5

4

0

1

0

RW

Y

N

Y

N

Y

N

EQ_REFA_SEL1

EQ_REFA_SEL0

EQ_REFD_SEL1

EQ_REFD_SEL0

RESERVED

Controls the signal detect assert

levels.

3

Controls the signal detect de-

assert levels.

2

1:0

7

15

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

DRV_PD

1: Powers down the high speed

driver

0: Normal operation

2

1

0

1

0

RW

Y

RESERVED

DRV_DEM1

DRV_DEM0

Degenerates the pre-driver

degeneration

00: 0 dB

01: 1 dB

10: 2 dB

11: 3 dB

16

17

18

7:0

7

0x7A

RW

Y

N

Y

RESERVED

0x25

RESERVED

0

1

0

RESERVED

6

PDIQ_SEL_DIV2

PDIQ_SEL_DIV1

PDIQ_SEL_DIV0

These bits will force the divider

setting if 0x09[2] is set.

000: Divide by 1

001: Divide by 2

010: Divide by 4

5

4

011: Divide by 8

All other values are reserved.

3

2

0

RW

N

RESERVED

DRV_PD_R_EN

1: Enables the shut down

termination resistor to be present

when the driver is powered down

with channel register 0x15[3]

0: Normal operation, resistor is

disconnected from output for

propper driver operation

1:0

7:6

5:0

7:4

3

0

RW

N

Y

N

RESERVED

19

1A

0x20

RESERVED

0xA

0

RESERVED

DRV_SEL_VCM1

DRV_SEL_VCM0

RESERVED

This feature is reserved for future

use.

2

0

1:0

0

36

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Table 14. Channel Registers, 0 to 1F (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

1B

7:2

1

0

1

0

RW

N

Y

RESERVED

CP_EN_CP_PD

1: Normal operation

0

CP_EN_CP_FD

1: Normal operation

1C

7

EN_IDAC_PD_CP2

EN_IDAC_PD_CP1

EN_IDAC_PD_CP0

Phase detector charge pump

setting

MSB located in channel register

0x0C[0]

Override bit required for these bits

to take effect

6

5

4

3

2

1

0

RW

Y

EN_IDAC_FD_CP2

EN_IDAC_FD_CP1

EN_IDAC_FD_CP0

Frequency detector charge pump

setting

MSB located in channel register

0x0C[1]

Override bit required for these bits

to take effect

1:0

7

0

RW

N

Y

RESERVED

SBT_EN

1D

1E

SBT enable override

0: Normal operation

6:0

7

0

1

RW

N

Y

RESERVED

PFD_SEL_DATA_MUX2

PFD_SEL_DATA_MUX1

PFD_SEL_DATA_MUX0

For these values to take effect,

register 0x09[5] must be set to 1.

000: Raw Data*

6

5

001: Retimed Data

100: Pattern Generator

111: Mute

All other values are reserved.

*Note in this mode the FIR filter

will not function. Data is routed

only through the pre cursor tap.

See Functional Description section

for more information.

4

3

0

1

RW

N

Y

SER_EN

DFE_PD

1: Enables the serializer for

pattern generation

0: Disables the serializer

This bit must be cleared for the

DFE to be functional in any adapt

mode.

0: DFE enabled

1: DFE disabled

2

0

RW

Y

PFD_PD_PD

PFD phasee detector power down

override

1

0

1

RW

Y

PFD_EN_FLD

PFD_EN_FD

PFD enable FLD override

PFD enable frequency detector

override

1F

7:6

5:0

0x55

RW

Y

RESERVED

37

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Table 15. Channel Registers, 20 to 39

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

20

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

RW

Y

N

DFE_WT5[3]

DFE_WT5[2]

DFE_WT5[1]

DFE_WT5[0]

DFE_WT4[3]

DFE_WT4[2]

DFE_WT4[1]

DFE_WT4[0]

DFE_WT3[3]

DFE_WT3[2]

DFE_WT3[1]

DFE_WT3[0]

DFE_WT2[3]

DFE_WT2[2]

DFE_WT2[1]

DFE_WT2[0]

EOM_OV

Bits force DFE tap 5 weight,

manual DFE operation

required to take effect

Bits force DFE tap 4 weight,

manual DFE operation

required to take effect

21

Bits force DFE tap 3 weight,

manual DFE operation

required to take effect

Bits force DFE tap 2 weight,

manual DFE operation

required to take effect

22

23

1: Override enable for EOM

manual control

0: Normal operation

6

0

RW

N

EOM_SEL_RATE_OV

1: Override enable for EOM

rate selection

0: Normal operation

5:0

7

0

RW

N

RESERVED

EOM_GET_HEO_VEO_OV

1: Override enable for

manual control of the

HEO/VEO trigger

0: Normal operation

6

1

0

RW

Y

N

DFE_OV

1: Normal operation, DFE

must be enabled in channel

register 0x1E[3]

5:0

RESERVED

38

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 15. Channel Registers, 20 to 39 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

24

7

0

RW

N

FAST_EOM

1: Enables fast EOM mode

for fully eye capture. In this

mode the phase DAC and

voltage DAC of the EOM are

automatically incremented

through a 64 x 64 matrix.

Values for each point are

stored in channel registers

25 and 26.

6

5

4

0

R

N

DFE_EQ_ERROR_NO_LOCK

DFE/CTLE SM quit due to

loss of lock

GET_HEO_VEO_ERROR_

NO_HITS

GET_HEO_VEO sees no

hits at zero crossing

GET_HEO_VEO_ERROR_

NO_OPENING

GET_HEO_VEO cannot see

a vertical eye opening

3

2

0

RW

N

RESERVED

DFE_ADAPT

RWSC

1: Manually start DFE

adaption, self clearing.

0: Normal operation

1

0

RWSC

N

EOM_GET_HEO_VEO

1: Manually triggers a

HEO/VEO measurement.

Must be enabled with

channel register 0x23[7].

0

RWSC

N

EOM_START

1: Starts EOM counter, self

clearing

25

26

27

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

R

N

EOM_COUNT15

EOM_COUNT14

EOM_COUNT13

EOM_COUNT12

EOM_COUNT11

EOM_COUNT10

EOM_COUNT9

EOM_COUNT8

EOM_COUNT7

EOM_COUNT6

EOM_COUNT5

EOM_COUNT4

EOM_COUNT3

EOM_COUNT2

EOM_COUNT1

EOM_COUNT0

HEO7

MSBs of EOM counter

LSBs of EOM counter

HEO value, requires CDR to

be locked for valid

measurement

HEO6

HEO5

HEO4

HEO3

HEO2

HEO1

HEO0

39

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Table 15. Channel Registers, 20 to 39 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

28

7

6

5

4

3

2

1

0

7

6

5

0

R

N

VEO7

VEO value, requires CDR to

be locked for valid

measurement

VEO6

R

VEO5

R

VEO4

R

VEO3

R

VEO2

R

VEO1

R

VEO0

29

RW

R

RESERVED

EOM_VRANGE_SETTING1

EOM_VRANGE_SETTING0

Use these bits to read back

the EOM voltage range

setting

R

00: ±100 mV

01: ±200 mV

10: ±300 mV

11: ±400 mV

4

0

RW

N

EN_FOM_RESET

1: Enables resetting the FOM

before issuing a manual

adaption

3

2

0

RW

N

VEO_MIN_HITS_1

VEO_MIN_HITS_0

These bits set the number of

hits for a particular phase

and voltage location in the

EOM before the EOM will

indicate a hit has occured.

This filtering only affects the

VEO measurement.

Filter thresholds:

00: 0 hits

01: 15 hits

10, 11: 255 hits

1:0

7

0

1

0

1

RW

N

Y

N

Y

RESERVED

2A

EOM_TIMER_THR7

EOM_TIMER_THR6

EOM_TIMER_THR5

EOM_TIMER_THR4

EOM_TIMER_THR3

EOM_TIMER_THR2

EOM_TIMER_THR1

EOM_TIMER_THR0

RESERVED

Controls the amount of time

the EOM samples each point

in the eye for. The total

counter bit width is 16-bits,

this register is the upper 8-

bits. The counter counts in

32-bit words, therefore, the

total number of bits counted

is 32 times this value.

6

5

4

3

2

1

0

2B

7:6

5:4

3

RESERVED

EOM_MIN_REQ_HITS3

EOM_MIN_REQ_HITS2

EOM_MIN_REQ_HITS1

EOM_MIN_REQ_HITS0

These bits set the number of

hits for a particular phase

and voltage location in the

EOM before the EOM will

indicate a hit has occured.

This filtering only affects the

HEO measurement.

2

1

0

Filter threshold ranges from

0 to 15 hits.

40

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Table 15. Channel Registers, 20 to 39 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

7

Mode

RW

EEPROM

Field Name

RELOAD_DFE_TAPS

VEO_SCALE

Description

2C

1

N

Y

1: Reload DFE taps from last

adapted value

6

1

RW

1: Scale VEO based on EOM

vertical range

0: Manual control of vertical

range

5

4

1

RW

Y

DFE_SM_FOM1

DFE_SM_FOM0

00: not valid

01: SM uses only HEO

10: SM uses only VEO

11: SM uses both HEO and

VEO

3

2

1

0

7

0

1

0

RW

Y

DFE_ADAPT_COUNTER3

DFE_ADAPT_COUNTER2

DFE_ADAPT_COUNTER1

DFE_ADAPT_COUNTER0

PD_SCP

DFE look-beyond count.

2D

1: Power down the short

circuit protection for the high

speed driver outputs

0: Normal operation, short

circuit protection is enabled

for the high speed driver

outputs

6

5

4

3

0

RW

Y

SD_EN_FAST_OOB

SD_REF_HIGH

SD_GAIN

Feature is reserved for future

use.

Feature is reserved for future

use.

Feature is reserved for future

use.

EQ_BST_OV

Allow override control of the

EQ setting by writing to

channel register 0x03. Not

recommended for normal

operation.

2

1

0

1

RW

Y

N

Y

DRV_SEL_VOD2

DRV_SEL_VOD1

DRV_SEL_VOD0

RESERVED

RATE1

Used in conjunction with

0x0D[5:4] to control the VOD

levels of the high speed

drivers

0

2E

2F

7:0

7

4 bits determine standard.

0x6: 11.5 Gbps

0x7: 12.5, 6.5, 3.125 Gbps

0x8: 9.8304, 4.9152, 2.4576

Gbps

0x9: 6.144, 3.072 Gbps

0xA: 10, 5, 2.5 Gbps

0xB: 10.3125, 1.25

6

RATE0

5

SUBRATE1

SUBRATE0

4

3

0

RW

Y

INDEX_OV

If this bit is set to 1, reg 0x13

is to be used as a 5 bit index

to the [31:0] array of EQ

settings.

2

1

0

1

0

RW

Y

N

EN_PPM_CHECK

EN_FLD_CHECK

CTLE_ADAPT

1: PPM check to be used as

a qualifier when performing

lock detect

1: False lock detector is used

as a qualifier when

performing lock detect

RWSC

Starts CTLE adaption, self

clearing

41

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Table 15. Channel Registers, 20 to 39 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

FREEZE_PPM_CNT

Description

30

7

0

RW

N

1: Freeze PPM counter to

allow safe read

asynchronously

6

5

RW

Y

N

EQ_SEARCH_OV_EN

EN_PATT_INV

Enables the EQ search bit to

be force by channel register

0x13[2]

1: Enables automatic pattern

inversion of successive 16-

bit words when using the

user defined pattern

generator option.

4

3

0

RW

N

RELOAD_PRBS_CHKR

PRBS_EN_DIG_CLK

Feature is reserved for future

use.

This bit enables the clock to

operate the PRBS generator

and/or the PRBS checker.

Toggling this bit is the

primary method to reset the

PRBS pattern generator and

PRBS checker.

2

0

RW

N

PRBS_PROGPATT_EN

1: Enable a fixed user

defined pattern. Requires

that the pattern generator be

configured properly to be

enabled

1

0

RW

N

PRBS_PATTERN_SEL1

PRBS_PATTERN_SEL0

Selects the PRBS generator

pattern to output. Requires

that the pattern generator be

configured properly.

00: PRBS-7

01: PRBS-9

10: PRBS-15

11: PRBS-31

31

7

0

RW

N

PRBS_INT_EN

1: Enables interrupt for

detection of PRBS errors.

The PRBS checker must be

properly configured for this

feature to work

6

5

0

RW

Y

ADAPT_MODE1

ADAPT_MODE0

00: no adaption

01: adapt CTLE only

10: adapt CTLE until optimal,

then DFE, then CTLE again

11: adapt CTLE until

HEO/VEO threshold in reg

0x33 are met, then DFE,

then EQ until optimal

4

3

0

RW

Y

EQ_SM_FOM1

EQ_SM_FOM0

Sets the desired FoM for EQ

adaption

00: not valid

01: SM uses HEO only

10: SM uses VEO only

11: SM uses both HEO and

VEO

2

1

0

RW

N

RESERVED

CDR_LOCK_LOSS_INT_EN

1: enables loss of CDR lock

interrupt

0

RW

N

SIG_DET_LOSS_INT_EN

1: enable loss of signal

detect interrupt

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Table 15. Channel Registers, 20 to 39 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

32

33

34

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

1

0

1

0

1

0

RW

Y

N

HEO_INT_THRESH3

These bits set the threshold

for the HEO and VEO

interrupt. Each threshold bit

represents 8 counts of HEO

or VEO.

HEO_INT_THRESH2

HEO_INT_THRESH1

HEO_INT_THRESH0

VEO_INT_THRESH3

VEO_INT_THRESH2

VEO_INT_THRESH1

VEO_INT_THRESH0

HEO_THRESH3

In adapt mode 3, this register

sets the minimum HEO and

VEO required for CTLE

adaption, before starting

DFE adaption. This can be a

max of 15

HEO_THRESH2

HEO_THRESH1

HEO_THRESH0

VEO_THRESH3

VEO_THRESH2

VEO_THRESH1

VEO_THRESH0

PPM_ERR_RDY

1: Indicates that a PPM error

count is read to be read from

channel register 0x3B and

0x3C

6

0

RW

Y

LOW_POWER_MODE_DISABLE

By default, all blocks (except

signal detect) power down

after 100ms after signal

detect goes low.

5

4

1

RW

Y

LOCK_COUNTER1

LOCK_COUNTER0

After achieving lock, the

CDR continues to monitor

the lock criteria.If the lock

criteria fail, the lock is

checked for a total of N

number of times before

declaring an out of lock

condition, where N is set by

this the value in these

registers, with a max value

of +3, for a total of 4. If

during the N lock checks,

lock is regained, then the

lock condition is left HI, and

the counter is reset back to

zero.

3

2

1

0

1

RW

Y

DFE_MAX_TAP2_5[3]

DFE_MAX_TAP2_5[2]

DFE_MAX_TAP2_5[1]

DFE_MAX_TAP2_5[0]

These 4 bits are used to set

the maximum value by which

DFE taps 2-5 are able to

adapt with each subsequent

adaptation. Same used for

both polarities.

43

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Table 15. Channel Registers, 20 to 39 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

35

7

6

0

RW

Y

DATA_LOCK_PPM1

DATA_LOCK_PPM0

Modifies the value of the

ppm delta tolerance from

channel register 0x64

00 - ppm_delta[7:0] =1 x

ppm_delta[7:0]

01 - ppm_delta[7:0] =1 x

ppm_delta[7:0] +

ppm_delta[3:1]

10 - ppm_delta[7:0] =2 x

ppm_delta[7:0]

11 - ppm_delta[7:0] =2 x

ppm_delta[7:0] +

ppm_delta[3:1]

5

0

RW

N

GET_PPM_ERROR

Get ppm error from

ppm_count - clears when

done. Normally updates

continuously, but can be

manually triggered with read

value from channel register

0x3B and 0x3C

4

3

2

1

0

7

1

0

RW

Y

N

DFE_MAX_TAP1[4]

DFE_MAX_TAP1[3]

DFE_MAX_TAP1[2]

DFE_MAX_TAP1[1]

DFE_MAX_TAP1[0]

UNCORR_ERR_INT_EN

Determines max tap limit for

DFE tap 1

36

Feature is reserved for future

use.

6

0

RW

N

HEO_VEO_INT_EN

1: Enable HEO/VEO interrupt

capability

5

4

1

RW

Y

REF_MODE1

REF_MODE0

11: Fast_lock all cap dac ref

clock enabled

(recommended)

10: Reserved

01: Reserved

00: referenceless all cap dac,

for debug use only

3

2

1

0

RW

Y

N

EN_6466B_LOCK_GATE

CDR_CAP_DAC_RNG_OV

EN_6466B_RESTART

K28P5_6466_INT_EN

Feautre is reserved for future

use.

Override enable for cap dac

range

Feature is reserved for future

use.

Feature is reserved for future

use.

37

7

6

5

4

3

2

1

0

R

N

CTLE_STATUS7

CTLE_STATUS6

CTLE_STATUS5

CTLE_STATUS4

CTLE_STATUS3

CTLE_STATUS2

CTLE_STATUS1

CTLE_STATUS0

Feature is reserved for future

use.

44

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Table 15. Channel Registers, 20 to 39 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

38

7

6

5

4

3

2

1

0

7

0

R

N

DFE_STATUS7

Feature is reserved for future

use.

DFE_STATUS6

DFE_STATUS5

DFE_STATUS4

DFE_STATUS3

DFE_STATUS2

DFE_STATUS1

DFE_STATUS0

R

39

RW

PRELOCK_COMPARATOR_

ABRT_MODE

Feature is reserved for future

use.

6

5

0

RW

Y

EOM_RATE1

EOM_RATE0

With eom_ov=1, these bits

control the Eye Monitor Rate.

11: Use for Full Rate,

Fastest

10 : Use for 1/2 Rate

01: Use for 1/4 Rate

00: Use for 1/8 Rate,

Slowest

4

3

2

1

0

RW

Y

START_INDEX4

START_INDEX3

START_INDEX2

START_INDEX1

START_INDEX0

Start index for EQ adaptation

Table 16. Channel Registers, 3A to 59

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

3A

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

RW

R

Y

N

FIXED_EQ_BST0[1]

FIXED_EQ_BST0[0]

FIXED_EQ_BST1[1]

FIXED_EQ_BST1[0]

FIXED_EQ_BST2[1]

FIXED_EQ_BST2[0]

FIXED_EQ_BST3[1]

FIXED_EQ_BST3[0]

PPM_COUNT15

During adaptation, if the

divider setting is >2, then a

fixed EQ setting from this

register will be used.

However, if channel register

0x6F[7] is enabled, then an

EQ adaptation will be

performed instead.

3B

PPM count MSB

R

PPM_COUNT14

R

PPM_COUNT13

R

PPM_COUNT12

R

PPM_COUNT11

R

PPM_COUNT10

R

PPM_COUNT9

R

PPM_COUNT8

45

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Table 16. Channel Registers, 3A to 59 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

3C

7

6

5

4

3

2

1

0

7

0

R

N

Y

PPM_COUNT7

PPM_COUNT6

PPM_COUNT5

PPM_COUNT4

PPM_COUNT3

PPM_COUNT2

PPM_COUNT1

PPM_COUNT0

FIR_PD_pd

PPM count LSB

R

3D

RW

FIR_C0_SGN

FIR main cursor polarity

1: negative

6

0

RW

Y

0: positive

5

4

3

2

1

0

7

1

0

1

0

1

0

RW

Y

FIR_C0[5]

FIR_C0[4]

FIR_C0[3]

FIR_C0[2]

FIR_C0[1]

FIR_C0[0]

FIR_PD_TX

FIR_CN1_SGN

FIR main cursor setting

3E

3F

40

FIR pre cursor polarity

1: negative

0: positive

6

1

RW

Y

5

4

3

2

1

0

7

0

1

RW

Y

FIR_CN1[5]

FIR_CN1[4]

FIR_CN1[3]

FIR_CN1[2]

FIR_CN1[1]

FIR_CN1[0]

FIR_SEL_I_MAX

FIR_CP1_SGN

FIR pre cursor setting

FIR post cursor polarity

1: negative

0: positive

6

1

RW

Y

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

RW

Y

FIR_CP1[5]

FIR post cursor setting

FIR_CP1[4]

FIR_CP1[3]

FIR_CP1[2]

FIR_CP1[1]

FIR_CP1[0]

EQ_ARRAY_INDEX_0_BST0[1]

EQ_ARRAY_INDEX_0_BST0[0]

EQ_ARRAY_INDEX_0_BST1[1]

EQ_ARRAY_INDEX_0_BST1[0]

EQ_ARRAY_INDEX_0_BST2[1]

EQ_ARRAY_INDEX_0_BST2[0]

EQ_ARRAY_INDEX_0_BST3[1]

EQ_ARRAY_INDEX_0_BST3[0]

46

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Address

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 16. Channel Registers, 3A to 59 (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

41

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

RW

Y

EQ_ARRAY_INDEX_1_BST0[1]

EQ_ARRAY_INDEX_1_BST0[0]

EQ_ARRAY_INDEX_1_BST1[1]

EQ_ARRAY_INDEX_1_BST1[0]

EQ_ARRAY_INDEX_1_BST2[1]

EQ_ARRAY_INDEX_1_BST2[0]

EQ_ARRAY_INDEX_1_BST3[1]

EQ_ARRAY_INDEX_1_BST3[0]

EQ_ARRAY_INDEX_2_BST0[1]

EQ_ARRAY_INDEX_2_BST0[0]

EQ_ARRAY_INDEX_2_BST1[1]

EQ_ARRAY_INDEX_2_BST1[0]

EQ_ARRAY_INDEX_2_BST2[1]

EQ_ARRAY_INDEX_2_BST2[0]

EQ_ARRAY_INDEX_2_BST3[1]

EQ_ARRAY_INDEX_2_BST3[0]

EQ_ARRAY_INDEX_3_BST0[1]

EQ_ARRAY_INDEX_3_BST0[0]

EQ_ARRAY_INDEX_3_BST1[1]

EQ_ARRAY_INDEX_3_BST1[0]

EQ_ARRAY_INDEX_3_BST2[1]

EQ_ARRAY_INDEX_3_BST2[0]

EQ_ARRAY_INDEX_3_BST3[1]

EQ_ARRAY_INDEX_3_BST3[0]

EQ_ARRAY_INDEX_4_BST0[1]

EQ_ARRAY_INDEX_4_BST0[0]

EQ_ARRAY_INDEX_4_BST1[1]

EQ_ARRAY_INDEX_4_BST1[0]

EQ_ARRAY_INDEX_4_BST2[1]

EQ_ARRAY_INDEX_4_BST2[0]

EQ_ARRAY_INDEX_4_BST3[1]

EQ_ARRAY_INDEX_4_BST3[0]

EQ_ARRAY_INDEX_5_BST0[1]

EQ_ARRAY_INDEX_5_BST0[0]

EQ_ARRAY_INDEX_5_BST1[1]

EQ_ARRAY_INDEX_5_BST1[0]

EQ_ARRAY_INDEX_5_BST2[1]

EQ_ARRAY_INDEX_5_BST2[0]

EQ_ARRAY_INDEX_5_BST3[1]

EQ_ARRAY_INDEX_5_BST3[0]

42

43

44

45

47

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Table 16. Channel Registers, 3A to 59 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

46

47

48

49

4A

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

RW

Y

EQ_ARRAY_INDEX_6_BST0[1]

EQ_ARRAY_INDEX_6_BST0[0]

EQ_ARRAY_INDEX_6_BST1[1]

EQ_ARRAY_INDEX_6_BST1[0]

EQ_ARRAY_INDEX_6_BST2[1]

EQ_ARRAY_INDEX_6_BST2[0]

EQ_ARRAY_INDEX_6_BST3[1]

EQ_ARRAY_INDEX_6_BST3[0]

EQ_ARRAY_INDEX_7_BST0[1]

EQ_ARRAY_INDEX_7_BST0[0]

EQ_ARRAY_INDEX_7_BST1[1]

EQ_ARRAY_INDEX_7_BST1[0]

EQ_ARRAY_INDEX_7_BST2[1]

EQ_ARRAY_INDEX_7_BST2[0]

EQ_ARRAY_INDEX_7_BST3[1]

EQ_ARRAY_INDEX_7_BST3[0]

EQ_ARRAY_INDEX_8_BST0[1]

EQ_ARRAY_INDEX_8_BST0[0]

EQ_ARRAY_INDEX_8_BST1[1]

EQ_ARRAY_INDEX_8_BST1[0]

EQ_ARRAY_INDEX_8_BST2[1]

EQ_ARRAY_INDEX_8_BST2[0]

EQ_ARRAY_INDEX_8_BST3[1]

EQ_ARRAY_INDEX_8_BST3[0]

EQ_ARRAY_INDEX_9_BST0[1]

EQ_ARRAY_INDEX_9_BST0[0]

EQ_ARRAY_INDEX_9_BST1[1]

EQ_ARRAY_INDEX_9_BST1[0]

EQ_ARRAY_INDEX_9_BST2[1]

EQ_ARRAY_INDEX_9_BST2[0]

EQ_ARRAY_INDEX_9_BST3[1]

EQ_ARRAY_INDEX_9_BST3[0]

EQ_ARRAY_INDEX_10_BST0[1]

EQ_ARRAY_INDEX_10_BST0[0]

EQ_ARRAY_INDEX_10_BST1[1]

EQ_ARRAY_INDEX_10_BST1[0]

EQ_ARRAY_INDEX_10_BST2[1]

EQ_ARRAY_INDEX_10_BST2[0]

EQ_ARRAY_INDEX_10_BST3[1]

EQ_ARRAY_INDEX_10_BST3[0]

48

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Address

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 16. Channel Registers, 3A to 59 (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

4B

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

Y

EQ_ARRAY_INDEX_11_BST0[1]

EQ_ARRAY_INDEX_11_BST0[0]

EQ_ARRAY_INDEX_11_BST1[1]

EQ_ARRAY_INDEX_11_BST1[0]

EQ_ARRAY_INDEX_11_BST2[1]

EQ_ARRAY_INDEX_11_BST2[0]

EQ_ARRAY_INDEX_11_BST3[1]

EQ_ARRAY_INDEX_11_BST3[0]

EQ_ARRAY_INDEX_12_BST0[1]

EQ_ARRAY_INDEX_12_BST0[0]

EQ_ARRAY_INDEX_12_BST1[1]

EQ_ARRAY_INDEX_12_BST1[0]

EQ_ARRAY_INDEX_12_BST2[1]

EQ_ARRAY_INDEX_12_BST2[0]

EQ_ARRAY_INDEX_12_BST3[1]

EQ_ARRAY_INDEX_12_BST3[0]

EQ_ARRAY_INDEX_13_BST0[1]

EQ_ARRAY_INDEX_13_BST0[0]

EQ_ARRAY_INDEX_13_BST1[1]

EQ_ARRAY_INDEX_13_BST1[0]

EQ_ARRAY_INDEX_13_BST2[1]

EQ_ARRAY_INDEX_13_BST2[0]

EQ_ARRAY_INDEX_13_BST3[1]

EQ_ARRAY_INDEX_13_BST3[0]

EQ_ARRAY_INDEX_14_BST0[1]

EQ_ARRAY_INDEX_14_BST0[0]

EQ_ARRAY_INDEX_14_BST1[1]

EQ_ARRAY_INDEX_14_BST1[0]

EQ_ARRAY_INDEX_14_BST2[1]

EQ_ARRAY_INDEX_14_BST2[0]

EQ_ARRAY_INDEX_14_BST3[1]

EQ_ARRAY_INDEX_14_BST3[0]

EQ_ARRAY_INDEX_15_BST0[1]

EQ_ARRAY_INDEX_15_BST0[0]

EQ_ARRAY_INDEX_15_BST1[1]

EQ_ARRAY_INDEX_15_BST1[0]

EQ_ARRAY_INDEX_15_BST2[1]

EQ_ARRAY_INDEX_15_BST2[0]

EQ_ARRAY_INDEX_15_BST3[1]

EQ_ARRAY_INDEX_15_BST3[0]

4C

4D

4E

4F

49

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Table 16. Channel Registers, 3A to 59 (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

50

51

52

53

54

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

Y

EQ_ARRAY_INDEX_16_BST0[1]

EQ_ARRAY_INDEX_16_BST0[0]

EQ_ARRAY_INDEX_16_BST1[1]

EQ_ARRAY_INDEX_16_BST1[0]

EQ_ARRAY_INDEX_16_BST2[1]

EQ_ARRAY_INDEX_16_BST2[0]

EQ_ARRAY_INDEX_16_BST3[1]

EQ_ARRAY_INDEX_16_BST3[0]

EQ_ARRAY_INDEX_17_BST0[1]

EQ_ARRAY_INDEX_17_BST0[0]

EQ_ARRAY_INDEX_17_BST1[1]

EQ_ARRAY_INDEX_17_BST1[0]

EQ_ARRAY_INDEX_17_BST2[1]

EQ_ARRAY_INDEX_17_BST2[0]

EQ_ARRAY_INDEX_17_BST3[1]

EQ_ARRAY_INDEX_17_BST3[0]

EQ_ARRAY_INDEX_18_BST0[1]

EQ_ARRAY_INDEX_18_BST0[0]

EQ_ARRAY_INDEX_18_BST1[1]

EQ_ARRAY_INDEX_18_BST1[0]

EQ_ARRAY_INDEX_18_BST2[1]

EQ_ARRAY_INDEX_18_BST2[0]

EQ_ARRAY_INDEX_18_BST3[1]

EQ_ARRAY_INDEX_18_BST3[0]

EQ_ARRAY_INDEX_19_BST0[1]

EQ_ARRAY_INDEX_19_BST0[0]

EQ_ARRAY_INDEX_19_BST1[1]

EQ_ARRAY_INDEX_19_BST1[0]

EQ_ARRAY_INDEX_19_BST2[1]

EQ_ARRAY_INDEX_19_BST2[0]

EQ_ARRAY_INDEX_19_BST3[1]

EQ_ARRAY_INDEX_19_BST3[0]

EQ_ARRAY_INDEX_20_BST0[1]

EQ_ARRAY_INDEX_20_BST0[0]

EQ_ARRAY_INDEX_20_BST1[1]

EQ_ARRAY_INDEX_20_BST1[0]

EQ_ARRAY_INDEX_20_BST2[1]

EQ_ARRAY_INDEX_20_BST2[0]

EQ_ARRAY_INDEX_20_BST3[1]

EQ_ARRAY_INDEX_20_BST3[0]

50

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 16. Channel Registers, 3A to 59 (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

55

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RW

Y

EQ_ARRAY_INDEX_21_BST0[1]

EQ_ARRAY_INDEX_21_BST0[0]

EQ_ARRAY_INDEX_21_BST1[1]

EQ_ARRAY_INDEX_21_BST1[0]

EQ_ARRAY_INDEX_21_BST2[1]

EQ_ARRAY_INDEX_21_BST2[0]

EQ_ARRAY_INDEX_21_BST3[1]

EQ_ARRAY_INDEX_21_BST3[0]

EQ_ARRAY_INDEX_22_BST0[1]

EQ_ARRAY_INDEX_22_BST0[0]

EQ_ARRAY_INDEX_22_BST1[1]

EQ_ARRAY_INDEX_22_BST1[0]

EQ_ARRAY_INDEX_22_BST2[1]

EQ_ARRAY_INDEX_22_BST2[0]

EQ_ARRAY_INDEX_22_BST3[1]

EQ_ARRAY_INDEX_22_BST3[0]

EQ_ARRAY_INDEX_23_BST0[1]

EQ_ARRAY_INDEX_23_BST0[0]

EQ_ARRAY_INDEX_23_BST1[1]

EQ_ARRAY_INDEX_23_BST1[0]

EQ_ARRAY_INDEX_23_BST2[1]

EQ_ARRAY_INDEX_23_BST2[0]

EQ_ARRAY_INDEX_23_BST3[1]

EQ_ARRAY_INDEX_23_BST3[0]

EQ_ARRAY_INDEX_24_BST0[1]

EQ_ARRAY_INDEX_24_BST0[0]

EQ_ARRAY_INDEX_24_BST1[1]

EQ_ARRAY_INDEX_24_BST1[0]

EQ_ARRAY_INDEX_24_BST2[1]

EQ_ARRAY_INDEX_24_BST2[0]

EQ_ARRAY_INDEX_24_BST3[1]

EQ_ARRAY_INDEX_24_BST3[0]

EQ_ARRAY_INDEX_25_BST0[1]

EQ_ARRAY_INDEX_25_BST0[0]

EQ_ARRAY_INDEX_25_BST1[1]

EQ_ARRAY_INDEX_25_BST1[0]

EQ_ARRAY_INDEX_25_BST2[1]

EQ_ARRAY_INDEX_25_BST2[0]

EQ_ARRAY_INDEX_25_BST3[1]

EQ_ARRAY_INDEX_25_BST3[0]

56

57

58

59

51

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Table 17. Channel Registers, 5A to 9B

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

5A

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

Y

EQ_ARRAY_INDEX_26_BST0[1]

EQ_ARRAY_INDEX_26_BST0[0]

EQ_ARRAY_INDEX_26_BST1[1]

EQ_ARRAY_INDEX_26_BST1[0]

EQ_ARRAY_INDEX_26_BST2[1]

EQ_ARRAY_INDEX_26_BST2[0]

EQ_ARRAY_INDEX_26_BST3[1]

EQ_ARRAY_INDEX_26_BST3[0]

EQ_ARRAY_INDEX_27_BST0[1]

EQ_ARRAY_INDEX_27_BST0[0]

EQ_ARRAY_INDEX_27_BST1[1]

EQ_ARRAY_INDEX_27_BST1[0]

EQ_ARRAY_INDEX_27_BST2[1]

EQ_ARRAY_INDEX_27_BST2[0]

EQ_ARRAY_INDEX_27_BST3[1]

EQ_ARRAY_INDEX_27_BST3[0]

EQ_ARRAY_INDEX_28_BST0[1]

EQ_ARRAY_INDEX_28_BST0[0]

EQ_ARRAY_INDEX_28_BST1[1]

EQ_ARRAY_INDEX_28_BST1[0]

EQ_ARRAY_INDEX_28_BST2[1]

EQ_ARRAY_INDEX_28_BST2[0]

EQ_ARRAY_INDEX_28_BST3[1]

EQ_ARRAY_INDEX_28_BST3[0]

EQ_ARRAY_INDEX_29_BST0[1]

EQ_ARRAY_INDEX_29_BST0[0]

EQ_ARRAY_INDEX_29_BST1[1]

EQ_ARRAY_INDEX_29_BST1[0]

EQ_ARRAY_INDEX_29_BST2[1]

EQ_ARRAY_INDEX_29_BST2[0]

EQ_ARRAY_INDEX_29_BST3[1]

EQ_ARRAY_INDEX_29_BST3[0]

EQ_ARRAY_INDEX_30_BST0[1]

EQ_ARRAY_INDEX_30_BST0[0]

EQ_ARRAY_INDEX_30_BST1[1]

EQ_ARRAY_INDEX_30_BST1[0]

EQ_ARRAY_INDEX_30_BST2[1]

EQ_ARRAY_INDEX_30_BST2[0]

EQ_ARRAY_INDEX_30_BST3[1]

EQ_ARRAY_INDEX_30_BST3[0]

5B

5C

5D

5E

52

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

5F

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

1

0

1

0

1

0

1

0

RW

Y

EQ_ARRAY_INDEX_31_BST0[1]

EQ_ARRAY_INDEX_31_BST0[0]

EQ_ARRAY_INDEX_31_BST1[1]

EQ_ARRAY_INDEX_31_BST1[0]

EQ_ARRAY_INDEX_31_BST2[1]

EQ_ARRAY_INDEX_31_BST2[0]

EQ_ARRAY_INDEX_31_BST3[1]

EQ_ARRAY_INDEX_31_BST3[0]

GRP0_OV_CNT7

60

Group 0 count LSB

GRP0_OV_CNT6

GRP0_OV_CNT5

GRP0_OV_CNT4

GRP0_OV_CNT3

GRP0_OV_CNT2

GRP0_OV_CNT1

GRP0_OV_CNT0

61

CNT_DLTA_OV_0

Override enable for group 0

manual data rate selection

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

RW

Y

GRP0_OV_CNT14

GRP0_OV_CNT13

GRP0_OV_CNT12

GRP0_OV_CNT11

GRP0_OV_CNT10

GRP0_OV_CNT9

GRP0_OV_CNT8

GRP1_OV_CNT7

GRP1_OV_CNT6

GRP1_OV_CNT5

GRP1_OV_CNT4

GRP1_OV_CNT3

GRP1_OV_CNT2

GRP1_OV_CNT1

GRP1_OV_CNT0

CNT_DLTA_OV_1

Group 0 count MSB

62

Group 1 count LSB

63

Override enable for group 1

manual data rate selection

6

5

4

3

2

1

0

RW

Y

GRP1_OV_CNT14

GRP1_OV_CNT13

GRP1_OV_CNT12

GRP1_OV_CNT11

GRP1_OV_CNT10

GRP1_OV_CNT9

GRP1_OV_CNT8

Group 1 count MSB

53

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

64

7

6

0

1

RW

Y

N

Y

GRP0_OV_DLTA3

GRP0_OV_DLTA2

GRP0_OV_DLTA1

GRP0_OV_DLTA0

GRP1_OV_DLTA3

GRP1_OV_DLTA2

GRP1_OV_DLTA1

GRP1_OV_DLTA0

RESERVED

Sets the PPM delta tolerance

for the PPM counter lock

check for group 0. Must also

program channel register

0x67[7].

5

4

3

Sets the PPM delta tolerance

for the PPM counter lock

check for group 1. Must also

program channel register

0x67[6].

2

1

0

65

66

67

7:0

7:00

7

RESERVED

GRP0_OV_DLTA4

GRP1_OV_DLTA4

HV_LOCKMON_EN

6

5

1: Normal operation,

HEO/VEO measurements are

used for lock monitoring

4:1

0

RW

N

RESERVED

LOCKMON_FRC_EN

This feature is reserved for

future use.

68

69

6A

7:5

4

0

RW

N

RESERVED

ADPT_FRC_EN

This feature is reserved for

future use.

3

2

0

RW

N

SCN_OBS_CTRL3

SCN_OBS_CTRL2

SCN_OBS_CTRL1

SCN_OBS_CTRL0

RESERVED

This feature is reserved for

future use.

1

0

7:5

4

CTLE_ADPT_FRC_EN

This feature is reserved for

future use.

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

RW

Y

HV_LCKMON_CNT_MS3

HV_LCKMON_CNT_MS2

HV_LCKMON_CNT_MS1

HV_LCKMON_CNT_MS0

VEO_LCK_THRSH3

VEO_LCK_THRSH2

VEO_LCK_THRSH1

VEO_LCK_THRSH0

HEO_LCK_THRSH3

HEO_LCK_THRSH2

HEO_LCK_THRSH1

HEO_LCK_THRSH0

This feature is reserved for

future use.

VEO threshold to meet before

lock is established. The LSB

step size is 4 counts of VEO.

HEO threshold to meet before

lock is established. The LSB

step size is 4 counts of HEO.

54

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

6B

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

1

0

1

0

1

0

RW

Y

FOM_A7

FOM_A6

FOM_A5

FOM_A4

FOM_A3

FOM_A2

FOM_A1

FOM_A0

FOM_B7

FOM_B6

FOM_B5

FOM_B4

FOM_B3

FOM_B2

FOM_B1

FOM_B0

FOM_C7

FOM_C6

FOM_C5

FOM_C4

FOM_C3

FOM_C2

FOM_C1

FOM_C0

EN_NEW_FOM_CTLE

Alternate Figure of Merit

variable A

Max value for this register is

128, do not use the MSB

6C

6D

6E

HEO adjustment for Alternate

FoM, variable B

VEO adjustment for alternate

FoM, variable C

1: CTLE adaption state

machine will use the alternate

FoM

HEO_ALT = (HEO-B)*A*2

VEO_ALT = (VEO-C)*(1-A)*2

The values of A,B,C are set

in channel register 0x6B,

0x6C, and 0x6D. The value of

A is equal to the register

value divided by 128

The Alternate FoM = (HEO-

B)*A*2 + (VEO-C)*(1-A)*2

6

0

RW

Y

EN_NEW_FOM_DFE

1: DFE adaption state

machine will use the alternate

FoM

HEO_ALT = (HEO-B)*A*2

VEO_ALT = (VEO-C)*(1-A)*2

The values of A,B,C are set

in channel register 0x6B,

0x6C, and 0x6D. The value of

A is equal to the register

value divided by 128

The Alternate FoM = (HEO-

B)*A*2 + (VEO-C)*(1-A)*2

5:1

0

RW

N

RESERVED

GET_HV_ST_FRC_EN

This feature is reserved for

future use.

55

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

6F

7

0

RW

Y

EN_LOW_DIVSEL_EQ

1: EQ adaption will be

performed for all divider

settings

0: EQ adaption will only be

performed for dividers of 1

and 2

6:5

4:0

7:4

3

0

1

0

RW

R

Y

N

Y

N

RESERVED

EQ_LB_CNT2

EQ_LB_CNT1

EQ_LB_CNT0

PRBS_INT

70

71

2

CTLE look beyond count for

adaption.

1

0

7

1: Indicates that a PRBS

error has been detected.

Requires the PRBS checker

to be properly configured.

This bit will stay set until it

has been cleared by being

read.

This bit will clear after reading

6

5

0

R

N

K28P5_6466_COND_MET_INT

DFE_POL_1_OBS

This feature is reserved for

future use.

Primary observation point for

DFE tap 1 polarity

4

3

0

R

N

DFE_WT1_OBS4

DFE_WT1_OBS3

DFE_WT1_OBS2

DFE_WT1_OBS1

DFE_WT1_OBS0

RESERVED

Primary observation point for

DFE tap 1 weight

2

R

1

R

0

R

72

73

74

7:5

4

RW

R

DFE_POL_2_OBS

Primary observation point for

DFE tap 2 polarity

3

2

0

R

N

DFE_WT2_OBS3

DFE_WT2_OBS2

DFE_WT2_OBS1

DFE_WT2_OBS0

RESERVED

Primary observation point for

DFE tap 2 weight

1

R

0

R

7:5

4

RW

R

DFE_POL_3_OBS

Primary observation point for

DFE tap 3 polarity

3

2

0

R

N

DFE_WT3_OBS3

DFE_WT3_OBS2

DFE_WT3_OBS1

DFE_WT3_OBS0

RESERVED

Primary observation point for

DFE tap 3 weight

1

R

0

R

7:5

4

RW

R

DFE_POL_4_OBS

Primary observation point for

DFE tap 4 polarity

3

2

1

0

R

N

DFE_WT4_OBS3

DFE_WT4_OBS2

DFE_WT4_OBS1

DFE_WT4_OBS0

Primary observation point for

DFE tap 4 weight

56

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

75

7:5

4

0

RW

R

N

RESERVED

DFE_POL_5_OBS

Primary observation point for

DFE tap 5 polarity

3

2

1

0

7

6

5

4

3

2

1

0

7

0

1

0

1

0

R

N

Y

N

DFE_WT5_OBS3

Primary observation point for

DFE tap 5 weight

R

DFE_WT5_OBS2

R

DFE_WT5_OBS1

R

DFE_WT5_OBS0

76

RW

POST_LOCK_VEO_THR3

POST_LOCK_VEO_THR2

POST_LOCK_VEO_THR1

POST_LOCK_VEO_THR0

POST_LOCK_HEO_THR3

POST_LOCK_HEO_THR2

POST_LOCK_HEO_THR1

POST_LOCK_HEO_THR0

PRBS_GEN_POL_EN

VEO threshold after lock is

established. The LSB step

size is 4 counts of VEO.

HEO threshold after lock is

established. The LSB step

size is 4 counts of HEO.

77

This feature is reserved for

future use. To invert the

polarity of the PRBS data use

the normal method of

inverting of the sign bits for

the FIR taps.

6

5

4

3

2

1

0

1

0

1

0

RW

Y

CDR_CAP_DAC_START1[5]

CDR_CAP_DAC_START0[5]

POST_LOCK_SBTTHR4

POST_LOCK_SBTTHR3

POST_LOCK_SBTTHR2

POST_LOCK_SBTTHR1

POST_LOCK_SBTTHR0

This feature is reserved for

future use

SBT threshold after lock is

established.

57

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

7

Mode

EEPROM

Field Name

Description

78

0

R

N

UNCORR_ERR_INT

PRBS_LOCKUP_STATUS

SD_STATUS

This feature is reserved for

future use.

6

This feature is reserved for

future use.

5

Primary observation point for

signal detect status

4

CDR_LOCK_STATUS

CDR_LOCK_INT

Primary observation point for

CDR lock status

3

Requires that channel

register 0x79[1] be set.

1: Indicates CDR has

achieved lock, lock goes from

LOW to HIGH. This bit is

cleared after reading. This bit

will stay set until it has been

cleared by reading.

2

0

R

N

SD_INT

Requires that channel

register 0x79[0] be set.

1: Indicates signal detect

status has changed. This will

trigger when signal detect

goes from LOW to HIGH or

HIGH to LOW. This bit is

cleared after reading. This bit

will stay set until it has been

cleared by reading.

1

0

R

N

EOM_VRANGE_LIMIT_ERROR

HEO_VEO_INT

This feature is reserved for

future use.

Requires that channel

register 0x36[6] be set.

1: Indicates that HEO/VEO

dropped below the limits set

in channel register 0x76 This

bit is cleared after reading.

This bit will stay set until it

has been cleared by reading.

58

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

79

7

6

5

0

R

N

PWDN_SD

This feature is reserved for

future use.

PRBS_CHKR_EN

PRBS_GEN_EN

1: Enable the PRBS checker.

0: Disable the PRBS checker

1: Enable the pattern

generator

0: Disable the pattern

generator

4

3

1

0

RW

R

N

Y

PRBS_LCKUP_EXIT_EN

EN_K285

This feature is reserved for

future use.

1: Enables K28.5 checking as

a requirement for lock

0: Normal operation

2

1

0

R

Y

N

CAL_OVERRIDE

This feature is reserved for

future use.

CDR_LOCK_INT_EN

1: Enable CDR lock interrupt,

observable in channel

register 0x78[3]

0: Disable CDR lock interrupt

0

R

N

SD_INT_EN

1: Enable signal detect

interrupt, observable in

channel register 0x78[3]

0: Disable signal detect

interrupt

7A

7B

7C

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

RW

W

N

SEL_A7

This feature is reserved for

future use.

SEL_A6

SEL_A5

SEL_A4

SEL_A3

SEL_A2

SEL_A1

SEL_A0

SEL_D7

This feature is reserved for

future use.

SEL_D6

SEL_D5

SEL_D4

SEL_D3

SEL_D2

SEL_D1

SEL_D0

PRBS_FIXED7

PRBS_FIXED6

PRBS_FIXED5

PRBS_FIXED4

PRBS_FIXED3

PRBS_FIXED2

PRBS_FIXED1

PRBS_FIXED0

Pattern generator user

defined pattern LSB. MSB

located at channel register

0x97.

W

59

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

7D

7E

7F

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

1

0

1

0

1

0

1

0

RW

Y

N

CONT_ADAPT_HEO_CHNG_THRS3 Limit for HEO change before

triggering a DFE adaption

while continous DFE adaption

CONT_ADAPT_HEO_CHNG_THRS2

CONT_ADAPT_HEO_CHNG_THRS1

CONT_ADAPT_HEO_CHNG_THRS0

is enabled.

CONT_ADAPT_VEO_CHNG_THRS3 Limit for VEO change before

triggering a DFE adaption

while continous DFE adaption

CONT_ADAPT_VEO_CHNG_THRS2

CONT_ADAPT_VEO_CHNG_THRS1

CONT_ADAPT_VEO_CHNG_THRS0

CONT_ADPT_TAP_INCR3

is enabled.

Limit of allowable DFE tap

weight change from the

previous base point

CONT_ADPT_TAP_INCR2

CONT_ADPT_TAP_INCR1

CONT_ADPT_TAP_INCR0

CONT_ADPT_FOM_CHNG_THRS3

CONT_ADPT_FOM_CHNG_THRS2

CONT_ADPT_FOM_CHNG_THRS1

CONT_ADPT_FOM_CHNG_THRS0

EN_OBS_ALT_FOM

This feature is reserved for

future use.

1: Allows for alternate FoM

calculation to be shown in

channel registers 0x27, 0x28

and 0x29 instead of HEO and

VEO

6

5

0

1

RW

N

Y

RESERVED

DIS_HV_CHK_FOR_CONT_ADAPT

1: Ignore HEO/VEO lock

condition checks during

continous adaption. Normal

operation for continous DFE

adaption

4

3

1

RW

Y

EN_DFE_CONT_ADAPT

CONT_ADPT_CMP_BOTH

1: Continous DFE adaption is

enabled

0: DFE adapts only during

lock and then freezes

1: If continous DFE adaption

is enabled, a DFE adaption

will trigger if either HEO or

VEO degrades

2

1

0

1

0

RW

R

Y

N

CONT_ADPT_COUNT2

CONT_ADPT_COUNT1

CONT_ADPT_COUNT0

HEO_CENTER7

HEO_CENTER6

HEO_CENTER5

HEO_CENTER4

HEO_CENTER3

HEO_CENTER2

HEO_CENTER1

HEO_CENTER0

RESERVED

Limit for number of weights

the DFE can look ahead in

continous adaption

0

80

7

This feature is reserved for

future use.

6

R

5

R

4

R

3

R

2

R

1

R

0

R

81

7:0

R

60

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ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

82

7

0

RW

N

FREEZE_PRBS_CNTR

1: Freeze the PRBS bit and

error counts to allow for read

back

0: Normal operation. Both bit

and error counters are

allowed to increment if the

PRBS checker is properly

configured.

6

0

RW

N

RST_PRBS_CNTS

1: Reset PRBS bit and error

counts

0: Normal operation, counters

are released from reset

5

4

0

RW

N

RESERVED

PRBS_PATT_OV

1: Override PRBS pattern

auto detection. Forces the

pattern checker to only lock

onto the pattern defined in

bits 3 and 2 of this register.

0: Normal operation, pattern

checker will automatically

detect the PRBS pattern

3

2

0

RW

N

PRBS_PATT1

PRBS_PATT0

Usage is enabled with

channel reg 0x82[4]

Select PRBS pattern to be

checked 00: PRBS-7

01: PRBS-9

10: PRBS-15

11: PRBS-31

1

0

RW

N

PRBS_POL_OV

1: Override PRBS pattern

auto polarity detection.

Forces the pattern checker to

only lock onto the polarity

defined in bit 0 of this

register.

0: Normal operation, pattern

checker will automatically

detect the PRBS pattern

polarity

0

RW

N

PRBS_POL

Usage is enabled with

channel register 0x82[1]

0: Forced polarity = true

1 - Forced polarity = inverted

83

84

7:3

2

0

R

N

RESERVED

PRBS_ERR_CNT10

PRBS_ERR_CNT9

PRBS_ERR_CNT8

PRBS_ERR_CNT7

PRBS_ERR_CNT6

PRBS_ERR_CNT5

PRBS_ERR_CNT4

PRBS_ERR_CNT3

PRBS_ERR_CNT2

PRBS_ERR_CNT1

PRBS_ERR_CNT0

PRBS error count MSB

PRBS error count LSB

1

0

7

6

5

4

3

2

1

0

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

Mode

EEPROM

Field Name

Description

85

86

87

88

89

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

R

N

RESERVED

PRBS_DATA_CNT46

PRBS_DATA_CNT45

PRBS_DATA_CNT44

PRBS_DATA_CNT43

PRBS_DATA_CNT42

PRBS_DATA_CNT41

PRBS_DATA_CNT40

PRBS_DATA_CNT39

PRBS_DATA_CNT38

PRBS_DATA_CNT37

PRBS_DATA_CNT36

PRBS_DATA_CNT35

PRBS_DATA_CNT34

PRBS_DATA_CNT33

PRBS_DATA_CNT32

PRBS_DATA_CNT31

PRBS_DATA_CNT30

PRBS_DATA_CNT29

PRBS_DATA_CNT28

PRBS_DATA_CNT27

PRBS_DATA_CNT26

PRBS_DATA_CNT25

PRBS_DATA_CNT24

PRBS_DATA_CNT23

PRBS_DATA_CNT22

PRBS_DATA_CNT21

PRBS_DATA_CNT20

PRBS_DATA_CNT19

PRBS_DATA_CNT18

PRBS_DATA_CNT17

PRBS_DATA_CNT16

PRBS_DATA_CNT15

PRBS_DATA_CNT14

PRBS_DATA_CNT13

PRBS_DATA_CNT12

PRBS_DATA_CNT11

PRBS_DATA_CNT10

PRBS_DATA_CNT9

PRBS_DATA_CNT8

PRBS bit count, 47-bit word

from channel registers 0x85

to 0x8A

PRBS bit count, 47-bit word

from channel registers 0x85

to 0x8A

PRBS bit count, 47-bit word

from channel registers 0x85

to 0x8A

PRBS bit count, 47-bit word

from channel registers 0x85

to 0x8A

PRBS bit count, 47-bit word

from channel registers 0x85

to 0x8A

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

8A

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

0

R

N

Y

PRBS_DATA_CNT7

PRBS bit count, 47-bit word

from channel registers 0x85

to 0x8A

R

PRBS_DATA_CNT6

R

PRBS_DATA_CNT5

R

PRBS_DATA_CNT4

R

PRBS_DATA_CNT3

R

PRBS_DATA_CNT2

R

PRBS_DATA_CNT1

R

PRBS_DATA_CNT0

8B

8C

8D

RW

UNCORR_ERR_PATT15

UNCORR_ERR_PATT14

UNCORR_ERR_PATT13

UNCORR_ERR_PATT12

UNCORR_ERR_PATT11

UNCORR_ERR_PATT10

UNCORR_ERR_PATT9

UNCORR_ERR_PATT8

UNCORR_ERR_PATT7

UNCORR_ERR_PATT6

UNCORR_ERR_PATT5

UNCORR_ERR_PATT4

UNCORR_ERR_PATT3

UNCORR_ERR_PATT2

UNCORR_ERR_PATT1

UNCORR_ERR_PATT0

RESERVED

This feature is reserved for

future use.

This feature is reserved for

future use.

EQ_EN_HR_MODE

Used with bit 2 to set Full

rate, Mid rate or Half rate EQ

bandwidth. Bit 6 is MSB. Bit 2

is LSB.

00: Full rate

01: Mid rate

11: Half rate

5

4

3

2

0

1

RW

Y

PFD_EN_HR_MODE

DIV_EN_HR_MODE

EQ_EN_MR_MODE

Used with bit 6 to set Full

rate, Mid rate or Half rate EQ

bandwidth. Bit 6 is MSB. Bit 2

is LSB.

00: Full rate

01: Mid rate

10: Alternate mid rate

11: Half rate

1

0

1

0

RW

Y

SD_DC_EN

This feature is reserved for

future use.

EQ_SEL_LOOP_OUT

This feature is reserved for

future use.

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

7

Mode

RW

EEPROM

Field Name

Description

8E

0

N

SD_CAL_RESET_LV

SEL_DIV48_LV

This feature is reserved for

future use.

6

0

RW

Output reference clock

selection

1: Selects reference clock

from in channel digital

0: Selects reference clock

from adjacent channel output

5

0

RW

Y

EN_CLK_LOOPTHRU_LV

1: Enable the reference clock

loop through mux

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

RW

R

Y

N

FIR_SEL_EDGE2

FIR_SEL_EDGE1

FIR_SEL_EDGE0

DFE_SEL_GAIN1

DFE_SEL_GAIN0

EQ_BST_TO_ANA7

EQ_BST_TO_ANA6

EQ_BST_TO_ANA5

EQ_BST_TO_ANA4

EQ_BST_TO_ANA3

EQ_BST_TO_ANA2

EQ_BST_TO_ANA1

EQ_BST_TO_ANA0

Edge rate (slew rate) control

VGA gain control

8F

Primary observation point for

the EQ boost setting.

R

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

90

7

6

5

4

0

RW

Y

K28P5_COMPR_PERIOD3

K28P5_COMPR_PERIOD2

K28P5_COMPR_PERIOD1

K28P5_COMPR_PERIOD0

Used when one of these

modes are enabled, k28.5

lock check(channel register

0x79[5]), 64b66b lock

check(channel register

0x36[3]), k28.5 or 64b66b

Interrupt(register 0x36[0])

k28.5_compr_period defines

period within which k28.5 is

expected to be seen.

Also used for expected

frequency of 64B66B

transitions

The number of bits to check

is equal to

2^(min_k28.5_reqd[11:0]) *

32

Enable K28.5 checking with

reg_79[3]

3

2

1

0

RW

Y

MIN_K28P5_REQD11

MIN_K28P5_REQD10

MIN_K28P5_REQD9

MIN_K28P5_REQD8

Used when one of these

modes are enabled, k28.5

lock check(channel register

0x79[5]), 64b66b lock

check(channel register

0x36[3]), k28.5 or 64b66b

Interrupt(register 0x36[0])

Channel register 0x90[3:0]

together with channel register

0x91[7:0] defines number of

k28.5+ patterns that need to

be detected in the number of

bits checked(set by channel

register 0x90[7:4]

Also used for expected

frequency of 64B66B

transitions

Enable k28.5 checking with

channel register 0x79[3]

91

7

6

0

RW

Y

N

MIN_K28P5_REQD7

MIN_K28P5_REQD6

MIN_K28P5_REQD5

MIN_K28P5_REQD4

MIN_K28P5_REQD3

MIN_K28P5_REQD2

MIN_K28P5_REQD1

MIN_K28P5_REQD0

RESERVED

See channel register

0x90[3:0]

5

4

3

2

1

0

92

93

7:0

RESERVED

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

7

Mode

RW

EEPROM

Field Name

DFE_EN

Description

94

0

N

This feature is reserved for

future use.

6

DFE_DIS

This feature is reserved for

future use.

5

EOM_EN

This feature is reserved for

future use.

4

EOM_DIS

DRV_EN

This feature is reserved for

future use.

3

This feature is reserved for

future use.

2

DRV_DIS

This feature is reserved for

future use.

1

PEAK_DET_EN

PEAK_DET_DIS

SD_EN

This feature is reserved for

future use.

0

This feature is reserved for

future use.

95

7

This feature is reserved for

future use.

6

SD_DIS

This feature is reserved for

future use.

5

DC_OFF_EN

DC_OFF_DIS

EQ_EN

This feature is reserved for

future use.

4

This feature is reserved for

future use.

3

This feature is reserved for

future use.

2

EQ_DIS

This feature is reserved for

future use.

1

COMP_EN

COMP_DIS

This feature is reserved for

future use.

0

This feature is reserved for

future use.

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Bits

Mode

EEPROM

Field Name

Description

(Hex)

96

7

6

5

0

RW

N

Y

RESERVED

XPNT_SLAVE

Always configure this bit to be

master. Master control is

assigned by mux selection

1: Channel is a slave

0: Channel is a master

(recommended)

4

0

RW

Y

XPNT_EN

1: Cross Point is enabled

0: Cross Point is disabled

3

2

0

1

RW

Y

EQ_BUFFER_EN[1]

EQ_BUFFER_EN[0]

Enable EQ output buffers:

00: Neither buffer in ON (not

recommended)

01: Only local buffer is ON

10: Only multi-drive buffer is

ON

11: Both buffers are ON

1

0

RW

Y

EQ_DATA_MUX_IN[1]

EQ_DATA_MUX_IN[0]

Select EQ data and signal

detect bus from one channel:

00: channel A

01: Channel B

10: Channel C

11: Channel D

Channel A = 0,4,8,12

Channel B = 1,5,9,13

Channel C = 2,6,10,14

Channel D = 3,7,11,15

97

7

6

0

W

N

Y

PRBS_FIXED15

PRBS_FIXED14

PRBS_FIXED13

PRBS_FIXED12

PRBS_FIXED11

PRBS_FIXED10

PRBS_FIXED9

PRBS_FIXED8

RESERVED

Pattern generator user

defined pattern MSB. LSB

located at channel register

0x7C.

0

5

0

W

4

0

W

3

0

W

2

0

W

1

0

W

0

W

98

99

7:6

5:0

7

0

RW

0x0C0

RESERVED

0

1

DIVSEL_START1_OV

DIVSEL_STOP1_OV

DIVSEL_START2

DIVSEL_START1

DIVSEL_START0

DIVSEL_STOP2

DIVSEL_STOP1

DIVSEL_STOP0

This feature is reserved for

future use.

6

5

This feature is reserved for

future use.

4

3

2

This feature is reserved for

future use.

1

0

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Table 17. Channel Registers, 5A to 9B (continued)

Default

Value

(Hex)

Address

(Hex)

Bits

7

Mode

RW

EEPROM

Field Name

Description

9A

0

Y

DIVSEL_START0_OV

DIVSEL_STOP0_OV

This feature is reserved for

future use.

6

0

RW

This feature is reserved for

future use.

5

4

1

0

RW

Y

N

Y

DIVSEL_START0[2]

DIVSEL_START0[1]

DIVSEL_START0[0]

DIVSEL_STOP0[2]

DIVSEL_STOP0[1]

DIVSEL_STOP0[0]

RESERVED

This feature is reserved for

future use.

3

2

This feature is reserved for

future use.

1

0

9B

7:3

2

RESERVED

1

EQ_CTRL_MUX_IN[1]

EQ_CTRL_MUX_IN[0]

Select EQ control bus from

one channel:

00: channel A

0

01: Channel B

10: Channel C

11: Channel D

Channel A = 0,4,8,12

Channel B = 1,5,9,13

Channel C = 2,6,10,14

Channel D = 3,7,11,15

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS125DF1610 is a 16 channel retimer that support many different data rates and application spaces. The

following sections describe the typical use cases and common implementation practices.

图 5. DS125DF1610 Example Application

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8.2 Typical Applications

图 5 shows a typical implementation for the DS125DF1610 in a back plane application. The DS125DF1610 can

also be used for front port applications. The DS125DF1610 supports data rates for CPRI, Infiniband, Ethernet,

Interlaken and other custom data rates.

图 6 and 图 7 show a typical application of the DS125DF1610. In these diagrams, the DS125DF1610 is

configured for SMBus slave mode programming. Power is supplied to the device through a single 2.5 V plane.

The power supply filtering shown in these diagrams may need to be adjusted to accommodate additional system

power noise. The SMBus and LVCMOS signals in this example use 2.5 V logic. A differential reference clock for

the digital block is applied to the device through 1 µF AC-coupling capacitors. In this example, the high speed

signals are connected to the device in groups of four to allow for the system designer to make use of the 4x4

cross point switches. Note that since the device contains AC-coupling capacitors on the high speed receiver

inputs, the signals can be directly connected to the device. The transmitter outputs of this device should connect

to AC-coupling capacitors placed near the receive inputs of the receiving ASIC.

2.5V

TMS_IO

TDO_IO

TRST_IO

TCK_IO

TDI_IO

VDD

C₂

C₁

C₂

GND

5{12ꢀ5C1610

tower and /onꢁrol

tin /onnecꢁions

2.5V

R₂

R₃

R₁

ADDR0

ADDR1

INTERR_IO

Populate as needed to set

desired SMBus address

R₂

R₃

ALL_DONE

RESET_IO

READ_EN

EN_SMB

R₂

C₃

REF_CLK_P

REF_CLK_N

2.5V

CLK_MON_P

CLK_MON_N

R₁

SDA_IO

SCL_IO

R1 = 4.7 kW

R₂= 1 kW

R₃= 1 kW or 20 kW

C₁= 22 mF

C₂= 0.1 mF

C₃= 1 mF

图 6. Typical Connection Diagram: Power and Control Pins

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Typical Applications (接下页)

5{12ꢀ5C1610 Iigh

{peed /onnections

RX_0A

RX_0B

TX_0A

TX_0B

Quad 0

Cross Point Switch

RX_1A

RX_1B

TX_1A

TX_1B

Quad 1

Cross Point Switch

RX_2A

RX_2B

TX_2A

TX_2B

RX_3A

RX_3B

TX_3A

TX_3B

RX_4A

RX_4B

TX_4A

TX_4B

Quad 2

Cross Point Switch

RX_5A

RX_5B

TX_5A

TX_5B

RX_6A

RX_6B

TX_6A

TX_6B

Quad 3

Cross Point Switch

RX_7A

RX_7B

TX_7A

TX_7B

图 7. Typical Connection Diagram: High Speed Signals

8.2.1 Design Requirements

This section lists some critical areas for high speed printed circuit board design consideration and study.

•

Utilize 100Ω differential impedance traces.

Back-drill connector vias and signal vias to minimize stub length.

Use reference plane vias to ensure a low inductance path for the return current.

Place AC-Coupling capacitors for the transmitter links near the receiver for that channel.

The maximum body size for AC-coupling capacitors is 0402.

8.2.2 Detailed Design Procedure

To begin the design process determine the following:

•

Maximum power draw for PCB regulator selection. For this calculation use the CDR locking power number

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Typical Applications (接下页)

specified in the datasheet, multiplied by the number of channels allowed to lock at a time by the lock

sequencer. Then add the static power. The lock sequencer defaults to 8 channels allowed to lock at a time.

To ease the peak power draw, the lock sequencer can be set to allow for only 1 channel to lock at a time.

The lock time for each channel is typically very short, so this power calculation should not be used for the

thermal simulations of the PCB.

•

Maximum operational power for thermal calculations. For this calculation use the CDR locked power numbers

specified in the datasheet, multiplied by the number of channels that will be active in the device. Then add the

static power. If it is desired to use the Pattern Generator or PRBS checker, add these powers per channel.

Note that a channel's PRBS Checker and Pattern Generator cannot both be active at the same time. So the

total count of active PRBS Checkers and Pattern Generators should not be more than 16 per device.

•

Select a reference clock frequency and routing scheme.

Plan out channel connectivity. Be sure to note any desired cross point routing in the board schematics.

Ensure that each device has a unique SMBus address if the control bus is shared with other devices or

components.

•

Use the IBIS-AMI model for simple channel simulations before PCB layout is complete.

Compare schematic against the typical connection diagrams in the datasheet, 图 6 and 图 7

8.2.3 Typical Application Performance Plots

图 9. FIR Transmit Equalization Example, 10.3125Gbps

图 8. Typical Transmit Eye Diagram, 10.3125 Gbps

图 8 shows a typical output eye diagram for the DS125DF1610 operating at 10.3125 Gbps with the 1V_PPV_OD

settings. All other device settings are left at default.

图 9 shows an example of FIR transmit equalization for a DS125DF1610 operating at 10.3125 Gbps. In this

example, the high speed output is configured for 1V_PPV_OD. The FIR filter is then further adjusted such that the

pre cursor tap is set to -5, the main cursor tap is set to +42, and the post cursor tap is set to -10. An 8T pattern is

used to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.

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8.3 Initialization Setup

The typical device initialization sequence for a DS125DF1610 includes the following:

•

Shared Register Configurations:

–

Reference Clock Divider Setting (default is 25MHz)

Lock Sequencer Configuration (default is 8 channels allowed lock concurrently)

•

Channel Register Configurations repeated for all desired channels:

–

CDR reset

Adapt Mode Configuration

Data rate selection

Output driver VOD and FIR configuration

Optional Continuous DFE adaption configuration

Optional Interrupt enable

Optional Reference clock loop through enable

Optional Cross point switch configuration

CDR reset release

8.3.1 Data Rate Selection (Rate/Sub-Rate Table)

The data rates for the DS125DF1610 must be known and programmed into each desired channel. The

DS125DF1610 will only lock to programmed data rates and the programmed divider settings. For ease of use

several common data rates have been preprogrammed into the DS125DF1610 along with the associated sub-

rates for those various standards. These rate/sub-rate settings comprise the Rate/Sub-rate 表 18. Note that each

channel operates independently, so different channels in the DS125DF1610 can operate at different data rates at

the same time.

The Rate/Sub-rate 表 18 for the DS125DF1610 shown below includes all of the available preprogrammed data

rates and associated divider groupings.

表 18. Rate/Sub-Rate Options

CHANNEL REGISTER

0x2F[7:4] SETTING

FIRST GROUP DIVIDER

SETTINGS

SECOND GROUP

DIVIDER SETTINGS

STANDARD

DATA RATES (Gbps)

0x6

0x7

0x8

0x9

0xA

0xB

Custom

Interlaken

CPRI 1

11.5

12.5, 6.25, 3.125

9.8304, 4.9152, 2.4576

6.144, 3.072

1

1, 2, 4

2, 4

1, 2, 4

2, 4

CPRI 2

Infiniband

Ethernet

10, 5, 2.5

1, 2, 4

8

1, 2, 4

1

10.3125, 1.25

8.3.2 Data Rate Selection (Manual Programming)

The DS125DF1610 is capable of supporting any data rate within the specified range of 9.8 Gbps to 12.5 Gbps

including the divide by 2, 4, and 8 sub-rates of this range. If it is desired to operate the DS125DF1610 at a data

rate or data rate and sub-rate combination that is not available in the Rate/Sub-rate 表 18, then these desired

data rates can be programmed into the device manually.

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The following procedure describes how to calculate and manually program data rates into the DS125DF1610.

1. Select a divider grouping from the Rate/Sub-rate Table and program that value to channel register 0x2F.

When manually programming the data rate into the device, other rate/sub-rate values may be used to allow

for different divider and group combinations. A list of all preprogrammed divider, group combinations is

shown in the 表 19 below.

表 19. Divider Options

CHANNEL REGISTER

0x2F[7:4] SETTING

FIRST GROUP DIVIDER SETTINGS

SECOND GROUP DIVIDER SETTINGS

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

2, 4

1

2, 4

1

1, 2, 4

1

1, 2, 4

1

1, 2, 4

2, 4

1, 2, 4

8

1, 2, 4

2, 4

1, 2, 4

1

8

1

1, 2, 4

1

1, 2

2. Calculate the first group settings:

表 20. Manual Data Rate Configuration -- 1^STGroup Instructions

PARAMETER

VALUE/EQUATION

F0 = 25e6

COMMENT

Reference Clock

Internally the reference clock always operates at 25 MHz

F1 is the frequency of the VC0 which is equal to the

desired data rate. If the desired data rate uses dividers, be

sure to multiply the data rate by the divide setting to get

the correct VCO frequency

Desired VCO Frequency

F1

Number of Reference Clocks

VCO Freq ÷ 32

N = 1024

F2 = F1 ÷ 32

F3 = F2 x N ÷ F0

Counts of VCO Freq ÷ 32 required

Round F3 to the nearest integer value. Convert this value

to binary. Program the upper 8 bits to ch register 0x61 and

the lower 8 bits to ch register 0x60. Be sure to set channel

register 0x61[7] to 1 to enable the override function for

manual programming.

Counts of VCO Freq ÷ 32 required rounded F4

PPM error due to rounding

Required PPM tolerance

Err = 1e6 x (F4 – F3) ÷ F3

T

Enter the desired PPM tolerance

VCO Freq ÷ 32 +PPM tolerance

F5 = (1+ T÷1e6) * F2

Rounded Counts of the VCO Freq ÷ 32

+PPM tolerance required

F6 = F5 x N ÷ F0

Round F6 to the nearest integer value

Convert this value to binary. Program the most significant

bit channel register 0x67[7] and the rest of the bits to

channel register 0x64[7:4]

PPM Counts delta

F7 = F6 – F3

74

DS125DF1610

www.ti.com.cn

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

3. Calculate the second group settings:

表 21. Manual Data Rate Configuration -- 2^ndGroup Instructions

PARAMETER

VALUE/EQUATION

F0 = 25e6

COMMENT

Reference Clock

Internally the reference clock always operates at 25 MHz

F1 is the frequency of the VC0 which is equal to the

desired data rate. If the desired data rate uses dividers, be

sure to multiply the data rate by the divide setting to get

the correct VCO frequency

Desired VCO Frequency

F1

Number of Reference Clocks

VCO Freq ÷ 32

N = 1024

F2 = F1 ÷ 32

F3 = F2 x N ÷ F0

Counts of VCO Freq ÷ 32 required

Round F3 to the nearest integer value. Convert this value

to binary. Program the upper 8 bits to ch register 0x63 and

the lower 8 bits to ch register 0x62. Be sure to set channel

register 0x63[7] to 1 to enable the override function for

manual programming.

Counts of VCO Freq ÷ 32 required rounded F4

PPM error due to rounding

Required PPM tolerance

Err = 1e6 x (F4 – F3) ÷ F3

T

Enter the desired PPM tolerance

VCO Freq ÷ 32 +PPM tolerance

F5 = (1+ T÷1e6) * F2

Rounded Counts of the VCO Freq ÷ 32

+PPM tolerance required

F6 = F5 x N ÷ F0

Round F6 to the nearest integer value

Convert this value to binary. Program the most significant

bit channel register 0x67[6] and the rest of the bits to

channel register 0x64[3:0]

PPM Counts delta

F7 = F6 – F3

An example for setting group 0 and group 1 to 11.3 Gbps is shown in the 表 22 below.

表 22. Manual Data Rate Configuration Example

CHANNEL REGISTER (HEX)

VALUE

0x80

0x60

0x61

0xB8

0x80

0x62

0x63

0xB8

0xEE

2'b00

0x64

0x67[7:6]

9 Power Supply Recommendations

9.1 Power Supply Filtering

The power pins on the DS125DF1610 are all internally shorted together on the BGA substrate. This allows board

designers to more easily distribute the bypass capacitors for power supply filtering.

Power supply filtering typically consists of a bulk 22 µF capacitor with an array of 0.1 µF capacitors all placed

near the device. Additional bypass capacitors or capacitors of different values may be required depending on

system conditions. An example array of power supply filtering capacitors is shown in 图 6.

10 Layout

10.1 Layout Guidelines

The high speed inputs and outputs have been optimized to work with interconnects using a controlled differential

impedance of 100Ω. Vias should be used sparingly and must be placed symmetrically for each side of a given

differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for

the return currents as well. Route the differential signals away from other signals and noise sources on the

printed circuit board.

75

DS125DF1610

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

www.ti.com.cn

10.2 Layout Example

Common BGA routing techniques such as trace necking, using blind vias and buried vias, are OK as long as the

differential traces are balanced in their routing and the signals see few impedance changes. For example,

necking lengths should be the same for the differential traces and implemented symmetrically for both traces. 图

10 shows general Dos and Don'ts for high speed layout, such as differential trace gathering, differential trace

necking, and high speed signal and return via implementation.

Do:

Don‘t

图 10. Layout Guidelines

76

DS125DF1610

www.ti.com.cn

ZHCSCD5B –APRIL 2014–REVISED JANUARY 2017

11 器件和文档支持

11.1 器件支持

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产

品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。

11.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，

我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。

77

PACKAGE OUTLINE

ABB0196A

FCBGA - 2.94 mm max height

SCALE 0.900

BALL GRID ARRAY

15.2

14.9

A

B

BALL A1 CORNER

PIN 1 ID

(OPTIONAL)

(

11)

15.2

14.9

(

9)

C

2.94 MAX

SEATING PLANE

0.2 C

0.6

BALL TYP

TYP

0.4

13 TYP

(1) TYP

SYMM

1

TYP

P

N

M

L

K

J

SYMM

13

H

G

F

TYP

E

D

C

B

A

0.7

0.5

C A B

196X

0.25

0.1

C

1

2

3

4

5

6

7

8

9 10

11 12 13 14

1

TYP

4218164/A 05/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Pb-Free die bump and solder ball.

www.ti.com

EXAMPLE BOARD LAYOUT

ABB0196A

FCBGA - 2.94 mm max height

BALL GRID ARRAY

(1) TYP

1

2

3

4

5

6

7

8

9

10 11 12 13

14

A

B

C

(1) TYP

196X ( 0.45)

D

E

F

G

H

SYMM

J

K

L

M

N

P

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SNOWN

SCALE:6X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.45)

METAL

EXPOSED METAL

(

0.45)

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4218164/A 05/2017

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com

EXAMPLE STENCIL DESIGN

ABB0196A

FCBGA - 2.94 mm max height

BALL GRID ARRAY

(1) TYP

1

2

3

4

5

6

7

8

9

10 11 12 13

14

A

B

C

(1) TYP

D

E

F

196X ( 0.45)

SYMM

G

H

J

K

L

M

N

P

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:6X

4218164/A 05/2017

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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型号：	DS125DF1610
厂家：	TEXAS INSTRUMENTS
描述：	9.8 至 12.5Gbps 16 通道重定时器
文件：	总85页 (文件大小：1932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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