DS15BR401 [TI]
具有预加重功能的 4 通道 LVDS 缓冲器/中继器;
| 型号： | DS15BR401 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有预加重功能的 4 通道 LVDS 缓冲器/中继器 中继器 |
| 文件： | 总23页 (文件大小：624K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS15BR400, DS15BR401
www.ti.com
SNLS224G –AUGUST 2006–REVISED APRIL 2013
DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis
Check for Samples: DS15BR400, DS15BR401
1
FEATURES
DESCRIPTION
The DS15BR400/DS15BR401 are four channel LVDS
buffer/repeaters capable of data rates of up to 2
Gbps. High speed data paths and flow-through pinout
minimize internal device jitter and simplify board
layout, while pre-emphasis overcomes ISI jitter
effects from lossy backplanes and cables. The
differential inputs interface to LVDS, and Bus LVDS
signals such as those on TI's 10-, 16-, and 18- bit
Bus LVDS SerDes, as well as CML and LVPECL.
The differential inputs and outputs of the DS15BR400
are internally terminated with 100Ω resistors to
improve performance and minimize board space. The
DS15BR401 does not have input termination
resistors. The repeater function is especially useful
for boosting signals for longer distance transmission
over lossy cables and backplanes.
2
•
DC to 2 Gbps Low Jitter, High Noise Immunity,
Low Power Operation
•
•
•
•
6 dB of Pre-emphasis Drives Lossy
Backplanes and Cables
LVDS/CML/LVPECL Compatible Input, LVDS
Output
On-chip 100 Ω output termination, optional 100
Ω Input Termination
15 kV ESD Protection on LVDS Inputs and
Outputs
•
•
•
Single 3.3V Supply
Industrial -40 to +85°C Temperature Range
Space Saving WQFN-32 or TQFP-48 Packages
The DS15BR400/DS15BR401 are powered from a
single 3.3V supply and consume 578 mW (typ). They
operate over the full -40°C to +85°C industrial
temperature range and are available in space saving
WQFN-32 and TQFP-48 packages.
APPLICATIONS
•
•
•
Cable Extension Applications
Signal Repeating and Buffering
Digital Routers
Typical Application
DS15BR400
Cable or Backplane
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS15BR400, DS15BR401
SNLS224G –AUGUST 2006–REVISED APRIL 2013
www.ti.com
Block and Connection Diagrams
PEM PWDN
PEM PWDN
Pre-emphasis
and Control
Pre-emphasis
and Control
OUT0+
IN0+
IN0-
OUT0+
OUT0-
IN0+
IN0-
OUT0-
OUT1+
OUT1-
IN1+
IN1-
OUT1+
OUT1-
IN1+
IN1-
OUT2+
OUT2-
OUT2+
OUT2-
IN2+
IN2-
IN2+
IN2-
OUT3+
OUT3-
IN3+
IN3-
OUT3+
OUT3-
IN3+
IN3-
Figure 1. DS15BR400 Block Diagram
Figure 2. DS15BR401 Block Diagram
12 11 10
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
IN0+
IN0-
OUT0+
OUT0-
OUT1+
OUT1-
GND
OUT0+
OUT0-
OUT1+
OUT1-
OUT2+
IN0+
9
32
31
30
29
28
IN1+
IN1-
IN0- 10
IN1+ 11
GND
GND
IN2+
IN2-
DAP
(GND)
12
13
14
15
16
IN1-
IN2+
IN2-
IN3+
IN3-
GND
OUT2+
OUT2-
OUT3+
OUT3-
GND
27 OUT2-
26 OUT3+
IN3+
IN3-
GND
GND
25
OUT3-
GND
17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32 33 34 35 36
Figure 3. TQFP Pinout - Top View
Package Number PFB0048A
Figure 4. WQFN Pinout - Top View
Package Number RTV0032A
PIN DESCRIPTIONS
Pin
Name
TQFP Pin
Number
WQFN Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS
IN0+
IN0−
13
14
9
10
I, LVDS
I, LVDS
I, LVDS
I, LVDS
Channel 0 inverting and non-inverting differential inputs.
Channel 1 inverting and non-inverting differential inputs.
Channel 2 inverting and non-inverting differential inputs.
Channel 3 inverting and non-inverting differential inputs.
IN1+
IN1−
15
16
11
12
IN2+
IN2−
19
20
13
14
IN3+
IN3−
21
22
15
16
2
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SNLS224G –AUGUST 2006–REVISED APRIL 2013
PIN DESCRIPTIONS (continued)
Pin
Name
TQFP Pin
Number
WQFN Pin
Number
I/O, Type
Description
DIFFERENTIAL OUTPUTS
(1)
OUT0+
OUT0−
48
47
32
31
O, LVDS
O, LVDS
O, LVDS
O, LVDS
Channel 0 inverting and non-inverting differential outputs.
Channel 1 inverting and non-inverting differential outputs.
Channel 2 inverting and non-inverting differential outputs.
Channel 3 inverting and non-inverting differential outputs.
(1)
(1)
(1)
OUT1+
OUT1−
46
45
30
29
OUT2+
OUT2−
42
41
28
27
OUT3+
OUT3-
40
39
26
25
DIGITAL CONTROL INTERFACE
PWDN
PEM
12
2
8
2
I, LVTTL
I, LVTTL
A logic low at PWDN activates the hardware power down mode (all channels).
Pre-emphasis Control Input (affects all Channels)
POWER
VDD
3, 4, 5, 7, 10,
11, 28, 29, 32,
33
3, 4, 6, 7, 20,
21
I, Power
VDD = 3.3V, ±10%
(2)
GND
N/C
8, 9, 17, 18, 23,
24, 37, 38, 43,
44
5
I, Ground Ground reference for LVDS and CMOS circuitry. For the WQFN package, the
DAP is used as the primary GND connection to the device in addition to the pin
numbers listed. The DAP is the exposed metal contact at the bottom of the
WQFN-32 package. It should be connected to the ground plane with at least 4
vias for optimal AC and thermal performance.
1,6, 25, 26, 27,
1, 17,
No Connect
30, 31, 34, 35, 18,19,22, 23,
36 24
(1) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and
DS15BR401 are optimized for point-to-point backplane and cable applications.
(2) Note that for the WQFN package the GND is connected thru the DAP on the back side of the WQFN package in addition to the actual
pin numbers listed.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)
Supply Voltage (VDD
)
−0.3V to +4.0V
−0.3V to (VDD+0.3V)
−0.3V to (VDD+0.3V)
−0.3V to (VDD+0.3V)
+40 mA
CMOS Input Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Current
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
260°C
Lead Temperature (Solder, 4sec)
Max Pkg Power Capacity @ 25°C
TQFP
WQFN
1.64W
4.16W
Thermal Resistance (θJA
)
TQFP
WQFN
76°C/W
30°C/W
Package Derating above +25°C
TQFP
WQFN
13.2mW/°C
33.3mW/°C
ESD Last Passing Voltage
HBM, 1.5kΩ, 100pF
8 kV
15 kV
250V
LVDS pins to GND only
EIAJ, 0Ω, 200pF
Charged Device Model
1000V
(1) Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI
does not recommend operation of products outside of recommended operation conditions.
Recommended Operating Conditions
Supply Voltage (VDD
)
3.0V to 3.6V
0V to VDD
0V to VDD
(1)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Industrial
−40°C to +85°C
(1) VID max < 2.4V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(1)
LVCMOS DC SPECIFICATIONS (PWDN, PEM)
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
High Level Input Current
Low Level Input Current
LVCMOS Input Capacitance
Input Clamp Voltage
2.0
GND
−10
40
VDD
0.8
V
V
VIN = VDD = 3.6V (PWDN pin)
+10
200
+10
µA
µA
µA
pF
V
IIHR
IIL
VIN = VDD = 3.6V (PEM pin)
VIN = VSS, VDD = 3.6V
−10
CIN1
VCL
Any Digital Input Pin to VSS
ICL = −18 mA, VDD = 0V
5.5
−1.5
−0.8
(1) Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
4
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(1)
LVDS INPUT DC SPECIFICATIONS (INn±)
VTH
VTL
Differential Input High
Threshold
VCM = 0.8V to 3.55V,
VDD = 3.6V
0
0
100
mV
mV
(2)
Differential Input Low
VCM = 0.8V to 3.55V,
VDD = 3.6V
−100
(2)
Threshold
VID
Differential Input Voltage
VCM = 0.8V to 3.55V, VDD = 3.6V
100
2400
3.55
mV
V
VCMR
CIN2
IIN
Common Mode Voltage Range VID = 150 mV, VDD = 3.6V
0.05
LVDS Input Capacitance
Input Current
IN+ or IN− to VSS
3.0
pF
µA
µA
VIN = 3.6V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
−10
−10
+10
+10
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
VOD
Differential Output Voltage,
0% Pre-emphasis
RL = 100Ω external resistor between OUT+ and OUT−
Figure 5
250
360
500
mV
(2)
ΔVOD
Change in VOD between
Complementary States
−35
1.05
−35
35
1.475
35
mV
V
(3)
VOS
Offset Voltage
1.18
ΔVOS
Change in VOS between
Complementary States
mV
COUT
IOS
LVDS Output Capacitance
Output Short Circuit Current
OUT+ or OUT− to VSS
2.5
−21
6
pF
mA
mA
OUT+ or OUT− Short to GND
OUT+ or OUT− Short to VDD
−40
40
SUPPLY CURRENT (Static)
ICC
Supply Current
All inputs and outputs enabled and active, terminated with
differential load of 100Ω between OUT+ and OUT-. PEM = L
175
20
215
200
mA
µA
ICCZ
Supply Current - Power Down PWDN = L, PEM = L
Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High
Transition Time
Use an alternating 1 and 0 pattern at 200 Mbps, measure
170
170
1.0
250
250
2.0
ps
ps
ns
(4)
between 20% and 80% of VOD
.
Figure 6 , Figure 8
tHLT
Differential High to Low
(4)
Transition Time
tPLHD
tPHLD
Differential Low to High
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps, measure at
50% VOD between input to output.
Figure 6 , Figure 7
Differential High to Low
Propagation Delay
1.0
10
25
2.0
60
ns
ps
ps
ps
(4)
tSKD1
tSKCC
Pulse Skew
|tPLHD–tPHLD|
Output Channel to Channel
Difference in propagation delay (tPLHD or tPHLD) among all
output channels.
75
(4)
Skew
(4)
tSKP
Part to Part Skew
Common edge, parts at same temp and VCC
550
(2) Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
(3) Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(1)
(6)
tJIT
Jitter (0% Pre-emphasis)
RJ - Alternating 1 and 0 at 750 MHz
0.5
14
14
1.5
30
31
ps
ps
ps
(5)
(7)
DJ - K28.5 Pattern, 1.5 Gbps
(8)
TJ - PRBS 223-1 Pattern, 1.5 Gbps
tON
LVDS Output Enable Time
LVDS Output Disable Time
Time from PWDN to OUT± change from TRI-STATE to active.
Figure 9, Figure 10
20
12
µs
ns
tOFF
Time from PWDN to OUT± change from active to TRI-STATE.
Figure 9, Figure 10
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 50% duty cycle at 750 MHz, tr = tf = 50 ps
(20% to 80%).
(7) Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500 mV,
input common mode voltage = VICM = 1.2V, K28.5 pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50
ps (20% to 80%).
DC Test Circuits
1/4 DS15BR400
V
OH
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
R
L
R
D
V
OL
Figure 5. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
1/4 DS15BR400
OUT+
OUT-
IN+
IN-
Signal Generator
R
L
R
D
Figure 6. Differential Driver AC Test Circuit
Figure 7. Propagation Delay Timing Diagram
6
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Figure 8. LVDS Output Transition Times
1/4 DS15BR400
R / 2
OUT+
OUT-
L
IN+
IN-
Power Supply
Power Supply
1.2V
R
D
R / 2
L
PWDN
Pulse Generator
50W
Figure 9. Enable/Disable Time Test Circuit
Figure 10. Enable/Disable Time Diagram
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APPLICATION INFORMATION
INTERNAL TERMINATIONS
The DS15BR400 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω
resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the
device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to
minimize the output return loss and does not take the place of the 100 ohm termination at the inputs to the
receiving device. The integrated terminations improve signal integrity and decrease the external component
count resulting in space savings. The DS15BR401 has 100Ω output terminations only.
OUTPUT CHARACTERISTICS
The output characteristics of the DS15BRB400/DS15BR401 have been optimized for point-to-point backplane
and cable applications, and are not intended for multipoint or multidrop signaling.
POWERDOWN MODE
The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all
input and output buffers and internal bias circuitry are powered off. When exiting powerdown mode, there is a
delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS
Output Switching Characteristics.
Upon asserting the power down function (PWDN = Low), and if the Pre-emphasis feature is enable, it is possible
for the driver output to source current for a short amount of time lifting the output common mode to VDD. To
prevent this occurrence, a load discharge pull down path can be used on either output (1 kΩ to ground
recommended). Alternately, a commonly deployed external failsafe network will also provide this path (see
INPUT FAILSAFE BIASING). The occurrence of this is application dependant, and parameters that will effect if
this is of concern include: AC coupling, use of the powerdown feature, presence of the discharge path, presence
of the failsafe biasing, the usage of the pre-emphasis feature, and input characteristics of the downstream LVDS
Receiver.
PRE-EMPHASIS
Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. One pin is used to select the
pre-emphasis level for all outputs, off or on. The pre-emphasis boost is approximately 6 dB at 750 MHz.
Table 1. Pre-emphasis Control Selection Table
PEM
Pre-Emphasis
0
1
Off
On
INPUT FAILSAFE BIASING
Failsafe biasing of the LVDS link should be considered if the downstream Receiver is ON and enabled when the
source is in TRI-STATE, powered off, or removed. This will set a valid known input state to the active receiver.
This is accomplished by using a pull up resistor to VDD on the ‘plus’ line, and a pull down resistor to GND on the
‘minus’ line. Resistor values are in the 750 Ohm to several kΩ range. The exact value depends upon the desired
common mode bias point, termination resistor(s) and desired input differential voltage setting. Please refer to
application note AN-1194 “Failsafe Biasing of LVDS interfaces” (SNLA051) for more information and a general
discussion.
DECOUPLING
Each power or ground lead of the DS15BR400 should be connected to the PCB through a low inductance path.
For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via
placement is immediately adjacent to the pin to avoid adding trace inductance. Placing power plane closer to the
top of the board reduces effective via length and its associated inductance.
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Bypass capacitors should be placed close to VDD pins. Small physical size capacitors, such as 0402, X7R,
surface mount capacitors should be used to minimize body inductance of capacitors. Each bypass capacitor is
connected to the power and ground plane through vias tangent to the pads of the capacitor. An X7R surface
mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30 MHz or so, X7R
capacitors behave as low impedance inductors. To extend the operating frequency range to a few hundred MHz,
an array of different capacitor values like 100 pF, 1 nF, 0.03 µF, and 0.1 µF are commonly used in parallel. The
most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2–3
mils. With a 2 mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.
The center dap of the WQFN package housing the DS15BR400 should be connected to a ground plane through
an array of vias. The via array reduces the effective inductance to ground and enhances the thermal
performance of the WQFN package.
INPUT INTERFACING
The DS15BR400 and DS15BR401 accept differential signals and allow simple AC or DC coupling. With a wide
common mode range, the DS15BR400 and DS15BR401 can be DC-coupled with all common differential drivers
(i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common
differential drivers. Note that the DS15BR400 inputs are internally terminated with a 100Ω resistor while the
DS15BR401 inputs are not, therefore the latter requires external input termination.
LVDS
Driver
DS15BR400
Receiver
100W Differential T-Line
OUT+
IN+
100W
IN-
OUT-
Figure 11. Typical LVDS Driver DC-Coupled Interface to DS15BR400 Input
CML3.3V or CML2.5V
Driver
V
CC
DS15BR400
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 12. Typical CML Driver DC-Coupled Interface to DS15BR400 Input
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
Figure 13. Typical LVPECL Driver DC-Coupled Interface to DS15BR400 Input
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OUTPUT INTERFACING
The DS15BR400 and DS15BR401 output signals that are compliant to the LVDS standard. Their outputs can be
DC-coupled to most common differential receivers. Figure 14 illustrates typical DC-coupled interface to common
differential receivers and assumes that the receivers have high impedance inputs. While most differential
receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to
check respective receiver's data sheet prior to implementing the suggested interface implementation.
DS15BR400
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 14. Typical DS15BR400 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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Typical Performance Characteristics
Power Supply Current vs. Data Rate
Total Jitter vs. Ambient Temperature
30
300
25
250
200
20
15
10
150
V
= 3.3V
CC
= 500 mV
ID
V
= 3.3V
CC
V
100
50
V
= 500 mV
ID
V
= 1.2V
CM
V
= 1.2V
CM
NRZ PRBS-23
NRZ PRBS-23
1.5 Gbps
5
0
T
=25°C
A
0
-40 -20
0
20
40
60
80 100
0
0.4
0.8
1.2
1.6
2.0
TEMPERATURE (°C)
DATA RATE (Gbps)
Figure 15.
Figure 16.
Total Jitter vs. Data Rate
Data Rate vs. Cable Length (0.25 UI Criteria)
30
2.5
V
CC
= 3.3V
NRZ PRBS-23
Jitter = 0.25 UI
25
20
2.0
1.5
T
A
= 25 °C
CAT5e
PEM
ON
PEM
OFF
15
V
= 3.3V
1.0
0.5
CC
10
5
V
= 500 mV
ID
V
= 1.2V
CM
NRZ PRBS-23
T
= 25°C
A
0
0
1.0
1.2
1.4
1.6
1.8
2.0
1
10
20
30
40
DATA RATE (Gbps)
CABLE LENGTH (m)
(1)
Figure 17.
Figure 18.
Data Rate vs. Cable Length (0.5 UI Criteria)
2.5
V
CC
= 3.3V
NRZ PRBS-23
Jitter = 0.5 UI
2.0
1.5
T
A
= 25°C
CAT5e
PEM
OFF
PEM
ON
1.0
0.5
0
1
10
20
30
40
CABLE LENGTH (m)
(1)
Figure 19.
(1) Data presented in this graph was collected using the DS15BR400EVK, a pair of RJ-45 to SMA adapter boards and various length
Belden 1700a cables. The maximum data rate was determined based on total jitter (0.25 UI criteria) measured after the cable. The total
jitter was a peak to peak value measured with a histogram including 3000 window hits.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS15BR400 DS15BR401
DS15BR400, DS15BR401
SNLS224G –AUGUST 2006–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15BR400 DS15BR401
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS15BR400TSQ
NRND
WQFN
RTV
32
1000
Non-RoHS
& Green
Call TI
Level-3-260C-168 HR
-40 to 85
5R400SQ
DS15BR400TSQ/NOPB
DS15BR400TVS
ACTIVE
NRND
WQFN
TQFP
RTV
PFB
32
48
1000 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
5R400SQ
250
250
Non-RoHS
& Green
Call TI
DS15BR
400TVS
DS15BR400TVS/NOPB
DS15BR400TVSX/NOPB
ACTIVE
ACTIVE
TQFP
TQFP
PFB
PFB
48
48
RoHS & Green
SN
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
DS15BR
400TVS
1000 RoHS & Green
1000 RoHS & Green
DS15BR
400TVS
DS15BR401TSQ/NOPB
DS15BR401TVS/NOPB
ACTIVE
ACTIVE
WQFN
TQFP
RTV
PFB
32
48
SN
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
5R401SQ
250
RoHS & Green
DS15BR
401TVS
DS15BR401TVSX/NOPB
ACTIVE
TQFP
PFB
48
1000 RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS15BR
401TVS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS15BR400TSQ
WQFN
RTV
RTV
PFB
RTV
PFB
32
32
48
32
48
1000
1000
1000
1000
1000
178.0
178.0
330.0
178.0
330.0
12.4
12.4
16.4
12.4
16.4
5.3
5.3
9.3
5.3
9.3
5.3
5.3
9.3
5.3
9.3
1.3
1.3
2.2
1.3
2.2
8.0
8.0
12.0
12.0
16.0
12.0
16.0
Q1
Q1
Q2
Q1
Q2
DS15BR400TSQ/NOPB WQFN
DS15BR400TVSX/NOPB TQFP
DS15BR401TSQ/NOPB WQFN
DS15BR401TVSX/NOPB TQFP
12.0
8.0
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS15BR400TSQ
WQFN
WQFN
TQFP
WQFN
TQFP
RTV
RTV
PFB
RTV
PFB
32
32
48
32
48
1000
1000
1000
1000
1000
208.0
208.0
356.0
208.0
356.0
191.0
191.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
DS15BR400TSQ/NOPB
DS15BR400TVSX/NOPB
DS15BR401TSQ/NOPB
DS15BR401TVSX/NOPB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS15BR400TVS
DS15BR400TVS
PFB
PFB
PFB
PFB
TQFP
TQFP
TQFP
TQFP
48
48
48
48
250
250
250
250
10 x 25
10 x 25
10 x 25
10 x 25
150
150
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
DS15BR400TVS/NOPB
DS15BR401TVS/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
RTV0032A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
9
16
8
17
SYMM
33
2X 3.5
3.1 0.1
28X 0.5
1
24
0.30
32X
0.18
32
25
PIN 1 ID
0.1
C A B
0.5
0.3
32X
0.05
4224386/B 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
SYMM
SEE SOLDER MASK
DETAIL
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(3.1)
33
SYMM
(4.8)
(1.3)
8
17
(R0.05) TYP
(
0.2) TYP
VIA
9
16
(1.3)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.775) TYP
25
32
32X (0.6)
1
32X (0.24)
28X (0.5)
24
(0.775) TYP
(4.8)
33
SYMM
(R0.05) TYP
4X (1.35)
17
8
9
16
4X (1.35)
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
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