DS160PR1601ZDGR [TI]
PCIe® 4.0 16-Gbps 16-Lane linear redriver | ZDG | 354 | -40 to 85;
| 型号： | DS160PR1601ZDGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCIe® 4.0 16-Gbps 16-Lane linear redriver | ZDG | 354 | -40 to 85 PC |
| 文件： | 总39页 (文件大小：2423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS160PR1601
ZHCSRO2 –FEBRUARY 2023
DS160PR1601 16Gbps 16 通道线性转接驱动器
1 特性
3 说明
• 支持PCIe 4.0 和UPI 2.0 的16 通道线性转接驱动
器
• 支持高达16Gbps 的数据速率
• 与Intel 重定时器通用封装引脚对引脚兼容
• 封装内TX 引脚上有64 个集成交流耦合电容器，可
节省布板空间
• CTLE 在8GHz 时提升16dB
• 模拟EyeScan 以帮助转接驱动器进行调谐、调试和
远程监控
DS160PR1601 是一款 32 通道（每个方向 16 通道）
x16（16 通道）低功耗高性能线性中继器或转接驱动
器，设计用于支持 PCIe 4.0、UPI 2.0 和其他接口，最
高可支持16Gbps 的传输速率。
DS160PR1601 接收器部署了连续时间线性均衡器
(CTLE)，用以提供可编程高频增强功能。均衡器可以
打开由于 PCB 布线等互连介质引起的码间串扰 (ISI)
而完全关闭的输入眼图。CTLE 接收器后跟一个线性输
出驱动器。DS160PR1601 的线性数据路径保留了发射
预设信号特性。线性转接驱动器成为无源通道的一部
分，该通道作为一个整体进行链路训练，可获得更优发
送和接收均衡设置。对这种链路训练协议进行透明管理
可实现更优的电气链路和尽可能低的延迟。该器件具有
低通道间串扰、低附加抖动和超低的回波损耗，因此在
链路中几乎可用作无源元件，而又具有均衡功能。
• 130 ps 的超低延迟
• PRBS 数据的100 fs 低附加随机抖动
• 8GHz 时具有−13dB 的超低RX/TX 回波损耗
• 3.3V 单电源
• 160mW/通道的低有功功率
• I2C/SMBus 或EEPROM 编程
• 针对PCIe 用例的自动接收器检测
• 无缝支持PCIe 链路训练
封装信息(1)
封装尺寸（标称值）
器件型号
封装
• 内部稳压器具有抗电源噪声能力
• 高速量产测试可确保制造可靠性
• 支持x4、x8、x16 总线宽度
• 8.90mm × 22.80mm BGA 封装
DS160PR1601
22.89 mm x 8.90 mm
ZDG（nfBGA、354）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
.
.
• 机架式服务器、微服务器和塔式服务器
• 高性能计算
• 硬件加速器
• 网络连接存储
• 存储区域网络(SAN) 和主机总线适配器(HBA) 卡
• 网络接口卡(NIC)
• 台式计算机或主板
x16
PR1601
16 Tx Ch
PCIe x16 Network Interface Card
PCIe
X16
x16
CPU
Riser Card
Root
Complex
End
Point
Connector
CPU
x16
16 Rx Ch
Server Motherboard
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS732
DS160PR1601
ZHCSRO2 –FEBRUARY 2023
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Table of Contents
7.3 Control and Configuration Interface..........................22
7.4 Feature Description...................................................25
7.5 Device Functional Modes..........................................26
8 Application and Implementation..................................27
8.1 Application Information............................................. 27
8.2 Typical Applications.................................................. 27
8.3 Power Supply Recommendations.............................31
8.4 Layout....................................................................... 31
9 Device and Documentation Support............................33
9.1 Documentation Support............................................ 33
9.2 接收文档更新通知..................................................... 33
9.3 支持资源....................................................................33
9.4 Trademarks...............................................................33
9.5 静电放电警告............................................................ 33
9.6 术语表....................................................................... 33
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications................................................................ 15
6.1 Absolute Maximum Ratings...................................... 15
6.2 ESD and Latchup Ratings.........................................15
6.3 Recommended Operating Conditions.......................15
6.4 Thermal Information..................................................16
6.5 DC Electrical Characteristics.................................... 16
6.6 High Speed Electrical Characteristics.......................17
6.7 SMBUS/I2C Timing Charateristics............................18
6.8 Typical Characteristics..............................................20
6.9 Typical Jitter Characteristics..................................... 20
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................21
Information.................................................................... 33
4 Revision History
DATE
REVISION
NOTES
February 2023
*
Initial Release
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5 Pin Configuration and Functions
图5-1. ZDG Package, 354-Pin BGA (Top View 1/3)
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图5-2. ZDG Package, 354-Pin BGA (Top View 2/3)
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图5-3. ZDG Package 354-Pin BGA Top View 3/3
Legend
Ground
Power
IOs, RSVD /NC
Differential Input
Differential Output
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表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
A1
NAME
N/C
No internal connection.
—
A35
B12
B16
B19
B23
N/C
No internal connection.
—
RSVD8
RSVD7
GND
Reserved for future use. No internal connection.
Reserved for future use. No internal connection.
Ground
—
—
Ground
Input
A_ADDR0_7-0
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
B25
B28
B_ADDR0_7-0
SDA
Input
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
Input /Output
3.3 V SMBus/I2C data IO pin SDA. External 1 kΩ to 5 kΩ pullup resistor is required as
per SMBus / I2C interface standard. The device can alter between SMBus/I2C
primary and secondary mode through exercising MODE pin.
B3
RSVD11
SCL
Reserved for future use. No internal connection.
—
B31
Input /Output
3.3 V SMBus/I2C clock IO pin SCL. External 1 kΩ to 5 kΩ pullup resistor is required
as per SMBus / I2C interface standard. The device can alter between SMBus/I2C
primary and secondary mode through exercising MODE pin.
B6
RSVD10
RSVD9
N/C
Reserved for future use. No internal connection.
Reserved for future use. No internal connection.
No internal connection.
—
B9
—
C2
—
C34
D1
N/C
No internal connection.
—
N/C
No internal connection.
—
D35
E11
E14
E18
E27
E30
E33
E8
N/C
No internal connection.
—
RSVD13
GND
Reserved for future use. No internal connection.
Ground
—
Ground
RSVD14
GND
Reserved for future use. No internal connection.
Ground
—
Ground
Ground
Ground
GND
Ground
GND
Ground
RSVD12
RSVD3
B_ADDR1_7-0
Reserved for future use. No internal connection.
Reserved for future use. No internal connection.
—
F2
—
F34
Input
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
G1
A_ADDR1_7-0
Input
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
G35
H12
H16
H19
H31
J22
J4
RSVD4
GND
Reserved for future use. No internal connection.
—
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Diff Output
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
K2
GND
Ground
K34
L1
GND
Ground
GND
Ground
L35
M26
GND
Ground
A_PETp0
Differential transmit signal, channel A, lane 0, positive
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PIN
表5-1. Pin Functions (continued)
TYPE
DESCRIPTION
NO.
NAME
M7
B_PETn0
A_PERp0
B_PERn0
B_PETp0
A_PETn0
A_PERn0
B_PERp0
GND
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel B, lane 0, negative
N2
Differential receive signal, channel A, lane 0, positive
N34
P10
Differential receive signal, channel B, lane 0, negative
Differential transmit signal, channel B, lane 0, positive
P29
Differential transmit signal, channel A, lane 0, negative
R1
Differential receive signal, channel A, lane 0, negative
R35
T13
Differential receive signal, channel B, lane 0, positive
Ground
T17
VCC1
Power
3.3 V Supply Voltage
T20
VCC1
Power
3.3 V Supply Voltage
T22
GND
Ground
Ground
T32
GND
Ground
Ground
T4
GND
Ground
Ground
U2
GND
Ground
Ground
U34
V1
GND
Ground
Ground
GND
Ground
Ground
V35
GND
Ground
Ground
W26
W7
A_PETp1
B_PETn1
A_PERp1
B_PERn1
B_PETp1
A_PETn1
A_PERn1
B_PERp1
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 1, positive
Differential transmit signal, channel B, lane 1, negative
Differential receive signal, channel A, lane 1, positive
Differential receive signal, channel B, lane 1, negative
Differential transmit signal, channel B, lane 1, positive
Differential transmit signal, channel B, lane 1, negative
Differential receive signal, channel A, lane 1, negative
Differential receive signal, channel B, lane 1, positive
Ground
Y2
Y34
AA10
AA29
AB1
AB35
AC13
AC17
AC20
AC22
AC32
AC4
AD2
AD34
AE1
AE35
AF26
AF7
AG2
AG34
AH10
AH29
AJ1
VCC1
Power
3.3 V Supply Voltage
VCC1
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
A_PETp2
B_PETn2
A_PERn2
B_PERp2
B_PETp2
A_PETn2
A_PERp2
B_PERn2
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 2, positive
Differential transmit signal, channel B, lane 2, negative
Differential receive signal, channel A, lane 2, negative
Differential receive signal, channel B, lane 2, positive
Differential transmit signal, channel B, lane 2, positive
Differential transmit signal, channel A, lane 2, negative
Differential receive signal, channel A, lane 2, positive
Differential receive signal, channel B, lane 2, negative
Ground
AJ35
AK13
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
VCC1
AK17
AK20
AK22
AK32
AK4
Power
3.3 V Supply Voltage
3.3 V Supply Voltage
Ground
VCC1
Power
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
GND
Ground
GND
Ground
AL2
GND
Ground
AL34
AM1
GND
Ground
GND
Ground
AM35
AN26
AN7
GND
Ground
A_PETp3
B_PETn3
A_PERn3
B_PERp3
B_PETp3
A_PETn3
A_PERp3
B_PERn3
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 3, positive
Differential transmit signal, channel B, lane 3, negative
AP2
Differential receive signal, channel A, lane 3, negative
AP34
AR10
AR29
AT1
Differential receive signal, channel B, lane 3, positive
Differential transmit signal, channel B, lane 3, positive
Differential transmit signal, channel A, lane 3, negative
Differential receive signal, channel A, lane 3, positive
AT35
AU13
AU17
AU20
AU22
AU32
AU4
Differential receive signal, channel B, lane 3, negative
Ground
VCC1
Power
3.3 V Supply Voltage
VCC2
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
AV2
GND
Ground
Ground
AV34
AW1
AW35
AY26
AY7
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
A_PETp4
B_PETn4
A_PERp4
B_PERn4
B_PETp4
A_PETn4
A_PERn4
B_PERp4
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 4, positive
Differential transmit signal, channel B, lane 4, negative
BA2
Differential receive signal, channel A, lane 4, positive
BA34
BB10
BB29
BC1
Differential receive signal, channel B, lane 4, negative
Differential transmit signal, channel B, lane 4, positive
Differential transmit signal, channel A, lane 4, negative
Differential receive signal, channel A, lane 4, negative
BC35
BD13
BD17
BD20
BD22
BD32
BD4
Differential receive signal, channel B, lane 4, positive
Ground
VCC2
Power
3.3 V Supply Voltage
3.3 V Supply Voltage
Ground
VCC2
Power
GND
Ground
GND
Ground
Ground
GND
Ground
Ground
BE2
GND
Ground
Ground
BE34
BF1
GND
Ground
Ground
GND
Ground
Ground
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PIN
表5-1. Pin Functions (continued)
TYPE
DESCRIPTION
NO.
NAME
BF35
BG26
BG7
GND
Ground
Ground
A_PETp5
B_PETn5
A_PERp5
B_PERn5
B_PETp5
A_PETn5
A_PERn5
B_PERp5
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 5, positive
Differential transmit signal, channel B, lane 5, negative
BH2
Differential receive signal, channel A, lane 5, positive
BH34
BJ10
BJ29
BK1
Differential receive signal, channel B, lane 5, negative
Differential transmit signal, channel B, lane 5, positive
Differential transmit signal, channel A, lane 5, negative
Differential receive signal, channel A, lane 5, negative
BK35
BL13
BL17
BL20
BL22
BL32
BL4
Differential receive signal, channel B, lane 5, positive
Ground
VCC2
Power
3.3 V Supply Voltage
VCC2
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
BM2
GND
Ground
Ground
BM34
BN1
GND
Ground
Ground
GND
Ground
Ground
BN35
BP26
BP7
GND
Ground
Ground
A_PETp6
B_PETn6
A_PERn6
B_PERp6
B_PETp6
A_PETn6
A_PERp6
B_PERn6
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 6, positive
Differential transmit signal, channel B, lane 6, negative
Differential receive signal, channel A, lane 6, negative
Differential receive signal, channel B, lane 6, positive
Differential transmit signal, channel B, lane 6, positive
Differential transmit signal, channel A, lane 6, negative
Differential receive signal, channel A, lane 6, positive
Differential receive signal, channel B, lane 6, negative
Ground
BR2
BR34
BT10
BT29
BU1
BU35
BV13
BV17
BV20
BV22
BV32
BV4
VCC2
Power
3.3 V Supply Voltage
VCC2
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
BW2
BW34
BY1
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
BY35
CA26
CA7
GND
Ground
Ground
A_PETp7
B_PETn7
A_PERn7
B_PERp7
B_PETp7
A_PETn7
A_PERp7
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Differential transmit signal, channel A, lane 7, positive
Differential transmit signal, channel B, lane 7, negative
Differential receive signal, channel A, lane 7, negative
Differential receive signal, channel B, lane 7, positive
Differential transmit signal, channel B, lane 7, positive
Differential transmit signal, channel A, lane 7, negative
Differential receive signal, channel A, lane 7, positive
CB2
CB34
CC10
CC29
CD1
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
B_PERn7
GND
CD35
CE13
CE17
CE20
CE22
CE32
CE4
Diff Input
Ground
Power
Differential receive signal, channel B, lane 7, negative
Ground
VCC2
3.3 V Supply Voltage
3.3 V Supply Voltage
Ground
VCC3
Power
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
GND
Ground
GND
Ground
CF2
GND
Ground
CF34
CG1
GND
Ground
GND
Ground
CG35
CH26
CH7
GND
Ground
A_PETp8
B_PETn8
A_PERp8
B_PERn8
B_PETp8
A_PETn8
A_PERn8
B_PERp8
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 8, positive
Differential transmit signal, channel B, lane 8, negative
CJ2
Differential receive signal, channel A, lane 8, positive
CJ34
CK10
CK29
CL1
Differential receive signal, channel B, lane 8, negative
Differential transmit signal, channel B, lane 8, positive
Differential transmit signal, channel A, lane 8, negative
Differential receive signal, channel A, lane 8, negative
CL35
CM13
CM17
CM20
CM22
CM32
CM4
Differential receive signal, channel B, lane 8, positive
Ground
VCC3
Power
3.3 V Supply Voltage
VCC3
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
CN2
GND
Ground
Ground
CN34
CP1
GND
Ground
Ground
GND
Ground
Ground
CP35
CR26
CR7
GND
Ground
Ground
A_PETp9
B_PETn9
A_PERp9
B_PERn9
B_PETp9
A_PETn9
A_PERn9
B_PERp9
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 9, positive
Differential transmit signal, channel B, lane 9, negative
Differential receive signal, channel A, lane 9, positive
Differential receive signal, channel B, lane 9, negative
Differential transmit signal, channel B, lane 9, positive
Differential transmit signal, channel A, lane 9, negative
Differential receive signal, channel A, lane 9, negative
Differential receive signal, channel B, lane 9, positive
Ground
CT2
CT34
CU10
CU29
CV1
CV35
CW13
CW17
CW20
CW22
CW32
CW4
CY2
VCC3
Power
3.3 V Supply Voltage
VCC3
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
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PIN
表5-1. Pin Functions (continued)
TYPE
DESCRIPTION
NO.
NAME
CY34
DA1
GND
Ground
Ground
Ground
Ground
Ground
Ground
GND
DA35
DB26
DB7
GND
A_PETp10
B_PETn10
A_PERn10
B_PERp10
B_PETp10
A_PETn10
A_PERp10
B_PERn10
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 10, positive
Differential transmit signal, channel B, lane 10, negative
DC2
Differential receive signal, channel A, lane 10, negative
DC34
DD10
DD29
DE1
Differential receive signal, channel B, lane 10, positive
Differential transmit signal, channel B, lane 10, positive
Differential transmit signal, channel A, lane 10, negative
Differential receive signal, channel A, lane 10, positive
DE35
DF13
DF17
DF20
DF22
DF32
DF4
Differential receive signal, channel B, lane 10, negative
Ground
VCC3
Power
3.3 V Supply Voltage
VCC3
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
DG2
GND
Ground
Ground
DG34
DH1
GND
Ground
Ground
GND
Ground
Ground
DH35
DJ26
DJ7
GND
Ground
Ground
A_PETp11
B_PETn11
A_PERn11
B_PERp11
B_PETp11
A_PETn11
A_PERp11
B_PERn11
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 11, positive
Differential transmit signal, channel B, lane 11, negative
Differential receive signal, channel A, lane 11, negative
Differential receive signal, channel B, lane 11, positive
Differential transmit signal, channel B, lane 11, positive
Differential transmit signal, channel A, lane 11, negative
Differential receive signal, channel A, lane 11, positive
Differential receive signal, channel B, lane 11, negative
Ground
DK2
DK34
DL10
DL29
DM1
DM35
DN13
DN17
DN20
DN22
DN32
DN4
VCC3
Power
3.3 V Supply Voltage
VCC4
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
DP2
GND
Ground
Ground
DP34
DR1
GND
Ground
Ground
GND
Ground
Ground
DR35
DT26
DT7
GND
Ground
Ground
A_PETp12
B_PETn12
A_PERp12
B_PERn12
B_PETp12
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Differential transmit signal, channel A, lane 12, positive
Differential transmit signal, channel B, lane 12, negative
Differential receive signal, channel A, lane 12, positive
Differential receive signal, channel B, lane 12, negative
Differential transmit signal, channel B, lane 12, positive
DU2
DU34
DV10
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
DV29
DW1
DW35
DY13
DY17
DY20
DY22
DY32
DY4
A_PETn12
A_PERn12
B_PERp12
GND
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 12, negative
Differential receive signal, channel A, lane 12, negative
Differential receive signal, channel B, lane 12, positive
Ground
VCC4
Power
3.3 V Supply Voltage
VCC4
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
EA2
GND
Ground
Ground
EA34
EB1
GND
Ground
Ground
GND
Ground
Ground
EB35
EC26
EC7
GND
Ground
Ground
A_PETp13
B_PETn13
A_PERp13
B_PERn13
B_PETp13
A_PETn13
A_PERn13
B_PERp13
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 13, positive
Differential transmit signal, channel B, lane 13, negative
ED2
Differential receive signal, channel A, lane 13, positive
ED34
EE10
EE29
EF1
Differential receive signal, channel B, lane 13, negative
Differential transmit signal, channel B, lane 13, positive
Differential transmit signal, channel A, lane 13, negative
Differential receive signal, channel A, lane 13, negative
EF35
EG13
EG17
EG20
EG22
EG32
EG4
Differential receive signal, channel B, lane 13, positive
Ground
VCC4
Power
3.3 V Supply Voltage
VCC4
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
EH2
GND
Ground
Ground
EH34
EJ1
GND
Ground
Ground
GND
Ground
Ground
EJ35
EK26
EK7
GND
Ground
Ground
A_PETp14
B_PETn14
A_PERn14
B_PERp14
B_PETp14
A_PETn14
A_PERp14
B_PERn14
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 14, positive
Differential transmit signal, channel B, lane 14, negative
Differential receive signal, channel A, lane 14, negative
Differential receive signal, channel B, lane 14, positive
Differential transmit signal, channel B, lane 14, positive
Differential transmit signal, channel A, lane 14, negative
Differential receive signal, channel A, lane 14, positive
Differential receive signal, channel B, lane 14, negative
Ground
EL2
EL34
EM10
EM29
EN1
EN35
EP13
EP17
EP20
EP22
EP32
VCC4
Power
3.3 V Supply Voltage
VCC4
Power
3.3 V Supply Voltage
GND
Ground
Ground
GND
Ground
Ground
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PIN
表5-1. Pin Functions (continued)
TYPE
DESCRIPTION
NO.
NAME
EP4
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
ER2
GND
ER34
ET1
GND
GND
ET35
EU26
EU7
GND
A_PETp15
B_PETn15
A_PERn15
B_PERp15
B_PETp15
A_PETn15
A_PERp15
B_PERn15
GND
Diff Output
Diff Output
Diff Input
Diff Input
Diff Output
Diff Output
Diff Input
Diff Input
Ground
Differential transmit signal, channel A, lane 15, positive
Differential transmit signal, channel B, lane 15, negative
EV2
Differential receive signal, channel A, lane 15, positive
EV34
EW10
EW29
EY1
Differential receive signal, channel B, lane 15, positive
Differential transmit signal, channel B, lane 15, negative
Differential transmit signal, channel A, lane 15, negative
Differential receive signal, channel A, lane 15, positive
EY35
FA15
FA32
FB2
Differential receive signal, channel B, lane 15, negative
Ground
GND
Ground
Ground
GND
Ground
Ground
FB34
FC19
FC23
FC25
FC28
FC3
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
GND
Ground
Ground
FC6
GND
Ground
Ground
FC9
GND
Ground
Ground
FD1
GND
Ground
Ground
FD35
FE2
GND
Ground
Ground
N/C
No internal connection.
—
FE34
FF11
FF14
FF18
FF21
FF24
N/C
No internal connection.
—
RSVD2
GND
Reserved for future use. No internal connection.
Ground
—
Ground
RSVD6
GND
Reserved for future use. No internal connection.
Ground
—
Ground
Input
MODE
5-level input strap pin. Sets device control configuration modes. The pin can be
exercised at device power up or in normal operation mode.
L1: SMBus/I2C Primary Mode - device control configuration is read from external
EEPROM. When the device has finished reading from the EEPROM successfully, it
will drive the ALL_DONE_N pin LOW. SMBus/I2C secondary operation is available in
this mode before, during or after EEPROM reading. Note during EEPROM reading if
the external SMBus/I2C primary wants to access the device registers it must support
arbitration. To set the pin for L1 pull-down with 2.062 kΩ±10% resistor.
L2: SMBus/I2C Secondary Mode –device control configuration is done by an
external controller with SMBus/I2C primary. To set the pin for L1 pull-down with 18.75
kΩ±10% resistor.
L0, L3 and L4: RESERVED –TI internal test modes.
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
FF27
ALL_DONE#
Output
EEPROM loading is done. Active low 3.3 V open drain output pin. The pin can be left
unconnected.
In SMBus/I2C Primary Mode: Indicates the completion of a valid EEPROM register
load operation. External pullup resistor such as 4.7 kΩ required for operation.
•
•
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C secondary: The pin is High-Z.
FF30
B_ADDR1_15-8
Input
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
FF33
FF5
PD_3-0
Input
Input
3.3 V LVCMOS input. Implements device power-down /reset according to 表7-1.
A_ADDR0_15-8
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
FF8
PD_15-12
N/C
Input
3.3 V LVCMOS input. Implements device power-down /reset according to 表7-1.
FG1
No internal connection.
No internal connection.
No internal connection.
No internal connection.
Ground
—
FG35
FH2
N/C
—
N/C
—
FH34
FJ12
FJ16
FJ19
FJ23
N/C
—
GND
RSVD5
GND
Ground
Reserved for future use. No internal connection.
Ground
—
Ground
Input
RSVD1
TI internal use. Leave unconnected.
FJ25
READ_EN_#
Input
Initiate EEPROM load. Active low 3.3 V LVCMOS input..
In SMBus/I2C Primary Mode: After device power up, when the pin is low, it initiates
the EEPROM read function. Once EEPROM read is complete (indicated by
ALL_DONE# asserted low), this pin can be held low for normal device operation.
During the EEPROM load process the device’s signal path is disabled.
In SMBus/I2C Secondary: In these modes the pin is not used. The pin can be left
floating. The pin has internal 1-MΩ weak pulldown resistor.
FJ28
FJ3
B_ADDR0_15-8
A_ADDR1_15-8
Input
Input
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
5-level input strap pins as defined in 表7-2. Sets SMBus/I2C secondary address
according to 表7-1 and 表7-3.
FJ31
FJ6
PD_7-4
Input
Input
Input
3.3 V LVCMOS input. Implements device power-down /reset according to 表7-1.
3.3 V LVCMOS input. Implements device power-down /reset according to 表7-1.
TI internal use. Leave unconnected.
PD_11-8
FJ9
RSVD0
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.0
UNIT
V
VCCABSMAX
VIOCMOS,ABSMAX
VIO5LVL,ABSMAX
VIOHS-RX,ABSMAX
VIOHS-TX,ABSMAX
TJ,ABSMAX
Supply Voltage (VCC)
3.3 V LVCMOS and Open Drain I/O voltage
5-level Input I/O voltage
4.0
V
2.75
3.2
V
High-speed I/O voltage (RXnP, RXnN)
High-speed I/O voltage (TXnP, TXnN)
Junction temperature
V
2.75
150
150
V
°C
°C
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD and Latchup Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
+100
-100
V(Signal+) Positive signal pin latch-up Signal pin test, per JESD78F class II, immunity level A (all signal pins)
Signal pin test, per JESD78F class II, immunity level A (all signal pins
except RX pins)
V(Signal-) Negative signal pin latch-up
mA
Signal pin test, per JESD78F class II, immunity level B, annex A flow 1F
-100
(RX pins are connected through 75nF - 265 nF capacitors)(3)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Per annex A flow 1F, negative pulse immunity on RX pins is –50 mA without series capacitors.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
DC plus AC power should not
exceed these limits
VCC
NVCC
Supply voltage, VCC to GND
Supply noise tolerance
3.0
3.3
3.6
V
DC to <50 Hz, sinusoidal1
250
100
33
mVpp
mVpp
mVpp
50 Hz to 500 kHz, sinusoidal1
500 kHz to 2.5 MHz, sinusoidal1
Supply noise, >2.5 MHz,
sinusoidal1
10
mVpp
TRampVCC
TJ
VCC supply ramp time
From 0 V to 3.0 V
0.150
100
120
ms
°C
Operating junction temperature
Minimum pulse width required for
–40
PWLVCMOS the device to detect a valid signal PD1/0, and READ_EN_N
on LVCMOS inputs
200
10
μs
SMBus/I2C SDA and SCL Open Supply voltage for open drain
VCCSMBUS
3.6
V
Drain Termination Voltage
pull-up resistor
SMBus/I2C clock (SCL) frequency
in secondary mode
FSMBus
400
kHz
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
800
1
NOM
MAX
1200
16
UNIT
mVpp
Gbps
Source differential launch
VIDLAUNCH
amplitude
DR
Data rate
6.4 Thermal Information
DSPR16
NJX, 64
THERMAL METRIC(1)
UNIT
Pins
17.4
6.5
RθJA-High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
Junction-to-board thermal resistance
6.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.6
ψJT
5.9
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 DC Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
PACT
Device active power
Device active power
32-channels (16-lanes), EQ = 0-3
32-channels (16-lanes), EQ = 4-19
4.7
5.8
6.0
7.0
W
W
PACT
Device power consumption while
waiting for far end receiver
terminations
All channels enabled but no far end
receiver detected
PRXDET
660
92
mW
mW
Device power consumption in standby
power mode
PSTBY
All channels disabled
Control IO
VOH
Rpull-up = 4.7 kΩ (SDA, SCL,
High level output voltage
Low level output voltage
Input high leakage current
Input low leakage current
2.1
-40
V
V
ALL_DONE_N pins)
IOL = –4 mA (SDA, SCL,
ALL_DONE_N pins)
VOL
IIH
0.4
40
VInput = VCC, (SCL, SDA, PD,
READ_EN_N pins)
µA
µA
VInput = 0 V, (SCL, SDA, PD,
READ_EN_N pins)
IIL
Input high leakage current for fail safe VInput = 3.6 V, VCC = 0 V, (SCL, SDA,
IIH,FS
800
40
µA
pF
input pins
PD, READ_EN_N pins)
CIN-CTRL
Input capacitance
SDA, SCL, PD, READ_EN_Npins
1.2
5 Level IOs (MODE, A/B_ADDR pins)
IIH_5L Input high leakage current, 4 level IOs VIN = 2.5 V
µA
µA
Input low leakage current for all 4 level
IOs except MODE.
IIL_5L
VIN = GND
VIN = GND
-40
Input low leakage current for MODE
pin
IIL_5L,MODE
-800
µA
V
Receiver
VRX-DC-CM
RX DC Common Mode Voltage
Device is in active or standby state
1.4
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6.5 DC Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ZRX-DC
Rx DC Single-Ended Impedance
50
Ω
ZRX-HIGH-IMP- DC input CM input impedance during
Inputs are at VRX-DC-CM voltage
15
kΩ
Reset or power-down
DC-POS
Transmitter
Impedance of Tx during active
signaling, VID,diff = 1Vpp
ZTX-DIFF-DC
VTX-DC-CM
ITX-SHORT
DC Differential Tx Impedance
Tx DC common mode Voltage
Tx Short Circuit Current
100
1.0
70
Ω
V
Total current the Tx can supply when
shorted to GND
mA
6.6 High Speed Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver
50 MHz to 1.25 GHz
-20
-19
-16
-12
-15
-15
dB
dB
dB
dB
dB
dB
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
50 MHz to 2.5 GHz
2.5 GHz to 8.0 GHz
RLRX-DIFF
Input differential return loss
RLRX-CM
Input common-mode return loss
Receive-side pair-to-pair isolation
Pair-to-pair isolation (SDD21) between
two adjacent receiver pairs from 10
MHz to 8 GHz.
XTRX
-50
dB
Transmitter
Tx AC Peak-to-Peak Common Mode
Voltage
Measured with lowest EQ, flat_gain =
101
VTX-AC-CM-PP
50
mVpp
mV
Measured while Tx is sensing whether
a low-impedance Receiver is present.
No load is connected to the driver
output
VTX-RCV-
Amount of Voltage change allowed
during Receiver Detection
0
600
DETECT
50 MHz to 1.25 GHz
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
50 MHz to 2.5 GHz
2.5 GHz to 8.0 GHz
-19
-17
-12
-10
-14
-12
dB
dB
dB
dB
dB
dB
RLTX-DIFF
Output differential return loss
RLTX-CM
Output Common-mode return loss
Transmit-side pair-to-pair isolation
Minimum pair-to-pair isolation
(SDD21) between two adjacent
transmitter pairs from 10 MHz to 8
GHz.
XTTX
-50
dB
nF
AC coupling capacitors on transmit
pins
CAC,TX
220
Device Datapath
Input-to-output latency (propagation
For either Low-to-High or High-to-Low
transition.
TPLHD/PHLD
130
170
24
ps
ps
delay) through a data channel
Between any two lanes within a single
transmitter.
LTX-SKEW
Lane-to-Lane Output Skew
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6.6 High Speed Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Jitter through redriver minus the
calibration trace. 16 Gbps PRBS15.
800 mVpp-diff input swing.
TRJ-DATA
Additive Random Jitter with data
100
fs
Jitter through redriver minus the
calibration trace. 8 Ghz CK. 800
mVpp-diff input swing.
Intrinsic additive Random Jitter with
clock
TRJ-INTRINSIC
100
2.0
1.3
fs
Jitter through redriver minus the
calibration trace. 16 Gbps PRBS15.
800 mVpp-diff input swing.
JITTERTOTAL-
Additive Total Jitter with data
ps
ps
DATA
Jitter through redriver minus the
Intrinsic additive Total Jitter with clock calibration trace. 8 Ghz CK. 800
mVpp-diff input swing.
JITTERTOTAL-
INTRINSIC
EQ boost at min setting (EQ INDEX = AC gain at 8 GHz relative to gain at
EQ-MIN8G
EQ-MAX8G
1.7
16
dB
dB
0)
100 MHz.
EQ boost at max setting (EQ INDEX = AC gain at 8 GHz relative to gain at
19)
100 MHz.
Flat_gain = 000, 001, 011, 101 or 111,
at minimum EQ setting. Max-Min for a
single channel.
FLAT-
GAINVAR
Flat gain variation across PVT
measured at DC
-1.0
-1.5
1.0
1.5
dB
dB
At 8 Ghz. Flat_gain = 101, maximum
EQ setting. Max-Min for a single
channel.
EQ-
GAINVAR,8G
EQ boost variation across PVT
LINEARITY-
DC
Flat_gain = 101. 128T pattern at 2.5
Gbps.
Output DC Linearity
Output AC Linearity
1800
1000
mVpp
mVpp
LINEARITY-
AC
Flat_gain = 101. 1T pattern at 16
Gbps.
6.7 SMBUS/I2C Timing Charateristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Secondary Mode
Pulse width of spikes which must be
suppressed by the input filter
tSP
50
ns
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA
0.6
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
µs
µs
THIGH
Set-up time for a repeated START
condition
tSU-STA
0.6
µs
tHD-DAT
TSU-DAT
Data hold time
Data setup time
0
µs
µs
0.1
Rise time of both SDA and SCL
signals
tr
120
2
ns
Pull-up resistor = 4.7 kΩ, Cb = 10pF
Pull-up resistor = 4.7 kΩ, Cb = 10pF
tf
Fall time of both SDA and SCL signals
Set-up time for STOP condition
ns
µs
tSU-STO
0.6
1.3
Bus free time between a STOP and
START condition
tBUF
µs
tVD-DAT
tVD-ACK
Cb
Data valid time
0.9
0.9
µs
µs
pF
Data valid acknowledge time
Capacitive load for each bus line
400
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6.7 SMBUS/I2C Timing Charateristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Primary Mode
fSCL-M
SCL clock frequency
SCL low period
MODE = L1 (Primary Mode)
303
1.90
1.40
kHz
µs
tLOW-M
THIGH-M
SCL high period
µs
Set-up time for a repeated START
condition
tSU-STA-M
2
µs
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA-M
1.5
TSU-DAT-M
tHD-DAT-M
Data setup time
Data hold time
1.4
0.5
µs
µs
Rise time of both SDA and SCL
signals
tR-M
120
ns
Pull-up resistor = 4.7 kΩ, Cb = 10pF
Pull-up resistor = 4.7 kΩ, Cb = 10pF
TF-M
Fall time of both SDA and SCL signals
Stop condition setup time
2
ns
µs
tSU-STO-M
1.5
EEPROM Timing
TEEPROM EEPROM configuration load time
TPOR Time to first SMBus access
Time to assert ALL_DONE_N after
READ_EN_N has been asserted.
30
50
ms
ms
Power supply stable after initial ramp.
Includes initial power-on reset time.
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6.8 Typical Characteristics
图 6-1 shows typical EQ gain curves versus frequency for different EQ settings for the DS160PR1601. 图 6-2
shows typical differential return loss for Rx and Tx pins.
28
24
20
16
12
8
-8
-12
-16
-20
-24
EQ = 0
EQ = 1
EQ = 2
EQ = 3
EQ = 4
EQ = 5
EQ = 6
EQ = 7
EQ = 8
EQ = 9
EQ = 10
EQ = 11
EQ = 12
EQ = 13
EQ = 14
EQ = 15
EQ = 16
EQ = 17
EQ = 18
EQ = 19
Rx
Tx
4
0
-4
0
4
8
12
16
20
0
4
8
12
16
20
Frequency (GHz)
Frequency (GHz)
图6-1. Typical EQ Boost vs Frequency
图6-2. Typical Differential Return Loss
6.9 Typical Jitter Characteristics
图 6-3 and 图 6-4 show eye diagrams through calibration traces, and through the DS160PR1601 respectively.
Note: DS160PR1601 adds little to no random or deterministic jitter.
图6-3. Through Baseline Calibration Trace Setup 图6-4. Through the DS160PR1601 with DUT EQ = 0
(10.26 ps Total Jitter Including Source)
(12.08ps Total Jitter –Very Little Added Jitter Due
to Redriver)
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7 Detailed Description
7.1 Overview
The DS160PR1601 is a 16-lane multi-rate linear repeater with integrated signal conditioning. The device's signal
channels operate independently from one another. Each channel includes a continuous-time linear equalizer
(CTLE) and a linear output driver, which together compensate for a lossy transmission channel between the
source transmitter and the final receiver. The linearity of the data path is specifically designed to preserve any
transmit equalization while keeping receiver equalization effective.
The DS160PR1601 can be configured two different ways:
SMBus/I2C Primary mode – device control configuration is read from external EEPROM. When the
DS160PR1601 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW.
SMBus/I2C secondary operation is available in this mode before, during or after EEPROM reading. Note during
EEPROM reading if the external SMBus/I2C primary wants to access DS160PR1601 registers it must support
arbitration. The mode is prefferred when software implementation is not desired.
SMBus/I2C Secondary mode – provides most flexibility. Requires a SMBus/I2C primary device to configure
DS160PR1601 though writing to its secondary address.
7.2 Functional Block Diagram
1-Channel of 16
Term
Term
A_PERp_xx
A_PERn_xx
A_PETp_xx
A_PETn_xx
Linear
Driver
CTLE
Receiver
Detect
Analog
EyeScan
READ_EN_x
ALL_DONE_x
Analog Bias
Circuits
GND
VCC
Linear Voltage
A_ADDRx_x
Power-On
Reset
Regulators
(Datapath &
logic)
B_ADDRx_x
MODE
Digital Core
Design for
Production
Testing
Always-On
10MHz
PD_x
SDA
SCL
1-Channel of 16
Term
Term
B_PETp_xx
B_PETn_xx
B_PERp_xx
B_PERn_xx
Linear
Driver
CTLE
Receiver
Detect
Analog
EyeScan
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7.3 Control and Configuration Interface
7.3.1 Pin Configurations for Lanes
The DS160PR1601 has 16 data lanes with 16-Tx channels and 16-Rx channels. The data channels are grouped
for I2C configurations and PCIe state machine grouping as shown in 图 7-1 using xADDRx and PDx pins. 表 7-1
defines the channel grouping.
Side A
Side B
A_PER
B_PET
Ln15-12 Ln 11-8
Ln 7-4
Ln 3-0
Ln15-12 Ln 11-8
Ln 7-4
Ln 3-0
A_PET
B_PER
Side A
Side B
图7-1. Pin Configurations for Lanes
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Pin Name
表7-1. Definition of PDx and xADDRx pins
Description
PD_15-12
PD_11-8
PD_7-4
Active in all device control modes. The pin has internal 1-MΩ weak pulldown resistor. The pin triggers
PCIe RX detect state machine when toggled.
•
•
High: power down
PD_3-0
Low: power up normal operation.
Each PD pin sets control for a bank of 8 lanes (4 from Side A and 4 from Side B) to provide flexibility
for x4 and x8 bifurcation:
•
•
•
•
PD_15-12: Lanes 15-12, both Side A and B
PD_11-8: Lanes 11-8, both Side A and B
PD_7-4: Lanes 7-4, both Side A and B
PD_3-0: Lanes 3-0, both Side A and B
PCIe hot plug insertion implementation varies from system to system. One way to implement will be to
use CEM interface PRSNT# signal. For PCIe x16 application all four PD signals can be shorted
together and connect to CEM interface PRSNT# signal.
A_ADDR1_15-8
A_ADDR0_15-8
A_ADDR1_7-0
A_ADDR0_7-0
B_ADDR1_15-8
B_ADDR0_15-8
B_ADDR1_7-0
B_ADDR0_7-0
5-level input pins as implemented by pull-down resistor on the pin according to 表7-2.
These pins are sampled at device power-up only. Sets SMBus / I2C secondary address according to
表7-3. Each set of ADDR1 and ADDR0 pins defines the addresses for bank of 8 lanes:
•
•
•
•
A_ADDR1_15-8, A_ADDR0_15-8: Lanes 15-8 of Side A
A_ADDR1_7-0, A_ADDR0_7-0: Lanes 7-0 of Side A
B_ADDR1_15-8, B_ADDR0_15-8: Lanes 15-8 of Side B
B_ADDR1_7-0, B_ADDR0_7-0: Lanes 7-0 of Side B
图7-1 shows how I2C secondary addresses are accessed for specific lanes.
7.3.1.1 Five-Level Control Inputs
The has 5-level inputs pins that are used to control the configuration of the device. These 5-level inputs use a
resistor divider to help set the 5 valid levels and provide a wider range of control settings. External resistors must
be of 10% tolerance or better. The pins are sampled at power-up only.
表7-2. 5-level Control Pin Settings
LEVEL
L0
SETTING
1 kΩ to GND
8.25 kΩ to GND
24.9 kΩ to GND
75 kΩ to GND
F (Float)
L1
L2
L3
L4
7.3.2 SMBUS/I2C Register Control Interface
If MODE = L2 (SMBus / I2C secondary control mode), the DS160PR1601 is configured through a standard I2C or
SMBus interface that may operate up to 400 kHz. The device also can be configured through loading settings
from EEPROM. The SMBus / I2C primary / secondary address of the DS160PR1601 is determined by the pin
strap settings on the xADDRx pins. Note addresses to access differental channels are different. To illustrate
A_ADDR1_15_8 and A_ADDR0_15_8 sets the primary / secondary address for bank of lanes 15-12 and 11-8 of
Side A, while A_ADDR1_7_0 and A_ADDR0_7_0 sets for bank of lanes 7-4 and 3-0 of Side A. B side address is
also set similarly. 表7-3 show SMBus / I2C primary / secondary addresses.
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表7-3. SMBus / I2C Primary / Secondary Address
x_ADDR1_x
x_ADDR0_x
7-bit address
7-bit address
Upper (for Side A) / Lower (for Side B) 4 Lower (for Side A) / Upper (for Side B) 4
Lanes of each Bank
Lanes of each Bank
L0
L0
L0
L0
L0
L1
L1
L1
L1
L1
L2
L2
L2
L2
L2
L3
L3
L3
L3
L3
L0
L1
L2
L3
L4
L0
L1
L2
L3
L4
L0
L1
L2
L3
L4
L0
L1
L2
L3
L4
0x19
0x18
0x1B
0x1A
0x1D
0x1C
0x1F
0x1E
Reserved
0x21
Reserved
0x20
0x23
0x22
0x25
0x24
0x27
0x26
Reserved
0x29
Reserved
0x28
0x2B
0x2A
0x2D
0x2C
0x2F
0x2E
Reserved
0x31
Reserved
0x30
0x33
0x32
0x35
0x34
0x37
0x36
Reserved
Reserved
In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of
the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 50
pF.
Refer to the DS160PR1601 Programming Guide for detail register sets and control configuration procedures.
7.3.3 SMBus/I2C Primary Mode Configuration (EEPROM Self Load)
The DS160PR1601 can also be configured by reading from EEPROM. To enter into this mode MODE pin must
be set to L1. The EEPROM load operation only happens once after device's initial power-up. If the
DS160PR1601 is configured for SMBus primary mode, it will remain in the SMBus IDLE state until the
READ_EN_N pin is asserted to LOW. After the READ_EN_N pin is driven LOW, the DS160PR1601 becomes an
SMBus primary and attempts to self-configure by reading device settings stored in an external EEPROM
(SMBus 8-bit address 0xA0). When the DS160PR1601 has finished reading from the EEPROM successfully, it
will drive the ALL_DONE_N pin LOW. SMBus/I2C secondary operation is available in this mode before, during or
after EEPROM reading. Note during EEPROM reading if the external SMBus/I2C primary wants to access
DS160PR1601 registers it must support arbitration.
When designing a system for using the external EEPROM, the user must follow these specific guidelines:
• EEPROM size of 2 kb (256 × 8-bit) is recommended.
• Set MODE = L1, configure for SMBus primary mode
• The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 3.3 V supply
• In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value
of the resistor depends on total bus capacitance. 4.7 kΩis a good first approximation for a bus capacitance
of 10 pF.
Refer to the DS160PR1601 Programming Guide for detail register sets and control configuration procedures.
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7.4 Feature Description
7.4.1 Linear Equalization
The DS160PR1601 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency
boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the
passive channel. The device has 20 available equalization boost settings that can be set though SMBus/I2C
registers. 表7-4 shows the device EQ settings.
Refer to the DS160PR1601 Programming Guide for detail register sets and control configuration procedures.
表7-4. Equalization Control Settings
EQ INDEX
TYPICAL EQ BOOST (dB) at 8 GHz
0
1
2.0
3.5
2
5.0
3
7.0
4
8.0
5
9.0
6
9.8
7
10.2
10.8
11.2
11.8
12.2
12.8
13.2
13.8
14.2
14.8
15.2
15.6
16.0
8
9
10
11
12
13
14
15
16
17
18
19
7.4.2 Flat-Gain
The overall datapath Flat-Gain (DC and AC) of the DS160PR1601 can be programmed through SMBus/I2C
registers. 表7-5 shows five available flat gain settings to configure the DS160PR1601 datapaths.
表7-5. Flat Gain Settings
Flat_gain
SETTING
000
-6 dB
001
-4 dB
011
-2 dB
0 dB (default and recommended)
+2dB
101
111
The default recommendation for most systems will be 0 dB.
The Flat-Gain and equalization of the DS160PR1601 must be set such that the output signal swing at DC and
high frequency does not exceed the DC and AC linearity ranges of the devices, respectively.
Refer to the DS160PR1601 Programming Guide for detail register sets and control configuration procedures.
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7.4.3 Analog EyeScan
The DS160PR1601 implements Analog EyeScan feature that enables monitoring of the internal eye for each
data channel after the receiver CTLE stage. It provides a measure of vertical eye opening estimation using
signal statistics. The Analog EyeScan feature is useful for redriver tuning to choose CTLE and Flat-Gain settings
to optimize an electrical link between a transmitter and a receiver. This is also useful for hardware engineers for
initial system bring-up and at field system diagnostics. The EyeScan feature can be invoked by I2C or SMBus
interface.
7.4.4 Receiver Detect State Machine
The DS160PR1601 deploys an RX detect state machine that governs the RX detection cycle as defined in the
PCI express specifications. At power up, after a manually triggered event through PDx pins, or writing to the
relevant I2C/SMBus register, the redriver determines whether or not a valid PCI express termination is present at
the far end of the link. The Rx Detect Registers provide additional flexibility for system designers to appropriately
set the device in desired mode through SMBus/I2C control interface.
7.4.5 Integrated Capacitors
The DS160PR1601 has intergrated AC coupling caps for all TX pins (64 count). The capacitors are 220 nF each
with 2.5 V voltage rating and 20% tolerance.
7.5 Device Functional Modes
7.5.1 Active PCIe Mode
The device is in normal operation with PCIe state machine enabled through SMBus/I2C registers. In this mode
PDx pins are driven low in a system (for example by PCIE connector "PRSNT" or inverted "PERST" signal). In
this mode, the DS160PR1601 redrives and equalizes PCIe RX or TX signals to provide better signal integrity.
7.5.2 Active Buffer Mode
The device is in normal operation with PCIe state machine disabled through I2C registers. This mode is
recommended for non-PCIe use cases. In this mode the device is working as a buffer to provide linear
equalization to improve signal integrity.
7.5.3 Standby Mode
The device is in standby mode invoked by PDx pins. In this mode, the device is in standby mode conserving
power.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DS160PR1601 is a high-speed linear repeater which extends the reach of differential channels impaired by
loss from transmission media like PCBs and cables. It can be deployed in a variety of different systems. The
following sections outline typical applications and their associated design considerations.
8.2 Typical Applications
The DS160PR1601 is a 16-lane protocol agnostic PCI Express linear redriver. Its protocol agnostic nature allows
it to be used in PCI Express x4, x8, and x16 applications. 图 8-1 shows how single DS160PR1601 can be used
in four x4, two x8 or single x16 links.
Riser Card
SSD
x4
x4
SSD
x4
PR1601 x4
SSD
x4
x4
x4
SSD
x4
Connector
CPU
x16
Server Motherboard
Four x4 PCIe link using single PR1601
x8
PCIe x8 EP
x8
PR1601
x8
PCIe x8 EP
Riser Card
x8
Connector
CPU
Server Motherboard
Two x8 PCIe link using single PR1601
x16
PR1601
PCIe x16 Network Interface Card
x16
Riser Card
Connector
CPU
x16
Server Motherboard
x16 PCIe link using single PR1601
图8-1. PCI Express x4, x8, and x16 Implementation Using DS160PR1601
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8.2.1 PCIe x16 Lane Configuration
The DS160PR1601 can be used in server or motherboard applications to boost transmit and receive signals to
increase the reach of the host or root complex processor to PCI Express slots or connectors. The section
outlines detailed procedure and design requirement for a typical PCIe x16 lane confuration. However, the design
recommendations can also be used in x4 or x8 lane configuration.
8.2.1.1 Design Requirements
As with any high-speed design, there are many factors which influence the overall performance. The following
list indicates critical areas for consideration during design.
• Use 85 Ωimpedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N
traces should be done on the single-end segments of the differential pair.
• Use a uniform trace width and trace spacing for differential pairs.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
In PCIe Gen 3.0 and 4.0 applications, the specification requires Rx-Tx (of root-complex and endpoint) link
training to establish and optimize signal conditioning settings. In link training, the Rx partner requests a series of
FIR – preshoot and deemphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-levels
of CTLE followed by a single tap DFE. The link training would pre-condition the signal, with an equalized link
between the root-complex and endpoint resulting an optimized link. Note that there is no link training in PCIe
Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications.
The DS160PR1601 is designed with linear datapth to pass the Tx Preset signaling (by root complex and end
point) onto the Rx (of root complex and end point) for a PCIe link to train and optimize for the Rx equalization
settings. The linear redriver helps extend the PCB trace reach distance by boosting the attenuated signals with
its own equalization, which allows the Rx to recover signals more easily. The device must be placed in between
the Tx and Rx (of root complex and end point) such a way that signal swing of both upstream and downstream
signals stays within the linearity range of the device. Adjustments to the DS160PR1601 EQ setting should be
performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ gain
settings are provided in 表 7-4. For most PCIe systems the default Flat gain setting of 0 dB (flat_gain = 101)
would be sufficient.
The DS160PR1601 can be optimized for a given system utlizing its two configuration modes – SMBus/I2C
Primary mode and SMBus/I2C Secondary mode. In SMBus/I2C modes the SCL, SDA pins must be pulled up to a
3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩis a good
first approximation for a bus capacitance of 10 pF.
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图8-2 shows a simplified schematic for x16 lane configuration in SMBus/I2C Primary mode.
1-Channel of 16
Term
A_PETp_xx
A_PETn_xx
Term
A_PERp_xx
A_PERn_xx
Linear
Driver
CTLE
Receiver
Detect
Analog
EyeScan
Pin strap to set SMBus
Secondary address for
group of channels.
Initiates
EEPROM read
READ_EN_x
ALL_DONE_x
A_ADDRx_x
B_ADDRx_x
GND
GND
Indicates
EEPROM read
complete
Minimum
recommended
decoupling
0.1 F
3.3V
(multiple)
1 F
VCC
13 k
MODE
Digital Core
Analog Core
GND
Sets SMBus
Primary Mode
Drive all PD pins with the
appropriate PRSNT# or
PERST with polarity
reversal for appropriate
system behavior. Group PD
pins based on x4, x8 or x16
operation.
4.7 k
SDA
SCL
PD_x
VCC
VCC
I2C data and clock pins. Same
pins serve as both secondary
and primary interface
4.7 k
1-Channel of 16
Term
Term
B_PETp_xx
B_PETn_xx
B_PERp_xx
B_PERn_xx
Linear
Driver
CTLE
Receiver
Detect
Analog
EyeScan
图8-2. Simplified Schematic for PCIe x16 Lane Configuration in SMBus/I2C Primary Mode
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8.2.1.3 Application Curves
The DS160PR1601 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-
compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 28
dB at 16 Gbps (8 GHz) PCIe 4.0. With the DS160PR1601, the total channel loss between a PCIe root complex
and an end point can be extended up to 42 dB (16 dB additional) at 8 GHz.
To demonstrate the reach extension capability of the DS160PR1601, two comparative setups are constructed. In
first setup as shown in 图8-3 there is no redriver in the PCIe 5.0 link. 图8-4 shows eye diagram at the end of the
link using SigTest. In second setup as shown in 图8-5, the DS160PR1601 is inserted in the middle to extend link
reach. 图8-6 shows SigTest eye diagram.
Keysight
M8040
BERT
Tek 33GHz
Scope
PCIe
Comp pa ern
P9 800mV
SigTest
Phoenix
PCIe
PCIe
Loss Board
Loss Board
PCIe
Baseboard
(CBB)
PCIe
Load Board
(CLB)
图8-3. PCIe 4.0 Link Baseline Setup Without
Redriver –Link Elements
图8-4. PCIe 4.0 link Baseline Setup Without
Redriver –Eye Diagram Using SigTest
Keysight
M8040
BERT
Tek 33GHz
Scope
PCIe
SigTest
Comp pa ern
P9 800mV
Phoenix
PCIe
PCIe
Loss Board
Loss Board
PCIe
Baseboard
(CBB)
PCIe
Load Board
(CLB)
DS160PR1601
Redriver
Riser card
图8-5. PCIe 4.0 Link Setup with the DS160PR1601
–the Link Elements
图8-6. PCIe 4.0 Link Setup with the DS160PR1601
–Eye Diagram Using SigTest
表 8-1 summarizes the PCIe 4.0 links without and with the DS160PR1601. The illustration shows that redriver is
capable of ≅16 dB (additional) reach extension at PCIe 4.0 speed with EQ = 15 and flat_gain = 101. Note: actual
reach extension depends on various signal integrity factors. It is recommended to run signal intergrity
simulations with all the components in the link to get any guidance.
表8-1. PCIe 4.0 Reach Extension Using the DS160PR1601
Setup
Pre Channel Loss
Post Channel Loss
Total Loss
Eye at BER 1E-12 SigTest Pass?
29 ps, 48 mV
30 ps, 55 mV
Pass
Pass
Baseline –no DUT
With DUT (DS160PR1601)
—
—
≅27 dB
≅25 dB
≅18 dB
≅43 dB
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8.3 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the operating conditions outlined in the recommended
operating conditions section in terms of DC voltage, AC noise, and start-up ramp time.
2. The DS160PR1601 does not require any special power supply filtering, such as ferrite beads, provided that
the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply
decoupling consists of adequate numbers of 0.1 µF capacitors near device VCC pins, several 1.0 µF and
10.0 bulk capacitors on VCC power plane. The local decoupling (0.1 µF) capacitors must be connected as
close to the VCC pins as possible and with minimal path to the DS160PR1601 ground pad. For more
specific guidance, refer to DS320PR1601RSC-EVM User's Guide.
8.4 Layout
8.4.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VCC pins as possible. Placing the decoupling
capacitors directly underneath the device is recommended if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take
care to minimize the via stub, either by transitioning through most/all layers or by back drilling.
4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve
signal integrity by counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board.
8.4.2 Layout Example
图8-7. Top Layer View of TI PCIe Riser Card Using DS160PR1601 with CEM Connectors
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图8-8. Bottom Layer View of TI PCIe Riser Card Using DS160PR1601 with CEM Connectors
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: DS160PR1601
DS160PR1601
ZHCSRO2 –FEBRUARY 2023
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, DS320PR1601RSC-EVM User's Guide
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: DS160PR1601
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS160PR1601ZDGR
DS160PR1601ZDGT
ACTIVE
ACTIVE
NFBGA
NFBGA
ZDG
ZDG
354
354
1000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
PR16X
PR16X
Samples
Samples
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2023
Addendum-Page 2
PACKAGE OUTLINE
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
ZDG0354A
A
9
8.8
B
BALL A1 CORNER
22.9
22.7
1.4
1.237
C
SEATING PLANE
C
BALL TYP
0.6 TYP
0.26
0.16
0.15
(0.3) TYP
0.6 TYP
FJ9
FJ12
FJ16
FJ19
FJ23
FJ25
FJ28
FJ31
FH34
FE34
FB34
FH
FJ3
FJ6
FH
2
FG1
FG35
FD35
FF8
FF11
FF14
FF18
FF21
FF24
FF27
FF30
FF33
FE
2
FF5
FC
FD1
3
FC
6
FC9
FC19
FC23
FC25
FC28
FB
2
FA15
FA32
EY35
EY1
E
W
10
EW29
EV34
EV2
0.6 TYP
E
U
7
ET35
ET1
EU26
ER
2
ER34
E
P
4
E
P
13
E
P
17
E
P
20
E
P
22
EP32
E
N
1
EN35
E
M
10
E
M
29
EL2
EL34
(0.3) TYP
E
K
7
EK26
E
J1
EJ35
E
H
2
EH34
E
G
4
E
G
13
13
E
G
17
17
E
G
20
20
E
G
22
22
E
G
32
EF1
EF35
E
E
10
E
E
29
0.6 TYP
E
E
D
2
E
D
34
EC
7
EC26
EB
1
EB35
A
2
E
A
34
DY
4
D
D
Y
D
D
Y
D
D
Y
D
D
Y
DY
32
DW
1
DW35
DV
10
DV29
D
D
U
2
D
U
34
DT7
DT26
DR
1
D
R
35
P
2
D
P
34
N
13
N
17
N
20
N
22
DN32
DN4
DM
1
D
M
35
DL10
DL29
DK
2
D
K
34
1.2 TYP
D
J26
D
H
1
D
H
35
D
J7
D
G
2
D
G
34
D
F13
D
F17
D
F20
D
F22
DF32
D
F4
DD29
DE
1
DE
35
DD10
DC
2
DC
34
0.8 TYP
D
B7
DB26
DA
1
DA
35
CY
2
CY
34
CW
4
CW
13
CW
17
CW
20
CW
22
C
W
32
C
V
1
C
V
35
(0.4) TYP
C
U
10
CU29
C
T2
CT34
C
R
7
7
C
R
26
CP
1
CP35
CN
2
CN34
C
M
4
C
M
13
13
C
M
17
17
C
C
M
20
C
M
22
22
C
M
32
CL1
CL35
C
C
K
10
C
K
29
CJ2
CJ34
PKG
CH
CH
26
CG
1
CG35
CF2
CF34
C
B
E
4
C
B
E
C
B
E
E20
C
B
E
C
E32
21.9
CD
1
CD
35
C
10
CC29
CB
2
CB34
CA
7
7
CA
26
BY
1
BY
35
BW
2
B
W
34
V
4
V
13
V
17
BV
20
V
22
BV32
BU
1
BU
35
BT10
BT29
BR
2
B
R
34
BP
BP
26
BN
1
BN
35
B
B
M
2
B
M
34
BL4
BL13
BL17
BL20
BL22
BL32
B
K
1
BK35
BJ10
BJ29
H2
BH
34
B
G
7
B
G
26
BF1
BF35
B
B
E
2
B
E
34
B
D
4
B
D
13
B
D
17
B
D
20
B
D
22
BD32
B
C
1
BC35
B
B
10
BB29
A2
BA
34
A
Y
7
A
Y
26
A
W
1
AW35
A
A
V
2
A
V
34
A
U
4
A
U
13
A
U
17
A
U
20
A
U
22
A
U
32
(9.6)
A
T1
A
T35
A
R
10
A
R
29
P2
AP
34
A
N
7
AN26
AM
1
AM35
(10.89)
A
L2
AL34
A
K
4
A
K
13
A
K
17
A
K
20
A
K
22
A
K
32
AJ1
AJ35
A
H
10
A
H
29
AG
2
AG34
AF7
AF26
A
E
1
A
E
35
A
D
2
AD34
A
C
4
A
C
17
A
C
20
A
C
22
AC32
AC13
A
B
1
AB35
A
A
10
AA29
Y2
Y34
1.2 TYP
W7
W26
V
1
V35
U
2
U34
T4
T20
T22
T32
T13
T17
R1
R35
P10
P29
N2
N34
M7
L1
L35
M26
K2
K34
J22
J4
G1
H12
H16
H19
H31
G35
F2
F34
E8
E11
E14
E18
E27
E30
E33
D1
D35
C2
C34
0.37
0.27
B6
B9
B12
B16
B19
B23
B
25
B
28
B31
B3
354X Ø
A1
A
35
A
1
35
0.15
0.05
C
C
A B
(1.34)
BALL A1 CORNER
(0.8)
0.5 TYP
(2.82)
(2.89)
(3.94)
4226484/D 08/2021
NanoFree is a trademark of Texas Instruments.
7.88
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
ZDG0354A
(7.88)
(0.6) TYP
(0.3) TYP
(0.6) TYP
A1
A35
C34
B3
B12
B16
B19
B23
B25
B28
B6
B9
B31
C2
F2
K2
N2
U2
D1
D35
E11
E14
E18
E27
E30
E33
E8
F34
G
1
H12
H16
H19
H31
G35
J4
J22
K34
N34
L1
L35
R35
M7
M26
(0.3) TYP
P10
AA10
AH10
AR10
BB10
BJ10
BT10
CC10
CK10
CU10
DD10
DL10
DV10
EE10
EM10
P29
R1
T4
AC4
AK4
AU4
BD4
T13
T17
T20
T22
T32
U34
V35
W
AF7
AN7
AY7
7
W26
V1
Y34
Y2
AA29
AH29
AR29
BB29
BJ29
BT29
CC29
CK29
CU29
DD29
AB35
AE35
AJ35
AM35
AT35
AW35
BC35
BF35
BK35
BN35
BU35
BY35
CD35
CG35
CL35
CP35
CV35
DA35
DE35
DH35
DM35
DR35
DW35
EB35
EF35
EJ35
EN35
ET35
EY35
FD35
FG35
AB1
AC13
AC17
AC20
AC22
AK22
AU22
BD22
BL22
BV22
CE22
CM22
CW22
DF22
DN22
DY22
AC32
AK32
AU32
BD32
BL32
BV32
CE32
AD2
AD34
AG34
AL34
AP34
AV34
BA34
BE34
BH34
BM34
BR34
BW34
CB34
CF34
CJ34
CN34
CT34
CY34
DC34
DG34
DK34
DP34
DU34
EA34
ED34
EH34
EL34
ER34
EV34
FB34
FE34
FH34
AE1
AF26
AN26
AY26
BG26
BP26
CA26
CH26
CR26
DB26
DJ26
DT26
EC26
EK26
(0.6) TYP
AG
2
(0.6) TYP
AJ1
AK13
AU13
BD13
BL13
AK17
AU17
BD17
BL17
AK20
AU20
BD20
BL20
AL2
AP2
AV2
BA2
BE2
BH2
AM
1
AT1
(10.89)
AW
1
BC1
BF1
BK1
BN1
BU1
BY1
CD1
(0.4) TYP
BG7
BM
2
BL4
BP7
(0.8) TYP
BR2
BV4
CE4
BV13
CE13
CM13
CW13
DF13
DN13
DY13
EG13
EP13
BV17
CE17
CM17
CW17
DF17
DN17
DY17
EG17
EP17
BV20
CE20
CM20
CW20
DF20
DN20
DY20
EG20
BW
CB2
CF2
CJ2
CN2
CT2
CY2
DC2
2
CA7
CH7
CR7
DB7
DJ7
DT7
EC7
EK7
EU7
(1.2) TYP
(21.9)
PKG
CG
1
CL1
CP1
CV1
DA1
DE1
DH1
CM4
CM32
CW32
DF32
DN32
DY32
EG32
EP32
CW4
DF4
DN4
DY4
DG
2
DK2
DP2
DU2
EA2
ED2
EH2
EL2
ER2
EV2
(8.4)
DL29
DV29
EE29
EM29
EW29
DM
1
(9.2)
(9.6)
DR1
(10.85)
DW
EB1
EF1
EJ1
EN1
ET1
EY1
1
EG4
EG22
EP4
EP20
EP22
EU26
FC25
FJ25
(1.2) TYP
EW10
FA15
FF14
FB2
FE2
FA32
FC19
FJ19
FC23
FC28
FC3
FC6
FC9
FD1
FF8
FF18
FF21
FF24
FF27
FF30
FF33
FF5
FF11
FG1
FH2
FJ3
FJ6
FJ9
FJ16
FJ23
FJ28
FJ31
FJ12
354X (Ø0.3)
(1.43)
(3.42)
(0.5) TYP
(0.7)
(2.72)
LAND PATTERN EXAMPLE
SCALE: 5X
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
METAL
(Ø0.30)
SOLDER MASK
OPENING
(Ø0.30)
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
(PREFERRED)
NOT TO SCALE
4226484/D 08/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
ZDG0354A
(7.88)
(0.6) TYP
(0.3) TYP
(0.6) TYP
A1
A35
C34
B3
B12
B16
B19
B23
B25
B28
B6
B9
B31
C2
F2
K2
N2
U2
D1
D35
E11
E14
E18
E27
E30
E33
E8
F34
K34
G
1
H12
H16
H19
H31
G35
J4
J22
L1
L35
M7
M26
N34
(0.3) TYP
P10
AA10
AH10
AR10
BB10
BJ10
BT10
CC10
CK10
CU10
DD10
DL10
DV10
EE10
EM10
P29
R1
R35
T4
AC4
AK4
AU4
BD4
T13
T17
T20
T22
T32
AC32
AK32
AU32
BD32
BL32
BV32
CE32
U34
V35
W
7
W
26
V1
Y34
Y2
AA29
AH29
AR29
BB29
BJ29
BT29
CC29
CK29
AB35
AE35
AJ35
AM35
AT35
AW35
BC35
BF35
BK35
BN35
BU35
BY35
CD35
CG35
CL35
CP35
CV35
DA35
DE35
DH35
DM35
DR35
DW35
EB35
EF35
EJ35
EN35
ET35
EY35
FD35
FG35
AB1
AC13
AC17
AC20
AC22
AK22
AU22
BD22
BL22
BV22
CE22
CM22
CW22
DF22
DN22
DY22
AD2
AD34
AG34
AL34
AP34
AV34
BA34
BE34
BH34
BM34
BR34
BW34
CB34
CF34
CJ34
CN34
CT34
CY34
DC34
DG34
DK34
DP34
DU34
EA34
ED34
EH34
EL34
ER34
EV34
FB34
FE34
FH34
AE1
AF7
AN7
AY7
AF26
AN26
AY26
BG26
BP26
CA26
CH26
CR26
DB26
DJ26
DT26
EC26
EK26
(0.6) TYP
AG
2
(0.6) TYP
AJ1
AK13
AU13
BD13
BL13
AK17
AU17
BD17
BL17
AK20
AU20
BD20
BL20
AL2
AP2
AV2
BA2
BE2
BH2
AM
1
AT1
(10.89)
AW
1
BC1
BF1
BK1
BN1
BU1
BY1
CD1
(0.4) TYP
BG7
BM
2
BL4
BP7
(0.8) TYP
BR2
BV4
CE4
BV13
CE13
CM13
CW13
DF13
DN13
DY13
EG13
EP13
BV17
CE17
CM17
CW17
DF17
DN17
DY17
EG17
EP17
BV20
CE20
CM20
CW20
DF20
DN20
DY20
EG20
BW
CB2
CF2
CJ2
CN2
CT2
CY2
DC2
2
CA7
CH7
CR7
DB7
DJ7
DT7
EC7
EK7
EU7
(1.2) TYP
(21.9)
PKG
CG
1
CL1
CP1
CV1
DA1
DE1
DH1
CM4
CM32
CW32
DF32
DN32
DY32
EG32
EP32
CU29
DD29
CW4
DF4
DN4
DY4
DG
2
DK2
DP2
DU2
EA2
ED2
EH2
EL2
ER2
EV2
(8.4)
DL29
DV29
EE29
EM29
EW29
DM
1
(9.2)
(9.6)
DR1
(10.85)
DW
EB1
EF1
EJ1
EN1
ET1
EY1
1
EG4
EG22
EP4
EP20
EP22
EU26
FC25
FJ25
(1.2) TYP
EW10
FA15
FF14
FB2
FE2
FA32
FC19
FJ19
FC23
FC28
FC3
FC6
FC9
FD1
FF8
FF18
FF21
FF24
FF27
FF30
FF33
FF5
FF11
FG1
FH2
FJ3
FJ6
FJ9
FJ16
FJ23
FJ28
FJ31
FJ12
354X (Ø0.3)
(1.43)
(3.42)
(0.5) TYP
(0.7)
(2.72)
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
SCALE: 5X
4226484/D 08/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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