DS160PR410RNQR [TI]

4 通道 PCI Express 第 4 代线性转接驱动器 | RNQ | 40 | -40 to 85;


型号：	DS160PR410RNQR
厂家：	TEXAS INSTRUMENTS
描述：	4 通道 PCI Express 第 4 代线性转接驱动器 \| RNQ \| 40 \| -40 to 85 PC 驱动驱动器
文件：	总32页 (文件大小：1214K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DS160PR410

ZHCSK36 –AUGUST 2019

DS160PR410 四通道 PCI-Express 第 4 代线性转接驱动器

1 特性

3 说明

•

四通道线性均衡器，可支持第 1/2/3/4 代 PCIe 传输

速率高达 16Gbps 的接口

DS160PR410 器件是一款低功耗高性能线性中继器/转

接驱动器，专为支持第 1、2、3 和 4 代 PCIe 而设

计。接收器的连续时间线性均衡器 (CTLE) 提供可编程

高频增强功能，后接一个线性输出驱动器。CTLE 接收

器能够打开一个因码间串扰 (ISI)（由 PC 电路板引线

或铜质同轴电缆等互连介质引起）而完全关闭的输入眼

型状态。可编程的均衡能够可在互连通道内的实体布局

方面实现最大限度的灵活性并提高通道的总体性能。

•

提供均衡功能，以处理高达 45dB 的 PCIe 通道

8GHz 下高达 18dB 的 CTLE 升压有助于扩展通道

长度

•

针对 PCIe 用例的自动接收器检测

与协议无关的线性转接驱动器可无缝支持 PCIe 链

接训练

•

支持高达 25Gbps 的数据速率，包括超级路径互联

DS160PR410 保留了发射预设信号的特性，因此允许

主机控制器和终点协商发射均衡器系数。这种链路协商

协议的透明管理有助于实现系统级互操作性并最大程度

地减小延迟。

(UPI)

•

100ps 的超低延迟

160fs 的低附加随机抖动

3.3V 单电源

130mW/通道的低有功功率支持在无散热器的情况

下运行

可通过软件（SMBus 或 I2C）、直接从外部

EEPROM 加载或使用引脚控制来轻松应用可编程设

置。在 EEPROM 模式下，配置信息在加电时自动加

载，这样就免除了对于外部微控制器或软件驱动程序的

需要。

•

引脚搭接、SMBus 或 EEPROM 编程

通过一个或多个 DS160PR410 支持 x2、x4、x8、

x16 PCIe 总线宽度

•

–40ºC 至 85ºC 的工业温度范围

4mm × 6mm 40 引脚 WQFN 封装

器件信息⁽¹⁾

器件型号

封装

WQFN (40)

封装尺寸（标称值）

2 应用

DS160PR410

4.00mm × 6.00mm

•

机架式服务器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

高性能计算

微服务器和塔式服务器

网络附加存储、存储附加网络

硬件加速器

主机总线适配器、网络接口卡

台式计算机/主板

典型应用

PCIe

End Point

PCIe Root

Complex

Pre-Channel

Post-Channel

DS160PR410

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS645

DS160PR410

ZHCSK36 –AUGUST 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 12

7.5 Programming........................................................... 12

Application and Implementation ........................ 15

8.1 Application Information............................................ 15

8.2 Typical Applications ................................................ 15

Power Supply Recommendations...................... 22

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 DC Electrical Characteristics .................................... 6

6.6 High Speed Electrical Characteristics....................... 7

6.7 SMBUS/I2C Timing Charateristics............................ 8

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

7.3 Feature Description................................................. 10

10 Layout................................................................... 22

10.1 Layout Guidelines ................................................. 22

10.2 Layout Example .................................................... 23

11 器件和文档支持 ..................................................... 24

11.1 文档支持 ............................................................... 24

11.2 接收文档更新通知 ................................................. 24

11.3 社区资源................................................................ 24

11.4 商标....................................................................... 24

11.5 静电放电警告......................................................... 24

11.6 Glossary................................................................ 24

12 机械、封装和可订购信息....................................... 24

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

8 月2019 年

初始发行版。

DS160PR410

www.ti.com.cn

ZHCSK36 –AUGUST 2019

5 Pin Configuration and Functions

RNQ Package

40-Pin WQFN

Top View

EN_SMB

SCL

RX_DET

PWDN2

RSVD

SDA

GAIN

Thermal

Pad

EQ1_ADDR1

EQ0_ADDR0

ALL_DONE_N

VOD

READ_EN_N

PWDN1

Not to scale

Pin Functions

I/O, TYPE

DESCRIPTION

NAME

ALL_DONE_N

NO.

Indicates the completion of a valid EEPROM register load operation when in SMBus/I2C

Master Mode (EN_SMB = L1):

High: External EEPROM load failed or incomplete

Low: External EEPROM load successful and complete

When in SMBus/I2C slave mode (EN_SMB = L3), this output will be High-Z until

READ_EN_N is driven low, at which point ALL_DONE_N will be driven low.

External pullup required for operation. TI recommends a 4.7k value.

O, 3.3-V open

drain

EN_SMB

Four-level control input used to select SMBus / I2C or Pin control.

The four defined levels are:

L0: Pin mode

L1: I2C or SMBus Master Mode

L2: RESERVED

I, 4-level

L3: I2C or SMBus Slave Mode

EQ0_ADDR0

EQ1_ADDR1

I, 4-level

The 4-Level Control Input pins of DS160PR410 is defined according to 表 3.

If EN_SMB = L1 or L3, the pins are used to set the I2C or SMBus address of the device. The

pin state is read on power up and decoded according to 表 4.

If EN_SMB = L0, the pins are decoded at power up to control the CTLE boost setting

according to 表 1.

GAIN

Sets DC gain of CTLE at power up.

L0: Reserved

I, 4-level

L1: Reserved

L2: 0 dB

L3: 3.5 dB

GND

EP is the Exposed Pad at the bottom of the WQFN package. It is used as the GND return for

the device. The EP should be connected to ground plane(s) through low resistance path. A

via array provides a low impedance path to GND, and also improves thermal dissipation.

1, 14, 15,

27, 28

No connect

—

DS160PR410

ZHCSK36 –AUGUST 2019

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NO.

PWDN1

Two-level logic controlling the operating state of the redriver.

High: Power down for channels 0 and 1

Low: Power up, normal operation for channels 0 and 1.

I, 3.3-V

LVCMOS

PWDN2

Two-level logic controlling the operating state of the redriver.

High: Power down for channels 2 and 3

Low: Power up, normal operation for channels 2 and 3.

I, 3.3-V

LVCMOS

READ_EN_N

SMBus / I2C Master Mode (with EN_SMB = L1): When asserted low, initiates the SMBus /

I2C master mode EEPROM read function. When the EEPROM read is complete (indicated

by assertion of ALL_DONE_N low), this pin can be held low for normal device operation.

SMBus / I2C Slave Mode (with EN_SMB = L3): When asserted low, this causes the device to

be held in reset (I2C state machine reset and register reset). This pin should be pulled high

to 3.3 V with a external 4.7-kΩ pullup for normal operation in SMBus / I2C Slave Mode or in

pin control mode.

I, 3.3-V

LVCMOS

RSVD

—

Reserved use for TI. The pin must be left floating (NC).

RX_DET

The RX_DET pin controls the receiver detect function. Depending on the input level, a 50-Ω

or >50-kΩ termination to the power rail is enabled. See 表 2 for details.

I, 4-level

RX0N

RX0P

RX1N

RX1P

RX2N

RX2P

RX3N

RX3P

SCL

Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects

RXP to RXN. Channel 0.

Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor

connects RXP to RXN. Channel 0.

Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects

RXP to RXN. Channel 1.

Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor

connects RXP to RXN. Channel 1.

Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects

RXP to RXN. Channel 2.

Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor

connects RXP to RXN. Channel 2.

Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects

RXP to RXN. Channel 3.

Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor

connects RXP to RXN. Channel 3.

I/O, 3.3-V

LVCMOS,

open drain

SMBus / I2C clock input / open-drain output. External 1-kΩ to 5-kΩ pullup resistor is required

as per SMBus / I2C interface standard. This pin is 3.3-V tolerant.

SDA

I/O, 3.3-V

LVCMOS,

open drain

SMBus / I2C data input / open-drain clock output. External 1-kΩ to 5-kΩ pullup resistor is

required as per SMBus interface standard. This pin is 3.3-V tolerant.

TX0N

TX0P

TX1N

TX1P

TX2N

TX2P

TX3N

TX3P

VDD

Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for

RX detection at power up. Channel 0.

Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used

for RX detection at power up. Channel 0.

Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for

RX detection at power up. Channel 1.

Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used

for RX detection at power up. Channel 1.

Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for

RX detection at power up. Channel 2.

Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used

for RX detection at power up. Channel 2.

Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for

RX detection at power up. Channel 3.

Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used

for RX detection at power up. Channel 3.

31, 34, 35,

Power supply pins. V_DD= 3.3 V ±10%. The VDD pins on this device should be connected

through a low-resistance path to the board VDD plane.

DS160PR410

www.ti.com.cn

ZHCSK36 –AUGUST 2019

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NO.

VOD

Sets TX VOD setting at power up.

L0: –6 dB

I, 4-level

L1: –3.5 dB

L2: 0 dB

L3: –1.6 dB

VREG

Internal voltage regulator output. Must add decoupling caps of 0.1 µF near each pins. The

regulator is only for internal use. Do not use to power any external components.

11, 18

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

4.0

UNIT

VDD_ABSMAX

VIO_CMOS,ABSMAX

VIO_4LVL,ABSMAX

VIO_HS,ABSMAX

T_J,ABSMAX

Supply Voltage (VDD)

3.3 V LVCMOS and Open Drain I/O voltage

4-level Input I/O voltage

4.0

2.75

150

High-speed I/O voltage (RXnP, RXnN, TXnP, TXnN)

Junction temperature

°C

T_stg

Storage temperature range

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV

may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

DC plus AC power should not

exceed these limits

VDD

N_VDD

Supply voltage, VDD to GND

Supply noise tolerance

3.0

3.3

3.6

Supply noise, DC to <50 Hz,

sinusoidal¹

250

mVpp

Supply noise, 50 Hz to 10 MHz,

sinusoidal¹

Supply noise, >10 MHz,

sinusoidal¹

T_RampVDD

VDD supply ramp time

From 0 V to 3.0 V

0.150

–40

100

125

T_J

Operating junction temperature

Operating ambient temperature

Minimum pulse width required for

T_A

–40

PW_LVCMOSthe device to detect a valid signal PWDN1/2, READ_EN_N

on LVCMOS inputs

100

SMBus SDA and SCL Open

Drain Termination Voltage

Supply voltage for open drain

pull-up resistor

VDD_SMBUS

3.6

SMBus clock (SCL) frequency in

SMBus slave mode

F_SMBus

400

kHz

DS160PR410

ZHCSK36 –AUGUST 2019

www.ti.com.cn

Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

800

NOM

MAX

1200

UNIT

mVpp

Gbps

Source differential launch

VID_LAUNCH

amplitude

Data rate

6.4 Thermal Information

DS160PR410

THERMAL METRIC⁽¹⁾

UNIT

RNQ, 40 Pins

R_θJA-High

Junction-to-ambient thermal resistance

31.1

℃/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

21.4

12.1

0.3

℃/W

ψ_JT

ψ_JB

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

12.1

4.1

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power

Device current consumption when all

four channels are active

All four channels enabled with VOD =

I_ACTIVE

150

200

110

Device current consumption when two Two channels enabled with VOD = L2,

channels are active PWDN1 or PWDN2=L

I_ACTIVE-HALF

I_STBY

Device current consumption in standby All four channels disabled (PWDN1,2

power mode

= H)

V_REG

Internal regulator output

2.5

Control IO

SDA, SCL, PWDN1, PWDN2,

READ_EN_N pins

V_IH

V_IL

High level input voltage

Low level input voltage

High level output voltage

Low level output voltage

Input high leakage current

2.1

SDA, SCL, PWDN1, PWDN2,

READ_EN_N pins

1.08

R_pull-up= 100K (SDA, SCL,

ALL_DONE_N pins)

V_OH

V_OL

I_IH

I_OL= –4 mA (SDA, SCL,

ALL_DONE_N pins)

0.4

V_Input= VDD, (SCL, SDA, PWDN1,

PWDN2, READ_EN_N pins)

µA

V_Input= 0 V, (SCL, SDA, PWDN1,

PWDN2, READ_EN_N pins)

I_IL

Input low leakage current

Input capacitance

-10

µA

C_IN-CTRL

1.5

4 Level IOs (EQ0_ADDR0, EQ1_ADDR1, EN_SMB, RX_DET, VOD, GAIN pins)

I_{IH_4L}

Input high leakage current, 4 level IOs VIN=2.5V

Input low leakage current, , 4 level IOs VIN=GND

µA

I_{IL_4L}

-150

Receiver

Z_RX-DC

Rx DC Single-Ended Impedance

Rx DC Differential Impedance

Ω

Z_RX-DIFF-DC

Transmitter

100

Impedance of Tx during active

signaling, VID,diff=1Vpp

Z_TX-DIFF-DC

DC Differential Tx Impedance

100

Ω

DS160PR410

www.ti.com.cn

ZHCSK36 –AUGUST 2019

DC Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total current the Tx can supply when

shorted to GND

I_TX-SHORT

Tx Short Circuit Current

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TYP

MAX

UNIT

Receiver

XT_RX

Minimum pair-to-pair isolation

(SDD21) between two adjacent

receiver pairs from 10 MHz to 8 GHz.

Receive-side pair-to-pair isolation

-45

Transmitter

Measured with lowest EQ, VOD = L2;

PRBS-7, 16 Gbps, over at least

10⁶bits using a bandpass-Pass Filter

from 30Khz-500Mhz

Tx AC Peak-to-Peak Common Mode

Voltage

V_TX-AC-CM-PP

mVpp

V_TX-CM-DC= |V_OUTn++ V_OUTn–|/2,

Measured by taking the absolute

difference of V_TX-CM-DCduring PCIe

state L0 and Electrical Idle

V_TX-CM-DC-

ACTIVE-IDLE-

DELTA

Absolute Delta of DC Common Mode

Voltage during L0 and Electrical Idle

100

Absolute Delta of DC Common Mode

Voltage between V_OUTn+and V_OUTn–

during L0

Measured by taking the absolute

difference of V_OUTn+and V_OUTn–during

PCIe state L0

V_TX-CM-DC-

LINE-DELTA

Measured by taking the absolute

difference of V_OUTn+and V_OUTn–during

Electrical Idle, Measured with a band-

pass filter consisting of two first-order

filters. The High-Pass and Low-

Pass –3-dB bandwidths are 10 kHz

and 1.25 GHz, respectively - zero at

input

V_{TX-IDLE-DIFF-}AC Electrical Idle Differential Output

Voltage

AC-p

Measured by taking the absolute

difference of V_OUTn+and V_OUTn–during

Electrical Idle, Measured with a first-

order Low-Pass Filter with –3-dB

bandwidth of 10 kHz

V_{TX-IDLE-DIFF-}DC Electrical Idle Differential Output

Voltage

Measured while Tx is sensing whether

a low-impedance Receiver is present.

No load is connected to the driver

output

V_TX-RCV-

DETECT

Amount of Voltage change allowed

during Receiver Detection

600

Minimum pair-to-pair isolation

(SDD21) between two adjacent

transmitter pairs from 10 MHz to 8

GHz.

XT_TX

Transmit-side pair-to-pair isolation

-45

Device Datapath

Input-to-output latency (propagation

Measured by observing propagation

delay during either Low-to-High or

High-to-Low transition

T_PLHD/PHLD

100

130

delay) through a channel

Measured between any two lanes

within a single transmitter

L_TX-SKEW

Lane-to-Lane Output Skew

Difference between measurement

through redriver and baseline setup

with 16Gbps PRBS15 with minimum

input and output channels with

minimum EQ setting.

T_TX-DJ-ADD

Added Deterministic Jitter

2.5

DS160PR410

ZHCSK36 –AUGUST 2019

www.ti.com.cn

High Speed Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Difference between measurement

through redriver and baseline setup

with 16Gbps PRBS15 with minimum

input and output channels with

minimum EQ setting.

T_TX-RJ-ADD

Additive Random Jitter

160

200

fs RMS

DCGAIN_VAR,

max

Maximum DC gain variation

Maximum EQ boost variation

Input amplitude linear range. The

VOD=L2, GAIN=L2, min EQ setting

-1.5

-3.0

1.5

3.0

ACGAIN_VAR,

max

VOD=L2, GAIN=L2, max EQ setting,

at 8Ghz

Measured with the highest wide-band

gain setting (VOD = L2,). Measured

with minimal input channel and

minimum EQ using 128T pattern at 2.5

Gbps.

LINEARITY_Dmaximum VID for which the repeater

800

750

mVpp

remains linear, defined as ≤1 dB

compression of Vout/Vin.

Measured with the highest wide-band

gain setting (VOD = L2,). Measured

with minimal input channel and

minimum EQ using 1T pattern at 16

Gbps

Input amplitude linear range. The

LINEARITY_Amaximum VID for which the repeater

remains linear, defined as ≤1 dB

compression of Vout/Vin.

Difference between measurement

through redriver and baseline setup

with 8Ghz clock signals, lowest EQ

JITTER_INTRINRedriver intrinsic additive Random

160

0.4

2.5

190

1.2

3.5

Jitter (RMS)

SIC-RJ

Difference between measurement

through redriver and baseline setup

with 8Ghz clock signals, lowest EQ

JITTER_INTRINRedriver intrinsic additive Deterministic

Jitter

SIC-DJ

Difference between measurement

through redriver and baseline setup

with 8Ghz clock signals, lowest EQ

JITTER_INTRIN

SIC-TOTAL

Redriver intrinsic additive Total Jitter

6.7 SMBUS/I2C Timing Charateristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Slave Mode

T_SDA-HD

T_SDA-SU

T_SDA-R

Data hold time

0.75

100

150

4.5

Data setup time

SDA rise time, read operation

SDA fall time, read operation

Pull-up resistor = 1 kΩ, Cb = 50pF

T_SDA-F

Master Mode

f_SCL

SCL clock frequency

SCL low period

EN_SMB = L3 (Master Mode)

260

1.66

1.22

303

1.90

1.40

0.6

346

2.21

1.63

kHz

µs

T_SCL-LOW

T_SCL-HIGH

T_HD-START

T_SU-START

T_SDA-HD

T_SDA-SU

T_SU-STOP

T_BUF

SCL high period

Hold time start operation

Setup time start operation

Data hold time

0.6

0.9

Data setup time

0.1

Stop condition setup time

Bus free time between Stop-Start

SCL rise time

0.6

1.3

T_SDC-R

Pull-up resistor = 1 kΩ

300

T_SDC-F

SCL fall time

EEPROM Timing

DS160PR410

www.ti.com.cn

ZHCSK36 –AUGUST 2019

SMBUS/I2C Timing Charateristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Time to assert ALL_DONE_N after

READ_EN_N has been asserted.

Single device reading its configuration

from an EEPROM with common

channel configuration. This time scales

with the number of devices reading

from the same EEPROM. Does not

include power-on reset time.

T_EEPROM

EEPROM configuration load time

Time to assert ALL_DONE_N after

READ_EN_N has been

asserted. Single device reading its

configuration from an EEPROM. Non-

common channel configuration. This

time scales with the number of devices

reading from the same EEPROM.

Does not include power-on reset time.

T_EEPROM

EEPROM configuration load time

Internal power-on reset (PoR) stretch

between stable power supply and de-

assertion of internal PoR. The SMBus

address is latched on the completion

of the PoR stretch, and SMBus

accesses are permitted once PoR

completes.

T_POR

Power-on reset assertion time

DS160PR410

ZHCSK36 –AUGUST 2019

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7 Detailed Description

7.1 Overview

The DS160PR410 is a four-channel multi-rate linear repeater with integrated signal conditioning. The four

channels operate independently from one another. Each channel includes a continuous-time linear equalizer

(CTLE) and a linear output driver, which together compensate for a lossy transmission channel between the

source transmitter and the final receiver. The linearity of the data path is specifically designed to preserve any

transmit equalization while keeping receiver equalization effective.

The DS160PR410 can be configured three different ways: through control pins (pin mode), SMBus/I²C, or

EEPROM. The device is configurable through a single SMBus or I²C port. The DS160PR410 can also act as a

SMBus master to configure itself from an EEPROM. Pin-only control can also be used for most applications.

7.2 Functional Block Diagram

One Channel of Four

Term

RXnP

RXnN

TXnP

TXnN

CTLE

Linear Driver

Receiver

Detect

Shared Digital

EQ1_ADDR1

EQ0_ADDR0

Power-On

Reset

Always-On

10MHz

Shared Digital Core

SCL

SDA

READ_EN_N

ALL_DONE_N

EN_SMB

PWDN

7.3 Feature Description

7.3.1 Linear Equalization

The DS160PR410 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost

and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive

channel. 表 1 shows available equalization boost through EQ0_ADDR0 and EQ1_ADDR1 control pins, when in

Pin Control mode (EN_SMB=L0).

表 1. Equalization Control Settings

EQUALIZATION SETTING

TYPICAL EQ BOOST

INDEX

EQ1_ADDR1

EQ0_ADDR0

@ 4 GHz

–0.3

0.4

@ 8 GHz

–0.8

1.3

3.3

5.7

3.8

7.1

DS160PR410

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ZHCSK36 –AUGUST 2019

Feature Description (接下页)

表 1. Equalization Control Settings (接下页)

EQUALIZATION SETTING

EQ1_ADDR1

TYPICAL EQ BOOST

INDEX

EQ0_ADDR0

@ 4 GHz

4.9

@ 8 GHz

8.4

5.2

9.1

5.4

9.8

6.5

10.7

11.3

12.6

13.6

14.4

15.0

15.9

16.5

17.8

6.7

7.7

8.7

9.1

9.4

10.3

10.6

11.8

The equalization of the device can also be set by writing to SMBus/I²C registers in slave or master mode. Refer

to the DS160PR410 Programming Guide (SNLU255) for details.

7.3.2 DC Gain

The VOD or GAIN pins can be used to set the overall datapath DC (low frequency) gain of the DS160PR410 as

outlined in the Pin Configuration and Functions section.

It is advised that the DC gain and equalization of the DS160PR410 are set such that the signal swing at DC and

high frequency does not exceed the DC and AC linearity ranges of the devices, respectively.

7.3.3 Receiver Detect State Machine

The DS160PR410 deploys an RX detect state machine that governs the RX detection cycle as defined in the PCI

express specifications. At power up, after a manually triggered event through PWDN1 and PWDN2 pins (in pin

mode), or writing to the relevant I²C / SMBus register, the redriver determines whether or not a valid PCI express

termination is present at the far end of the link. The RX_DET pin of DS160PR410 provides additional flexibility

for system designers to appropriately set the device in desired mode according to 表 2.

If all four channels of DS160PR410 is used for same PCI express link, the PRWDN1 and PWDN2 pin can be

shorted and driven together.

表 2. Receiver Detect State Machine Settings

PWDN1 and PWDN2

RXDET

COMMENTS

PCI Express RX detection state machine is

enabled. RX detection is asserted after 2x valid

detections.

Pre Detect: Hi-Z, Post Detect: 50 Ω.

PCI Express RX detection state machine is

enabled. RX detection is asserted after 3x valid

detections.

Pre Detect: Hi-Z, Post Detect: 50 Ω.

PCI Express RX detection state machine is

enabled. RX detection is asserted after 1x valid

detection.

L2 (Float)

Pre Detect: Hi-Z, Post Detect: 50 Ω.

DS160PR410

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表 2. Receiver Detect State Machine Settings (接下页)

PWDN1 and PWDN2

RXDET

COMMENTS

PCI Express RX detection state machine is

disabled.

Recommended for non PCI Express interface use

case where the DS160PR410 is used as buffer

with equalization.

Always 50 Ω.

Manual reset, input is high impedance.

7.4 Device Functional Modes

7.4.1 Active PCIe Mode

The device is in normal operation with PCIe state machine enabled by RX_DET=L0/L1/L2. In this mode

PWDN1/PWDN2 pins are driven low in a system (for example by PCIE connector "PRSNT" signal). In this mode,

the DS160PR410 redrives and equalizes PCIe RX or TX signals to provide better signal integrity.

7.4.2 Active Buffer Mode

The device is in normal operation with PCIe state machine disabled by RX_DET=L3. This mode is recommended

for non-PCIe use cases. In this mode the device is working as a buffer to provide linear equalization to improve

signal integrity.

7.4.3 Standby Mode

The device is in standby mode invoked by PWDN1/PWDN2=H. In this mode, the device is in standby mode

conserving power.

7.5 Programming

7.5.1 Control and Configuration Interface

7.5.1.1 Pin Mode

The DS160PR410 can be fully configured through GPIO/Pin-strap pins. In this mode the device uses 2-level and

4-level pins for device control and signal integrity optimum settings. The Pin Configuration and Functions section

defines the control pins.

7.5.1.1.1 Four-Level Control Inputs

The DS160PR410 has six (GAIN, VOD, EQ1_ADDR1, EQ0_ADDR0, EN_SMB, and RX_DET) 4-level inputs pins

that are used to control the configuration of the device. These 4-level inputs use a resistor divider to help set the

4 valid levels and provide a wider range of control settings. External resistors must be of 10% tolerance or better.

表 3. 4-Level Control Pin Settings

LEVEL

SETTING

1 kΩ to GND

13 kΩ to GND

F (Float)

59 kΩ to GND

7.5.1.2 SMBUS/I²C Register Control Interface

If EN_SMB=L3 (SMBus / I²C control mode), the DS160PR410 is configured through a standard I²C or SMBus

interface that may operate up to 400 kHz. The slave address of the DS160PR410 is determined by the pin strap

settings on the EQ1_ADDR1 and EQ0_ADDR0 pins. The device can be configured for best signal integrity and

power settings in the system using the I²C or SMBus interface. The sixteen possible slave addresses (8-bit) for

the DS160PR410 are shown in 表 4.

DS160PR410

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ZHCSK36 –AUGUST 2019

表 4. SMBUS/I2C Slave Address Settings

EQ1_ADDR1

EQ0_ADDR0

ADDRESS (DEC)

ADDRESS (HEX)

The DS160PR410 can also be configured by reading from EEPROM. To enter into this mode SMB_EN must be

set to L1. Refer to the Understanding EEPROM Programming for DS160PR410 PCI-Express Gen-4 Redriver

application report (SNLA320) for details.

7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)

To configure the DS16PR410 for SMBus master mode, set the EN_SMB pin to L1. If the DS160PR410 is

configured for SMBus master mode, it will remain in the SMBus IDLE state until the READ_EN_N pin is asserted

to LOW. After the READ_EN_N pin is driven LOW, the DS160PR410 becomes an SMBus master and attempts

to self-configure by reading device settings stored in an external EEPROM (SMBus 8-bit address 0xA0). When

the DS160PR410 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW

and then change from a SMBus master to a SMBus slave. Not all bits in the register map can be configured

through an EEPROM load. Refer to the Understanding EEPROM Programming for DS160PR410 PCI-Express

Gen-4 Redriver application report (SNLA320) for more information.

When designing a system for using the external EEPROM, the user must follow these specific guidelines:

•

EEPROM size of 2 kb (256 × 8-bit) is recommended.

Set EN_SMB = L1, configure for SMBus master mode

The external EEPROM device address byte must be 0xA0 and capable of 400-kHz operation at 3.3-V supply

图 1 outlines how multiple devices can be configured through single external EEPROM device. 图 1 shows a use

case with four DS160PR410, but the user can cascade and number of DS160PR410 devices in a similar way, for

brevity pullup resistors (for open-drain outputs) are not shown in the block diagram. Tie first device’s

READ_EN_N pin low to automatically initiate EEPROM read at power up. Alternately the READ_EN_N pin of the

first device can also be controlled by a microcontroller to initiate the EEPROM read manually. Leave the final

device’s ALL_DONE_N pin floating, or connect the pin to a microcontroller input to monitor the completion of the

final EEPROM read.

DS160PR410

ZHCSK36 –AUGUST 2019

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EN_SMB

DS160PR410

SDA

SCL

SDA

SCL

8-bit SMBus

address: 0xA0

EEPROM

图 1. Example Daisy Chain for Multiple Device Single EEPROM Configuration

DS160PR410

www.ti.com.cn

ZHCSK36 –AUGUST 2019

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS160PR410 is a high-speed linear repeater which extends the reach of differential channels impaired by

loss from transmission media like PCBs and cables. It can be deployed in a variety of different systems. The

following sections outline typical applications and their associated design considerations.

8.2 Typical Applications

The DS160PR410 is a PCI Express linear redriver that can also be configured as interface agnostic redriver by

disabling its RX detect feature. The device can be used in wide range of interfaces including:

•

PCI Express

Ultra Path Interconnect (UPI)

SATA

SAS

Display Port

DS160PR410

ZHCSK36 –AUGUST 2019

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Typical Applications (接下页)

The DS160PR410 is a protocol agnostic 4-channel linear redriver with PCI Express receiver-detect capability. Its

protocol agnostic nature allows it to be used in PCI Express x2, x4, x8, and x16 applications. 图 2 shows how a

number of DS160PR410 devices can be used to obtain signal conditioning for PCI Express buses of varying

widths. Note all four channels of the DS160PR410 flow in same direction. Therefore, if the device is used for x2

configuration, careful layout consideration is needed. In x2 configuration, the two-channel grouping can be used

for PCIe receiver detect. PWDN1 pin puts channels 1 and 2, and PWDN2 pin puts channels 3 and 4 into

standby.

CPU/

Root

Complex

DS160PR410

CPU/

Root

X2 PCIe

Complex

DS160PR410

Two X2 PCIe

DS160PR410

CPU/

Root

DS160PR410

Complex

DS160PR410

X4 PCIe

CPU/

Root

Complex

DS160PR410

CPU/

Root

Complex

X8 PCIe

X16 PCIe

图 2. PCI Express x2, x4, x8, and x16 Use Cases Using DS160PR410

DS160PR410

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ZHCSK36 –AUGUST 2019

Typical Applications (接下页)

8.2.1 PCIE x4 Lane Configuration

The DS160PR410 can be used in server or motherboard applications to boost transmit and receive signals to

increase the reach of the host or root complex processor to PCI Express slots/connectors. The following design

recommendations can be used in any lane configuration. 图 3 shows a simplified schematic for x4 configuration.

DS160PR410

TX Repeater

RX0P

RX0N

TX0P

TX0N

RX3P

RX3N

TX3P

TX3N

GPIO mode

EN_SMB

Optional pin strap

control for best

signal integrity

VOD

GAIN

1 kΩ

GND

Pin strap to fine

tune EQ gain

settings

EQ0_ADDR0

EQ1_ADDR1

SDA

SDC

RX_DET

ALL_DONE_N

System level

power control

PWDN1,2

READ_EN_N

VREG

GND

0.1ꢀF

(2x)

3.3V

Minimum

recommended

decoupling

VDD

0.1ꢀF

(4x)

1ꢀF

(2x)

Host/Root

complex side

Connector/

Socket Side

DS160PR410

RX Repeater

TX0P

TX0N

RX0P

RX0N

TX3P

TX3N

RX3P

RX3N

GPIO mode

EN_SMB

Optional pin strap

control for best

signal integrity

VOD

GAIN

1 kΩ

GND

Pin strap to fine

tune EQ gain

settings

EQ0_ADDR0

EQ1_ADDR1

SDA

SDC

RX_DET

PWDN1,2

ALL_DONE_N

System level

power control

VREG

GND

READ_EN_N

0.1ꢀF

(2x)

3.3V

Minimum

recommended

decoupling

VDD

0.1ꢀF

(4x)

1ꢀF

(2x)

图 3. Simplified Schematic for PCIe x4 Lane Configuration

DS160PR410

ZHCSK36 –AUGUST 2019

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Typical Applications (接下页)

8.2.1.1 Design Requirements

As with any high-speed design, there are many factors which influence the overall performance. The following list

indicates critical areas for consideration during design.

•

Use 85-Ω impedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N

traces should be done on the single-end segments of the differential pair.

•

Use a uniform trace width and trace spacing for differential pairs.

Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.

For Gen-3 and Gen-4, AC-coupling capacitors of 220 nF are recommended, set the maximum body size to

0402, and add a cutout void on the GND plane below the landing pad of the capacitor to reduce parasitic

capacitance to GND.

•

Back-drill connector vias and signal vias to minimize stub length.

Use reference plane vias to ensure a low inductance path for the return current.

8.2.1.2 Detailed Design Procedure

In PCIe Gen-4 and Gen-3 applications, the specification requires Rx-Tx link training to establish and optimize

signal conditioning settings at 16 Gbps and 8 Gbps, respectively. In link training, the Rx partner requests a series

of FIR – preshoot and deemphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-levels

(6 dB to 12 dB) of CTLE followed by a single tap DFE. The link training would pre-condition the signal, with an

equalized link between the root-complex and endpoint.

Note that there is no link training in PCIe Gen-1 (2.5 Gbps) or PCIe Gen-2 (5.0 Gbps) applications. The

DS160PR410 is placed in between the Tx and Rx. It helps extend the PCB trace reach distance by boosting the

attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx more

easily.

For operation in Gen-4 and Gen-3 links, the DS160PR410 transmit outputs are designed to pass the Tx Preset

signaling onto the Rx for the PCIe Gen-4 or Gen-3 link to train and optimize the equalization settings. The

suggested setting for the DS160PR410 are VOD = 0 dB and DC GAIN = 3.5 dB. Adjustments to the EQ setting

should be performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ

gain settings are provided in 表 1.

The Tx equalization presets or CTLE and DFE coefficients in the Rx can also be adjusted to further improve the

eye opening.

DS160PR410

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Typical Applications (接下页)

图 4 shows as an example for DS160PR410 Typical Connection Schematic.

3.3 V (filtered)

VDD

3.3 V

VDD

10µF

1µF

0.1µF

VDD

0.1µF

VREG

TX0P

TX0N

TX1P

RX0P

RX0N

RX1P

C10

C11

C12

C13

TX1N

TX2P

RX1N

RX2P

High-speed

inputs

High-speed

outputs

C14

C15

C16

TX2N

TX3P

TX3N

RX2N

RX3P

RX3N

3.3 V

4.7k

ALL_DONE_N

READ_EN_N

SDA

SCL

I2C

Control

PWDN1

PWDN2

RSVD

EN_SMB

RX_DET

R₁

NC (x5)

DAP

R₂

VOD

R₃

GAIN

R₄

R₅

R₆

EQ0_ADDR0

EQ1_ADDR1

NOTES:

C₁œ C₁₆= 220 nF (10 V / X7R / 0402)

R₁(see EN_SMB Resistor Values Table)

R₂(see RX_DET Resistor Values Table)

R₃(see VOD Resistor Values Table)

R₄(see GAIN Resistor Values Table)

R₅, R₆(see EQ Control or I2C Slave Address

Settings Table)

DS160PR410

R₃

图 4. DS160PR410 Typical Connection Schematic

DS160PR410

ZHCSK36 –AUGUST 2019

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Typical Applications (接下页)

8.2.1.3 Application Curves

The DS160PR410 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-

compliant TX and RX are equipt with signal-conditioning functions and can handle channel losses of up to 28 dB

at 8 GHz. With the DS160PR410, the total channel loss between a PCIe root complex and an end point can be

up to 45 dB at 8 GHz.

图 5 shows an electric link that models a single channel of a PCIe link and eye diagrams measured at different

locations along the link. The source that models a PCIe TX sends a 16-Gbps PRBS-15 signal with P7 presets.

After a transmission channel with –30 dB at 8-GHz insertion loss, the eye diagram is fully closed. The

DS160PR410 with its CTLE set to the maximum (18-dB boost) together with the source TX equalization

compensates for the losses of the pre-channel (TL1) and opens the eye at the output of the DS160PR410.

The post-channel (TL2) losses mandate the use of PCIe RX equalization functions such as CTLE and DFE that

are normally available in PCIe-compliant receivers.

RX CTLE: 12 dB

PCIe Root

Complex

DS160PR410

PCIe

End Point

TL1

-30 dB @ 8 GHz

TL2

-15 dB @ 8 GHz

Pre-Cursor: 3.5 dB

Post-Cursor: -6 dB

RX EQ Boost: 18 dB

图 5. PCIe Gen-4 Link Reach Extension Using DS160PR410

DS160PR410

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ZHCSK36 –AUGUST 2019

Typical Applications (接下页)

8.2.2 DisplayPort Application

The DS160PR410 can be used as a 4 channel DIsplayPort (DP) redriver for data rates up to 20 Gbps. To use

the device in a non-PCIe application, the RX_DET pin must be pin-strapped to VDD with 59-kΩ resistor (L3).

The DS160PR410 is a linear redriver which is agnostic to DP link training. The DP link training negotiation

between a display source and sink stays effective through the DS160PR410. The redriver becomes part of the

electrical channel along with passive traces, cables, and so forth, resulting into optimum source and sink

parameters for best electrical link.

图 6 shows a simplified schematic for DisplayPort application. Auxiliary and Hot plug detect (HPD) are bypassed

outside of DS160PR410. If system use case requires implementing DP power states, the device must be

controlled by the I2C or the pin-strap pins.

DS160PR410

DP Main Link Redriver

ML0p

RX0P

RX0N

TX0P

TX0N

ML0n

ML3p

RX3P

RX3N

TX3P

TX3N

ML3n

GPIO mode

EN_SMB

Optional pin strap

control for best

signal integrity

VOD

GAIN

1 kΩ

GND

Pin strap to fine

tune EQ gain

settings

EQ0_ADDR0

EQ1_ADDR1

SDA

SDC

3.3V 3.3V

59kꢁ

RX_DET

ALL_DONE_N

59kꢁ

DisplayPort

Source

DisplayPort

Sink

PWDN1,2

READ_EN_N

VREG

GND

0.1ꢀF

(2x)

3.3V

VDD

0.1ꢀF

(4x)

1ꢀF

(2x)

0.1ꢀF

Minimum

recommended

decoupling

100kꢁ

HPD

For brevity AUX

biasing is not shown

AUXp

AUXn

图 6. Simplified Schematic for DisplayPort Application

DS160PR410

ZHCSK36 –AUGUST 2019

www.ti.com.cn

9 Power Supply Recommendations

Follow these general guidelines when designing the power supply:

1. The power supply should be designed to provide the operating conditions outlined in the Recommended

Operating Conditions table in terms of DC voltage, AC noise, and start-up ramp time.

2. The DS160PR410 does not require any special power supply filtering, such as ferrite beads, provided that

the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply

decoupling consists of a 0.1-µF capacitor per VDD pin, one 1.0-µF bulk capacitor per device, and one 10-µF

bulk capacitor per power bus that delivers power to one or more DS160PR410 devices. The local decoupling

(0.1 µF) capacitors must be connected as close to the VDD pins as possible and with minimal path to the

DS160PR410 ground pad.

10 Layout

10.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing the decoupling

capacitors directly underneath the device is recommended if the board design permits.

2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and

impedance controlled.

3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take

care to minimize the via stub, either by transitioning through most/all layers or by back drilling.

4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve signal

integrity by counteracting the pad capacitance.

5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to

the GND planes on other layers. This has the added benefit of improving thermal conductivity from the

device to the board.

DS160PR410

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ZHCSK36 –AUGUST 2019

10.2 Layout Example

Top Layer

Use ac-coupling

capacitors with 0201

package

Ensure high-speed

trace length is

matched with ≤ 5 mils

intra-pair; pair-pair

skew is less critical

Route high-speed

traces as differential

coupled microstrips

(S=2W*) with tight

impedance control

( 10%)

Avoid acute angles

when routing high-

speed traces

Bottom Layer

Use recommended

package footprint and

ground via placement

Place decoupling

capacitors close to

VDD and VREG pins;

minimize ground

loops

Ensure pair-pair gap

is > 5W* for minimal

pair-pair coupling

Add ground pours for

additional isolation

Follow connector

manufacturer

guidelines

*W is a trace width. S is a

gap between adjacent

traces.

图 7. DS160PR410 Layout Example - Sub-Section of a PCIe Riser Card With CEM Connectors

DS160PR410

ZHCSK36 –AUGUST 2019

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《DS160PR410 编程指南》(SNLU255)

德州仪器 (TI)，《了解 DS160PR410 第 4 代 PCI-Express 转接驱动器的 EEPROM 编程》(SNLA320)

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jun-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DS160PR410RNQR

DS160PR410RNQT

ACTIVE

WQFN

RNQ

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 85

PX410

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jun-2022

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DS160PR410RNQR

DS160PR410RNQT

WQFN

RNQ

3000

250

330.0

180.0

12.4

4.3

6.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DS160PR410RNQR

DS160PR410RNQT

WQFN

RNQ

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RNQ0040A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

PIN 1 INDEX AREA

4.1

3.9

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

4.7±0.1

2X 4.4

(0.2) TYP

EXPOSED

THERMAL PAD

36X 0.4

2.8

2.7±0.1

0.25

40X

0.15

PIN 1 ID

0.1

C A

0.5

0.3

(OPTIONAL)

40X

0.05

4222125/B 01/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RNQ0040A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(4.7)

2X (2.1)

6X (0.75)

40X (0.6)

40X (0.2)

SYMM

(1.1)

(3.8)

(2.7)

36X (0.4)

(R0.05) TYP

SYMM

(5.8)

(

0.2) TYP

VIA

LAND PATTERN EXAMPLE

SCALE:15X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222125/B 01/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RNQ0040A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

4X (1.5)

40X (0.6)

40X (0.2)

SYMM

(0.695)

(3.8)

(1.19)

36X (0.4)

(R0.05) TYP

METAL

TYP

6X (1.3)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD

73% PRINTED SOLDER COVERAGE BY AREA

SCALE:18X

4222125/B 01/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DS160PR410RNQR [TI]

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