DS160PR822NJXR [TI]
具有四个 2x2 交叉点多路复用器的 PCIe® 4.0、16Gbps、8 通道线性转接驱动器 | NJX | 64 | -40 to 85;
| 型号： | DS160PR822NJXR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有四个 2x2 交叉点多路复用器的 PCIe® 4.0、16Gbps、8 通道线性转接驱动器 | NJX | 64 | -40 to 85 PC 驱动 复用器 驱动器 |
| 文件： | 总36页 (文件大小：2054K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS160PR822
ZHCSML4 –DECEMBER 2020
DS160PR822 PCIe 4.0 16Gbps8 通道线性转接驱动器，具有四个2x2 交叉点
1 特性
3 说明
• 八通道线性均衡器，支持高达16Gbps 的PCIe 4.0
• 与协议无关的线性转接驱动器支持多种高速接口，
包括UPI、DisplayPort、SAS、SATA、XFI
• 提供四个2x2 交叉点多路复用器功能
• 提供均衡功能，以处理高达42dB 的PCIe 4.0 通道
• CTLE 在8GHz 下可升至18dB
• 90 ps 的超低延迟
• PRBS 数据具有70fs 的低附加随机抖动
• 3.3V 单电源
• 107mW/通道的低有功功率
DS160PR822 是八通道低功耗高性能线性转接驱动
器，专为支持速率高达 16Gbps 的 PCIe 4.0 和 Ultra
Path Interface (UPI) 2.0 而设计。该器件是一款与协议
无关的线性转接驱动器，可通过多种差分接口来运行。
DS160PR822 接收器部署了连续时间线性均衡器
(CTLE)，可提供高频增强。均衡器可以打开由于 PCB
布线或电缆等互连介质引起的码间串扰 (ISI) 而完全关
闭的输入眼图。线性转接驱动器和无源通道作为一个整
体接受链路训练，以便达到出色的传输和接收均衡设
置，从而实现更优的电气链路和尽可能低的延迟。该器
件具有低通道间串扰、低附加抖动和超低的回波损耗，
因此在链路中几乎可用作无源元件。这些器件具有内部
线性稳压器，对板上电源噪声具有高抗扰度，从而为高
速数据路径提供纯净电源。
• 无需散热器
• 引脚搭接、SMBus/I2C 或EEPROM 编程
• 针对PCIe 用例的自动接收器检测
• 无缝支持PCIe 链路训练
• 利用一个或多个DS160PR822，支持x2、x4、
x8、x16、PCIe 总线宽度
• -40°C 至85°C 的工业温度范围
• 64 引脚5.5mm × 10mm WQFN 封装
DS160PR822 在量产期间实施了高速测试，从而确保
可靠的大批量生产。此器件还具有低交流和直流增益变
化，可在各种平台部署中提供一致的均衡功能。
器件信息(1)
2 应用
封装尺寸（标称值）
器件型号
封装
• 机架式服务器
DS160PR822
WQFN (64)
5.5 mm × 10.00 mm
• 微服务器和塔式服务器
• 高性能计算
• 硬件加速器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 网络连接存储
• 存储区域网络(SAN) 和主机总线适配器(HBA) 卡
• 网络接口卡(NIC)
• 台式计算机/主板
x16
x16
TX
RX
PCIe Card-1 (x16)
CPU-1
DS160PR822
Quad 2x2 x-point
RX
Connector-1
TX
x16
x16
x16
x16
RX
TX
PCIe Card-2 (x16)
DS160PR822
Quad 2x2 x-point
TX
CPU-2
x24
x16
RX
Connector-2
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS689
DS160PR822
ZHCSML4 –DECEMBER 2020
www.ti.com.cn
Table of Contents
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................19
7.5 Programming............................................................ 20
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Applications.................................................. 23
9 Power Supply Recommendations................................27
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Example...................................................... 29
11 Device and Documentation Support..........................30
11.1 Receiving Notification of Documentation Updates..30
11.2 Community Resources............................................30
11.3 Trademarks............................................................. 30
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings ....................................... 7
6.2 ESD Ratings .............................................................. 7
6.3 Recommended Operating Conditions ........................7
6.4 Thermal Information ...................................................8
6.5 DC Electrical Characteristics ..................................... 8
6.6 High Speed Electrical Characteristics ........................9
6.7 SMBUS/I2C Timing Characteristics ......................... 10
6.8 Typical Characteristics..............................................12
7 Detailed Description......................................................16
7.1 Overview...................................................................16
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2020
*
Initial release
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English Data Sheet: SNLS689
DS160PR822
ZHCSML4 –DECEMBER 2020
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5 Pin Configuration and Functions
图5-1. NJX Package 64-Pin WQFN Top View
1
RX0P
RX0N
55
55
1
TX0P
TX0N
GND
TX1P
TX1N
VCC
2
2
54
54
53
53
3
3
VREG1
52
52
4
4
RX1P
RX1N
51
51
5
5
50
50
6
6
VCC
RX2P
49
49
TX2P
TX2N
7
7
RX2N
48
48
8
8
47
47
VREG1
GND
RX3P
RX3N
9
9
46
46
10
10
TX3P
TX3N
GND
TX4P
TX4N
GND
11
11
45
45
EP=GND
12
GND 12
44
44
RX4P
RX4N
13
13
43
43
14
14
42
42
15
VREG2 15
41
41
16
16
40
40
RX5P
RX5N
TX5P
17
17
39
39
TX5N
VCC
18
VCC 18
38
38
RX6P
19
19
37
37
TX6P
RX6N 20
20
36
36
TX6N
VREG2
GND 21
21
35
35
22
22
34
34
TX7P
TX7N
RX7P
RX7N
23
23
33
33
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English Data Sheet: SNLS689
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ZHCSML4 –DECEMBER 2020
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Pin Functions
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
In SMBus/I2C Master Mode:
Indicates the completion of a valid EEPROM register load operation. External pullup
resistor such as 4.7 kΩ required for operation.
O, 3.3 V open
drain
ALL_DONE_N
31
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C slave/Pin Mode:
This output is High-Z. The pin can be left floating.
Sets device control configuration modes. 4-level IO pin as defined in 表7-1. The pin
can be exercised at device power up or in normal operation mode.
L0: Pin Mode –device control configuration is done solely by strap pins.
L1: SMBus/I2C Master Mode - device control configuration is read from external
EEPROM. When the device has finished reading from the EEPROM successfully, it will
drive the ALL_DONE_N pin LOW. SMBus/I2C slave operation is available in this mode
before, during or after EEPROM reading. Note during EEPROM reading if the external
SMBus/I2C master wants to access the device registers it must support arbitration.
L2: SMBus/I2C Slave Mode –device control configuration is done by an external
controller with SMBus/I2C master.
MODE
61
I, 4-level
L3 (Float): RESERVED –TI internal test mode.
EQ0_0 / ADDR0
EQ1_0 / ADDR1
59
60
I, 4-level
I, 4-level
In Pin Mode:
Sets receiver linear equalization (CTLE) for channels 0-3 according to 表7-3. These
pins are sampled at device power-up only.
In SMBus/I2C Mode:
Sets SMBus / I2C slave address according to 表7-4. These pins are sampled at device
power-up only.
Sets receiver linear equalization (CTLE) for channels 4-7 according to 表7-3 in Pin
mode. The pin is sampled at device power-up only.
EQ0_1
EQ1_1
27
29
I, 4-level
I, 4-level
Sets receiver linear equalization (CTLE) for channels 4-7 according to 表7-3 in Pin
mode. The pin is sampled at device power-up only.
In Pin Mode:
Flat gain (DC and AC) from the input to the output of the device for channels 0-3. The
pin is sampled at device power-up only.
I, 4-level / I/O,
3.3 V
LVCMOS,
open drain
GAIN0 / SDA
63
28
In SMBus/I2C Mode:
3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /
I2C interface standard.
Flat gain (DC and AC) from the input to the output of the device for channels 4-7 in Pin
mode. The pin is sampled at device power-up only.
GAIN1
GND
I, 4-level
P
Ground reference for the device.
EP, 9, 12, 21,
24, 32, 41, 44,
53, 56, 64
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return
for the device. The EP should be connected to ground plane(s) through low resistance
path. A via array provides a low impedance path to GND. The EP also improves
thermal dissipation.
2-level logic controlling the operating state of the redriver. Active in all device control
modes. The pin has internal 1-MΩ weak pulldown resistor.
High: Power down for channels 0-3
I, 3.3 V
LVCMOS
PD0
PD1
25
26
Low: Power up, normal operation for channels 0-3
2-level logic controlling the operating state of the redriver. Active in all device control
modes. The pin has internal 1-MΩ weak pulldown resistor.
High: Power down for channels 4-7
I, 3.3 V
LVCMOS
Low: Power up, normal operation for channels 4-7
In SMBus/I2C Master Mode:
After device power up, when the pin is low, it initiates the SMBus / I2C master mode
EEPROM read function. Once EEPROM read is complete (indicated by assertion of
ALL_DONE_N low), this pin can be held low for normal device operation. During the
EEPROM load process the device’s signal path is disabled.
In SMBus/I2C Slave and Pin Modes:
I, 3.3 V
LVCMOS
READ_EN_N
57
In these modes the pin is not used. The pin can be left floating. The pin has internal 1-
MΩ weak pulldown resistor.
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English Data Sheet: SNLS689
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ZHCSML4 –DECEMBER 2020
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NAME
PIN
I/O, TYPE
DESCRIPTION
The pin selects the mux path for channels 0-3.
NO.
L: straight data path - RX[0/1/2/3][P/N] connected to TX[0/1/2/3][P/N] through the
redriver.
H: cross data path - RX[0/1/2/3][P/N] connected to TX[1/0/3/2][P/N] through the
I, 3.3 V
LVCMOS
SEL0
58
redriver Active in all device control modes. 59 kΩinternal pull-down.
The pin selects the mux path for channels 4-7.
L: straight data path - RX[4/5/6/7][P/N] connected to TX[4/5/6/7][P/N] through the
redriver.
H: cross data path - RX[4/5/6/7][P/N] connected to TX[5/4/7/6][P/N] through the
I, 3.3 V
LVCMOS
SEL1
30
62
redriver Active in all device control modes. 59 kΩinternal pull-down.
In Pin Mode: Sets receiver detect state machine options according to 表7-2. The pin
is sampled at device power-up only.
I, 4-level / I/O,
3.3 V
LVCMOS,
open drain
RX_DET / SCL
In SMBus/I2C Mode:
3.3V SMBus/I2C clock. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /
I2C interface standard.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 0.
RX0N
RX0P
RX1N
RX1P
RX2N
RX2P
RX3N
RX3P
RX4N
RX4P
RX5N
RX5P
RX6N
RX6P
RX7N
RX7P
2
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Noninverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 0.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 1.
5
Noninverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 1.
4
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 2.
8
Noninverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 2.
7
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 3.
11
10
14
13
17
16
20
19
23
22
Noninverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 3.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 4.
Noninverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 4.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 5.
Noninverting differential inputs to the equalizer. An on-chip, 100 Ωtermination resistor
connects RXP to RXN. Channel 5.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 6.
Noninverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 6.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 7.
Noninverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 7.
TX0N
TX0P
TX1N
TX1P
TX2N
54
55
51
52
48
O
O
O
O
O
Inverting pin for 100 Ω differential driver output. Channel 0.
Non-inverting pin for 100 Ω differential driver output. Channel 0.
Inverting pin for 100 Ω differential driver output. Channel 1.
Non-inverting pin for 100 Ω differential driver output. Channel 1.
Inverting pin for 100 Ω differential driver output. Channel 2.
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English Data Sheet: SNLS689
DS160PR822
ZHCSML4 –DECEMBER 2020
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PIN
I/O, TYPE
DESCRIPTION
NAME
TX2P
TX3N
TX3P
TX4N
TX4P
TX5N
TX5P
TX6N
TX6P
TX7N
TX7P
NO.
49
45
46
42
43
39
40
36
37
33
34
O
O
O
O
O
O
O
O
O
O
O
Non-inverting pin for 100 Ω differential driver output. Channel 2.
Inverting pin for 100 Ω differential driver output. Channel 3.
Non-inverting pin for 100 Ω differential driver output. Channel 3.
Inverting pin for 100 Ω differential driver output. Channel 4.
Non-inverting pin for 100 Ω differential driver output. Channel 4.
Inverting pin for 100 Ω differential driver output. Channel 5.
Non-inverting pin for 100 Ω differential driver output. Channel 5.
Inverting pin for 100 Ω differential driver output. Channel 6.
Non-inverting pin for 100 Ω differential driver output. Channel 6.
Inverting pin for 100 Ω differential driver output. Channel 7.
Non-inverting pin for 100 Ω differential driver output. Channel 7.
Power supply pins. VCC = 3.3 V ±10%. The VCC pins on this device should be
connected through a low-resistance path to the board VCC plane.
VCC
6, 18, 38, 50
3, 47
P
P
Internal voltage regulator output. Must add decoupling caps of 0.1 µF near each pins.
The regulator is only for internal use. Do not use to provide power to any external
component. Do not connect to VREG2.
VREG1
Internal voltage regulator output. Must add decoupling caps of 0.1 µF near each pins.
The regulator is only for internal use. Do not use to provide power to any external
component. Do not connect to VREG1.
VREG2
15, 35
P
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English Data Sheet: SNLS689
DS160PR822
ZHCSML4 –DECEMBER 2020
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCCABSMAX
VIOCMOS,ABSMAX
VIO4LVL,ABSMAX
VIOHS-RX,ABSMAX
VIOHS-TX,ABSMAX
TJ,ABSMAX
Supply voltage (VCC)
4.0
4.0
3.3 V LVCMOS and open drain I/O voltage
4-level input I/O voltage
V
2.75
3.2
V
High-speed I/O voltage (RXnP, RXnN)
High-speed I/O voltage (TXnP, TXnN)
Junction temperature
V
2.75
150
150
V
°C
°C
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±3 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
DC plus AC power should not
exceed these limits
VCC
NVCC
Supply voltage, VCC to GND
Supply noise tolerance1
3.0
3.3
3.6
V
DC to <50 Hz, sinusoidal
50 Hz to 500 kHz, sinusoidal
500 kHz to 2.5 MHz, sinusoidal
>2.5 MHz, sinusoidal
250
100
33
mVpp
mVpp
mVpp
mVpp
ms
10
TRampVCC
VCC supply ramp time
From 0 V to 3.0 V
0.150
–40
–40
100
115
85
TJ
Operating junction temperature
Operating ambient temperature
Minimum pulse width required for
°C
TA
°C
PD1/0, SEL1/0, and
READ_EN_N
PWLVCMOS the device to detect a valid signal
on LVCMOS inputs
200
uS
SMBus/I2C SDA and SCL open
VCCSMBUS
Supply voltage for open drain
pull-up resistor
3.6
V
drain termination voltage
SMBus/I2C clock (SCL) frequency
in SMBus slave mode
FSMBus
10
400
kHz
Source differential launch
VIDLAUNCH
amplitude
800
1
1200
16
mVpp
Gbps
DR
Data rate
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English Data Sheet: SNLS689
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ZHCSML4 –DECEMBER 2020
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6.4 Thermal Information
DS160PR 8
22
THERMAL METRIC(1)
UNIT
NJX, 64
Pins
RθJA-
Junction-to-ambient thermal resistance
22.9
℃/W
High K
RθJC(top) Junction-to-case (top) thermal resistance
9.6
7.2
1.8
7.1
2.5
℃/W
℃/W
℃/W
℃/W
℃/W
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 DC Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
GAIN1/0 = L3 (default)
107
99
mW
mW
POWERCH
Active power per channel
GAIN1/0 = L0
GAIN1/0 = L3
Device current consumption when all
eight channels are active
IACTIVE-8CH
260
360
45
mA
Device current consumption in standby
power mode
ISTBY
VREG
All channels disabled (PD1,0 = H)
30
mA
V
Internal regulator output
2.5
Control IO (SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins)
SDA, SCL, PD1, PD0, READ_EN_N,
SEL1, SEL0 pins
VIH
VIL
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
2.1
2.1
V
V
SDA, SCL, PD1, PD0, READ_EN_N,
SEL1, SEL0 pins
1.08
Rpull-up = 4.7 kΩ (SDA, SCL,
ALL_DONE_N pins)
VOH
VOL
IIH,SEL
IIH
V
IOL = –4 mA (SDA, SCL,
ALL_DONE_N pins)
0.4
80
10
V
Input high leakage current for SEL
pins
VInput = VCC for SEL1, SEL0 pins
µA
µA
µA
VInput = VCC, (SCL, SDA, PD1, PD0,
READ_EN_N pins)
Input high leakage current
Input low leakage current
VInput = 0 V, (SCL, SDA, PD1, PD0,
READ_EN_N, SEL1, SEL0 pins)
IIL
-10
VInput = 3.6 V, VCC = 0 V, (SCL, SDA, ,
PD1, PD0, READ_EN_N, SEL1, SEL0
pins)
Input high leakage current for fail safe
input pins
IIH,FS
200
10
µA
pF
SDA, SCL, PD1, PD0, READ_EN_N,
SEL1, SEL0 pins
CIN-CTRL
Input capacitance
1.5
4 Level IOs (MODE, GAIN0, GAIN1, EQ0_0, EQ1_0, EQ0_1, EQ1_1, RX_DET pins)
IIH_4L
IIL_4L
Input high leakage current, 4 level IOs VIN = 2.5 V
µA
µA
Input low leakage current for all 4 level
VIN = GND
-10
IOs except MODE.
Input low leakage current for MODE
pin
IIL_4L,MODE
VIN = GND
-200
µA
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over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver
VRX-DC-CM
ZRX-DC
RX DC common mode (CM) voltage
Rx DC single-ended impedance
Device is in active or standby state
2.5
50
V
Ω
ZRX-HIGH-IMP- DC input CM input impedance during
Inputs are at CM voltage
20
kΩ
Reset or power-down
DC-POS
Transmitter
Impedance of Tx during active
signaling, VID,diff = 1Vpp
ZTX-DIFF-DC
VTX-DC-CM
ITX-SHORT
DC differential Tx impedance
Tx DC common mode Voltage
Tx Short circuit current
100
Ω
V
0.75
Total current the Tx can supply when
shorted to GND
90
mA
6.6 High Speed Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver
50 MHz to 1.25 GHz
-25
-22
-21
-16
dB
dB
dB
dB
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
RLRX-DIFF
Input differential return loss
Pair-to-pair isolation (SDD21) between
two adjacent receiver pairs from 10
MHz to 8 GHz.
XTRX
Receive-side pair-to-pair isolation
-47
dB
Transmitter
Measured with lowest EQ, VOD = L2;
PRBS-7, 16 Gbps, over at least 10E6
bits using a bandpas filter from 30 Khz
to 500 Mhz
Tx AC peak-to-peak common mode
voltage
VTX-AC-CM-PP
50
mVpp
VTX-CM-DC = |VOUTn+ + VOUTn–|/2,
measured by taking the absolute
difference of VTX-CM-DC during PCIe
state L0 and Electrical Idle
VTX-CM-DC-
Absolute delta of DC common mode
voltage during L0 and Electrical Idle
0
100
10
mV
mV
ACTIVE-IDLE-
DELTA
Absolute delta of DC common mode
voltage between VOUTn+ and VOUTn–
during L0
Measured by taking the absolute
difference of VOUTn+ and VOUTn–
during PCIe state L0
VTX-CM-DC-
LINE-DELTA
Measured by taking the absolute
difference of VOUTn+ and VOUTn–
during Electrical Idle, measured with a
band-pass filter consisting of two first-
order filters. The high-pass and low-
pass -3-dB bandwidths are 10 kHz and
1.25 GHz, respectively - zero at input
VTX-IDLE-DIFF- AC Electrical Idle differential output
0
10
mV
voltage
AC-p
Measured by taking the absolute
difference of VOUTn+ and VOUTn–
during Electrical Idle, measured with a
first-order low-pass Filter with –3-dB
bandwidth of 10 kHz
VTX-IDLE-DIFF- DC Electrical Idle differential output
0
0
5
mV
mV
voltage
DC
Measured while Tx is sensing whether
a low-impedance Receiver is present.
No load is connected to the driver
output
VTX-RCV-
Amount of voltage change allowed
during receiver detection
600
DETECT
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over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
-20
-18
-18
-17
MAX
UNIT
dB
50 MHz to 1.25 GHz
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
dB
RLTX-DIFF
Output differential return loss
dB
dB
Minimum pair-to-pair isolation
(SDD21) between two adjacent
transmitter pairs from 10 MHz to 8
GHz.
XTTX
Transmit-side pair-to-pair isolation
-48
90
dB
Device Datapath
Input-to-output latency (propagation
For either low-to-high or high-to-low
transition.
TPLHD/PHLD
120
20
ps
ps
delay) through a data channel
Between any two lanes within a single
transmitter.
LTX-SKEW
Lane-to-lane output skew
-20
Jitter through redriver minus the
calibration trace. 16Gbps PRBS15.
Minimal input/output
channels. Minimum EQ. 800 mVpp-diff
input swing.
TRJ-DATA
Additive random jitter with data
70
90
4
fs
fs
Jitter through redriver minus the
calibration trace. 8 Ghz CK. Minimal
input/output channels. Minimum EQ.
400 mVpp-diff input swing.
Intrinsic additive random jitter with
clock
TRJ-INTRINSIC
Jitter through redriver minus the
calibration trace. 16 Gbps PRBS15.
Minimal input/output
channels. Minimum EQ. 800 mVpp-diff
input swing.
JITTERTOTAL-
Additive total jitter with data
ps
ps
DATA
Jitter through redriver minus the
calibration trace. 8 Ghz CK. Minimal
input/output channels. Minimum
EQ. 800 mVpp-diff input swing.
JITTERTOTAL-
Intrinsic additive total jitter with clock
1
INTRINSIC
Minimum EQ, GAIN1/0=L0
Minimum EQ, GAIN1/0=L1
Minimum EQ, GAIN1/0=L2
-4.2
-1.8
0.25
dB
dB
dB
FLAT-GAIN
EQ-MAX8G
Flat gain (DC and AC) input to output
Minimum EQ, GAIN1/0=L3 (float,
default)
2
dB
dB
EQ boost at max setting (EQ INDEX = AC gain at 8 GHz relative to gain at
18.0
15)
100 MHz. GAIN1/0=L3 (float, default).
GAIN1/0 = L2, minimum EQ setting.
Max-Min.
DCGAINVAR DC gain variation
EQGAINVAR EQ boost variation
-2.3
-3.3
1.7
3.7
dB
At 8 Ghz. GAIN1/0 = L2, maximum EQ
setting. Max-Min.
dB
GAIN1/0 = L3 (float, default). 128T
pattern at 2.5 Gbps.
LINDC
LINAC
Output DC linearity
Output AC linearity
1000
750
mVpp
mVpp
GAIN1/0 = L3 (float, default). 1T
pattern at 16 Gbps.
6.7 SMBUS/I2C Timing Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Slave Mode
Pulse width of spikes which must be
suppressed by the input filter
tSP
50
ns
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA
0.6
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
µs
µs
THIGH
Set-up time for a repeated START
condition
tSU-STA
0.6
µs
tHD-DAT
tSU-DAT
Data hold time
Data setup time
0
µs
µs
0.1
Rise time of both SDA and SCL
signals
tr
120
2
ns
Pull-up resistor = 4.7 kΩ, Cb = 10pF
Pull-up resistor = 4.7 kΩ, Cb = 10pF
tf
Fall time of both SDA and SCL signals
Set-up time for STOP condition
ns
µs
tSU-STO
0.6
1.3
Bus free time between a STOP and
START condition
tBUF
µs
tVD-DAT
tVD-ACK
Cb
Data valid time
0.9
0.9
µs
µs
pF
Data valid acknowledge time
capacitive load for each bus line
400
Master Mode
fSCL-M
SCL clock frequency
SCL low period
MODE = L1 (Master Mode)
303
1.9
1.4
kHz
µs
tLOW-M
tHIGH-M
SCL high period
µs
Set-up time for a repeated START
condition
tSU-STA-M
2
µs
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA-M
1.5
tSU-DAT-M
tHD-DAT-M
Data setup time
Data hold time
1.4
0.5
µs
µs
Rise time of both SDA and SCL
signals
tR-M
120
ns
Pull-up resistor = 4.7 kΩ, Cb = 10pF
Pull-up resistor = 4.7 kΩ, Cb = 10pF
tF-M
Fall time of both SDA and SCL signals
Stop condition setup time
2
ns
µs
tSU-STO-M
1.5
EEPROM Timing
Time to assert ALL_DONE_N after
READ_EN_N has been asserted.
Single device reading its configuration
from an EEPROM with common
channel configuration with
individual channel settings. This
time scales with the number of devices
reading from the same EEPROM.
Does not include power-on reset time.
TEEPROM
EEPROM configuration load time
7.5
50
ms
ms
Power supply stable after initial ramp.
Includes initial power-on reset time.
TPOR
Time to first SMBus access
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6.8 Typical Characteristics
Equalization Boost vs Frequency
20
EQ=0
EQ=1
EQ=7
EQ=13
EQ=2
EQ=8
EQ=14
EQ=3
EQ=9
EQ=15
EQ=4
EQ=5
18
EQ=6
EQ=10
EQ=11
16
14
12
10
8
EQ=12
6
4
2
0
-2
-4
0.1
1
10
Frequency (GHz)
图6-1. Typical EQ Boost vs Frequency
Equalization over Voltage and Temperature (EQ=15)
22
20
18
16
14
12
10
8
VCC=3.3V, Temp=25C
VCC=3.3V, Temp=-40C
VCC=3.3V, Temp=85C
VCC=3.0V, Temp=25C
VCC=3.0V, Temp=-40C
VCC=3.0V, Temp=85C
VCC=3.6V, Temp=25C
VCC=3.6V, Temp=-40C
VCC=3.6V, Temp=85C
6
4
2
0
0.1
1
10
Frequency (GHz)
图6-2. Typical EQ Boost over Voltage and Temperature with EQ=15
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6.8 Typical Characteristics
Input (RX) Differential Return Loss
0
-4
-8
-12
-16
-20
-24
-28
-32
SDD11
PCIe 4.0 Mask
-36
0
2
4
6
8
10
12
14
16
18
20
Frequency (GHz)
图6-3. Typical RX Differential Return Loss
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6.8 Typical Characteristics
Output (TX) Differential Return Loss
0
-4
-8
-12
-16
-20
-24
-28
-32
SDD22
PCIe 4.0 Mask
-36
0
2
4
6
8
10
12
14
16
18
20
Frequency (GHz)
图6-4. Typical TX Differential Return Loss
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6.8 Typical Characteristics
图6-5. Typical Jitter Characteristics - Top: 16Gbps PRBS15 Input to the Device, Bottom: Output of the Device.
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7 Detailed Description
7.1 Overview
The DS160PR822 is an eight-channel multi-rate linear repeater with integrated signal conditioning. The device
provides quad 2x2 crosspoint mux functionality selectable by pin control or SMBus/I2C. The device's signal
channels operate independently from one another. Each channel includes a continuous-time linear equalizer
(CTLE) and a linear output driver, which together compensate for a lossy transmission channel between the
source transmitter and the final receiver. The linearity of the data path is specifically designed to preserve any
transmit equalization while keeping receiver equalization effective.
The DS160PR822 can be configured three different ways:
Pin Mode – device control configuration is done solely by strap pins. Pin mode is expected to be good enough
for many system implementation needs.
SMBus/I2C Master Mode - device control configuration is read from external EEPROM. When the device has
finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I2C slave
operation is available in this mode before, during or after EEPROM reading. Note during EEPROM reading if the
external SMBus/I2C master wants to access device registers it must support arbitration. The mode is prefferred
when software implementation is not desired.
SMBus/I2C Slave Mode - provides most flexibility. Requires a SMBus/I2C master device to configure the device
through writing to its slave address.
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7.2 Functional Block Diagram
One of Four Dual Cross-Point Modules
RX Detect
Term
Term
RXnP
RXnN
TXnP
TXnN
Linear
Driver
CTLE
CTLE
RXnP
RXnN
TXnP
TXnN
Linear
Driver
Term
Term
RX Detect
RX
Detect
Control
Select
mux
control
CTLE
Control
Driver
Control
VCC
Voltage Regulator
VREG1,2
Power-
On Reset
Always-On
10MHz
Shared Digital Core
GAIN0/SDA
READ_EN_N
ALL_DONE_N
RX_DET/SCL
Shared Digital
GND
7.3 Feature Description
7.3.1 Linear Equalization
The DS160PR822 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost
and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive
channel. 表7-1 shows available equalization boost through EQ control pins (EQ1_0 and EQ0_0 for channels 0-3
and EQ1_1 and EQ0_1 for channels 4-7), when in Pin Control mode (MODE = L0).
表7-1. Equalization Control Settings
EQUALIZATION SETTING
TYPICAL EQ BOOST (dB)
EQ1_0 (Ch 0-3) / EQ1_1 (Ch EQ0_0 (Ch0-3) / EQ0_1 (Ch
EQ INDEX
@ 4 GHz
@ 8 GHz
4-7)
L0
L0
L0
L0
L1
L1
4-7)
L0
L1
L2
L3
L0
L1
0
1
2
3
4
5
0.0
1.5
2.0
2.5
2.7
3.0
-0.2
4.5
5.5
6.5
7.0
8.0
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表7-1. Equalization Control Settings (continued)
EQUALIZATION SETTING
TYPICAL EQ BOOST (dB)
EQ1_0 (Ch 0-3) / EQ1_1 (Ch EQ0_0 (Ch0-3) / EQ0_1 (Ch
EQ INDEX
@ 4 GHz @ 8 GHz
4-7)
L1
L1
L2
L2
L2
L2
L3
L3
L3
L3
4-7)
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
6
7
4.0
5.0
6.0
7.0
7.5
8.0
8.5
9.5
10.0
11.0
9.0
10.0
11.0
12.0
13.0
13.5
15.0
16.5
17.0
18.0
8
9
10
11
12
13
14
15
The equalization of the device can also be set by writing to SMBus/I2C registers in slave or master mode. Refer
to the DS160PR822 Programming Guide (SNLU279) for details.
7.3.2 Flat Gain
The GAIN1 and GAIN0 pins can be used to set the overall datapath flat gain (DC and AC) of the DS160PR822
when the device is in Pin Mode. The pin GAIN0 sets the flat gain for channels 0-3 and GAIN1 sets the same for
channels 4-7. The default recommendation for most systems will be GAIN1,0 = L3 (float).
The flat gain and equalization of the DS160PR822 must be set such that the output signal swing at DC and high
frequency does not exceed the DC and AC linearity ranges of the devices, respectively.
7.3.3 Receiver Detect State Machine
The DS160PR822 deploys an RX detect state machine that governs the RX detection cycle as defined in the
PCI express specifications. At power up, after a manually triggered event through PD0 and/or PD1 pins (in pin
mode), or writing to the relevant I2C/SMBus register, the redriver determines whether or not a valid PCI express
termination is present at the far end of the link. The RX_DET pin of DS160PR822 provides additional flexibility
for system designers to appropriately set the device in desired mode according to 表 7-2. PD0 and PD1 pins
impact channel groups 0-3 and 4-7 respectively. If all eight channels of DS160PR822 is used for a same PCI
express link, the PD1 and PD0 pins can be shorted and driven together. For most applications the RX_DET pin
can be left floating for default settings. Note mux selection pins SEL0 and SEL1 also triggers the RX detect state
machine.
表7-2. Receiver Detect State Machine Settings
Channels 0-3
RX_DET RX Common-mode
Impedance
Channels 4-7
RX Common-mode
Impedance
PD0
PD1
COMMENTS
PCI Express RX detection state machine is
disabled. Recommended for non PCIe interface
use case where the DS160PR822 is used as
buffer with equalization.
L
L
L0
Always 50Ω
Always 50Ω
TX polls every ~150us until valid termination is
detected. RX CM impedance held at Hi-Z until
detection Reset by asserting PD0/1 high for
200µs then low.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
L
L
L3 (Float)
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Reset Channels 0-3 signal path and set their RX
impedance to Hi-Z
H
L
L
X
X
Hi-Z
H
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Hi-Z
Reset Channels 4-7 signal path and set their RX
impedance to Hi-Z.
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表7-2. Receiver Detect State Machine Settings (continued)
Channels 0-3
RX_DET RX Common-mode
Impedance
Channels 4-7
RX Common-mode
Impedance
PD0
PD1
COMMENTS
H
H
X
Hi-Z
Hi-Z
7.3.4 Cross Point
The DS160PR822 provides quad 2x2 cross-point function. Using pin SEL1, SEL0 pins the 8 channel signal
paths can be configured as staright connection or quad cross connections. SEL1 pin impacts channel 0-3 and
SEL1 configures channels 4-7.
SEL0=H
(Ch 0-3)
SEL0=L
(Ch 0-3)
RX0
RX1
TX0
TX1
RX0
RX1
TX0
TX1
RX2
RX3
TX2
TX3
RX2
RX3
TX2
TX3
RX4
RX5
TX4
TX5
RX4
RX5
TX4
TX5
RX6
RX7
TX6
TX7
RX6
RX7
TX6
TX7
SEL1=H
(Ch 4-7)
SEL1=L
(Ch 4-7)
图7-1. DS160PR822 Signal Flow Diagram for Cross-Point Mux Operation
7.4 Device Functional Modes
7.4.1 Active PCIe Mode
The device is in normal operation with PCIe state machine enabled by RX_DET = L1/L2/L3. In this mode
PD0/PD1 pins are driven low in a system (for example by PCIE connector "PRSNT" signal). In this mode, the
DS160PR822 redrives and equalizes PCIe RX or TX signals to provide better signal integrity.
7.4.2 Active Buffer Mode
The device is in normal operation with PCIe state machine disabled by RX_DET = L0. This mode is
recommended for non-PCIe use cases. In this mode the device is working as a buffer to provide linear
equalization to improve signal integrity.
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7.4.3 Standby Mode
The device is in standby mode invoked by PD1,0 = H. In this mode, the device is in standby mode conserving
power.
7.5 Programming
7.5.1 Control and Configuration Interface
7.5.1.1 Pin Mode
The DS160PR822 can be fully configured through pin-strap pins. In this mode the device uses 2-level and 4-
level pins for device control and signal integrity optimum settings. The 节5 section defines the control pins.
7.5.1.1.1 Four-Level Control Inputs
The DS160PR822 has 4-level inputs pins (EQ0_0, EQ1_0, EQ0_1, EQ1_1, GAIN0, GAIN1, MODE, and
RX_DET) that are used to control the configuration of the device. These 4-level inputs use a resistor divider to
help set the 4 valid levels and provide a wider range of control settings. External resistors must be of 10%
tolerance or better. The pins are sampled at power-up only. The MODE pin can be exercised at device power up
or in normal operation mode.
表7-3. 4-Level Control Pin Settings
LEVEL
L0
SETTING
1 kΩ to GND
13 kΩ to GND
59 kΩ to GND
F (Float)
L1
L2
L3
7.5.1.2 SMBUS/I2C Register Control Interface
If MODE = L2 (SMBus / I2C slave control mode), the DS160PR822 is configured for best signal integrity through
a standard I2C or SMBus interface that may operate up to 400 kHz. The slave address of the device is
determined by the pin strap settings on the ADDR1 and ADDR0 pins. Note slave addresses to access channel
0-3 and Channels 4-7 is different. Channel bank 4-7 has address which is Channel bank 0-3 address +1. The
sixteen possible slave addresses (8-bit) for each channel banks of the the device are shown in 表 7-4. In
SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of
the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 50
pF.
Refer to the DS160PR822 Programming Guide (SNLU279) for register map details.
表7-4. SMBUS/I2C Slave Address Settings
7-bit Slave Address Channels
ADDR1
ADDR0
7-bit Slave Address Channels 4-7
0-3
L0
L0
L0
L0
L1
L1
L1
L1
L2
L2
L2
L2
L0
L1
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x19
0x1B
0x1D
0x1F
0x21
0x23
0x25
0x27
0x29
0x2B
0x2D
0x2F
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表7-4. SMBUS/I2C Slave Address Settings (continued)
7-bit Slave Address Channels
ADDR1
ADDR0
7-bit Slave Address Channels 4-7
0-3
L3
L3
L3
L3
L0
L1
L2
L3
0x30
0x32
0x34
0x36
0x31
0x33
0x35
0x37
7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
The DS160PR822 can also be configured by reading from EEPROM. To enter into this mode MODE pin must be
set to L1. The EEPROM load operation only happens once after device's initial power-up. If the device is
configured for SMBus master mode, it will remain in the SMBus IDLE state until the READ_EN_N pin is asserted
to LOW. After the READ_EN_N pin is driven LOW, the device becomes an SMBus master and attempts to self-
configure by reading device settings stored in an external EEPROM (SMBus 8-bit address 0xA0). When the
device has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I2C
slave operation is available in this mode before, during or after EEPROM reading. Note during EEPROM reading
if the external SMBus/I2C master wants to access the device registers it must support arbitration. Refer to the
Understanding EEPROM Programming for PCI-Express 4.0 Redrivers (SNLA342) application report for more
information.
When designing a system for using the external EEPROM, the user must follow these specific guidelines:
• EEPROM size of 2 kb (256 × 8-bit) is recommended.
• Set MODE = L1, configure for SMBus master mode
• The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 3.3 V supply
• In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value
of the resistor depends on total bus capacitance. 4.7 kΩis a good first approximation for a bus capacitance
of 10 pF.
图 7-2 shows a use case with four DS160PR822 to implement a 2x2 crosspoint for a x8 link configuration, but
the user can cascade any number of DS160PR822 devices in a similar way. Tie first device’s READ_EN_N pin
low to automatically initiate EEPROM read at power up. Alternately the READ_EN_N pin of the first device can
also be controlled by a microcontroller to initiate the EEPROM read manually. Leave the final device’s
ALL_DONE_N pin floating, or connect the pin to a microcontroller input to monitor the completion of the final
EEPROM read.
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VCC
VCC
VCC
VCC
4.7 kΩ
ADDR0=L3
4.7 kΩ
ADDR0=L2
4.7 kΩ
ADDR0=L1
4.7 kΩ
ADDR1=L0
MODE=L1
ADDR1=L0
MODE=L1
ADDR1=L0
MODE=L1
ADDR1=L0
ADDR0=L0
MODE=L1
ADDR1 MODE ADDR0
DS160PR822
Device-3 (TX)
ADDR1 MODE ADDR0
DS160PR822
Device-2 (TX)
ADDR1 MODE ADDR0
DS160PR822
Device-1 (RX)
ADDR1 MODE ADDR0
DS160PR822
Device-0 (RX)
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
Master
Master
Master
Master
SDA
SCL
8-bit SMBus
address: 0xA0
EEPROM
256-byte (2 kbit) max
图7-2. Daisy Chain Four DS160PR822 Devices to Read from Single EEPROM
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DS160PR822 is a high-speed linear repeater which extends the reach of differential channels impaired by
loss from transmission media like PCBs and cables. It can be deployed in a variety of different systems. The
following sections outline typical applications and their associated design considerations.
8.2 Typical Applications
The DS160PR822 is a protocol and interface agnostic linear redriver that can be used in wide range of
interfaces including:
• PCI Express 1.0/2.0/3.0/4.0
• Ultra Path Interconnect (UPI) 1.0/2.0
• DisplayPort 2.0
• SAS
• SATA
• XFI
The DS160PR822 is a protocol agnostic linear redriver with PCI Express receiver-detect capability. Its protocol
agnostic nature allows it to be used in PCI Express x4, x8, and x16 applications. 图 8-1 shows how eight
DS160PR822 devices can be used to implement 2x2 crosspoint for x16 bus width to connect two CPUs to two
EndPoints with flexibility.
PCIe Card-1
RX
TX
x16
x16
CPU-1
Connector-1
DS160
PR822
TX
RX
Quad 2x2
X-Point
x16
x16
x16
x16
DS160
PR822
TX
Quad 2x2
X-Point
RX
TX
PCIe Card-2
RX
Connector-2
CPU-2
x16
x16
图8-1. 2x2 Cross point for x16 bus width using DS160PR822
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8.2.1
The section outlines detailed procedure and design requirement for a typical . However, the design
recommendations can be used in any lane configuration.
8.2.1.1 Design Requirements
As with any high-speed design, there are many factors which influence the overall performance. The following
list indicates critical areas for consideration during design.
• Use 85 Ωimpedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N
traces should be done on the single-end segments of the differential pair.
• Use a uniform trace width and trace spacing for differential pairs.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• For PCIe Gen 3.0 and Gen 4.0, AC-coupling capacitors of 220 nF are recommended, set the maximum body
size to 0402, and add a cutout void on the GND plane below the landing pad of the capacitor to reduce
parasitic capacitance to GND.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
In PCIe Gen 4.0 and Gen 3.0 applications, the specification requires Rx-Tx (of root-complex and endpoint) link
training to establish and optimize signal conditioning settings at 16 Gbps and 8 Gbps, respectively. In link
training, the Rx partner requests a series of FIR – preshoot and deemphasis coefficients (10 Presets) from the
Tx partner. The Rx partner includes 7-levels (6 dB to 12 dB) of CTLE followed by a single tap DFE. The link
training would pre-condition the signal, with an equalized link between the root-complex and endpoint resulting
an optimized link. Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps)
applications.
For operation in PCIe 4.0 or 3.0 links, the DS160PR822 is designed with linear datapth to pass the Tx preset
signaling (by root complex and end point) onto the Rx (of root complex and end point) to train and optimize the
equalization settings. The linear redriver device helps extend the PCB trace reach distance by boosting the
attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx more
easily. The device must be placed in between the Tx and Rx (of root complex and end point) such a way that
both RX and TX signal swing stays within the linearity range of the device. Adjustments to the device EQ setting
should be performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ
gain settings are provided in 表 7-1. For most PCIe systems the default DC gain setting GAIN = floating would
be sufficient.
The DS160PR822 can be optimized for a given system utlizing its three configuration modes - Pin Mode,
SMBus/I2C Master Mode and SMBus/I2C Slave Mode. In SMBus/I2C modes the SCL, SDA pins must be pulled
up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩis
a good first approximation for a bus capacitance of 10 pF.
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图8-2 shows a simplified schematic for lane configuration in SMBus/I2C Master Mode.
图8-2. Simplified Schematic for Lane Configuration in SMBus/I2C Master Mode
Pin strap to set SMBus Slave address - each
DS160PR822 requires unique address
4.7 kΩ
4.7 kΩ
GND
ADDR0
ADDR1
SCL
SDA
VCC
VCC
GND
Driven for device
reset or pulled low
EQ1_1, EQ0_1, GAIN1
PD1,0
Term
Term
No Connect
TXnP
TXnN
RXnP
RXnN
Linear
Driver
220nF
220nF
220nF
220nF
CTLE
CTLE
CPU-1
EP-1
220nF
220nF
220nF
220nF
RXnP
RXnN
TXnP
TXnN
Linear
Driver
13 kΩ
Term
Term
READ_EN_N
ALL_DONE_N
MODE
VCC
GND
0.1ꢀF
1ꢀF
See —SMBus/I2C
Master Mode
Configuration“
section
(4x)
GND
VREG1,2
4 Data Modules for each PR822
0.1, 0.1ꢀF
4 PR822 for TX
Pin strap to set SMBus Slave
address - each DS160PR822
requires unique address
4.7 kΩ
GND
ADDR0
ADDR1
SCL
SDA
VCC
VCC
4.7 kΩ
GND
Driven for device
reset or pulled low
EQ1_1, EQ0_1, GAIN1
PD1,0
TXnP
TXnN
Term
Term
No Connect
RXnP
RXnN
Linear
Driver
220nF
220nF
CTLE
220nF
220nF
220nF
220nF
CPU-2
EP-2
220nF
220nF
TXnP
TXnN
RXnP
RXnN
Linear
Driver
CTLE
13 kΩ
Term
Term
MODE
VCC
READ_EN_N
ALL_DONE_N
GND
0.1ꢀF
1ꢀF
See —SMBus/I2C
Master Mode
Configuration“
section
(4x)
GND
VREG1,2
4 Data Modules for each PR822
0.1, 0.1ꢀF
4 PR822 for RX
图8-3. Simplified Schematic for Lane Configuration in SMBus/I2C Master Mode
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8.2.1.3 Application Curves
The DS160PR822 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-
compliant TX and RX are equipt with signal-conditioning functions and can handle channel losses of up to 28 dB
at 8 GHz. With the DS160PR822 in the link, the total channel loss between a PCIe root complex and an end
point can be up to 42 dB at 8 GHz.
图8-4 shows an electric link that models a single channel of a PCIe link and eye diagrams measured at different
locations along the link. The source that models a PCIe TX sends a 16 Gbps PRBS-15 signal with P7 presets.
After a transmission channel with –30 dB at 8 GHz insertion loss, the eye diagram is fully closed. The
DS160PR822 with its CTLE set to the maximum (18 dB boost) together with the source TX equalization
compensates for the losses of the pre-channel (TL1) and opens the eye at the output of the device.
The post-channel (TL2) losses mandate the use of PCIe RX equalization functions such as CTLE and DFE that
are normally available in PCIe-compliant receivers.
CPU / PCIe RC
16 Gbps, PRBS15
800mV
Pre-Cursor: 3.5 dB
Post-Cursor: -6 dB
PCIe
End Point
DUT
PCIe 4.0 Redriver
RX EQ = 15 (18 dB)
TL1
-30 dB @ 8 GHz
TL2
-15 dB @ 8 GHz
RX CTLE:
12 dB
图8-4. PCIe 4.0 Link Reach Extension Using DS160PR822
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9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the operating conditions outlined in the recommended
operating conditions section in terms of DC voltage, AC noise, and start-up ramp time.
2. The DS160PR822 does not require any special power supply filtering, such as ferrite beads, provided that
the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply
decoupling consists of a 0.1 µF capacitor per VCC pin, one 1.0 µF bulk capacitor per device, and one 10 µF
bulk capacitor per power bus that delivers power to one or more devices. The local decoupling (0.1 µF)
capacitors must be connected as close to the VCC pins as possible and with minimal path to the device
ground pad.
3. The DS160PR822 voltage regulator output pins require decoupling caps of 0.1 µF near each pins. The
regulator is only for internal use. Do not use to provide power to any external component.
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10 Layout
10.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VCC pins as possible. Placing the decoupling
capacitors directly underneath the device is recommended if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take
care to minimize the via stub, either by transitioning through most/all layers or by back drilling.
4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve
signal integrity by counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board.
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10.2 Layout Example
Top Layer
Use ac-coupling
capacitors with 0201
package
Ensure high-speed
trace length is
Route high-speed
traces as differential
coupled microstrips
(S=2W*) with tight
impedance control
( 10%)
matched with ≤ 5 mils
intra-pair; pair-pair
skew is less critical
Avoid acute angles
when routing high-
speed traces
Bottom Layer
Use recommended
package footprint and
ground via placement
Ensure pair-pair gap
is > 5W* for minimal
pair-pair coupling
Place decoupling
capacitors close to
VCC and VREG1,2
pins; minimize
Add ground pours for
additional isolation
ground loops
Follow connector
manufacturer
guidelines
*W is a trace width. S is a gap between adjacent traces.
图10-1. DS160PR822 Layout Example - Sub-Section of a PCIe Riser Card With CEM Connectors
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
11.3 Trademarks
所有商标均为其各自所有者的财产。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS160PR822NJXR
DS160PR822NJXT
ACTIVE
ACTIVE
WQFN
WQFN
NJX
NJX
64
64
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
PR8XX
PR8XX
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
NJX0064A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.6
5.4
A
B
PIN 1 INDEX AREA
10.1
9.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
4.1 0.1
2X 3.2
EXPOSED
THERMAL PAD
SYMM
(0.1) TYP
32
24
23
33
SYMM
65
8.6 0.1
2X 8.8
1
55
0.25
0.15
64
56
60X 0.4
PIN 1 ID
64X
0.5
0.3
0.1
C A B
64X
0.05
4225514/A 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
NJX0064A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.1)
SYMM
64X (0.6)
64X (0.2)
SEE SOLDER MASK
DETAIL
64
56
1
55
60X (0.4)
(4.05) TYP
(8.6)
(R0.05) TYP
(
0.2) TYP
VIA
1.15 TYP
SYMM
0.575 TYP
(9.8)
65
23
33
24
(0.68) TYP
32
(1.8) TYP
(5.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225514/A 11/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
NJX0064A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.36) TYP
64X (0.6)
64X (0.2)
56
64
1
55
60X (0.4)
(R0.05) TYP
(1.15) TYP
(9.8)
SYMM
65
23
21X (0.95)
33
24
32
SYMM
21X (1.16)
(5.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 65
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4225514/A 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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