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DS250DF230

SNLS590B –AUGUST 2018–REVISED OCTOBER 2019

DS250DF230 25-Gbps Multi-Rate 2-Channel Retimer

1 Features

2 Applications

1

•

Dual-channel multi-rate retimer with integrated

•

Jitter cleaning for front-port optical interface in

signal conditioning

wireless and wired systems

Backplane/mid-plane reach extension

Active cable assemblies

•

All channels lock independently from 19.6 to 25.8

Gbps (including sub-rates, such as 12.16512

Gbps, 9.8304 Gbps, 6.144 Gbps, and more)

•

802.3bj 100GbE, InfiniBand EDR, and OIF-CEI-

25G-LR/MR/SR/VSR electrical interfaces

•

Ultra-low latency: <500 ps Typical for 25.78125-

Gbps data rate

•

SFP28, QSFP28, CFP2/CFP4, CDFP

•

Adaptive continuous time linear equalizer (CTLE)

Continuous adaptive decision feedback equalizer

(DFE), capable of compensating large channel

loss variation over temperature

3 Description

The DS250DF230 is a dual-channel multi-rate retimer

with integrated signal conditioning. The device is

used to extend the reach and robustness of long,

lossy, crosstalk-impaired high-speed serial links and

while achieving a bit error rate (BER) of 10^–15or less.

•

Combined equalization supporting 35-dB channel

loss at 12.9 GHz

On-chip eye-opening monitor (EOM), PRBS

pattern checker and generator

Each channel of the DS250DF230 independently

locks to serial data rates in a continuous range from

19.6 Gbps to 25.8 Gbps or to any supported sub-rate

(÷2 and ÷4), including key data rates such as

12.16512 Gbps, 9.8304 Gbps, 6.144 Gbps.

•

Low-jitter transmitter with 3-Tap FIR filter

Integrated 2×2 cross-point

Recovered clock available for system clock

synchronization applications on channel 0

Device Information⁽¹⁾

•

Single power supply, no low-jitter reference clock

required

PART NUMBER

PACKAGE

BODY SIZE (NOM)

DS250DF230

NFBGA (36)

5.00 mm × 5.00 mm

Wide stay-in-lock temperature range

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic

RX0P

RX0N

TX0P

TX0N

CDR

X

RX

TX

RX1P

RX1N

TX1P

TX1N

CDR

RX

TX

2.5V or 3.3V

VDD

SMBus

Slave mode

1 kΩ

To other open-drain

interrupt pins

EN_SMB

INT_N

SDA⁽¹⁾

TEST0 /RCK0

THR /TEST1

To system

SMBus

SDC⁽¹⁾

Address straps

ADDR0

(pull-up, pull-

ADDR1

down, or float)

30.72 MHz or 25 MHz

To next device‘s

CAL_CLK_IN

READ_EN_N

CAL_CLK_OUT

ALL_DONE_N

SMBus Slave

mode

2.5 V

Float for SMBus Slave

mode, or connect to next

device‘s READ_EN_N for

SMBus Master mode

GND

VDD

0.01 ꢀF

(2x)

0.1 ꢀF

(2x)

(1) SMBus signals need to be pulled up elsewhere in the system.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS250DF230

SNLS590B –AUGUST 2018–REVISED OCTOBER 2019

www.ti.com

Table of Contents

8.5 Programming........................................................... 30

8.6 Register Maps......................................................... 32

Application and Implementation ........................ 78

9.1 Application Information............................................ 78

9.2 Typical Applications ............................................... 78

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (continued)......................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 Timing Requirements.............................................. 13

7.7 Switching Characteristics........................................ 14

7.8 Typical Characteristics ........................................... 15

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 28

9

10 Power Supply Recommendations ..................... 91

11 Layout................................................................... 92

11.1 Layout Guidelines ................................................. 92

11.2 Layout Examples................................................... 92

12 Device and Documentation Support ................. 94

12.1 Device Support...................................................... 94

12.2 Documentation Support ........................................ 94

12.3 Receiving Notification of Documentation Updates 94

12.4 Support Resources ............................................... 94

12.5 Trademarks........................................................... 94

12.6 Electrostatic Discharge Caution............................ 94

12.7 Glossary................................................................ 94

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 94

13.1 Package Option Addendum .................................. 95

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (December 2018) to Revision B

Page

•

Initial Public Release ............................................................................................................................................................. 1

Changed Reg_0x79[4] definition, marking this as RESERVED........................................................................................... 67

Changed Reg_0x7E[3:0] definition, marking this as RESERVED........................................................................................ 68

Changed Reg_0x7F[5] definition, marking this as RESERVED. ......................................................................................... 69

Changed Reg_0x8C definition, marking this register as RESERVED. ............................................................................... 72

Added expanded Reg_0x95 definition.................................................................................................................................. 73

2

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5 Description (continued)

The DS250DF230 has a single power supply and minimal need for external components. These features reduce

PCB routing complexity and BOM cost.

The advanced equalization features of the DS250DF230 include a low-jitter 3-tap transmit finite impulse

response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback

equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors

and crosstalk. The integrated CDR function is available for front-port optical module applications to reset the jitter

budget and retime the high-speed serial data. The DS250DF230 supplies 2x2 cross-point that gives the host lane

crossing, fanout, and multiplexing options.

The DS250DF230 can be configured either through the SMBus or through an external EEPROM. Up to 16

devices can share an EEPROM using common-channel configuration. A non-disruptive on-chip eye monitor and

a PRBS generator and checker is available for in-system diagnostics.

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6 Pin Configuration and Functions

ZLS Package

36-Pin NFBGA

Top View

Pin Functions

NAME

HIGH-SPEED DIFFERENTIAL I/Os

INTERNAL

PULL-UP/

PULL-

TYPE

DESCRIPTION

NO.

DOWN

A6

A5

A2

A1

RX0P

RX0N

RX1P

RX1N

Input

None

Inverting and noninverting differential inputs to the equalizer. An on-chip,

100-Ω termination resistor connects RXP to RXN. These inputs must be

AC-coupled.

Inverting and noninverting differential inputs to the equalizer. An on-chip,

100-Ω termination resistor connects RXP to RXN. These inputs must be

AC-coupled.

F6

F5

F2

F1

TX0P

TX0N

TX1P

TX1N

Output

None

Inverting and noninverting 50Ω driver outputs. These outputs must be AC-

coupled.

Inverting and noninverting 50Ω driver outputs. These outputs must be AC-

coupled.

CALIBRATION CLOCK PINS

30.72-MHz (±100 PPM), 2.5-V single-ended clock from external oscillator.

No stringent phase noise or jitter requirements on this clock. Also supports

25-MHZ (±100 PPM) clock by programming the corresponding registers.

Input, 2.5V

LVCMOS

D6

D1

CAL_CLK_IN

None

Output, 2.5V

LVCMOS

2.5-V buffered replica of calibration clock input (CAL_CLK_IN) for

connecting multiple (up to 20 or more) devices in a daisy-chained fashion.

CAL_CLK_OUT

4

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Pin Functions (continued)

NAME

SYSTEM MANAGEMENT BUS (SMBus) PINS

INTERNAL

PULL-UP/

PULL-

TYPE

DESCRIPTION

NO.

DOWN

C1

ADDR0

Input, 4-level

None

4-level strap pins used to set the SMBus address of the device. The pin

state is read on power-up. The multi-level nature of these pins allows for 16

unique device addresses. The four strap options include:

0: 1 kΩ to GND

R: 10 kΩ to GND

F: Float

B4

ADDR1

Input, 4-level

1: 1 kΩ to VDD

Refer to Device SMBus Address for more information.

Four-level, 2.5-V input used to select between SMBus master mode (float)

and SMBus slave mode (high). The three defined levels are:

R: 10 kΩ to GND - RESERVED, TI test mode

F: Float - SMBus Master Mode (2.5-V/3.3-V SMBUS interface only)

1: 1 kΩ to VDD - SMBus Slave Mode

C6

D5

EN_SMB

Input, 4-level

None

Select the electrical voltage of SMBus interface. 2.5-V/3.3-V or 1.8-V:

1: 1 kΩ to VDD - 1.8-V SMBus interface

F: Float - 1.8-V SMBus interface

THR /TEST1

0: 1 kΩ to GND - 2.5-V/3.3-V SMBus interface

In TI test mode (EN_SMB = 10k Ohm to GND), this is reserved TI test pin.

SMBus data input / open-drain output. External 2-kΩ to 5-kΩ pullup resistor

is required as per SMBus interface standard. This pin is 3.3-V tolerant.

D2

C2

SDA

SDC

I/O, Open Drain

None

SMBus clock input / open-drain clock output. External 2-kΩ to 5-kΩ pullup

resistor is required as per SMBus interface standard. This pin is 3.3-V

tolerant.

SMBus MASTER MODE PINS

Indicates the completion of a valid EEPROM register load operation when in

SMBus Master Mode (EN_SMB=Float):

Output, 2.5-V

LVCMOS

High = External EEPROM load failed or incomplete

Low = External EEPROM load successful and complete

When in SMBus slave mode (EN_SMB=1), this output reflects the status of

the READ_EN_N input.

E3

E4

ALL_DONE_N

READ_EN_N

None

SMBus Master Mode (EN_SMB=Float): When asserted low, initiates the

SMBus master mode EEPROM read function. Once EEPROM read is

complete (indicated by assertion of ALL_DONE_N low), this pin can be held

low for normal device operation.

SMBus Slave Mode (EN_SMB=1): When asserted low, this causes the

device to be held in reset (SMBus state machine reset and register reset).

This pin must be pulled high or left floating for normal operation in SMBus

Slave Mode.

Input, 3.3-V

LVCMOS

Weak pullup

to VDD

This pin is 3.3-V tolerant.

MISCELLANEOUS PINS

Open-drain, 3.3-V tolerant active-low interrupt output. It pulls low when an

interrupt occurs. The events which trigger an interrupt are programmable

through SMBus registers. This pin can be connected in a wired-OR fashion

with other device's interrupt pin. A single pullup resistor in the 2-kΩ to 5-kΩ

range is adequate for the entire INT_N net.

Output, Open-

Drain

B3

INT_N

None

In TI test mode (EN_SMB = 10k Ohm to GND), this is reserved TI test pin.

During normal (non-test-mode) operation, this pin is configured as input by

default and therefore is not affected by the presence of a signal. This pin

may be left floating, tied to GND, or connected to a 2.5-V (max) output.

This pin can be configured to offer the recovered clock for CH0 by

programming the corresponding registers. The signal is 2.5-V LVCMOS.

I/O, 2.5-V

LVCMOS

C5

TEST0 /RCK0

POWER

Power supply, VDD = 2.5 V ±5%. TI recommends connecting at least four

de-coupling capacitors between the Retimer VDD plane and GND as close

to the Retimer as possible. For example, two 0.1-µF capacitors, and two

0.01-µF capacitors directly beneath the device or as close to the VDD pins

as possible. The VDD pins on this device must be connected through a low-

resistance path to the board VDD plane.

C3,C4,

D3,D4

VDD

Power

None

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Pin Functions (continued)

INTERNAL

PULL-UP/

PULL-

TYPE

DESCRIPTION

NO.

NAME

DOWN

A3,A4,

B1,B2,

B5,B6,

E1,E2,

E5,E6,F

3,F4

Ground reference. The GND pins on this device must be connected through

a low-resistance path to the board GND plane.

GND

Power

None

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

2.75

4

UNIT

V

VDD_ABSMAX

Supply Voltage, VDD to GND

VIO_2.5V-ABSMAX2.5V I/O voltage (LVCMOS and Analog)

V

VIO_3.3V-ABSMAX3.3V I/O Voltage (SDA, SDC, INT_N, READ_EN)

V

VIN_ABSMAX

VOUT_ABSMAX

TJ_ABSMAX

T_stg

Signal Input voltage(RXnP, RXnN)

Signal Output voltage(TXnP, TXnN)

Junction Temperature

2.75

150

V

°C

Storage Temperature range

–40

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±2000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Supply voltage, VDD to GND.DC plus AC power should not exceed these

limits.

VDD

2.375

2.5

2.625

V

N_VDD

T_ramp

T_J

Supply noise, DC to <50 Hz, sinusoidal⁽¹⁾

Supply noise, 50 Hz to 10 MHz, sinusoidal⁽¹⁾

Supply noise, >10 MHz, sinusoidal⁽¹⁾

VDD supply ramp time, from 0 V to 2.375 V

Operating junction temperature

250

20

mVpp

us

10

150

–40

110

85⁽²⁾

2.625

3.6

°C

T_A

Operating ambient temperature

–40

°C

V_IO2.5V

2.5 V LVCMOS

2.375

2.5

V

V_{IO3.3V,INT_N}Open Drain I/O voltage(INT_N)

V_IO3.3V

Open Drain I/O voltage(SDA,SDC)⁽³⁾

(1) Steps must be taken to ensure the combined AC plus DC noise meets the VDD supply voltage limits.

V

3.6

V

(2) Steps must be taken to ensure the operating junction temperature range and stay-in-lock range (TEMP_LOCK+,TEMP_LOCK-)are met. Refer

to the Electrical Characteristics for more details concerning TEMP_LOCK+and TEMP_LOCK-.

(3) Set THR pin to select SMBUS electrical voltage

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7.4 Thermal Information

DS250DF230

ZLS (NFBGA)

36 PINS

49.3

THERMAL METRIC⁽¹⁾

CONDITIONS⁽²⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

4-layer JEDEC board

°C/W

20.7

24.5

0.5

Ψ_JB

Junction-to-board characterization parameter 4-layer JEDEC board

24.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, and/or reduced

ambient temperature (<85 C) may be required in order to meet the maximum junction temperature specification per the Recommended

Operating Conditions.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

POWER CONSUMPTION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Active mode with CTLE, Tx FIR, full DFE

and Crosspoint enabled. Idle power

consumption not included.

256

248

347

mW

Active mode with CTLE, Tx FIR, and full

DFE enabled. Crosspoint disabled. Idle

power consumption not included.

Active mode with CTLE, Tx FIR, and

partial DFE enabled(taps 1-2 only).

Crosspoint and DFE taps 3-5 disabled. Idle

power consumption not included.

235

226

380

mW

Power Consumption Per

Active Channel

W_Channel

Active mode with CTLE, and Tx FIR

enabled. DFE and crosspoint disabled. Idle

power consumption not included.

Assuming CDR acquiring lock with CTLE,

full DFE, Tx FIR, Driver, and Crosspoint

enabled. Idle power consumption not

included.

445

Assuming CDR acquiring lock with CTLE,

full DFE, Tx FIR, Driver, and Crosspoint

disabled. Idle power consumption not

included.

333

mW

PRBS Checker Power

Consumption only Per Channel

200

190

mW

W_PRBS

PRBS Generator Power

Consumption only Per Channel

Idle/Static mode. Power supplied, no high-

speed data present at inputs, channel

automatically powered down.

W_{Static_Total}Total Idle Power Consumption

165

66

mW

mA

Idle/Static mode. Power supplied, no high-

speed data present at inputs, channel

automatically powered down.

Idle mode total device supply

I_{Static_Total}

100

361

current consumption

Active mode with CTLE, Tx FIR, full DFE

and Crosspoint enabled.

271

265

mA

Active mode with CTLE, Tx FIR, and full

DFE enabled. Crosspoint disabled.

Active Mode Total Device Supply

Current Consumption

I_Total

Active mode with CTLE, Tx FIR, and

partial DFE enabled(taps 1-2 only).

Crosspoint and DFE taps 3-5 disabled.

255

247

mA

Active mode with CTLE, and Tx FIR

enabled. DFE and crosspoint disabled.

8

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL DEVICE-LEVEL SPECIFICATIONS

Full-rate (divide-by-1) mode of operation.

Half-rate (divide-by-2) mode of operation.

19.6

9.8

25.8

12.9

Gbps

R_baud

Supported input data rate

Quarter-rate (divide-by-4) mode of

operation.

4.9

6.45

Gbps

Single device reading its configuration

from an EEPROM. Common channel

EEPROM configuration load time configuration. This time scales with the

number of devices reading from the same

EEPROM.

15⁽¹⁾

ms

t_EEPROM

Single device reading its configuration

from an EEPROM. Unique-channel

EEPROM configuration load time configuration. This time scales with the

number of devices reading from the same

40⁽¹⁾

ms

EEPROM.

Internal power-on reset (PoR) stretch

between stable power supply and de-

assertion of internal PoR. The SMBus

address is latched on the completion of the

t_POR

Power-on reset assertion-time

50

PoR stretch, and SMBus accesses are

permitted.

HIGH-SPEED DIFFERENTIAL OUTPUTS (TXnP, TXnN)

Measured with c(0)=4 setting

(REG_0x3D[6:0]=0x04,

REG_0x3E[6:0]=0x40,

Output differential voltage

amplitude

REG_0x3F[6:0]=0x40). Differential

measurement using an 8T pattern (eight

1s followed by eight 0s) at 25.78125 Gbps

with TXPn and TXNn terminated by 50

Ohms to GND.

392

mVppd

V_OD

Measured with c(0)=31 setting

(REG_0x3D[6:0]=0x1F,

REG_0x3E[6:0]=0x40,

Output differential voltage

amplitude

REG_0x3F[6:0]=0x40). Differential

measurement using an 8T pattern (eight

1s followed by eight 0s) at 25.78125 Gbps

with TXPn and TXNn terminated by 50

Ohms to GND.

1195

mVppd

Raw Mode(CDR Bypassed), low swing

setting(REG_0xD[0]=0), differential

measurement using 8T pattern(eight 1s

followed by eight 0s) at 25.78125Gbps and

9.8304Gbps with TXPn and TXNn

terminated by 50 Ohms to GND.

RPH=REG_0x1A[7:6]=0

Output differential voltage

amplitude under Raw Mode, low

swing setting

V_{OD_Raw_L}

602

Raw Mode(CDR Bypassed), high swing

setting(REG_0xD[0]=1),,differential

measurement using 8T pattern(eight 1s

followed by eight 0s) at 25.78125Gbps and

9.8304Gbps with TXPn and TXNn

terminated by 50 Ohms to GND.

Output differential voltage

amplitude under Raw Mode,

high swing setting

V_{OD_Raw_H}

919

6.1

mVppd

RPH=REG_0x1A[7:6]=0x3

Differential output amplitude with

TX disabled

V_{OD_Idle}

(1) From low assertion of READ_EN_N to low_assertion of ALL_DONE_N. Does not include Power-On Reset time

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

With respect to signal ground. Measured

using an 8T pattern (eight 1s followed by

eight 0s) at 25.78125 Gbps with TXPn and

TXNn terminated by 50 Ohms to GND.

Measured for c(-1)=c(1)=0 and VOD

settings in the range of 600 mVppd to

1200 mVppd.

DC common-mode output

voltage

V_{cm_TX}

1.01

V

With respect to signal ground. Measured

Common-mode AC output noise with PRBS9 data pattern. Measured with a

33GHz (-3dB) low-pass filter.

mV,

RMS

V_{cm_TX_AC}

7.4

20%-to-80% rise time and 80%-to-20% fall

time on a clock-like {11111 00000} data

pattern at 25.78125 Gbps. Measured for

~750 mVppd output amplitude and no

equalization: REG_0x3D=+13,

REG_0x3E=0, REG_0x3F=0

Output transition-time

17.5

ps

t_r, t_f

Slow slew rate setting(REG_0x3D[5]=1),

20%-to-80% rise time and 80%-to-20% fall

time on a clock-like {11111 00000} data

Output transition-time, Low slew

pattern at 9.8304 Gbps. Measured for

rate setting

24

~750 mVppd output amplitude and no

equalization: REG_0x3D=+13,

REG_0x3E=0, REG_0x3F=0

Differential output return loss,

Between 50 MHz and 5 GHz

SDD22⁽²⁾

-15.9

-13

-24

-8

dB

RL_SDD22

Differential output return loss,

Between 5 GHz and 12.9 GHz

SDD22⁽²⁾

Differential to common-mode

Between 50 MHz and 12.9 GHz

output return loss, SCD22⁽²⁾

RL_SCD22

RL_SDC22

Common-mode to differential

Between 50 MHz and 12.9 GHz

output return loss, SDC22⁽²⁾

Common-mode output return

Between 50 MHz and 10 GHz

loss, SCC22⁽²⁾

RL_SCC22

Common-mode output return

Between 10 GHz and 12.9 GHz

loss, SCC22⁽²⁾

-8.5

RETIMER TIMING SPECIFICATIONS

4.5 UI +

175 ps

No Crosspoint; CDR enabled and locked.

ps

Input-to-output latency

t_D

(propagation delay) through a

channel

Crosspoint enabled; CDR enabled and

locked.

4.5 UI +

220 ps

ps

No crosspoint; CDR in raw mode.

140

Variation of Input-to-output

latency

Crosspoint enabled; CDR enabled and

locked.

t_{D_V}

t_SK

± 50

Channel-to-channel interpair

skew

Latency difference between channels at

full-rate.

30

ps

Measured at 25.78125 Gbps, Adapt mode

2(REG_0x31[6:5]=0x2)

CDR lock acquisition-time

<100

ms

Measured at 25.78125 Gbps, Adapt mode

2(REG_0x31[6:5]=0x2). Fast Lock Mode

Enabled(REG_0xAC[7] = 1). Adaptation

process still runs to find the best

CDR lock acquisition-time, Fast

Lock Mode

<10

<2

ms

t_Lock

CTLE/DFE values after CDR lock declares

Measured at 25.78125 Gbps, Adapt mode

0(Reg_0x31[6:5]=0x0), Fast Lock Mode

Enabled(REG_0xAC[7] = 1)

CDR lock acquisition-time, Fast

Lock Mode

(2) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9

GHZ between DS250DF230 and the measurement instrument.

10

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

0.16

6.8

MAX

UNIT

RETIMER JITTER SPECIFICATIONS

Measured at 25.78125 Gbps to a

probability level of 1E-12 with PRBS11

data pattern an evaluation board traces

de-embedded

UIpp @

1E-12

J_TJ

Output Total jitter (TJ)

Measured at 25.78125 Gbps to a

probability level of 1E-12 with PRBS11

data pattern an evaluation board traces

de-embedded

mUI

RMS

J_RJ

Output Random Jitter (RJ)

Measured at 25.78125 Gbps to a

probability level of 1E-12 with PRBS11

data pattern an evaluation board traces

de-embedded

Output Duty Cycle Distortion

(DCD)

J_DCD

3.7

mUIpp

HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN)

Maximum tolerable input

differential voltage

VID_Max

V_cm-Self

For normal operation

1200

1.79

-20

-13

-23

-11

-8

mVppd

V

Self-generated input common

mode

Differential input return loss,

SDD11⁽³⁾

Between 50 MHz and 3.69 GHz

Between 3.69 GHz and 12.9 GHz

Between 50 MHz and 12.9 GHz

Between 150 MHz and 10 GHz

Between 10 GHz and 12.9 GHz

dB

RL_SDD11

Differential input return loss,

SDD11⁽³⁾

dB

Common-mode to differential

input return loss, SDC11⁽³⁾

RL_SDC11

RL_SCD11

dB

Differential to common-mode

input return loss, SCD11⁽³⁾

dB

Common-mode input return loss,

SCC11⁽³⁾

dB

RL_SCC11

Common-mode input return loss,

SCC11⁽³⁾

dB

Minimum input peak-to-peak amplitude

level at device pins required to assert

signal detect. Assumes default assert

threshold setting. Measured at 25.78125

Gbps with PRBS7.

AC signal detect assert (ON)

threshold level

V_SDAT

145

84

mVppd

Maximum input peak-to-peak amplitude

level at device pins which causes signal

detect to de-assert. Assumes default de-

assert threshold setting . Measured at

25.78125 Gbps with PRBS7.

AC signal detect de-assert (OFF)

threshold level

V_SDDT

RETIMER CLOCK AND DATA RECOVERY SPECIFICATIONS

Measured at 9.8304 Gbps with PRBS7

data pattern

PLL bandwidth

Jitter peaking

4

4.7

0.5

MHz

dB

BW_PLL

Measured at 25.78125 Gbps with PRBS7

data pattern

Measured at 9.8304 Gbps with PRBS7

data pattern.

J_PEAK

Measured at 25.78125 Gbps with PRBS7

data pattern.

dB

(3) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9

GHZ between DS250DF230 and the measurement instrument.

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured at 25.78125 Gbps with SJ

frequency = 190 KHz, 30dB input channel

loss, PRBS31 data pattern, ~800 mVppd

launch amplitude, and 0.18 UIpp total

uncorrelated output jitter in addition to the

applied SJ. BER < 1E-12.

Input jitter tolerance

9

UIpp

Measured at 25.78125 Gbps with SJ

frequency = 940 KHz, 30dB input channel

loss, PRBS31 data pattern, ~800 mVppd

launch amplitude, and 0.18 UIpp total

uncorrelated output jitter in addition to the

applied SJ. BER < 1E-12.

J_TOL

Input jitter tolerance

1

0.33

150

UIpp

°C

Measured at 25.78125 Gbps with SJ

frequency > 15MHz, 30dB input channel

loss, PRBS31 data pattern, ~800 mVppd

launch amplitude, and 0.18 UIpp total

uncorrelated output jitter in addition to the

applied SJ. BER < 1E-12.

CDR stay-in-lock junction

temperature range, negative

ramp. Maximum junction

110 °C junction temperature starting, ramp

temperature change below initial rate -3°C/minute, 12 layer PCB

TEMP_LOCK-

CDR lock acquisition

temperature

CDR stay-in-lock junction

temperature range, positive

ramp. Maximum junction

-40 °C junction temperature starting, ramp

temperature change above initial rate +3°C/minute, 12 layer PCB

TEMP_LOCK+

°C

CDR lock acquisition

temperature

RECOVERED CLOCK SPECIFICATIONS

Measured with input data rate as 24.33024

Gbps or 12.16512 Gbps or 10.1376 Gbps

9.8304 Gbps or 6.144 Gbps or 4.9152

Gbps

Recovered Clock frequency on

RCK0 pin

30.72

MHz

RCK_f

Recovered Clock frequency on

RCK0 pin

Measured with input data rate as

25.78125Gbps or 10.3125Gbps

32.2265625

<=100 Hz

< -59

< -84

dBc/Hz

Between 100 Hz and 1 kHz

Between 1 kHz and 10 kHz

>10 kHz

RCK_fPhase Noise

RCK_Phase

Performance⁽⁴⁾

< -103

< -122

CALIBRATION CLOCK SPECIFICATIONS

Calibration clock frequency

CLK_f

Option 1: 30.72 MHZ

Option 2: 25 MHZ

30.72

25

MHz

PPM

Calibration clock frequency

CLK_ppm

CLK_IDC

Calibration clock PPM tolerance

Calibration clock input duty cycle

-100

40

100

50

60 Percent

Intrinsic duty cycle distortion of chip

calibration clock output at the

CAL_CLK_OUT pin, assuming 50% duty

cycle on CAL_CLK_IN pin.

Intrinsic calibration clock duty

cycle distortion

CLK_ODC

45

55 Percent

Assumes worst-case 60%/40% input duty

Number of devices which can be cycle on the first device. CAL_CLK_OUT

CLK_num

cascaded from CAL_CLK_OUT

to CAL_CLK_IN

from first device connects to CAL_CLK_IN

of second device, and so on until the last

device.

20

N/A

(4) Measured with input data from DS280DF810 evaluation board, at 24.33024 Gbps or 10.1376 Gbps or 25.78125Gbps or 10.3125 Gbps

12

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVCMOS DC SPECIFICATIONS

2.5 V LVCMOS pins

1.75

VDD

3.6

V

V_IH

V_IL

Input high-level voltage

Input low-level voltage

3.3 V LVCMOS pin (READ_EN_N)

2.5 V LVCMOS pins

GND

0.7

3.3 V LVCMOS pin (READ_EN_N)

0.8

4-level pins ADDR0, ADDR1, EN_SMB

and THR

High-level(1) input voltage

Float level input voltage

10K to GND input voltage

Low-level (0) input voltage

0.98 x VDD

0.69 x VDD

0.25 x VDD

0.1

V

4-level pins ADDR0, ADDR1, EN_SMB

and THR

Vth

4-level pins ADDR0, ADDR1, EN_SMB

and THR

4-level pins ADDR0, ADDR1, EN_SMB

and THR

V_OH

V_OL

High-level output voltage

Low-level output voltage

Input high leakage current

IOH = 4mA

2

V

IOL = -4mA

0.4

70

65

Vinput = VDD, Open drain pins

Vinput = VDD and CAL_CLK_IN pins

uA

I_IH

Vinput = VDD, ADDR[1:0] and EN_SMB

pins

Input high leakage current

65

15

uA

Input high leakage current

Input low leakage current

Vinput = VDD, READ_EN_N

Vinput = 0V, Open drain pins

Vinput = 0V, CAL_CLK_IN pins

uA

–15

I_IL

Vinput = 0V, ADDR[1:0], READ_EN_N,

and EN_SMB pins

Input low leakage current

–115

uA

7.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)

Input high-level voltage

1.8 V SMBUS Interface

V_IH

SDA and SDC

1.35

3.6

V

Input high-level voltage

2.5 V/3.3 V SMBUS Interface

SDA and SDC

1.75

3.6

0.8

V_IL

C_IN

V_OL

I_IN

Input low-level voltage

Input pin capacitance

Low-level output voltage

Input current

GND

V

pF

V

2

SDA or SDC or INT, IOL = 1.25 mA

SDA or SDC, VINPUT = VIN, VDD, GND

Pull up resistor = 1 kΩ, Cb = 50pF

0.4

15

–15

10

uA

ns

T_R

SDA rise time, read operation

SDA fall time, read operation

150

4.5

T_F

RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SLAVE MODE)

f_SDC

SDC clock frequency

Data hold time

100

0.75

100

400

kHz

ns

t_{HD_DAT}

t_{SU_DAT}

Data setup time

ns

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UNIT

7.7 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

SMBus SWITCHING CHARACTERISTICS (2.5 V and 3.3 V MASTER MODE)

f_SDC

SDC clock frequency

SDC low period

260

303

1.90

1.40

1.3

0.5

1.3

1.4

1.8

70

346

kHz

µs

ns

T_LOW

T_HIGH

T_{HD_STA}

T_{SU_STA}

T_{HD_DAT}

T_SD-DAT

T_{SU_STO}

T_BUF

SDC high period

Hold time start operation

Setup time start operation

Data hold time

Data setup time

Stop condition setup time

Bus free time between Stop-Start

SDC rise time

T_R

Pull up resistor = 1 kΩ

T_F

SDC fall time

8

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7.8 Typical Characteristics

21

1.5

1.4

1.3

1.2

1.1

1

C(0) = 7

C(0) = 16

C(0) = 31

C(0) = 7

C(0) = 16

C(0) = 31

20.5

20

19.5

19

18.5

18

0.9

0.8

0.7

0.6

0.5

0.4

17.5

17

16.5

16

15.5

15

-50

-30

-10

10

Temperature(°C)

30

50

70

90

110

-50

-30

-10

10

Temperature(°C)

30

50

70

90

110

D001

Figure 1. Output Transition-time vs Ambient Temperature

Figure 2. Typical VOD vs Ambient Temperature

1.4

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

T = 85°C, VDD = 2.65V

T = 85°C, VDD = 2.35V

T = -40°C, VDD = 2.65V

T = -40°C, VDD = 2.35V

TJ, VDD = 2.35V

DJ, VDD = 2.35V

TJ, VDD = 2.65V

DJ, VDD = 2.65V

1.2

1

0.8

0.6

0.4

0.2

3

6

9

12

15

Main Cursor C(0)

18

21

24

27

30

-40

-25

-10

5

20 35

Temperature °C

50

65

80

95

D001

Figure 3. Typical VOD vs FIR Main-Cursor

Figure 4. Typical Output Jitter vs Ambient Temperature

at 25.78125 Gbps

18

16

14

12

10

8

1.4

T = 95 °C, VDD = 2.35V

T = 95 °C, VDD = 2.65V

T = -40 °C, VDD = 2.35V

T = -40 °C, VDD = 2.65V

T = 95 °C, VDD = 2.35V

T = 95 °C, VDD = 2.65V

T = -40 °C, VDD = 2.35V

T = -40 °C, VDD = 2.65V

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

6

4

2

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Frequency(MHz)

1

11

21

31

41

51

61

Frequency(MHz)

71

81

91 100

D001

0.1 MHz to 1 MHz

Input Random Jitter = 0.078 UIpp

1 MHz to 100 MHz

Input Random Jitter = 0.078 UIpp

Figure 5. Typical Sinusoidal Input Jitter Tolerance for

30-dB Channel at 25.78125 Gbps

Figure 6. Typical Input Jitter Tolerance for

30-dB Channel at 25.78125 Gbps

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8 Detailed Description

8.1 Overview

The DS250DF230 is a dual-channel multi-rate retimer with integrated signal conditioning. Each of the two

channels operates independently. Each channel includes a continuous-time linear equalizer (CTLE) and a

Decision Feedback Equalizer (DFE), which together compensate for the presence of a dispersive transmission

channel between the source transmitter and the DS250DF230 receiver. The CTLE and DFE are self-adaptive.

Each channel includes an independent voltage-controlled oscillator (VCO) and phase-locked loop (PLL) which

produce a clean clock that is frequency-locked to the clock embedded in the input data stream. The high-

frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially reduced

jitter. This clean clock is used to re-time the incoming data, removing high-frequency jitter from the data stream

and reproducing the data on the output with significantly reduced jitter.

Each channel of the DS250DF230 features an output driver with adjustable differential output voltage and output

equalization in the form of a three-tap finite impulse response (FIR) filter. The output FIR compensates for

dispersion in the transmission channel at the output of the DS250DF230.

A full 2x2 cross-point switch is integrated inside. This allows multiplexing and de-multiplexing/fanout applications

for fail-over redundancy, as well as cross-over applications to aid PCB routing.

Each channel also includes diagnostic features such as a Pseudo-Random Bit Sequence (PRBS) pattern

generator and checker, as well as a non-destructive, eye-opening monitor (EOM). The EOM can be used to plot

the post-equalized eye at the input to the decision slicer or simply to read the horizontal eye opening (HEO) and

vertical eye opening (VEO).

The DS250DF230 is configurable through a single SMBus port. The DS250DF230 can also act as an SMBus

master to configure itself from an external EEPROM. Up to sixteen DS250DF230 devices can share a single

SMBus.

The sections which follow describe the functionality of various circuits and features within the DS250DF230. For

more information about how to program or operate these features, consult the DS250DF230 Programmer's

Guide (SNLU182).

8.2 Functional Block Diagram

To adjacent

channel

One of two channels

DFE

Term

Raw

Retimed

PRBS

RXnP

RXnN

TXnP

TXnN

X-

point

CTLE+VGA

Sampler

TX FIR

Driver

+

PRBS

Gen

Signal

Detect

Voltage

Regulator

Eye

Monitor

PRBS

Checker

Voltage

Regulator

PFD, CDR,

and Divider

VCO

Channel Digital Core

CAL_CLK_IN

ADDRn

Buffer

CAL_CLK_OUT

SCL

SDA

Power-On

Reset

Always-On

10MHz

Shared Digital Core

READ_EN_N

EN_SMB

ALL_DONE_N

INT_N

Shared Digital Core

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8.3 Feature Description

8.3.1 Device Data Path Operation

The DS250DF230 data path consists of several key blocks as shown in the functional block diagram. These key

circuits are:

•

Signal Detect

Continuous Time Linear Equalizer (CTLE)

Variable Gain Amplifier (VGA)

Cross-Point Switch

Decision Feedback Equalizer (DFE)

Clock and Data Recovery (CDR)

Calibration Clock

Differential Driver With FIR Filter

8.3.2 Signal Detect

The DS250DF230 receiver contains a signal detect circuit. The signal detect circuit monitors the energy level on

the receiver inputs and powers on or off the rest of the high-speed data path if a signal is detected or not. By

default, each channel allows the signal detect circuit to automatically power on or off the rest of the high-speed

data path depending on the presence of an input signal. The signal detect block can be manually controlled in

the SMBus channel registers. This can be useful if it is desired to manually force channels to be disabled. For

information on how to manually operate the signal detect circuit, refer to the DS250DF230 Programmer's Guide

(SNLU182).

8.3.3 Continuous Time Linear Equalizer (CTLE)

The CTLE in the DS250DF230 is a fully-adaptive equalizer. The CTLE adapts according to a Figure of Merit

(FOM) calculation during the lock acquisition process. The FOM calculation is based upon the horizontal eye

opening (HEO) and vertical eye opening (VEO). Once the CDR locks and the CTLE adapts, the CTLE boost

level is frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state.

The CTLE can be re-adapted by resetting the CDR.

The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for many boost

combinations, including bypassing the first three stages EQs. The CTLE adaption algorithm allows the CTLE to

adapt through 20 of these boost combinations. These 20 boost combinations comprise the EQ Table in the

channel registers. See channel registers 0x40 through 0x53.

The boost levels can be set between approximately 0 dB and 25 dB (at 12.89 GHz.)

8.3.4 Variable Gain Amplifier (VGA)

The DS250DF230 receiver implements a VGA. The VGA assists in the recovery of extremely small signals,

working in conjunction with the CTLE to equalize and scale amplitude. The VGA has 1-bit control through

Reg_0x8E[0], and the VGA is in the low-gain state (Reg_0x8E[0]=0) by default. In addition to the VGA, the CTLE

implements its own gain control through Reg_0x13[5] to adjust the DC amplitude similar to the VGA. For more

information on how to configure the VGA and EQ gain, refer to the DS250DF230 Programmer's Guide

(SNLU182).

8.3.5 Cross-Point Switch

DS250DF230 has a 2×2 cross-point that may be enabled to implement a 2-to-1 mux, a 1-to-2 fanout, or an A-to-

B/B-to-A lane cross.

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Feature Description (continued)

8.3.6 Decision Feedback Equalizer (DFE)

A 5-tap DFE can be enabled within the data path of each channel to assist in reducing the effects of crosstalk,

reflections, or post-cursor, inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the

selected adapt mode. Once the DFE is enabled, it can be configured to adapt only during lock acquisition or to

adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights.

However, when the DFE is configured manually, the DFE auto-adaption must be disabled. For many applications

with lower insertion loss (that is, < 30 dB) lower crosstalk, and/or lower reflections, part or all of the DFE can be

disabled to reduce power consumption. The DFE can either be fully enabled (taps 1-5), partially enabled (taps 1-

2 only), or fully disabled (no taps). The DFE taps support continuous adaptation, the device is capable of

compensating large channel loss variation over temperature

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity

bit.

Table 1. DFE Tap Weights

DFE PARAMETER

Tap 1 Weight Range

Tap 2-5 Weight Range

Tap Weight Step Size

DECIMAL (REGISTER VALUE)

VALUE (mV) (TYP)

0 - 31

0 - 15

NA

0 – 217

0 – 105

7

0: (+) positive; feedback value creates a low-pass filter response, thus providing attenuation to

correct for negative-sign, post-cursor ISI

Polarity

1: (-) negative; Feedback value creates a high-pass filter response, thus providing boost to correct

for positive-sign, post-cursor ISI.

8.3.7 Clock and Data Recovery (CDR)

The CDR consists of a Phase-Locked Loop (PLL), PPM counter, and Input and Output Data Multiplexers (mux)

that allow for retimed data, non-retimed data, a PRBS generator, and output muted modes.

By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output

to the FIR filter and differential driver together with the recovered clock that was cleaned of any high-frequency

jitter outside the bandwidth of the CDR clock recovery loop. The bandwidth of the CDR defaults to 4.7 MHz

(typical) in full-rate (divide-by-1) mode and 4 MHz (typical) in sub-rate mode. The CDR bandwidth is adjustable.

Refer to the DS250DF230 Programmer's Guide (SNLU182) for more information on adjusting the CDR

bandwidth. Users can configure the CDR data to route the recovered clock and data to the PRBS checker. Users

also have the option of configuring the output of the CDR to send raw non-retimed data, or data from the pattern

generator.

The CDR requires these items for proper configuration:

•

A 30.72-MHZ or 25-MHz calibration clock to run the PPM counter (CAL_CLK_IN).

Expected data rates must be programmed into the CDR either through the rate table or entered manually with

the corrected divider settings. Refer to the DS250DF230 Programmer's Guide (SNLU182) for more

information on configuring the CDR for different data rates.

The DS250DF230 offers a low-speed recovered clock for channel 0. This feature is useful for the cases when

recovered clock from FPGA or ASIC has in-band spurs on the phase noise plot because of the digital switching

noise. See the Table 6 for the recovered clock frequency versus input data rate.

The DS250DF230 offers fast lock option, so that the CDR Lock time can be as fast as 2 ms. See CDR lock time

parameter in Electrical Characteristics

When DS250DF230 is configured to Raw mode(CDR bypassed), the output differential voltage amplitude of the

transmitter is adjustable. See the V_{OD_Raw_L}and V_{OD_Raw_H}parameters from Electrical Characteristics. When

switching from Raw mode to Retimed mode(CDR Enabled), REG_0x1A[7:6] and REG_0x0D[0] values need to

be changed back to default. Refer to the DS250DF230 Programmer's Guide (SNLU182) for more information.

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8.3.8 Calibration Clock

The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The

calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable

lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates.

The host must provide an input calibration clock signal of 30.72-MHZ or 25-MHz frequency. This clock is not

used for clock and data recovery, thus there are no stringent jitter requirements placed on this calibration clock.

8.3.9 Differential Driver With FIR Filter

The DS250DF230 output driver has a three-tap finite impulse response (FIR) filter which allows for pre- and post-

cursor equalization to compensate for a wide variety of output channel media. The filter consists of a weighted

sum of three consecutive retimed bits as shown in Figure 7. C[0] can take on values in the range [-31, +31]. C[-1]

and C[+1] can take on values in the range [-15, 15].

Retimed

Data

FIR filter

output

x

+

1 UI

Delay

C[-1]

Pre-cursor

x

+

1 UI

Delay

C[0]

Main-curosr

x

C[+1]

Post-cursor

Figure 7. FIR Filter Functional model

When using the FIR filter, it is important to abide by these general rules:

•

|C[-1]| + |C[0]| + |C[+1]| ≤ 31; the FIR tap coefficients absolute sum must be less or equal to 31

sgn(C[-1]) = sgn(C[+1]) ≠ sgn(C[0]), for high-pass filter effect; the sign for the pre-cursor and/or post-cursor

tap must be different from main-cursor tap to realize boost effect

•

sgn(C[-1]) = sgn(C[+1]) = sgn(C[0]), for low-pass filter effect; the sign for the pre-cursor and/or post-cursor tap

must be equal to the main-cursor tap to realize attenuation effect

The FIR filter is used to pre-distort the transmitted waveform to compensate for frequency-dependant loss in the

output channel. The most common way of pre-distorting the signal is to accentuate the transitions and de-

emphasize the non-transitions. The bit before a transition is accentuated through the pre-cursor tap, and the bit

after the transition is accentuated through the post-cursor tap. The waveforms in Figure 8 through Figure 10 give

a conceptual illustration of how the FIR filter affects the output waveform. These characteristics can be derived

from the example waveforms:

•

VOD_pk-pk= v₇– v₈

VOD_{low-frequency}= v₂– v₅

Rpre_dB= 20 × log₁₀(v₃⁄v₂)

Rpst_dB= 20 × log₁₀(v₁⁄v₂)

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Transmitted

Bits: 0

0

1

0

1

0

1

Differential

Voltage

v₁

v₇

v₂

v₃

0V

Time [UI]

v₅

v₆

v₄

v₈

Figure 8. Conceptual FIR Waveform With Post-Cursor Only

Transmitted

Bits: 0

0

1

0

1

0

1

Differential

Voltage

v₃

v₇

v₁

v₂

0V

Time [UI]

v₄

v₅

v₆

v₈

Figure 9. Conceptual FIR Waveform With Pre-Cursor Only

Transmitted

Bits: 0

0

1

0

1

0

1

Differential

Voltage

v₇

v₁

v₃

v₂

0V

Time [UI]

v₅

v₆

v₄

v₈

Figure 10. Conceptual FIR Waveform With Both Pre- and Post-Cursor

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8.3.9.1 Setting the Output V_OD, Pre-Cursor, and Post-Cursor Equalization

The output differential voltage (V_OD), pre-cursor, and post-cursor equalization of the driver is controlled by

manipulating the FIR tap settings. The main cursor tap is the primary knob for amplitude adjustment. The pre-

and post-cursor FIR tap settings can then be adjusted to provide equalization. To maintain a constant peak-to-

peak VOD, the user must adjust the main cursor tap value relative to the pre- and post-cursor tap changes so as

to maintain a constant absolute sum of the FIR tap values. Table 2 shows various settings for V_ODsettings

ranging from 350 mVpp to 1195 mVpp (typical). Note that the output peak-to-peak amplitude is a function of the

sum of the absolute values of the taps, whereas the low-frequency amplitude is purely a function of the main-

cursor value.

Table 2. Typical VOD and FIR Values

FIR SETTINGS

Peak-to Peak

RPRE(dB)

RPST(dB)

PRE-CURSOR:

REG_0x3E[6:0]

MAIN-CURSOR:

REG_0x3D[6:0]

POST-CURSOR:

REG_0x3F[6:0]

VOD(V)

0

+3

0

0.350

0.392

0.436

0.482

0.524

0.562

0.602

0.638

0.678

0.710

0.748

0.782

0.816

0.846

0.880

0.910

0.944

0.968

0.998

1.028

1.056

1.076

1.096

1.120

1.140

1.155

1.175

1.185

1.195

0.880

NA

2.0

2.7

3.4

4.3

5.4

6.7

8.4

11

+4

+5

0

+6

0

+7

0

+8

0

+9

0

+10

+11

+12

+13

+14

+15

+16

+17

+18

+19

+20

+21

+22

+23

+24

+25

+26

+27

+28

+29

+30

+31

+16

+15

+14

+13

+12

+11

+10

+9

0

–1

–2

–3

–4

–5

–6

–7

–8

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Table 2. Typical VOD and FIR Values (continued)

FIR SETTINGS

Peak-to Peak

VOD(V)

RPRE(dB)

RPST(dB)

PRE-CURSOR:

REG_0x3E[6:0]

MAIN-CURSOR:

REG_0x3D[6:0]

POST-CURSOR:

REG_0x3F[6:0]

-1

-2

-3

-4

0

+16

+15

+14

+13

+30

+29

+28

+27

+26

+25

+24

+23

+22

+21

+20

+19

+30

+29

+28

+27

+26

+25

+24

0

0.880

1.195

0.7

1.5

2.5

3.5

NA

0.4

0.6

0.9

1.3

1.7

2.1

2.7

NA

0.6

0.8

1.1

1.4

1.8

2.3

2.8

3.4

4.1

4.9

5.9

6.9

NA

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

–11

–12

0

-1

-2

-3

-4

-5

-6

-7

0

The recommended pre-cursor and post-cursor settings for a given channel will depend on the channel

characteristics (mainly insertion loss) as well as the equalization capabilities of the downstream receiver. The

DS250DF230 receiver, with its highly-capable CTLE and DFE, does not require a significant amount of pre- or

post-cursor. The guidelines in Figure 11 through Figure 13 give general recommendations for pre- and post-

cursor for different channel loss conditions. The insertion loss (IL) in these plots refers to the total loss between

the link partner transmitter and the DS250DF230 receiver.

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Figure 11. Guideline for Link Partner FIR Settings When IL ≤ 15 dB

Figure 12. Guideline for Link Partner FIR Settings When IL ≤ 25 dB

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Figure 13. Guideline for Link Partner FIR Settings When IL ≤ 35 dB

8.3.9.2 Output Driver Polarity Inversion

In some applications, it may be necessary to invert the polarity of the data transmitted from the retimer. To invert

the polarity of the data, read back the FIR polarity settings for the pre-, main and post-cursor taps and then invert

these bits.

8.3.9.3 Slow Slew Rate

In some low speed applications, it may be needed to adjust the slew rate of the data transmitted from the

retimer. DS250DF230 does offer this option. See output transition-time parameter from Electrical Characteristics.

It is not recommended to use the slow rate setting for divide-by-1 data rate applications.

8.3.10 Debug Features

8.3.10.1 Pattern Generator

Each channel in the DS250DF230 can be configured to generate a 16-bit user-defined data pattern or a pseudo-

random bit sequence (PRBS). The user defined pattern can also be set to automatically invert every other 16-bit

symbol for DC balancing purposes. The DS250DF230 pattern generator supports the following PRBS

sequences:

•

PRBS – 2⁷– 1

PRBS – 2⁹– 1

PRBS – 2¹¹– 1

PRBS – 2¹⁵– 1

PRBS – 2²³– 1

PRBS – 2³¹– 1

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8.3.10.2 Pattern Checker

The pattern checker can be manually set to look for specific PRBS sequences and polarities or it can be set to

automatically detect the incoming pattern and polarity. The PRBS checker supports the same set of PRBS

patterns as the PRBS generator.

The pattern checker consists of an 11-bit error counter. The pattern checker uses 32-bit words, but every bit in

the word is checked for error, so the error count represents the count of single bit errors.

To read out the bit and error counters, the pattern checker must first be frozen. Continuous operation with

simultaneous read out of the bit and error counters is not supported in this implementation. Once the bit and

error counter is read, they can be unfrozen to continue counting.

8.3.10.3 Eye-Opening Monitor

The DS250DF230’s Eye-Opening Monitor (EOM) measures the internal data eye at the input of the decision

slicer and can be used for 2 functions:

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement

2. Full Eye Diagram Capture

The HEO measurement is made at the 0 V crossing and is read in channel register 0x27. The VEO

measurement is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can

be read from channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are

used to convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

•

HEO [UI] = Reg_0x27 ÷ 32

VEO [mV] = Reg_0x28 × 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a

64 × 64 array, where each cell in the matrix consists of an 16-bit word representing the total number of hits

recorded at that particular phase and voltage offset. Users can manually adjust the vertical scaling of the EOM or

allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the

state machine is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out four 16-bit words of residual data that must be

discarded followed by 4096 16-bit words that make up the 64 × 64 eye plot. The first actual word of the eye plot

from the retimer is for (X, Y) position (0,0), which is the earliest position in time and the most negative position in

voltage. Each time the eye plot data is read out, the voltage position is incremented. Once the voltage position

has incremented to position 63 (the most positive voltage), the next read will cause the voltage position to reset

to 0 (the most negative voltage) and the phase position to increment. This process will continue until the entire

64 × 64 matrix is read out. Figure 14 shows the EOM read out sequence overlaid on top of a simple eye opening

plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO.

Users can apply different algorithms to the output data to plot density or color gradients to the output data.

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63

127

63

4095

0

64

4032

63

Phase Position

Figure 14. EOM Full Eye Capture Readout

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To manually control the EOM vertical range, remove scaling control from the state machine then select the

desired range:

Channel Reg 0x2C[6] → 0 (see Table 3).

Table 3. Eye-Opening Monitor Vertical Range Settings

CH REG 0x11[7:6] VALUE

EOM VERTICAL RANGE [mV]

2’b00

2'b01

2'b10

2'b11

±100

±200

±300

±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over

equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit

error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

•

Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.

With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this

mode, the device must be addressed each time a new byte is read.

To perform a full eye capture with the EOM, follow the steps listed in Table 4 within the desired channel register

set:

Table 4. Eye-Opening Monitor Full Eye Capture Instructions

STEP

REGISTER [bits]

0x67[5]

Operation

Write

VALUE

DESCRIPTION

Disable lock EOM lock monitoring

1

0

0x2C[6]

Write

2

Set the desired EOM vertical range

0x11[7:6]

0x11[5]

Write

2'b--

0

3

4

Write

Power on the EOM

Enable fast EOM

0x24[7]

Write

1

Begin read out of the 64 × 64 array, discard first 4 words

Ch reg 0x24[0] is self-clearing.

0x24[0]

0x25

0x26

5

6

Read

1

0x25 is the MSB of the 16-bit word

0x26 is the LSB of the 16-bit word

0x25

0x26

Continue reading information until the 64 × 64 array is

complete.

Read

0x67[5]

0x2C[6]

0x11[5]

0x24[7]

Write

1

0

7

Return the EOM to its original state. Undo steps 1-4

8.3.11 Interrupt Signals

The DS250DF230 can be configured to report different events as interrupt signals. These interrupt signals do not

impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits in

the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that

interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once

the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The

DS250DF230 will report the occurrence of an interrupt through the INT_N pin. The INT_N pin is an open-drain

output that will pull the line low when an interrupt signal is triggered.

Note that all available interrupts are disabled by default. Users must activate the various interrupts before they

can be used.

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The interrupts available in the DS250DF230 are:

•

CDR loss of lock

CDR locked

Signal detect loss

Signal detected

PRBS pattern checker bit error detected

HEO/VEO threshold violation

When an interrupt occurs, share register 0x08 reports which channel generated the interrupt request. Users can

then select the channel(s) that generated the interrupt request and service the interrupt by reading the

appropriate interrupt status bits in the corresponding channel registers. For more information on reading interrupt

status, refer to the DS250DF230 Programmer's Guide (SNLU182).

8.4 Device Functional Modes

8.4.1 Supported Data Rates

The DS250DF230 supports a wide range of input data rates, including divide-by-2 and divide-by-4 sub-rates. The

supported data rates are listed in Table 5.

Table 5. Supported Data Rates

DATA RATE RANGE

DIVIDER

CDR MODE

COMMENT

MIN

MAX

≥ 19.6 Gbps

> 12.9 Gbps

≥ 9.8 Gbps

> 6.45 Gbps

≥ 4.9 Gbps

≤ 25.8 Gbps

<19.6 Gbps

≤ 12.9 Gbps

< 9.8 Gbps

6.45 ≤ Gbps

< 4.9 Gbps

1

N/A

2

Enabled

Bypassed

Enabled

Output jitter will be higher with CDR bypassed.

N/A

4

Bypassed

Enabled

N/A

Bypassed

The device can be configured to operate at different standard data rates by programming the Rate/Sub-Rate

register Reg_2F[7:4], For more information on data rate programming, refer to the DS250DF230 Programmer's

Guide (SNLU182).

Table 6. Rate/Sub-Rate Table⁽¹⁾

RATE Reg_0x2F[7:4]

Standard

CPRI Option 9

CPRI Option 7

CPRI Option 8

CPRI Option 10

CPRI Option 5

100GbE

Input Data Rates [Gbps]

12.16512

Recovered Clock Frequency [MHZ]

0

30.72

1

9.83040

2

10.13760

30.72

3

4

24.33024

30.72

4.91520

30.72

5 (Default)

25.78125

32.2265625

30.72

25.78125

6

100GbE/ 40GbE/ 10GbE

10.31250

7

8

40GbE/ 10GbE

CPRI Option 6

10.31250

6.14400

(1) This table is valid only when the calibration clock is 30.72-MHZ. Refer to the DS250DF230 Programmer's Guide (SNLU182) for more

information.

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8.4.2 SMBus Master Mode

SMBus master mode allows the DS250DF230 to program itself by reading directly from an external EEPROM.

When using the SMBus master mode, the DS250DF230 will read directly from specific location in the external

EEPROM. When designing a system for using the external EEPROM, the user must follow these specific

guidelines:

•

Maximum EEPROM size is 2048 Bytes

Minimum EEPROM size for a single DS250DF230 with individual channel configuration is 161 Bytes (3 base

header bytes + 12 address map bytes + 2 × 72 channel register bytes + 2 share register bytes; bytes are

defined to be 8-bits)

•

Set ENSMB = Float, for SMBus master mode

The external EEPROM device address byte must be 0xA0

The external EEPROM device must support 400kHz operation at 2.5-V or 3.3-V supply

THR pin is pulled low by 1 kΩ to GND, so that DS250DF230 is working under 2.5-V/3.3-V SMBus interface

mode

•

Set the SMBus address of the DS250DF230 by configuring the ADDR0 and ADDR1 pins

When loading multiple DS250DF230 devices from the same EEPROM, use these guidelines to configure the

devices:

•

Configure the SMBus addresses for each DS250DF230 to be sequential. The first device in the sequence

must have an address of 0x30

Daisy chain READ_EN_N and ALL_DONE_N from one device to the next device in the sequence so that they

do not compete for the EEPROM at the same time.

If all of the DS250DF230 devices share the same EEPROM channel and share register settings, configure

the common channel bit in the base header to 1. With common channel configuration enabled, each

DS250DF230 device will configure all 2 channels with the same settings.

When loading a single DS250DF230 from an EEPROM, use these guidelines to configure the device:

•

Set the common channel bit to 0 to allow for individual channel configuration, or set the common channel bit

to 1 to load the same configuration settings to all channels.

•

When configuring individual channels, a 512, 1024 or 2048 Byte EEPROM must be used.

If there are more than three DS250DF230 devices on a PCB that require individual channel configuration,

then each device must have its own EEPROM.

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8.4.3 Device SMBus Address

The DS250DF230’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is

read on power up, after the internal power-on reset signal is de-asserted. The ADDR[1:0] pins are four-level

LVCMOS IOs, which provides for 16 unique SMBus addresses. The four levels are achieved by pin strap options

as follows:

•

0: 1 kΩ to GND

R: 10 kΩ to GND (20 kΩ also acceptable)

F: Float

1: 1 kΩ to VDD

Table 7. SMBus Address Map

REQUIRED ADDRESS PIN STRAP VALUE

8-BIT WRITE ADDRESS [HEX]

ADDR1

ADDR0

0x30

0x32

0x34

0x36

0x38

0x3A

0x3C

0x3E

0x40

0x42

0x44

0x46

0x48

0x4A

0x4C

0x4E

0

R

F

1

0

R

F

1

0

R

F

1

0

R

F

1

0

1

R

F

1

8.5 Programming

8.5.1 Bit Fields in the Register Set

Many of the registers in the DS250DF230 are divided into bit fields. This allows a single register to serve multiple

purposes which may be unrelated. Often, configuring the DS250DF230 requires writing a bit field that makes up

only part of a register value while leaving the remainder of the register value unchanged. The procedure for

accomplishing this task is to read in the current value of the register to be written, modify only the desired bits in

this value, and write the modified value back to the register. Of course, if the entire register is to be changed,

rather than just a bit field within the register, it is not necessary to read in the current value of the register first. In

all register configuration procedures described in the following sections, this procedure must be kept in mind. In

some cases, the entire register is to be modified. When only a part of the register is to be changed, however, the

procedure described above must be used.

Most register bits can be read or written to. However, some register bits are constrained to specific interface

instructions.

Register bits can have the following interface constraints:

•

R - Read only

RW - Read/Write

RWSC - Read/Write, self-clearing

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Programming (continued)

8.5.2 Writing to and Reading from the Global/Shared/Channel Registers

The DS250DF230 has 3 types of registers:

1. Global Registers – These registers can be accessed at any time and are used to select individual channel

registers, the shared registers or to read back the TI ID and version information.

2. Shared Registers – These registers are used for device-level configuration, status read back or control.

3. Channel Registers – These registers are used to control and configure specific features for each individual

channel. All channels have the same channel register set and can be configured independent of each other.

The global registers can be accessed at any time, regardless of whether the shared or channel register set is

selected. The DS250DF230 global registers are located on addresses 0xEF-0xFF. The function of the global

registers falls into the following categories:

•

Channel selection and share enabling – Registers 0xFC and 0xFF

Device and version information – Registers 0xEF-0xF3

Reserved/unused registers – all other addresses

Register 0xFC is used to select the channel registers to be written to. To select a channel, write a 1 to its

corresponding bit in register 0xFC. Note that more than one channel may be written to by setting multiple bits in

register 0xFC. However, when performing an SMBus read transaction only one channel can be selected at a

time. If multiple channels are selected in register 0xFC when attempting to perform an SMBus read, the device

will return 0xFF.

Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read-

modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a

single channel in register 0xFC. This type of configuration allows for the reading of a single channel's register

information and then writing to all channels with the modified value. Register 0xFF bit 0 is used to select the

shared register page or the channel register page for the channels selected in register 0xFC.

TI repeaters/retimers have a vendor ID register (0xFE) which will always read back 0x03. In addition, there are

three device ID registers (0xF0, 0xF1, and 0xF3). These are useful to verify that there is a good SMBus

connection between the SMBus master and the DS250DF230.

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8.6 Register Maps

Table 8. Global Registers

DEFAULT

ADDRESS

(HEX)

BITS

VALUE

(HEX)

MODE

EEPROM

FIELD NAME

DESCRIPTION

EF

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

0

1

0

1

0

1

0

1

0

1

0

1

0

R

N

SPARE

R

CHAN_CONFIG_ID[3]

CHAN_CONFIG_ID[2]

CHAN_CONFIG_ID[1]

CHAN_CONFIG_ID[0]

VERSION[7]

TI device ID (Quad count).

DS250DF230: 0x0E

R

F0

F1

F3

FB

FC

R

TI version ID

DS250DF230: 0x01

R

VERSION[6]

R

VERSION[5]

R

VERSION[4]

R

VERSION[3]

R

VERSION[2]

R

VERSION[1]

R

VERSION[0]

R

DEVICE_ID[7]

DEVICE_ID[6]

DEVICE_ID[5]

DEVICE_ID[4]

DEVICE_ID[3]

DEVICE_ID[2]

DEVICE_ID[1]

DEVICE_ID[0]

CHAN_VERSION[3]

CHAN_VERSION[2]

CHAN_VERSION[1]

CHAN_VERSION[0]

SHARE_VERSION[3]

SHARE_VERSION[2]

SHARE_VERSION[1]

SHARE_VERSION[0]

RESERVED

Device ID DS250DF230: 0x15

R

Digital Share Version

R

RW

RESERVED

EN_CH7

EN_CH6

EN_CH5

EN_CH4

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Register Maps (continued)

Table 8. Global Registers (continued)

DEFAULT

ADDRESS

(HEX)

BITS

VALUE

(HEX)

MODE

EEPROM

FIELD NAME

DESCRIPTION

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

0

1

0

RW

R

N

EN_CH3

EN_CH2

EN_CH1

EN_CH0

Select channel 1

Select channel 0

RESERVED

TI vendor ID

FD

RESERVED

FE

VENDOR_ID[7]

VENDOR_ID[6]

VENDOR_ID[5]

VENDOR_ID[4]

VENDOR_ID[3]

VENDOR_ID[2]

VENDOR_ID[1]

VENDOR_ID[0]

RESERVED

R

FF

RW

RESERVED

EN_SHARE_Q1

Select shared registers for quad 1

(DS250DF810, DS280DF810 only)

DS250DF230: 0

5

0

RW

N

4

3

2

0

RW

N

EN_SHARE_Q0

RESERVED

Select shared registers for quad 0

RESERVED

WRITE_ALL_CH

Allows user to write to all channels as

if they are the same, but only allows

read back from the channel specified

in 0xFC.

1

0

RW

N

Note: EN_CH_SMB must be = 1 or

else this function is invalid.

EN_CH_SMB

1: Enables SMBUS access to the

channels specified in Reg_0xFC

0: The shared registers are selected

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Table 9. Shared Registers

DEFAULT

ADDRESS

(HEX)

FIELD

BITS

VALUE

(HEX)

MODE

EEPROM

NAME

DESCRIPTION

SMBus Address

Strapped 7-bit address is 0x18 +

SMBus_Addr[3:0]

00

7

6

0

1

0

1

0

1

0

R

N

SMBUS_ADDR[3]

SMBUS_ADDR[2]

SMBUS_ADDR[1]

SMBUS_ADDR[0]

RESERVED

5

R

4

R

3:0

7

R

RESERVED

01

R

RESERVED

6

R

RESERVED

5

R

RESERVED

4

R

RESERVED

3

R

RESERVED

2

R

RESERVED

1

R

RESERVED

0

R

RESERVED

02

03

04

7:0

7

RW

RESERVED

RST_I2C_REGS

1: Reset shared registers. This bit is

self-clearing.

6

0

RWSC

N

0: Normal operation

RST_I2C_MAS

1: Reset for SMBus/I2C Master. This

bit is self-clearing.

5

4

0

RWSC

RW

N

0: Normal operation

FRC_EEPRM_RD

1: Force EEPROM Configuration

0: Normal operation

3

2

1

0

1

0

1

RW

Y

N

RESERVED

05

DISAB_EEPRM_CFG

1: Disable Master Mode EEPROM

configuration (if not started; this bit is

not effective if EEPROM configuration

is already started)

7

0

RW

N

0: Normal operation

6:5

4

0

1

RW

R

N

RESERVED

EEPROM_READ_DONE

1: SMBus Master mode EEPROM

read complete

0: SMBus Master mode EEPROM

read not started or not complete

TEST0_AS_CAL_CLK_IN

CAL_CLK_INV_DIS

1: Use TEST0 as the input for the

25MHz CAL_CLK instead of

CAL_CLK_IN. This must be configured

for quad0 only.

0: Normal operation. Use

CAL_CLK_IN as the input for the

25MHz CAL_CLK.

3

2

0

RW

N

1: Disable the inversion of

CAL_CLK_OUT

0: Normal operation. CAL_CLK_OUT

is inverted with respect to

CAL_CLK_IN.

0

RW

Y

1

0

1

0

RW

Y

N

RESERVED

06

7:0

34

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Table 9. Shared Registers (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

FIELD

NAME

BITS

MODE

EEPROM

DESCRIPTION

08

7

6

5

4

0

R

N

RESERVED

INT_Q0C3

RESERVED

Interrupt from channel 3. For

DS250DF810 and DS280DF810, this

applies to the quad selected by

Reg_0xFF[5:4]. Not applicable to

DS250DF210

3

2

0

R

N

INT_Q0C2

Interrupt from channel 2. For

DS250DF810 and DS280DF810, this

applies to the quad selected by

Reg_0xFF[5:4]. Not applicable to

DS250DF210

INT_Q0C1

INT_Q0C0

RESERVED

Interrupt from channel 1. For

DS250DF810 and DS280DF810, this

applies to the quad selected by

Reg_0xFF[5:4].

1

0

R

N

Interrupt from channel 0. For

DS250DF810 and DS280DF810, this

applies to the quad selected by

Reg_0xFF[5:4].

0A

0B

7:1

0

R

Y

RESERVED

DIS_REFCLK_OUT

1: Disable CAL_CLK_OUT (high-Z)

RW

0: Normal operation. Enable

CAL_CLK_OUT

7

6

5

4

0

1

RW

R

N

RESERVED

REFCLK_DET

1: 25MHz clock detected on

CAL_CLK_IN

0: No clock detected on CAL_CLK_IN

RW

RESERVED

DS250DF230:１

Other Devices: RESERVED, 0

MR_REFCLK_DET_DIS

0: CAL_CLK_IN detection and status

reporting enabled (default)

3

0

RW

N

1: CAL_CLK_IN detection disabled

2

1

0

1

RW

R

N

Y

RESERVED

0

0C

0D

0E

7:0

7:2

1:0

7:0

7

RW

R

0F

10

RW

6

5

4

3

2

1

0

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Table 9. Shared Registers (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

FIELD

NAME

BITS

MODE

EEPROM

DESCRIPTION

11: Not valid

11

7

0

R

N

EECFG_CMPLT

10: EEPROM load completed

successfully

EECFG_FAIL

01: EEPROM load failed after 64

attempts

6

0

R

N

00: EEPROM load in progress

5

4

3

2

1

0

R

N

EECFG_ATMPT[5]

EECFG_ATMPT[4]

EECFG_ATMPT[3]

EECFG_ATMPT[2]

EECFG_ATMPT[1]

EECFG_ATMPT[0]

REG_I2C_FAST

Number of attempts made to load

EEPROM image

12

1: EEPROM load uses Fast I2C Mode

(400 kHz)

7

1

RW

N

0: EEPROM load uses Standard I2C

Mode (100 kHz)

6

5

4

3

2

1

0

1

0

1

RW

N

RESERVED

36

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Table 10. Channel Registers, 0 to 39

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

00

7

6

5

4

3

0

RW

N

RESERVED

RST_CORE

1: Reset the 10M core clock domain.

This is the main clock domain for all

the state machines

0: Normal operation

2

1

0

RW

N

RST_REGS

RST_VCO

1: Reset channel registers to power-up

defaults.

0: Normal operation

1: Resets the CDR S2P clock domain,

includes PPM counter, EOM counter.

0: Normal operation

RST_REFCLK

1: Resets the 25MHz reference clock

domain, includes PPM counter. Does

not work if 25MHz clock is not present.

0: Normal operation

01

7

6

0

R

N

SIGDET

Raw Signal Detect observation

POL_INV_DET

Indicates PRBS checker detected

polarity inversion in the locked data

sequence.

5

4

0

R

N

CDR_LOCK_LOSS_INT

PRBS_SEQ_DET[3]

1: Indicates loss of CDR lock after

having acquired it. Bit clears on read.

Feature must be enabled with

Reg_0x31[1]

Indicates the pattern detected on the

input serial stream

0xxx: No detect

3

2

1

0

R

N

PRBS_SEQ_DET[2]

PRBS_SEQ_DET[1]

PRBS_SEQ_DET[0]

1000: 7 bits PRBS sequence

1001: 9 bits PRBS sequence

1010: 11 bits PRBS sequence

1011: 15 bits PRBS sequence

1100: 23 bits PRBS sequence

1101: 31 bits PRBS sequence

1110: 58 bits PRBS sequence

1111: 63 bits PRBS sequence

0

7

0

R

N

SIG_DET_LOSS_INT

CDR_STATUS[7]

Loss of signal indicator, set once

signal is acquired and then lost. Clears

on read. Feature must be enabled with

reg_31[0]

02

This register is used to read the status

of internal signal.

Select what is observable on this bus

using Reg_0x0C[7:4]

6

5

4

3

2

1

0

R

N

CDR_STATUS[6]

CDR_STATUS[5]

CDR_STATUS[4]

CDR_STATUS[3]

CDR_STATUS[2]

CDR_STATUS[1]

CDR_STATUS[0]

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

03

04

05

06

07

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

RW

Y

N

EQ_BST0[1]

This register can be used to force an

EQ boost setting if used in conjunction

with channel Reg_0x2D[3].

EQ_BST0[0]

EQ_BST1[1]

EQ_BST1[0]

EQ_BST2[1]

EQ_BST2[0]

EQ_BST3[1]

EQ_BST3[0]

RESERVED

38

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

08

7

6

5

4

3

2

1

0

7

0

1

0

1

0

RW

Y

RESERVED

REG_VCO_CAP_OV

09

Enable bit to override cap_cnt with

value in Reg_0x0B[4:0]

6

0

RW

Y

REG_SET_CP_LVL_LPF_OV

Enable bit to override lpf_dac_val with

value in Reg_0x1F[4:0]

5

4

0

RW

Y

REG_BYPASS_PFD_OV

0: Normal operation.

REG_EN_FD_PD_VCO_PDIQ_ Enable bit to override en_fd, pd_pd,

OV

pd_vco, pd_pdiq with Reg_0x1E[0],

Reg_0x1E[2], Reg_0x1C[0],

Reg_0x1C[1]

3

2

0

RW

Y

REG_EN_PD_CP_OV

REG_DIVSEL_OV

Enable bit to override pd_fd_cp and

pd_pd_cp with value in Reg_0x1B[1:0]

Enable bit to override divsel with value

in Reg_0x18[6:4]

1

0

7

6

0

RW

Y

RESERVED

0A

RESERVED

REG_EN_IDAC_PD_CP_OV_

Enable bit to override phase detector

AND_REG_EN_IDAC_FD_CP_ charge pump settings with

OV

Reg_0x1C[7:5]

Enable bit to override frequency

detector charge pump settings with

Reg_0x1C[4:2]

5

0

RW

Y

REG_DAC_LPF_HIGH_PHASE_ Enable bit to loop filter comparator trip

OV_

voltages with Reg_0x16[7:0]

AND_REG_DAC_LPF_LOW_PH

ASE_OV

4

3

0

RW

Y

N

RESERVED

REG_CDR_RESET_OV

Enable CDR Reset override with

Reg_0x0A[2]

2

1

0

RW

N

REG_CDR_RESET_SM

REG_CDR_LOCK_OV

CDR Reset override bit

Enable CDR lock signal override with

Reg_0x0A[0]

0

7

6

5

4

3

2

1

0

1

0

1

RW

N

Y

REG_CDR_LOCK

RESERVED

CDR lock signal override bit

RESERVED

0B

RESERVED

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

0C

7

6

5

4

3

2

1

0

7

0

1

RW

N

RESERVED

DES_PD

0D

1: De-serializer (for PRBS checker) is

powered down

0: De-serializer (for PRBS checker) is

enabled

6

5

4

3

2

1

0

RW

N

Y

N

RESERVED

RAW_TX_SWING

RESERVED

DS250DF230 A1 Only:

0: Low Swing(Default)

1: High Swing, only when CDR is

bypassed. Not Recommended when

CDR is enabled

0E

0F

10

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

N

RESERVED

40

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

11

7

6

0

RW

Y

EOM_SEL_VRANGE[1]

EOM_SEL_VRANGE[0]

Manually set the EOM vertical range,

used with channel Reg_0x2C[6]:

00: ±100 mV

01: ±200 mV

10: ±300 mV

11: ±400 mV

5

1

RW

Y

EOM_PD

1: Normal operation. Eye opening

monitor (EOM) is automatically duty-

cycled.

0: EOM is force-enabled

4

3

0

RW

N

Y

RESERVED

DFE_TAP2_POL

Bit forces DFE tap 2 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the specified

tap weight

2

1

0

7

0

1

RW

Y

DFE_TAP3_POL

DFE_TAP4_POL

DFE_TAP5_POL

DFE_TAP1_POL

Bit forces DFE tap 3 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the specified

tap weight

Bit forces DFE tap 4 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the specified

tap weight

Bit forces DFE tap 5 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the specified

tap weight

12

Bit forces DFE tap 1 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the specified

tap weight

6

5

4

3

2

1

0

1

RW

N

Y

RESERVED

DFE_WT1[4]

DFE_WT1[3]

DFE_WT1[2]

DFE_WT1[1]

DFE_WT1[0]

RESERVED

These bits force DFE tap 1 weight.

Manual DFE operation is required for

this to take effect by setting

Reg_0x15[7]=1.

If Reg_0x15[7]=0, the value defined

here is used as the initial DFE tap 1

weight during adaptation.

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

13

7

1

0

1

RW

N

EQ_PD_PEAKDETECT

1: Normal operation. Power down test

mode.

0: Test mode.

6

5

RW

Y

EQ_PD_SD

1: Power down signal detect.

0: Normal operation. Enable signal

detect.

EQ_HI_GAIN

1: Enable high DC gain mode in the

equalizer

0: Enable low DC gain mode in the

equalizer

(Refer to the Programming Guide for

more details)

4

1

RW

Y

EQ_EN_DC_OFF

1: Normal operation.

0: Disable DC offset compensation.

3

2

0

RW

Y

RESERVED

EQ_LIMIT_EN

1: Configures the final stage of the

equalizer to be a limiting stage.

0: Normal operation, final stage of the

equalizer is configured to be a non-

limiting stage.

1

0

7

0

RW

Y

RESERVED

14

EQ_SD_PRESET

1: Forces signal detect HIGH, and

force enables the channel. Should not

be set if bit 6 is set.

0: Normal Operation.

6

0

RW

Y

EQ_SD_RESET

1: Forces signal detect LOW and force

disables the channel. Should not be

set if bit 7 is set.

0: Normal Operation.

5

4

0

RW

Y

EQ_REFA_SEL1

EQ_REFA_SEL0

Controls the signal detect assert

levels.

(Refer to the Programming Guide for

more details)

3

2

0

1

RW

Y

EQ_REFD_SEL1

EQ_REFD_SEL0

Controls the signal detect de-assert

levels.

(Refer to the Programming Guide for

more details)

1

0

7

0

RW

N

Y

RESERVED

15

DFE_FORCE_EN

1: Enables manual DFE tap settings

0: Normal operation

6

5

4

3

0

1

0

RW

N

Y

RESERVED

DRV_PD

RESERVED

1: Powers down the high speed driver

0: Normal operation

2

0

RW

Y

RESERVED

DS250DF230 Alpha Version Only:

EQ_EN_BYPASS: CTLE (EQ) stage

1-3 bypass

1: CTLE stages 1-3 are bypassed

0: CTLE stage 1-3 are not bypassed

(default)

1

0

RW

Y

RESERVED

42

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

16

17

18

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

0

1

0

1

0

1

0

1

0

1

0

RW

Y

N

Y

RESERVED

PDIQ_SEL_DIV[2]

PDIQ_SEL_DIV[1]

PDIQ_SEL_DIV[0]

These bits will force the divider setting

if 0x09[2] is set.

000: Divide by 1

001: Divide by 2

010: Divide by 4

011: Divide by 8

100: Divide by 16

All other values are reserved.

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

0

1

0

1

0

RW

N

Y

N

Y

RESERVED

BG_SEL_RPH_LV[1]

BG_SEL_RPH_LV[0]

RESERVED

RPH

19

1A

RPH

RESERVED

DS250DF230: en_rclk_lv

1: Enable Recovered clock output on

IO pin

0: Disable Recovered clock output on

IO pin

1

0

RW

N

RESERVED

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

1B

7

6

5

4

3

2

1

0

1

RW

N

Y

RESERVED

CP_EN_CP_PD

1: Normal operation, phase detector

charge pump enabled

0

1

RW

Y

CP_EN_CP_FD

1: Normal operation, frequency

detector charge pump enabled

1C

1D

1E

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

1

0

1

0

1

RW

Y

N

Y

EN_IDAC_PD_CP2

EN_IDAC_PD_CP1

EN_IDAC_PD_CP0

EN_IDAC_FD_CP2

EN_IDAC_FD_CP1

EN_IDAC_FD_CP0

RESERVED

Phase detector charge pump setting.

Override bit required for these bits to

take effect

Frequency detector charge pump

setting. Override bit required for these

bits to take effect

RESERVED

PFD_SEL_DATA_PRELCK[2]

PFD_SEL_DATA_PRELCK[1]

PFD_SEL_DATA_PRELCK[0]

Output mode for when the CDR is not

locked. For these values to take effect,

Reg_0x09[5] must be set to 0, which is

the default.

000: Raw Data

111: Mute (Default)

All other values are reserved. (Refer to

the Programming Guide for more

details)

4

3

0

1

RW

N

Y

SER_EN

DFE_PD

1: Enable serializer (used for PRBS

Generator)

0: Normal operation. Disable serializer.

This bit must be cleared for the DFE to

be functional in any adapt mode.

1: (Default) DFE disabled.

0: DFE enabled

2

1

0

1

RW

Y

PFD_PD_PD

1: Power down PFD phase detector.

0: Normal operation. Enable PFD

phase detector.

EN_PARTIAL_DFE

PFD_EN_FD

1: Enable DFE taps 3-5. DFE_PD

must also be set to 0.

0: (Default) Disable DFE taps 3-5.

1: Normal operation. Enable PFD

frequency detector.

0: Disable PFD frequency detector.

44

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

1F

7

6

5

4

3

0

1

RW

N

Y

RESERVED

MR_LPF_AUTO_ADJST_EN

1: Normal operation. Allow LPF to tune

to optimum value during fast-cap

search routine.

0: Otherwise LPF value is determined

by the Reg_0x9D.

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

1

0

RW

Y

N

RESERVED

DFE_WT5[3]

DFE_WT5[2]

DFE_WT5[1]

DFE_WT5[0]

DFE_WT4[3]

DFE_WT4[2]

DFE_WT4[1]

DFE_WT4[0]

DFE_WT3[3]

DFE_WT3[2]

DFE_WT3[1]

DFE_WT3[0]

DFE_WT2[3]

DFE_WT2[2]

DFE_WT2[1]

DFE_WT2[0]

EOM_OV

RESERVED

20

21

22

Bits force DFE tap 5 weight, manual

DFE operation required to take effect

by setting 0x15[7]=1.

Bits force DFE tap 4 weight, manual

DFE operation required to take effect

by setting 0x15[7]=1.

Bits force DFE tap 3 weight, manual

DFE operation required to take effect

by setting 0x15[7]=1.

Bits force DFE tap 2 weight, manual

DFE operation required to take effect

by setting 0x15[7]=1.

1: Override enable for EOM manual

control

0: Normal operation

6

0

RW

N

EOM_SEL_RATE_OV

1: Override enable for EOM rate

selection

0: Normal operation

5

4

3

2

1

0

RW

N

RESERVED

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

23

7

0

RW

N

EOM_GET_HEO_VEO_OV

1: Override enable for manual control

of the HEO/VEO trigger

0: Normal operation

6

1

RW

Y

DFE_OV

1: Normal operation; DFE must be

enabled in Reg_0x1E[3].

5

4

3

2

1

0

7

0

RW

N

RESERVED

FAST_EOM

RESERVED

24

1: Enables fast EOM for full eye

capture. In this mode the phase DAC

and voltage DAC or the EOM are

automatically incremented through a

64 x 64 matrix. Values for each point

are stored in Reg_0x25 and

Reg_0x26.

0: Normal operation.

6

5

0

R

N

DFE_EQ_ERROR_NO_LOCK

DFE/CTLE SM quit due to loss of lock

GET_HEO_VEO_ERROR_NO_ get_heo_veo sees no hits at zero

HITS crossing

4

0

R

N

GET_HEO_VEO_ERROR_NO_ get_heo_veo cannot see a vertical eye

OPENING

opening

3

2

0

RW

N

RESERVED

DFE_ADAPT

RESERVED

RWSC

1: Manually start DFE adaption (self-

clearing).

0: Normal operation.

1

0

R

N

EOM_GET_HEO_VEO

1: Manually triggers HEO/VEO

measurement; feature must be

enabled with Reg_0x23[7]; the

HEO/VEO values are read from

Reg_0x27, Reg_0x28

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

RWSC

R

N

EOM_START

1: Starts EOM counter, self-clearing

MSBs of EOM counter

25

EOM_COUNT15

EOM_COUNT14

EOM_COUNT13

EOM_COUNT12

EOM_COUNT11

EOM_COUNT10

EOM_COUNT9

EOM_COUNT8

EOM_COUNT7

EOM_COUNT6

EOM_COUNT5

EOM_COUNT4

EOM_COUNT3

EOM_COUNT2

EOM_COUNT1

EOM_COUNT0

R

26

R

LSBs of EOM counter

R

46

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

27

28

29

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

0

R

N

HEO7

HEO6

HEO5

HEO4

HEO3

HEO2

HEO1

HEO0

VEO7

VEO6

VEO5

VEO4

VEO3

VEO2

VEO1

VEO0

HEO value, requires CDR to be locked

for valid measurement

R

VEO value, requires CDR to be locked

for valid measurement

R

RW

R

RESERVED

EOM_VRANGE_SETTING[1]

EOM_VRANGE_SETTING[0]

Read the currently set Eye Monitor

Voltage Range:

11 - +/-400mV

R

10 - +/- 300mV

01 - +/- 200mV

00 - +/- 100mV"

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

RW

R

N

Y

RESERVED

VEO[8]

VEO MSB value

HEO MSB value

R

HEO[8]

2A

RW

EOM_TIMER_THR[3]

EOM_TIMER_THR[2]

EOM_TIMER_THR[1]

EOM_TIMER_THR[0]

VEO_MIN_REQ_HITS[3]

VEO_MIN_REQ_HITS[2]

VEO_MIN_REQ_HITS[1]

VEO_MIN_REQ_HITS[0]

The value of EOM_TIMER_THR[7:4]

controls the amount of time the Eye

Monitor samples each point in the eye.

(Refer to the Programming Guide for

more details)

Whenever the Eye Monitor is used to

measure HEO and VEO, the data is

sampled for some number of bits, set

by Reg_0x2A[7:4]. This register sets

the number of hits within that sample

size that is required before the EOM

will indicate a hit has occurred. This

filtering only affects the VEO

measurement.

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

2B

7

6

5

4

3

2

1

0

1

0

1

0

RW

N

Y

RESERVED

EOM_MIN_REQ_HITS[3]

EOM_MIN_REQ_HITS[2]

EOM_MIN_REQ_HITS[1]

EOM_MIN_REQ_HITS[0]

Whenever the Eye Monitor is used to

measure HEO and VEO, the data is

sampled for some number of bits, set

by Reg_0x2A[7:4]. This register sets

the number of hits within that sample

size that is required before the EOM

will indicate a hit has occurred. This

filtering only affects the HEO

measurement.

2C

7

6

1

RW

N

Y

RELOAD_DFE_TAPS

VEO_SCALE

Causes DFE taps to load from last

adapted values

1: Normal operation. Scale VEO

based on EOM vrange.

5

4

1

RW

Y

DFE_SM_FOM1

DFE_SM_FOM0

This register defines the Figure of

Merit used when adapting the DFE:

00: not valid

01: SM uses only HEO

10: SM uses only VEO

11: SM uses both HEO and VEO

Additionally, if Reg_0x6E[6] is set to

'1', the Alternate FOM is used. This bit

takes precedence over DFE_SM_FOM

3

2

1

0

7

6

5

4

3

0

1

0

1

0

RW

Y

DFE_ADAPT_COUNTER[3]

DFE_ADAPT_COUNTER[2]

DFE_ADAPT_COUNTER[1]

DFE_ADAPT_COUNTER[0]

RESERVED

DFE look-beyond count.

2D

RESERVED

REG_EQ_BST_OV

1: Allow override control of the EQ

setting by writing to Reg_0x03

0: Normal operation.

2

0

RW

Y

RESERVED

DS250DF230:

1: Set CTLE bypass Enabled when

REG_RQ_BST_OV=1

0: Normal operation.

1

0

RW

Y

RESERVED

48

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

2E

7

6

5

0

RW

R

N

RESERVED

EQ_BST3_BIT2_TO_EQ

Read-back of eq_BST3[2] driving the

EQ

4

3

2

0

RW

N

RESERVED

PRBS_PATTERN_SEL[2]

MSB for the PRBS_PATTERN_SEL

field. Lower bits are found on

Reg_0x30[1:0]. Refer to the Reg_0x30

description on this table.

1

0

7

6

5

4

3

0

1

0

1

0

RW

N

Y

RESERVED

RATE[2]

RESERVED

2F

Configure PPM register and divider for

a standard data rate.

(Refer to the Programming Guide for

more details)

RATE[1]

RATE[0]

INDEX_OV

If this bit is 1, then Reg_0x39 is to be

used as 4-bit index to the [15:0] array

of EQ settings. The EQ setting at that

index is loaded to the EQ boost

registers going to the analog and is

used as the starting point for adaption.

2

1

RW

Y

EN_PPM_CHECK

1: (Default) Enable the PPM to be

used as a qualifier when performing

Lock Detect

0: Remove the PPM check as a lock

qualifier.

1

0

RW

Y

N

RESERVED

DS250DF230:

1: Disable eq_bypass for first 4 indices

0: Enable eq_bypass for first 4 indices

RWSC

CTLE_ADAPT

1: Re-starts CTLE adaptation, self-

clearing

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

RW

EEPROM

FIELD NAME

FREEZE_PPM_CNT

EQ_SEARCH_OV_EN

EN_PATT_INV

DESCRIPTION

30

7

6

5

0

N

Y

N

1: Freeze the PPM counter to allow

safe read asynchronously

RW

1: Enables the EQ 'search" bit to be

forced by Reg_0x13[2]

RW

1: Enable automatic pattern inversion

of successive 16 bit words when using

the "Fixed Pattern" generator option.

4

3

0

RW

N

RELOAD_PRBS_CHKR

PRBS_EN_DIG_CLK

1: Force reload of seed into PRBS

checker LFSR without holding the

checker in reset.

This bit enables the clock to operate

the PRBS generator and/or the PRBS

checker. Toggling this bit is the

primary method to reset the PRBS

pattern generator and PRBS checker.

2

0

RW

N

PRBS_PROGPATT_EN

Enable a fixed data pattern output.

Requires that serializer is enabled with

Reg_0x1E[4]. PRBS generator and

checker should be disabled,

Reg_0x30[3]. The fixed data pattern is

set by Reg_0x7C and Reg_0x97.

Enable inversion of the pattern every

16 bits with Reg_0x30[5].

1

0

RW

N

PRBS_PATTERN_SEL[1]

PRBS_PATTERN_SEL[0]

Selects the pattern output when using

the PRBS generator. Requires the

pattern generator to be configured

properly. The MSB for the

PRBS_PATTERN_SEL field is in

Reg_0x2E[2].

Use Reg_0x30[3] to enable the PRBS

generator.

000: 2^7-1 bits PRBS sequence

001: 2^9-1 bits PRBS sequence

010: 2^11-1 bits PRBS sequence

011: 2^15-1 bits PRBS sequence

100: 2^23-1 bits PRBS sequence

101: 2^31-1 bits PRBS sequence

110: 2^58-1 bits PRBS sequence

111: 2^63-1 bits PRBS sequence

50

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

PRBS_INT_EN

DESCRIPTION

31

7

0

RW

N

1: Enables interrupt for detection of

PRBS errors. The PRBS checker must

be properly configured for this feature

to work.

6

5

0

1

RW

Y

ADAPT_MODE[1]

ADAPT_MODE[0]

00: no adaption

01: adapt CTLE only

10: adapt CTLE until optimal, then

DFE, then CTLE again

11: adapt CTLE until lock, then DFE,

then EQ until optimal

Note: for ADAPT_MODE=2 or 3, the

DFE must be enabled by setting

Reg_0x1E[3]=0 and Reg_0x1E[1]=1.

(Refer to the Programming Guide for

more details)

4

3

0

RW

Y

EQ_SM_FOM[1]

EQ_SM_FOM[0]

CTLE (EQ) adaption state machine

figure of merit.

00: (Default) SM uses both HEO and

VEO

01: SM uses HEO only

10: SM uses VEO only

11: SM uses both HEO and VEO

Additionally, if Reg_0x6E[7]=1, the

Alternate FOM is used. Reg_0x6E[7]

takes precedence over EQ_SM_FOM.

2

1

0

RW

N

Y

RESERVED

CDR_LOCK_LOSS_INT_EN

Enable for CDR Lock Loss Interrupt.

Observable in Reg_0x01[5]

0

RW

Y

SIGNAL_DET_LOSS_INT_EN

Enable for Signal Detect Loss

Interrupt. Observable in Reg_0x01[0]

32

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

RW

Y

HEO_INT_THRESH[3]

HEO_INT_THRESH[2]

HEO_INT_THRESH[1]

HEO_INT_THRESH[0]

VEO_INT_THRESH[3]

VEO_INT_THRESH[2]

VEO_INT_THRESH[1]

VEO_INT_THRESH[0]

HEO_THRESH[3]

These bits set the threshold for the

HEO and VEO interrupt. Each

threshold bit represents 8 counts of

HEO or VEO.

33

In adapt mode 3, the register sets the

minimum HEO and VEO required for

CTLE adaption, before starting DFE

adaption. This can be a max of 15.

HEO_THRESH[2]

HEO_THRESH[1]

HEO_THRESH[0]

VEO_THRESH[3]

VEO_THRESH[2]

VEO_THRESH[1]

VEO_THRESH[0]

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

PPM_ERR_RDY

DESCRIPTION

34

7

0

R

N

1: Indicates that a PPM error count is

read to be read from channel

Reg_0x3B and Reg_0x3C

6

0

RW

Y

LOW_POWER_MODE_DISABL By default, all blocks (except signal

E

detect) power down after 100 ms after

signal detect goes low. If set high, all

blocks get powered on after the signal

detect initially goes high.

5

4

1

RW

Y

LOCK_COUNTER[1]

LOCK_COUNTER[0]

After achieving lock, the CDR

continues to monitor the lock criteria. If

the lock criteria fail, the lock is

checked for a total of N number of

times before declaring an out of lock

condition, where N is set by this the

value in these registers, with a max

value of +3, for a total of 4. If during

the N lock checks, lock is regained,

then the lock condition is left HI, and

the counter is reset back to zero.

3

2

1

0

7

6

1

0

RW

Y

DFE_MAX_TAP2_5[3]

DFE_MAX_TAP2_5[2]

DFE_MAX_TAP2_5[1]

DFE_MAX_TAP2_5[0]

DATA_LOCK_PPM[1]

DATA_LOCK_PPM[0]

These four bits are used to set the

maximum value by which DFE taps 2-

5 are able to adapt with each

subsequent adaptation. Same used for

both polarities.

35

Modifies the value of the PPM delta

tolerance from channel Reg_0x64:

00 - ppm_delta[7:0] =1 x

ppm_delta[7:0]

01 - ppm_delta[7:0] =1 x

ppm_delta[7:0] + ppm_delta[3:1]

10 - ppm_delta[7:0] =2 x

ppm_delta[7:0]

11 - ppm_delta[7:0] =2 x

ppm_delta[7:0] + ppm_delta[3:1]

5

0

RW

N

GET_PPM_ERROR

Get PPM error from PPM_COUNT -

clears when done. Normally updates

continuously, but can be manually

triggered with read value from

Reg_0x3B and Reg_0x3C

4

3

2

1

0

7

6

0

1

0

RW

Y

N

Y

DFE_MAX_TAP1[4]

DFE_MAX_TAP1[3]

DFE_MAX_TAP1[2]

DFE_MAX_TAP1[1]

DFE_MAX_TAP1[0]

RESERVED

Limits DFE tap 1 maximum magnitude.

36

RESERVED

HEO_VEO_INT_EN

1: Enable HEO/VEO interrupt

capability

5

4

3

2

1

0

1

0

RW

Y

N

Y

N

REF_MODE[1]

REF_MODE[0]

RESERVED

11: Normal Operation. Refererence

mode 3.

RESERVED

52

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Table 10. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

37

38

39

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

0

1

R

N

Y

CTLE_STATUS[7]

Feature is reserved for future use

CTLE_STATUS[6]

CTLE_STATUS[5]

CTLE_STATUS[4]

CTLE_STATUS[3]

CTLE_STATUS[2]

CTLE_STATUS[1]

CTLE_STATUS[0]

DFE_STATUS[7]

DFE_STATUS[6]

DFE_STATUS[5]

DFE_STATUS[4]

DFE_STATUS[3]

DFE_STATUS[2]

DFE_STATUS[1]

DFE_STATUS[0]

RESERVED

R

Feature is reserved for future use

R

RW

RESERVED

MR_EOM_RATE[1]

MR_EOM_RATE[0]

With eom_ov = 1, these bits control

the Eye Monitor Rate:

11: Use for full rate, fastest

10: Use for 1/2 Rate

All other values are reserved

4

3

2

1

0

RW

Y

RESERVED

START_INDEX[3]

START_INDEX[2]

START_INDEX[1]

START_INDEX[0]

Start index for EQ adaptation

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Table 11. Channel Registers, 3A to A9

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

3A

3B

3C

3D

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

RW

R

Y

N

Y

FIXED_EQ_BST0[1]

During adaptation, if the divider

setting is >2, then a fixed EQ setting

from this register will be used.

However, if channel Reg_0x6F[7] is

enabled, then an EQ adaptation will

be performed instead

FIXED_EQ_BST0[0]

FIXED_EQ_BST1[1]

FIXED_EQ_BST1[0]

FIXED_EQ_BST2[1]

FIXED_EQ_BST2[0]

FIXED_EQ_BST3[1]

FIXED_EQ_BST3[0]

PPM_COUNT[15]

PPM_COUNT[14]

PPM_COUNT[13]

PPM_COUNT[12]

PPM_COUNT[11]

PPM_COUNT[10]

PPM_COUNT[9]

PPM_COUNT[8]

PPM_COUNT[7]

PPM_COUNT[6]

PPM_COUNT[5]

PPM_COUNT[4]

PPM_COUNT[3]

PPM_COUNT[2]

PPM_COUNT[1]

PPM_COUNT[0]

EN_FIR_CURSOR

PPM count MSB

R

PPM count LSB

R

RW

1: Enable Pre- and Post-cursor FIR

0: Disable Pre- and Post-cursor FIR

(lower power)

6

5

0

RW

Y

FIR_C0_SGN

Main-cursor sign bit

0: positive

1: negative

DRV_SEL_LOW_RATE_LV

0: Default

1: Slow slew rate. Not recommended

for divided-by-1 data rates

4

3

2

1

0

7

6

1

0

1

0

1

RW

Y

FIR_C0[4]

FIR_C0[3]

FIR_C0[2]

FIR_C0[1]

FIR_C0[0]

FIR_PD_TX

FIR_CN1_SGN

Main-cursor magnitude

(Refer to the Programming Guide for

more details)

3E

Pre-cursor sign bit

1: negative

0: positive

5

4

3

2

1

0

RW

Y

RESERVED

FIR_CN1[3]

FIR_CN1[2]

FIR_CN1[1]

FIR_CN1[0]

RESERVED

Pre-cursor magnitude

(Refer to the Programming Guide for

more details)

54

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Table 11. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

3F

7

6

0

1

RW

Y

RESERVED

FIR_CP1_SGN

RESERVED

Post-cursor sign bit

1: negative

0: positive

5

0

RW

Y

DS250DF230: rclk_sel_div_lv[1]

Valid only inconjuction with

mr_cipri_clk_div_sel_ov; Otherwise

decoded from rate table

Analog Div Digital Div

00: 30 11

01: 32 10

10: 36 11

11: 40 10

4

0

RW

Y

RESERVED

DS250DF230: rclk_sel_div_lv[0], see


型号：	DS250DF230RTVT
厂家：	TEXAS INSTRUMENTS
描述：	DS250DF230 25-Gbps Multi-Rate 2-Channel Retimer
文件：	总105页 (文件大小：2771K)
中文：	中文翻译
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