DS25BR440TSQ/NOPB [TI]
具有发送预加重和接收均衡功能的 3.125Gbps 四路 LVDS 缓冲器 | RTA | 40;
| 型号： | DS25BR440TSQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有发送预加重和接收均衡功能的 3.125Gbps 四路 LVDS 缓冲器 | RTA | 40 接口集成电路 |
| 文件： | 总21页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS25BR440
www.ti.com
SNLS258B –FEBRUARY 2008–REVISED MARCH 2013
DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive
Equalization
Check for Samples: DS25BR440
1
FEATURES
DESCRIPTION
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer
optimized for high-speed signal routing and repeating
over lossy FR-4 printed circuit board backplanes and
balanced cables. Fully differential signal paths ensure
exceptional signal integrity and noise immunity.
2
•
DC - 3.125 Gbps Low Jitter, Low Skew, Low
Power Operation
•
•
Pin Selectable Transmit Pre-Emphasis and
Receive Equalization Eliminate Data
Dependant Jitter
The DS25BR440 features two levels of transmit pre-
emphasis (PE) and two levels of receive equalization
(EQ). Both of these features compensate for
interconnect losses and ultimately maximize noise
margin. A loss-of-signal (LOS) circuit monitors each
input channel and a unique LOS pin is asserted when
no signal is detected at that input.
Wide Input Common Mode Voltage Range
Allows DC-Coupled Interface to LVDS, CML
and LVPECL Drivers
•
•
LOS Circuitry Detects Open Inputs Fault
Integrated 100Ω Input and Output
Terminations
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower device return
losses, reduce component count and further minimize
board space.
•
•
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 6 mm x 6 mm WQFN-40 Space Saving
Package
APPLICATIONS
•
•
•
•
Clock and Data Buffering and Repeating
Copper Cable Driving and Equalization
FR-4 Equalization
OC-48 / STM-16
Typical Application
DS25BR440
Cable or Backplane
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS25BR440
SNLS258B –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Block Diagram
PWDNn
4
EQ0
IN0+
IN0-
EQ1
IN1+
IN1-
EQ2
IN2+
IN2-
EQ3
IN3+
IN3-
PE0
OUT0+
OUT0+
PE1
EQ
EQ
EQ
EQ
PE
PE
PE
PE
OUT1+
OUT1-
PE2
OUT2+
OUT2-
PE3
OUT3+
OUT3-
4
PWDN
LOSn
Connection Diagram
IN0+
IN0-
VDD
IN1+
IN1-
IN2+
IN2-
VDD
IN3+
IN3-
1
2
30
VDD
29
28
27
26
25
24
23
22
21
OUT0+
OUT0-
OUT1+
OUT1-
VDD
3
4
DAP
5
6
GND
7
OUT2+
OUT2-
OUT3+
OUT3-
8
9
10
DS25BR440 Pin Diagram
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Pin Name
SNLS258B –FEBRUARY 2008–REVISED MARCH 2013
PIN DESCRIPTIONS
Pin
Number
I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
EQ0, EQ1,
EQ2, EQ3
40, 39,
11, 12
I, LVCMOS
I, LVCMOS
I, LVCMOS
Receive equalization level select pins.
Transmit pre-emphasis level select pins.
PE0, PE1,
PE2, PE3
31, 20,
19, 18
PWDN0,
PWDN1,
PWDN2,
PWDN3
35,
34,
33,
32
Channel output power down pins. When the PWDNn is set to L, the channel
output OUTn is in the power down mode. The LOS circuitry on the
corresponding input remains enabled.
LOS0, LOS1,
LOS2, LOS3
14, 37,
36, 13
O, LVCMOS
Loss Of Signal output pins, LOSn report when an open input fault condition is
detected at the input, INn. These are open drain outputs. External pull up
resistors are required.
NC
17
38
NC
NO CONNECT pins. May be left floating.
PWDN
I, LVCMOS
Device power down pin. When the PWDN is set to L, the device is in the
power down mode. The LOS circuitry is disabled as well.
VDD
GND
3, 8,
15,25, 30
Power
Power
Power supply pins.
16, DAP
Ground pin and a pad (DAP - die attach pad).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Supply Voltage
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +4V
1V
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Voltage
Differential Input Voltage |VID|
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
0.0V to +1V
LVDS Differential Output Voltage
LVDS Output Short Circuit Current Duration
Junction Temperature
5 ms
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
RTA0040A Package
Derate RTA0040A Package
Package Thermal Resistance
θJA
2.44W
19.49 mW/°C above +25°C
+26.9°C/W
+3.8°C/W
θJC
ESD Susceptibility
(3)
HBM
≥8 kV
≥250V
(4)
MM
(5)
CDM
≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
1
Units
V
Supply Voltage (VCC
)
3.3
Receiver Differential Input Voltage (VID
)
V
Operating Free Air Temperature (TA)
−40
+25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
2.0
VDD
0.8
V
V
GND
VIN = 3.6V
VCC = 3.6V
0
±10
μA
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
4
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SNLS258B –FEBRUARY 2008–REVISED MARCH 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Low Level Input Current
Conditions
Min
Typ
Max
Units
IIL
VIN = GND
VCC = 3.6V
0
±10
μA
VCL
VOL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
V
Low Level Output Voltage
IOL= 4 mA
0.26
0.4
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
1
V
mV
mV
V
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
0
+100
−100
VCMR
0.05
VCC -
0.05
VIN = +3.6V or 0V
VCC = 3.6V or 0V
±1
±10
μA
IIN
Input Current
CIN
RIN
Input Capacitance
Any LVDS Input Pin to GND
Between IN+ and IN-
1.7
pF
Input Termination Resistor
100
Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
-35
350
1.2
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
1.05
-35
1.375
35
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
mV
(4)
IOS
Output Short Circuit Current
OUT to GND
-35
7
-55
55
mA
mA
pF
Ω
OUT to VCC
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
SUPPLY CURRENT
ICC
Supply Current
PE = OFF, EQ = OFF
PWDN = H
162
55
190
63
mA
mA
ICCZ
Power Down Supply Current
PWDN = L
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
(1) (2)
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
tPHLD
tSKD1
Differential Propagation Delay Low to
High
390
400
10
600
600
50
ps
ps
ps
(3)
RL = 100Ω
Differential Propagation Delay High to
(3)
Low
Pulse Skew |tPLHD − tPHLD
|
(3) (4)
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
(3) Specification is guaranteed by characterization and is not tested in production.
(4) tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
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AC Electrical Characteristics (1) (2) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tSKD2
Parameter
Conditions
Min
Typ
Max
Units
Channel to Channel Skew
18
65
ps
(3) (5)
tSKD3
Part to Part Skew
50
170
ps
(3) (6)
(3)
tLHT
tHLT
tON
Rise Time
80
80
8
160
160
20
ps
ps
μs
ns
RL = 100Ω
(3)
Fall Time
Any PWDN to Output Active Time
Any PWDN to Output Inactive Time
tOFF
5
12
JITTER PERFORMANCE WITH EQ = Off, PE = Off (3) (Figure 5)
tRJ1
tRJ2
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
6
1
1
ps
ps
No Test Channels
(7)
3.125 Gbps
2.5 Gbps
tDJ1
tDJ2
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
22
ps
No Test Channels
(8)
3.125 Gbps
2.5 Gbps
10
29
ps
tTJ1
tTJ2
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.04
0.06
0.09
0.14
UIP-P
UIP-P
No Test Channels
(9)
3.125 Gbps
JITTER PERFORMANCE WITH EQ = Off, PE = On (3) (Figure 6, Figure 9)
tRJ1B
tRJ2B
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
7
1
1
ps
ps
Test Channel B
(7)
3.125 Gbps
2.5 Gbps
tDJ1B
tDJ2B
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
15
ps
Test Channel B
(8)
3.125 Gbps
2.5 Gbps
4
23
ps
tTJ1B
tTJ2B
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.05
0.06
0.10
0.14
UIP-P
UIP-P
Test Channel B
(10)
3.125 Gbps
JITTER PERFORMANCE WITH EQ = On, PE = Off (11) (Figure 7, Figure 9)
tRJ1D
tRJ2D
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
1
1
ps
ps
Test Channel D
(12)
3.125 Gbps
2.5 Gbps
tDJ1D
tDJ2D
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
14
30
ps
Test Channel D
(13)
3.125 Gbps
2.5 Gbps
15
30
ps
tTJ1D
tTJ2D
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.08
0.10
0.15
0.17
UIP-P
UIP-P
Test Channel D
(10)
3.125 Gbps
JITTER PERFORMANCE WITH EQ = On, PE = On (11) (Figure 8, Figure 9)
tRJ1BD
tRJ2BD
Random Jitter (RMS Value)
Input Test Channel D
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
1
1
ps
ps
Output Test Channel B
3.125 Gbps
(12)
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(6) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
(10) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
(11) Specification is guaranteed by characterization and is not tested in production.
(12) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(13) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
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AC Electrical Characteristics (1) (2) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tDJ1BD
Parameter
Conditions
2.5 Gbps
Min
Typ
Max
Units
Deterministic Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
11
23
ps
tDJ2BD
3.125 Gbps
2.5 Gbps
5
24
ps
(13)
tTJ1BD
tTJ2BD
Total Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
VID = 350 mV
VCM = 1.2V
0.08
0.10
0.14
0.20
UIP-P
UIP-P
PRBS-23 (NRZ)
3.125 Gbps
(10)
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DC TEST CIRCUITS
¼ DS25BR440
V
OH
OUT+
IN+
Power Supply
R
L
R
D
Power Supply
IN-
OUT-
V
OL
Figure 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
¼ DS25BR440
OUT+
OUT-
IN+
IN-
Signal Generator
R
L
R
D
Figure 2. Differential Driver AC Test Circuit
Figure 3. Propagation Delay Timing Diagram
Figure 4. LVDS Output Transition Times
Pre-Emphasis and Equalization Test Circuits
DS25BR440
CHARACTERIZATION BOARD
50W
Microstrip
50W
Microstrip
¼ DS25BR440
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
Figure 5. Jitter Performance Test Circuit
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DS25BR440
TEST
CHARACTERIZATION BOARD
CHANNEL
¼ DS25BR440
50W MS
50W MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W MS
50W MS
Figure 6. Pre-emphasis Performance Test Circuit
TEST
DS25BR440
CHANNEL
CHARACTERIZATION BOARD
¼ DS25BR440
50W MS
50W MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W MS
50W MS
Figure 7. Equalization Performance Test Circuit
TEST
DS25BR440
TEST
CHANNEL
CHARACTERIZATION BOARD
CHANNEL
50W
Microstrip
50W
Microstrip
¼ DS25BR440
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
Figure 8. Pre-emphasis and Equalization Performance Test Circuit
50W MS
50W MS
L = A, B or C
L=1"
L=1"
L=1"
L=1"
100W Diff.
Stripline
50W MS
50W MS
Figure 9. Test Channel Block Diagram
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
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Test Channel
Length
(inches)
Insertion Loss (dB)
1000 MHz 1250 MHz
-2.0 -2.4
500 MHz
-1.2
750 MHz
-1.7
1500 MHz
-2.7
1560 MHz
-2.8
A
B
C
D
E
F
10
20
30
15
30
60
-2.6
-3.5
-4.1
-7.0
-2.7
-5.6
-12.4
-4.8
-8.2
-3.2
-6.6
-14.5
-5.5
-5.6
-4.3
-5.7
-9.4
-9.7
-1.6
-2.2
-3.7
-3.8
-3.4
-4.5
-7.7
-7.9
-7.8
-10.3
-16.6
-17.0
Functional Description
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over
lossy FR-4 printed circuit board backplanes and balanced cables.
The DS25BR440 has a pre-emphasis control pin for each output for switching the transmit pre-emphasis to ON
and OFF setting and an equalization control pin for each input for switching the receive equalization to ON and
OFF setting. The following are the transmit pre-emphasis and receive equalization truth tables.
Table 1. Transmit Pre-Emphasis Truth Table(1)
OUTPUT OUTn, n = {0, 1, 2, 3}
CONTROL Pin (PEn) State
Pre-emphasis Level
0
1
OFF
ON
(1) Transmit Pre-emphasis Level Selection for an Output OUTn
Table 2. Receive Equalization Truth Table(1)
INPUT INn, n = {0, 1, 2, 3}
CONTROL Pin (EQn) State
Equalization Level
0
1
OFF
ON
(1) Receive Equalization Level Selection for an Input INn
Input Interfacing
The DS25BR440 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS25BR440 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS25BR440 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS25BR440
Receiver
100W Differential T-Line
OUT+
IN+
100W
IN-
OUT-
Figure 10. Typical LVDS Driver DC-Coupled Interface to an DS25BR440 Input
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CML3.3V or CML2.5V
Driver
V
CC
DS25BR440
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 11. Typical CML Driver DC-Coupled Interface to an DS25BR440 Input
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
Figure 12. Typical LVPECL Driver DC-Coupled Interface to an DS25BR440 Input
Output Interfacing
The DS25BR440 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check the
respective receiver's data sheet prior to implementing the suggested interface implementation.
DS25BR440
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 13. Typical DS25BR440 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
Copyright © 2008–2013, Texas Instruments Incorporated
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11
Product Folder Links: DS25BR440
DS25BR440
SNLS258B –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Typical Performance
60
150
V
CC
= 3.3V
V
CC
= 3.3V
T = 25°C
A
NRZ PRBS-7
EQ = Off
T = 25°C
A
NRZ PRBS7
EQ = On
50
40
125
100
PE = Off
20" FR4 Stripline
30
75
20
10
50
25
10" FR4 Stripline
2.4 3.2
0
0
0
0.8
1.6
4.0
0
0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 14. Total Jitter as a Function of Data Rate
Figure 15. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
150
240
V
CC
= 3.3V
V
CC
= 3.3V
T = 25°C
A
NRZ PRBS7
PEM = On
T = 25°C
A
NRZ PRBS7
125
100
220
200
40" FR4 Stripline
PE = On
PE = Off
75
180
30" FR4 Stripline
50
25
160
140
20" FR4 Stripline
0.8 1.6
0
120
0
0.8
1.6
2.4
3.2
4.0
0
2.4
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 16. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
Figure 17. Supply Current as a Function of Data Rate and
PE Level
12
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR440
DS25BR440
www.ti.com
SNLS258B –FEBRUARY 2008–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DS25BR440
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS25BR440TSQ/NOPB
DS25BR440TSQX/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
RTA
RTA
40
40
250
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
2BR440SQ
2BR440SQ
2500 RoHS & Green
SN
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS25BR440TSQ/NOPB WQFN
DS25BR440TSQX/NOPB WQFN
RTA
RTA
40
40
250
178.0
330.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS25BR440TSQ/NOPB
DS25BR440TSQX/NOPB
WQFN
WQFN
RTA
RTA
40
40
250
208.0
356.0
191.0
356.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RTA0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
0.5
0.3
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
(0.2) TYP
(0.1) TYP
4.6 0.1
EXPOSED
THERMAL PAD
20
11
36X 0.5
10
21
4X
4.5
SEE TERMINAL
DETAIL
1
30
0.3
40X
40
31
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
0.1
C A B
40X
0.05
4214989/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.6)
SYMM
40
31
40X (0.6)
40X (0.25)
1
30
36X (0.5)
SYMM
(5.8)
(0.74)
TYP
(
0.2) TYP
VIA
(1.31)
TYP
10
21
(R0.05) TYP
11
20
(0.74) TYP
(1.31 TYP)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214989/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.48) TYP
9X ( 1.28)
40
31
40X (0.6)
1
30
40X (0.25)
36X (0.5)
(1.48)
TYP
SYMM
(5.8)
METAL
TYP
10
21
(R0.05) TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4214989/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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