DS25CP114TSQX/NOPB [TI]
具有 TX 预加重和 RX 均衡功能的 3.125Gbps 4x4 LVDS 交叉点开关 | RTA | 40 | -40 to 85;
| 型号： | DS25CP114TSQX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 TX 预加重和 RX 均衡功能的 3.125Gbps 4x4 LVDS 交叉点开关 | RTA | 40 | -40 to 85 开关 输出元件 |
| 文件： | 总31页 (文件大小：663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS25CP104A, DS25CP114
www.ti.com
SNLS305C –AUGUST 2008–REVISED MARCH 2013
DS25CP104A / DS25CP114 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit
Pre-Emphasis and Receive Equalization
Check for Samples: DS25CP104A, DS25CP114
1
FEATURES
DESCRIPTION
The DS25CP104A and DS25CP114 are 3.125 Gbps
4x4 LVDS crosspoint switches optimized for high-
speed signal routing and switching over lossy FR-4
printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional
signal integrity and noise immunity. The non-blocking
architecture allows connections of any input to any
output or outputs. The switch configuration can be
accomplished via external pins or the System
Management Bus (SMBus) interface.
2
•
DC - 3.125 Gbps Low Jitter, Low Skew, Low
Power Operation
•
•
Pin and SMBus Configurable, Fully
Differential, Non-Blocking Architecture
Pin (Two Levels) and SMBus (Four Levels)
Selectable Pre-Emphasis and Equalization
Eliminate ISI Jitter
•
•
•
Wide Input Common Mode Range Enables
Easy Interface to CML and LVPECL Drivers
The DS25CP104A and DS25CP114 feature four
levels (Off, Low, Medium, High) of transmit pre-
emphasis (PE) and four levels (Off, Low, Medium,
High) of receive equalization (EQ) settable via the
SMBus interface. Off and Medium PE levels and Off
and Low EQ levels are settable with the external pins.
In addition, the SMBus circuitry enables the loss of
signal (LOS) monitors that can inform a system of the
presence of an open inputs condition (e.g.
disconnected cable).
LOS Circuitry Detects Open Inputs Fault
Condition
On-Chip 100Ω Input and Output Termination
Minimizes Insertion and Return Losses,
Reduces Component Count, Minimizes Board
Space The DS25CP114 Eliminates the On-Chip
Input Termination for Added Design Flexibility.
•
•
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout. On
the DS25CP104A each differential input and output is
internally terminated with a 100Ω resistor to lower
return losses, reduce component count and further
minimize board space. For added design flexibility the
100Ω input terminations on the DS25CP114 have
been eliminated. This enables a designer to build
custom crosspoint configurations and distribution
circuits that require a limited multidrop signaling
topology.
Small 6 mm x 6 mm WQFN-40 Space Saving
Package
APPLICATIONS
•
•
•
SD/HD/3G HD SDI Routers
OC-48 / STM-16
InfiniBand and FireWire
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS25CP104A, DS25CP114
SNLS305C –AUGUST 2008–REVISED MARCH 2013
www.ti.com
Typical Application
INPUT CARD
OUTPUT CARD
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
BACKPLANES
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
DS25CP104
4 x 4 LVDS
DS25CP104
4 x 4 LVDS
Crosspoint Switch
Crosspoint Switch
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
DS25CP104
4 x 4 LVDS
Crosspoint Switch
CROSSPOINT CARD
Table 1. Device Information
Device
Function
Termination Option
Available Signal Conditioning
4 Levels: PE and EQ
DS25CP104A
DS25CP114
4x4 Crosspoint Switch
4x4 Crosspoint Switch
Internal 100Ω for LVDS inputs
None: Requires external
termination
4 Levels : PE and EQ
Block Diagram
S00 œ S31
8
EQ0
PE0
IN0+
EQ
OUT0+
OUT0+
PE1
PE
PE
PE
PE
IN0-
EQ1
IN1+
EQ
OUT1+
OUT1-
PE2
IN1-
4 X 4
EQ2
IN2+
EQ
OUT2+
OUT2-
PE3
IN2-
EQ3
IN3+
EQ
OUT3+
OUT3-
IN3-
System
Management Bus
PWDN
4
DS25CP104A
2
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SNLS305C –AUGUST 2008–REVISED MARCH 2013
S00 œ S31
8
EQ0
IN0+
IN0-
EQ1
IN1+
IN1-
EQ2
IN2+
IN2-
EQ3
IN3+
IN3-
PE0
OUT0+
OUT0+
PE1
EQ
EQ
EQ
EQ
PE
PE
PE
PE
OUT1+
OUT1-
PE2
4 X 4
OUT2+
OUT2-
PE3
OUT3+
OUT3-
System
Management Bus
PWDN
4
DS25CP114
Connection Diagram
IN0+
1
2
30
29
28
27
26
25
24
23
22
21
VDD
IN0-
VDD
IN1+
IN1-
IN2+
IN2-
VDD
IN3+
IN3-
OUT0+
3
OUT0-
OUT1+
OUT1-
VDD
4
DAP
5
6
(GND)
7
OUT2+
OUT2-
OUT3+
OUT3-
8
9
10
DS25CP104A / DS25CP114 Pin Diagram
Copyright © 2008–2013, Texas Instruments Incorporated
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PIN DESCRIPTIONS(1)
Pin
Number
Pin Name
I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS
Inverting and non-inverting high speed LVDS input pins. These 4 input pairs
have a 100 Ohm differential input termination on the CP104A device. The
CP114 eliminates the input termination for added design flexibility.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
Inverting and non-inverting high speed LVDS output pins. Each output pair has
an internal 100 Ohm termination to improve device return loss characteristics.
EQ0, EQ1,
EQ2, EQ3
40, 39,
11, 12
I, LVCMOS
I, LVCMOS
I, LVCMOS
Receive equalization level select pins. These pins are functional regardless of
the EN_smb pin state.
PE0, PE1,
PE2, PE3
31, 20,
19, 18
Transmit pre-emphasis level select pins. These pins are functional regardless
of the EN_smb pin state.
EN_smb
17
System Management Bus (SMBus) enable pin. The pin has an internal pull
down. When the pin is set to a [1], the device is in the SMBus mode. All
SMBus registers are reset when this pin is toggled. There is a 20k pulldown
device on this pin.
S00/SCL
S01/SDA
37
36
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are SMBus clock
input and data input pins respectively.
I/O, LVCMOS
S10/ADDR0,
S11/ADDR1
35,
34
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the User-Set
SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
For EN_smb = [0], these pins select which LVDS input is routed to the OUT2.
In the SMBus mode, when the EN_smb = H, these pins are the User-Set
SMBus Slave Address inputs.
S30, S31
PWDN
13, 14
38
For EN_smb = [0], these pins select which LVDS input is routed to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are non-functional
and should be tied to either logic H or L.
For EN_smb = [0], this is the power down pin. When the PWDN is set to a [0],
the device is in the power down mode. The SMBus circuitry can still be
accessed provided the EN_smb pin is set to a [1].
In the SMBus mode, the device is powered up by either setting the PWDN pin
to [1] OR by writing a [1] to the Control Register D[7] bit ( SoftPWDN). The
device will be powered down by setting the PWDN pin to [0] AND by writing a
[0] to the Control Register D[7] bit ( SoftPWDN).
VDD
GND
3, 8,
15,25, 30
Power
Power
Power supply pins.
16, DAP
Ground pin and a pad (DAP - die attach pad).
(1) Center DAP connection must be made to GND for optimum electrical and thermal performance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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SNLS305C –AUGUST 2008–REVISED MARCH 2013
Absolute Maximum Ratings(1)(2)
Supply Voltage
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +4V
1.0V
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Voltage
Differential Input Voltage |VID| (DS25CP104A)
LVDS Differential Input Voltage (DS25CP114)
LVDS Output Voltage
VCC + 0.6V
−0.3V to (VCC + 0.3V)
0V to 1.0V
LVDS Differential Output Voltage
LVDS Output Short Circuit Current Duration
Junction Temperature
5 ms
+150°C
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
−65°C to +150°C
+260°C
Maximum Package Power Dissipation at 25°C
RTA0040A Package
4.65W
Derate RTA0040A Package
Package Thermal Resistance
θJA
37.2 mW/°C above +25°C
+26.9°C/W
+3.8°C/W
θJC
ESD Susceptibility
(3)
HBM
≥8 kV
≥250V
(4)
MM
(5)
CDM
≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
1
Units
V
Supply Voltage (VCC
)
3.3
Receiver Differential Input Voltage (VID) (DS25CP104A only)
Operating Free Air Temperature (TA)
SMBus (SDA, SCL)
V
−40
+25
+85
3.6
°C
V
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
2.0
VCC
0.8
V
V
GND
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
Copyright © 2008–2013, Texas Instruments Incorporated
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
Parameter
High Level Input Current
Conditions
Min
Typ
0
Max
Units
μA
IIH
VIN = 3.6V
VCC = 3.6V
±10
250
±10
EN_smb pin
40
175
0
μA
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
μA
VCL
VOL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
IOL= 4 mA SDA pin
−0.9
−1.5
V
V
Low Level Output Voltage
0.4
LVDS INPUT DC SPECIFICATIONS
VID
VTH
VTL
Input Differential Voltage(4)
0
1
V
Differential Input High Threshold
Differential Input Low Threshold
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
0
+100
mV
mV
−100
VCC
0.05
-
VCMR
IIN
Input Common Mode Voltage Range
Input Current(5)
0.05
V
VIN = +3.6V or 0V
VCC = 3.6V or 0V
±1
±10
μA
CIN
RIN
Input Capacitance
Input Termination Resistor(6)
Any LVDS Input Pin to GND
Between IN+ and IN-
1.7
pF
100
Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
-35
350
1.2
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
1.05
-35
1.375
35
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
mV
OUT to GND
-35
7
-55
55
mA
mA
pF
Ω
(7)
IOS
Output Short Circuit Current
OUT to VCC
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
SUPPLY CURRENT
ICC1 Supply Current
ICC2
PWDN = 0
40
50
mA
mA
Supply Current
PWDN = 1
145
175
PE = Off, EQ = Off
Broadcast (1:4) Mode
ICC3
Supply Current
PWDN = 1
157
190
mA
PE = Off, EQ = Off
Quad Buffer (4:4) Mode
(4) Input Differential Voltage (VID) The DS25CP104A limits input amplitude to 1 volt. The DS25CP114 supports any VID within the supply
voltage to GND range.
(5) IIN is applied to both pins of the LVDS input pair at the same time.
(6) Input Termination Resistor (RIN) The DS25CP104A provides an integrated 100 ohm input termination for each high speed LVDS pair.
The DS25CP114 eliminates this internal termination.
(7) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
6
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SNLS305C –AUGUST 2008–REVISED MARCH 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(3)
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
480
460
650
650
ps
ps
High
RL = 100Ω
tPHLD
Differential Propagation Delay High to
Low
(4)
tSKD1
tSKD2
tSKD3
tLHT
Pulse Skew |tPLHD − tPHLD| ,
20
40
50
80
80
6
100
125
200
150
150
20
ps
ps
ps
ps
ps
μs
ns
ns
(5)
Channel to Channel Skew ,
(6)
Part to Part Skew ,
Rise Time
RL = 100Ω
tHLT
Fall Time
tON
Power Up Time
Power Down Time
Select Time
Time from PWDN =LH to OUTn active
Time from PWDN =HL to OUTn inactive
tOFF
tSEL
8
25
Time from Sn =LH or HL to new signal
at OUTn
8
12
JITTER PERFORMANCE WITH EQ = Off, PE = Off (3)(Figure 5)
tRJ1
tRJ2
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
0.5
1.1
1.1
ps
ps
No Test Channels
(7)
1.5625 GHz
2.5 Gbps
tDJ1
tDJ2
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
10
22
ps
No Test Channels
(8)
3.125 Gbps
2.5 Gbps
10
27
ps
tTJ1
tTJ2
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.07
0.13
0.11
0.16
UIP-P
UIP-P
No Test Channels
(9)
3.125 Gbps
JITTER PERFORMANCE WITH EQ = Off, PE = Low(3) (Figure 6, Figure 9)
tRJ1A
tRJ2A
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
0.5
10
1.1
1.1
22
ps
ps
ps
ps
Test Channels A
(7)
1.5625 GHz
2.5 Gbps
tDJ1A
tDJ2A
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
Test Channels A
(8)
3.125 Gbps
10
27
JITTER PERFORMANCE WITH EQ = Off, PE = Medium (3) (Figure 6, Figure 9)
tRJ1B
tRJ2B
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
0.5
1.1
1.1
ps
ps
Test Channels B
(7)
1.5625 GHz
2.5 Gbps
tDJ1B
tDJ2B
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
12
30
ps
Test Channels B
(8)
3.125 Gbps
2.5 Gbps
12
30
ps
tTJ1B
tTJ2B
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.08
0.10
0.10
0.15
UIP-P
UIP-P
Test Channels B
(9)
3.125 Gbps
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operating Conditions
at the time of product characterization and are not guaranteed.
(3) Specification is guaranteed by characterization and is not tested in production.
(4) tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(6) tSKD3, Part to Part Skew, is defined as the difference between the same signal path of any two devices running at the same VCC and
within 5°C of each other within the operating temperature range.
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
Copyright © 2008–2013, Texas Instruments Incorporated
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
JITTER PERFORMANCE WITH EQ = Off, PE = High(3)(Figure 6, Figure 9)
tRJ1C
tRJ2C
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
0.5
30
1.1
1.1
60
ps
ps
ps
ps
Test Channels C
(7)
1.5625 GHz
2.5 Gbps
tDJ1C
tDJ2C
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
Test Channels C
(8)
3.125 Gbps
30
65
JITTER PERFORMANCE WITH PE = Off, EQ = Low (3) (Figure 7, Figure 9)
tRJ1D
tRJ2D
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
0.5
1.1
1.1
ps
ps
Test Channels D
(7)
1.5625 GHz
2.5 Gbps
tDJ1D
tDJ2D
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
20
40
ps
Test Channels D
(8)
3.125 Gbps
2.5 Gbps
20
40
ps
tTJ1D
tTJ2D
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.08
0.09
0.15
0.20
UIP-P
UIP-P
Test Channels D
(9)
3.125 Gbps
JITTER PERFORMANCE WITH PE = Off, EQ = Medium (3) (Figure 7, Figure 9)
tRJ1E
tRJ2E
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
1.5625 GHz
2.5 Gbps
0.5
0.5
35
1.1
1.1
60
ps
ps
ps
Test Channels E
(7)
tDJ1E
tDJ2E
Residual Deterministic Jitter (Peak to
Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
Test Channels E
3.125 Gbps
28
55
ps
(8)
JITTER PERFORMANCE WITH PE = Off, EQ = High (3) (Figure 7, Figure 9)
tRJ1F
tRJ2F
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
1.5625 GHz
2.5 Gbps
1.3
1.4
30
1.8
2.4
75
ps
ps
ps
Test Channels F
(7)
tDJ1F
tDJ2F
Residual Deterministic Jitter (Peak to
Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
Test Channels F
3.125 Gbps
35
90
ps
(10)
JITTER PERFORMANCE WITH PE = Medium, EQ = Low (11) (Figure 7, Figure 9)
tRJ1G
tRJ2G
Random Jitter (RMS Value)
Input Test Channels D
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
0.5
25
1.1
1.1
ps
ps
ps
ps
Output Test Channels B
1.5625 GHz
2.5 Gbps
(12)
tDJ1G
tDJ2G
Deterministic Jitter (Peak to Peak)
Input Test Channels D
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
Output Test Channels B
3.125 Gbps
20
(10)
SMBus AC SPECIFICATIONS
fSMB SMBus Operating Frequency
tBUF
10
100
kHz
Bus free time between Stop and Start
Conditions
4.7
μs
tHD:SDA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0
μs
tSU:SDA
tSU:SDO
tHD:DAT
Repeated Start Condition setup time.
Stop Condition setup time
Data hold time
4.7
4.0
μs
μs
ns
300
(10) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(11) Specification is guaranteed by characterization and is not tested in production.
(12) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
tSU:DAT
tTIMEOUT
tLOW
Parameter
Data setup time
Conditions
Min
250
25
Typ
Max
Units
ns
Detect clock low timeout
Clock low period
35
ms
μs
4.7
4.0
tHIGH
Clock high period
50
μs
tPOR
Time in which a device must be
operational after power-on reset
500
ms
DC TEST CIRCUITS
¼ DS25CP104
V
OH
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
R
L
R
D
V
OL
Figure 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
¼ DS25CP104
OUT+
OUT-
IN+
IN-
Signal Generator
R
L
R
D
DS25CP114 requires external 100Ω input termination.
Figure 2. Differential Driver AC Test Circuit
Figure 3. Propagation Delay Timing Diagram
Figure 4. LVDS Output Transition Times
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Pre-Emphasis and Equalization Test Circuits
DS25CP104
CHARACTERIZATION BOARD
50W
Microstrip
50W
Microstrip
¼ DS25CP104
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
DS25CP114 requires external 100Ω input termination.
Figure 5. Jitter Performance Test Circuit
DS25CP104
CHARACTERIZATION BOARD
TEST
CHANNEL
¼ DS25CP104
50W MS
50W MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W MS
50W MS
DS25CP114 requires external 100Ω input termination.
Figure 6. Pre-Emphasis Performance Test Circuit
TEST
DS25CP104
CHANNEL
CHARACTERIZATION BOARD
¼ DS25CP104
50W MS
50W MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W MS
50W MS
DS25CP114 requires external 100Ω input termination.
Figure 7. Equalization Performance Test Circuit
TEST
DS25CP104
TEST
CHANNEL
CHARACTERIZATION BOARD
CHANNEL
50W
Microstrip
50W
Microstrip
¼ DS25CP104
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
DS25CP114 requires external 100Ω input termination.
Figure 8. Pre-Emphasis and Equalization Performance Test Circuit
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50W MS
50W MS
L = A, B or C
L=1"
L=1"
L=1"
L=1"
100W Diff.
Stripline
50W MS
50W MS
Figure 9. Test Channel Block Diagram
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
Insertion Loss (dB)
1000 MHz 1250 MHz
-2.0 -2.4
500 MHz
-1.2
750 MHz
-1.7
1500 MHz
-2.7
1560 MHz
-2.8
A
B
C
D
E
F
10
20
30
15
30
60
-2.6
-3.5
-4.1
-7.0
-2.7
-5.6
-12.4
-4.8
-8.2
-3.2
-6.6
-14.5
-5.5
-5.6
-4.3
-5.7
-9.4
-9.7
-1.6
-2.2
-3.7
-3.8
-3.4
-4.5
-7.7
-7.9
-7.8
-10.3
-16.6
-17.0
Functional Description
The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4 LVDS digital crosspoint switch optimized for high-speed
signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. The
DS25CP104A and DS25CP114 operate in two modes: Pin Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with external pins. This is possible with two input select
pins per output (e.g. S00 and S01 pins for OUT0). There is also one transmit pre-emphasis (PE) level select pin
per output for switching the PE levels between Medium and Off settings and one receive equalization (EQ) level
select pin per input for switching the EQ levels between Low and Off settings.
In the Pin Mode, feedback from the LOS (Loss Of Signal) monitor circuitry is not available (there is not an LOS
output pin).
When in the SMBus Mode, the full switch configuration, four levels of transmit pre-emphasis (Off, Low, Medium
and High), four levels of receive equalization (Off, Low, Medium and High) and SoftPWDN can be programmed
via the SMBus interface. In addition, by using the SMBus interface, a user can obtain the feedback from the built-
in LOS circuitry which detects an open inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus clock (SCL) input and data (SDA) input pins
respectively; the S10, S11, S21 and S21 pins become the User-Set SMBus Slave Address input pins (ADDR0, 1,
2 and 3) while the S30 and S31 pins become non-functional (tieing these two pins to either H or L is
recommended if the device will function only in the SMBus mode).
In the SMBus Mode, the PE and EQ select pins as well as the PWDN pin remain functional. How these pins
function in each mode is explained in the following sections.
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OPERATION IN PIN MODE
Power Up
In the Pin Mode, when the power is applied to the device power suppy pins, the DS25CP104A/DS25CP114
enters the Power Up mode when the PWDN pin is set to logic H. When in the Power Down mode (PWDN pin is
set to logic L), all circuitry is shut down except the minimum required circuitry for the LOS and SMBus Slave
operation.
Switch Configuration
In the Pin Mode, the DS25CP104A/DS25CP114 operates as a fully pin-configurable crosspoint switch. The
following truth tables illustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
Table 2. Input Select Pins Configuration for the Output OUT0
S01
0
S00
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
Table 3. Input Select Pins Configuration for the Output OUT1
S11
0
S10
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
Table 4. Input Select Pins Configuration for the Output OUT2
S21
0
S20
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
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Table 5. Input Select Pins Configuration for the Output OUT3
S31
0
S30
0
INPUT SELECTED
IN0
IN1
IN2
IN3
0
1
1
0
1
1
Setting Pre-Emphasis Levels
The DS25CP104A/DS25CP114 has one PE level select pin per output for setting the transmit pre-emphasis to
either Medium or Off level. The following is the transmit pre-emphasis truth table.
Table 6. Transmit Pre-Emphasis Truth Table
OUTPUT OUTn, n = {0, 1, 2, 3}
Pre-Emphasis Control Pin (PEn) State
Pre-Emphasis Level
0
1
Off
Medium
Setting Equalization Levels
The DS25CP104A/DS25CP114 has one EQ level select pin per input for setting the receive equalization to either
Low or Off level. The following is the receive equalization truth table.
Table 7. Receive Equalization Truth Table
INPUT INn, n = {0, 1, 2, 3}
Equalization Control Pin (EQn) State
Equalization Level
0
1
Off
Low
OPERATION IN SMBUS MODE
The DS25CP104A/DS25CP114 operates as a slave on the System Management Bus (SMBus) when the
EN_smb pin is set to a high (1). Under these conditions, the SCL pin is a clock input while the SDA pin is a serial
data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS25CP104A/DS25CP114 has a 7-bit slave address. The three most
significant bits of the slave address are hard wired inside the DS25CP104A/DS25CP114 and are “101”. The four
least significant bits of the address are assigned to pins ADDR3-ADDR0 and are set by connecting these pins to
GND for a low (0) or to VCC for a high (1). The complete slave address is shown in the following table:
Table 8. Slave Address
1
0
1
ADDR3
ADDR2
ADDR1
ADDR0
LSB
MSB
This slave address configuration allows up to sixteen DS25CP104A/DS25CP114 devices on a single SMBus
bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition.
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IDLE: If SCK and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if they
are high for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS25CP104A SMBus into the START condition, then a byte (8
bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify
NACK, after this the host holds the SCL line low, and waits for the receiver to raise the SDA line as an
ACKnowledge that the byte has been received.
Writing to a Register
To write a register, the following protocol is used (see SMBus 2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and communication with other SMBus devices may now
occur.
Reading From a Register
To read a register, the following protocol is used (see SMBus 2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and communication with other SMBus devices may now
occur.
Register Descriptions
There are five data registers in the DS25CP104A/DS25CP114 accessible via the SMBus interface.
Table 9. SMBus Data Registers
Address
(hex)
Name
Access
Description
0
1
2
3
Switch Configuration
PE Level Select
EQ Level Select
Control
R/W
R/W
R/W
R/W
Switch Configuration Register
Transmit Pre-emphasis Level Select Register
Receive Equalization Level Select Register
Powerdown, LOS Enable and Pin Control Register
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Table 9. SMBus Data Registers (continued)
Address
(hex)
Name
Access
Description
4
LOS
RO
Loss Of Signal (LOS) Reporting Register
4
SCL
SDA
SMBus
EN_smb
Interface
Switch
Control
PE Level
Select Register
EQ Level
Select Register
LOS
Register
Configuration
Register
Register
Figure 10. Registers Block Diagram
SWITCH CONFIGURATION REGISTER
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch
Configuration Register mapping and associated truth table.
Switch Configuration Register Mapping
Bit
Default
00
Bit Name
Access
Description
D[1:0]
D[3:2]
D[5:4]
D[7:6]
Input Select 0
Input Select 1
Input Select 2
Input Select 3
R/W
Selects which input is routed to the OUT0.
Selects which input is routed to the OUT1.
Selects which input is routed to the OUT2.
Selects which input is routed to the OUT3.
00
R/W
00
R/W
00
R/W
Switch Configuration Register Truth Table
D1
D0
0
Input Routed to the OUT0
0
0
1
1
IN0
IN1
IN2
IN3
1
0
1
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power
consumption based on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the
power down state).
PE LEVEL SELECT REGISTER
The PE Level Select register selects the pre-emphasis level for each of the outputs. The following two tables
show the register mapping and associated truth table.
PE Level Select Register Table
Bit
Default
Bit Name
Access
Description
D[1:0]
00
PE Level Select
0
R/W
Sets pre-emphasis level on the OUT0.
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PE Level Select Register Table (continued)
Bit
Default
Bit Name
Access
Description
D[3:2]
00
PE Level Select
1
R/W
Sets pre-emphasis level on the OUT1.
D[5:4]
D[7:6]
00
00
PE Level Select
2
R/W
R/W
Sets pre-emphasis level on the OUT2.
Sets pre-emphasis level on the OUT3.
PE Level Select
3
PE Level Select Register Truth Table
D1
D0
0
Pre-Emphasis Level for the OUT0
0
0
1
1
Off
Low
1
0
Medium
High
1
EQ LEVEL SELECT REGISTER
The EQ Level Select register selects the equalization level for each of the inputs. The following two tables show
the register mapping and associated truth table.
Bit
Default
Bit Name
Access Description
D[1:0]
00
EQ Level
Select 0
R/W
R/W
R/W
R/W
Sets equalization level on the IN0.
D[3:2]
D[5:4]
D[7:6]
00
00
00
EQ Level
Select 1
Sets equalization level on the IN1.
Sets equalization level on the IN2.
Sets equalization level on the IN3.
EQ Level
Select 2
EQ Level
Select 3
Table 10. EQ Level Select Register Truth Table
D1
0
D0
0
Equalization Level for the IN0
Off
Low
0
1
1
0
Medium
High
1
1
CONTROL REGISTER
The Control register enables SoftPWDN control, individual output power down (PWDNn) control, LOS Circuitry
Enable control, PE Level Select Enable control and EQ Level Select Enable control via the SMBus. The following
table shows the register mapping.
Table 11. Register Mapping Table
Bit
Default
Bit Name
Access
Description
D[3:0]
1111
PWDNn
R/W
Writing a [0] to the bit D[n] will power down the output OUTn when either the
PWDN pin OR the Control Register bit D[7] (SoftPWDN) is set to a high [1].
D[4]
D[5]
D[6]
0
0
0
Ignore_External_
EQ
R/W
R/W
R/W
Writing a [1] to the bit D[4] will ignore the state of the external EQ pins and
will allow setting the EQ levels via the SMBus interface.
Ignore_External_
PE
Writing a [1] to the bit D[5] will ignore the state of the external PE pins and will
allow setting the PE levels via the SMBus interface.
EN_LOS
Writing a [1] to the bit D[6] will enable the LOS circuitry and receivers on all
four inputs. The SmartPWDN circuitry will not disable any of the inputs nor
any supporting LOS circuitry depending on the switch configuration.
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Table 11. Register Mapping Table (continued)
Bit
Default
Bit Name
Access
Description
D[7]
0
SoftPWDN
R/W
Writing a [0] to the bit D[7] will place the device into the power down mode.
This pin is ORed together with the PWDN pin.
Table 12. Power Modes Truth Table
PWDN
SoftPWDN
PWDNn
Power Mode
0
0
x
Power Down Mode. In this mode, all
circuitry is shut down except the minimum
required circuitry for the LOS and SMBus
Slave operation. The SMBus circuitry
allows enabling the LOS circuitry and
receivers on all inputs in this mode by
setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the
SmartPWDN circuitry will automatically
power down any unused I/O and logic
blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the
SmartPWDN circuitry indicates that that
particular output is needed for the
particular switch configuration and the
respective PWDNn bit has logic high [1].
An input will be enabled when the
SmartPWDN circuitry indicates that that
particular input is needed for the
particular switch configuration or the
EN_LOS bit is set to a [1].
LOS REGISTER
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the
register mapping.
Bit
Default
Bit Name
Access
Description
D[0]
0
LOS0
RO
Reading a [0] from the bit D[0] indicates an open inputs fault condition on the
IN0. A [1] indicates presence of a valid signal.
D[1]
D[2]
0
LOS1
RO
RO
RO
RO
Reading a [0] from the bit D[1] indicates an open inputs fault condition on the
IN1. A [1] indicates presence of a valid signal.
0
LOS2
Reading a [0] from the bit D[2] indicates an open inputs fault condition on the
IN2. A [1] indicates presence of a valid signal.
D[3]
0
LOS3
Reading a [0] from the bit D[3] indicates an open inputs fault condition on the
IN3. A [1] indicates presence of a valid signal.
D[7:4]
0000
Reserved
Reserved for future use. Returns undefined value when read.
INPUT INTERFACING
The DS25CP104A/DS25CP114 accepts differential signals and allows simple AC or DC coupling. With a wide
common mode range, the DS25CP104A/DS25CP114 can be DC-coupled with all common differential drivers
(i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common
differential drivers.
The DS25CP104A inputs are internally terminated with a 100Ω resistor for optimal device performance, reduced
component count, and minimum board space. External input terminations on the DS25CP114 need to be placed
as close as possible to the device inputs to achieve equivalent AC performance. When all four inputs are utilized
it may be necessary to alternate between the top and bottom layers to achieve the minimum device input to
termination distance. It is recommended that SMT resistors sized 0402 or smaller be used and the mounting
distance to the DS25CP114 pins kept under 200 mils.
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When using the DS25CP114 in a limited multi-drop topology, any transmission line stubs should be kept very
short to minimize any negative effects on signal quality. A single termination resistor or resistor network that
matches the differential line impedance should be used. If DS25CP114 input pairs from two separate devices are
to be connected to a single differential output, it is recommended that the DS25CP114 devices are mounted
directly opposite of each other. One on top of the PCB and the other directly under the first on the bottom of the
PCB, this keeps the distance between inputs equal to the PCB thickness.
LVDS
Driver
DS25CP104
Receiver
100W Differential T-Line
OUT+
IN+
100W
IN-
OUT-
Figure 11. Typical LVDS Driver DC-Coupled Interface to DS25CP104A Input
CML3.3V or CML2.5V
Driver
V
CC
DS25CP104
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 12. Typical CML Driver DC-Coupled Interface to DS25CP104A Input
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
DS25CP114 requires external 100Ω input termination.
Figure 13. Typical LVPECL Driver DC-Coupled Interface to DS25CP104A Input
OUTPUT INTERFACING
The DS25CP104A/DS25CP114 outputs signals that are compliant to the LVDS standard. Its outputs can be DC-
coupled to most common differential receivers. The following figure illustrates a typical DC-coupled interface to
common differential receivers and assumes that the receivers have high impedance inputs. While most
differential receivers have a common mode input range that can accommodate LVDS compliant signals, it is
recommended to check the respective receiver's data sheet prior to implementing the suggested interface
implementation.
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DS25CP104
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 14. Typical Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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Typical Performance Characteristics
60
150
V
CC
= 3.3V
V
CC
= 3.3V
T
= 25°C
T
= 25°C
A
A
50
40
125
100
NRZ PRBS-7
EQ = Off
PE = Off
NRZ PRBS7
EQ = Med
30" FR4 Stripline
30
75
20
10
50
25
20" FR4 Stripline
1.6 2.4
0
0
0
0.8
1.6
2.4
3.2
4.0
0
0.8
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 15. Total Jitter as a Function of Data Rate
Figure 16. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
150
150
V
= 3.3V
V
= 3.3V
CC
CC
T = 25°C
A
T
= 25°C
A
125
100
125
100
NRZ PRBS7
EQ = Low
NRZ PRBS7
EQ = High
20" FR4 Stripline
75
75
50
25
50
25
50" FR4 Stripline
40" FR4 Stripline
10" FR4 Stripline
2.4 3.2
0
0
0
0.8
1.6
4.0
0
0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 17. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
Figure 18. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
150
150
V
= 3.3V
V
= 3.3V
CC
CC
T = 25°C
A
T
= 25°C
A
125
100
125
100
NRZ PRBS7
PEM = Low
NRZ PRBS7
PEM = High
40" FR4 Stripline
75
75
30" FR4 Stripline
50
25
50
25
30" FR4 Stripline
10" FR4 Stripline
0.8 1.6
20" FR4 Stripline
2.4 3.2 4.0
0
0
0
0.8
1.6
2.4
3.2
4.0
0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 19. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
Figure 20. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
20
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP104A DS25CP114
DS25CP104A, DS25CP114
www.ti.com
SNLS305C –AUGUST 2008–REVISED MARCH 2013
Typical Performance Characteristics (continued)
150
240
V
CC
= 3.3V
V
CC
= 3.3V
T
= 25°C
A
T
= 25°C
A
125
100
220
200
NRZ PRBS7
PEM = Med
NRZ PRBS7
PEM 9
PEM 6
40" FR4 Stripline
75
180
PEM 3
PEM 0
30" FR4 Stripline
50
25
160
140
20" FR4 Stripline
0.8 1.6
0
120
0
0.8
1.6
2.4
3.2
4.0
0
2.4
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 21. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
Figure 22. Supply Current as a Function of Data Rate and
PE Level
Figure 23. A 2.5 Gbps NRZ PRBS-23 without PE
After 30" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 24. A 2.5 Gbps NRZ PRBS-23 with High PE
After 2" Differential FR-4 Microstrip
H: 75 ps / DIV, V: 100 mV / DIV
Figure 25. A 2.5 Gbps NRZ PRBS-23 with High PE
After 30" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 26. A 3.125 Gbps NRZ PRBS-23 without PE
After 30" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DS25CP104A DS25CP114
DS25CP104A, DS25CP114
SNLS305C –AUGUST 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Figure 27. A 3.125 Gbps NRZ PRBS-23 with High PE
After 2" Differential FR-4 Microstrip
Figure 28. A 3.125 Gbps NRZ PRBS-23 with High PE
After 30" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
H: 50 ps / DIV, V: 100 mV / DIV
Figure 29. A 2.5 Gbps NRZ PRBS-23 without EQ
After 60" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 30. A 2.5 Gbps NRZ PRBS-23 with High EQ
After 60" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 31. A 3.125 Gbps NRZ PRBS-23 without EQ
After 60" Differential FR-4 Stripline
Figure 32. A 3.125 Gbps NRZ PRBS-23 with High EQ
After 60" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
H: 50 ps / DIV, V: 100 mV / DIV
22
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP104A DS25CP114
DS25CP104A, DS25CP114
www.ti.com
SNLS305C –AUGUST 2008–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: DS25CP104A DS25CP114
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS25CP104ATSQ/NOPB
DS25CP104ATSQX/NOPB
DS25CP114TSQ/NOPB
DS25CP114TSQE/NOPB
DS25CP114TSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
RTA
RTA
RTA
RTA
RTA
40
40
40
40
40
250
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2CP104AS
2500 RoHS & Green
1000 RoHS & Green
SN
SN
SN
SN
2CP104AS
2CP114SQ
2CP114SQ
2CP114SQ
250
RoHS & Green
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS25CP104ATSQ/NOPB WQFN
RTA
RTA
40
40
250
178.0
330.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
DS25CP104ATSQX/
NOPB
WQFN
2500
DS25CP114TSQ/NOPB WQFN
DS25CP114TSQE/NOPB WQFN
DS25CP114TSQX/NOPB WQFN
RTA
RTA
RTA
40
40
40
1000
250
330.0
178.0
330.0
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS25CP104ATSQ/NOPB
DS25CP104ATSQX/NOPB
DS25CP114TSQ/NOPB
DS25CP114TSQE/NOPB
DS25CP114TSQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
RTA
RTA
RTA
RTA
RTA
40
40
40
40
40
250
2500
1000
250
208.0
356.0
356.0
208.0
356.0
191.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RTA0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
0.5
0.3
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
(0.2) TYP
(0.1) TYP
4.6 0.1
EXPOSED
THERMAL PAD
20
11
36X 0.5
10
21
4X
4.5
SEE TERMINAL
DETAIL
1
30
0.3
40X
40
31
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
0.1
C A B
40X
0.05
4214989/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.6)
SYMM
40
31
40X (0.6)
40X (0.25)
1
30
36X (0.5)
SYMM
(5.8)
(0.74)
TYP
(
0.2) TYP
VIA
(1.31)
TYP
10
21
(R0.05) TYP
11
20
(0.74) TYP
(1.31 TYP)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214989/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.48) TYP
9X ( 1.28)
40
31
40X (0.6)
1
30
40X (0.25)
36X (0.5)
(1.48)
TYP
SYMM
(5.8)
METAL
TYP
10
21
(R0.05) TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4214989/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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