DS25CP152 [TI]

3.125Gbps LVDS 2x2 交叉点开关;
DS25CP152
型号: DS25CP152
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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3.125Gbps LVDS 2x2 交叉点开关

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DS25CP152  
www.ti.com  
SNLS274D JANUARY 2008REVISED APRIL 2013  
DS25CP152 3.125 Gbps LVDS 2x2 Crosspoint Switch  
Check for Samples: DS25CP152  
1
FEATURES  
DESCRIPTION  
The DS25CP152 is  
a 3.125 Gbps 2x2 LVDS  
2
DC - 3.125 Gbps Low Jitter, Low Skew, Low  
Power Operation  
crosspoint switch optimized for high-speed signal  
routing and switching over lossy FR-4 printed circuit  
board backplanes and balanced cables. Fully  
differential signal paths ensure exceptional signal  
integrity and noise immunity. The non-blocking  
architecture allows connections of any input to any  
output or outputs.  
Pin Configurable, Fully Differential, Non-  
Blocking Architecture  
On-Chip 100Input and Output Terminations  
Minimize Return Losses, Reduce Component  
Count and Minimize Board Space  
8 kV ESD on LVDS I/O Pins Protects Adjoining  
Components  
Wide input common mode range allows the switch to  
accept signals with LVDS, CML and LVPECL levels;  
the output levels are LVDS. A very small package  
footprint requires a minimal space on the board while  
the flow-through pinout allows easy board layout.  
Each differential input and output is internally  
terminated with a 100resistor to lower device return  
losses, reduce component count and further minimize  
board space.  
Small 4 mm x 4 mm WQFN-16 Space Saving  
Package  
APPLICATIONS  
High-Speed Channel select Applications  
Clock and Data Buffering and Muxing  
OC-48 / STM-16  
SD/HD/3G HD SDI Routers  
Typical Application  
INPUT CARD  
OUTPUT CARD  
SD/HD/3G HD  
Reclocker +  
Cable Driver  
SD/HD/3G HD  
Adaptive Equalizer  
BACKPLANES  
DS25CP152  
2x2 LVDS  
DS25CP152  
2x2 LVDS  
Crosspoint Switch  
Crosspoint Switch  
SD/HD/3G HD  
Reclocker +  
Cable Driver  
SD/HD/3G HD  
Adaptive Equalizer  
SD/HD/3G HD  
Reclocker +  
Cable Driver  
SD/HD/3G HD  
Adaptive Equalizer  
DS25CP152  
2x2 LVDS  
DS25CP152  
2x2 LVDS  
Crosspoint Switch  
Crosspoint Switch  
SD/HD/3G HD  
Reclocker +  
Cable Driver  
SD/HD/3G HD  
Adaptive Equalizer  
Large  
(e.g. 128x128)  
Crosspoint Switch  
CROSSPOINT  
CARD  
Figure 1. Typical Application  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  
DS25CP152  
SNLS274D JANUARY 2008REVISED APRIL 2013  
www.ti.com  
Block Diagram  
SEL1 SEL0  
EN0  
IN0+  
IN0-  
OUT0+  
OUT0-  
EN1  
2 X 2  
IN1+  
IN1-  
OUT1+  
OUT1-  
Figure 2. Block Diagram  
Connection Diagram  
IN0+  
IN0-  
IN1+  
IN1-  
1
2
3
4
12  
11  
10  
9
OUT0+  
OUT0-  
OUT1+  
OUT1-  
DAP  
(GND)  
Figure 3. DS25CP152 Pin Diagram  
PIN DESCRIPTIONS  
Pin  
Number  
Pin Name  
I/O, Type  
Pin Description  
IN0+, IN0- ,  
IN1+, IN1-  
1, 2,  
3, 4  
I, LVDS  
Inverting and non-inverting high speed LVDS input pins.  
Inverting and non-inverting high speed LVDS output pins.  
OUT0+, OUT0-,  
OUT1+, OUT1-  
12, 11,  
10, 9  
O, LVDS  
SEL0, SEL1  
EN0, EN1  
NC  
7, 8  
I, LVCMOS  
I, LVCMOS  
I, LVCMOS  
Power  
Switch configuration pins. There is a 20 kpulldown resistor on each pin.  
Output enable pins. There is a 20 kpulldown resistor on each pin.  
"NO CONNECT" pins.  
14, 13  
6, 15  
16  
VDD  
Power supply pin.  
GND  
5, DAP  
Power  
Ground pin and Device Attach Pad (DAP) ground.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
2
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Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: DS25CP152  
DS25CP152  
www.ti.com  
SNLS274D JANUARY 2008REVISED APRIL 2013  
Absolute Maximum Ratings(1)(2)  
Supply Voltage  
0.3V to +4V  
0.3V to (VCC + 0.3V)  
0.3V to +4V  
1.0V  
LVCMOS Input Voltage  
LVDS Input Voltage  
Differential Input Voltage |VID|  
LVDS Output Voltage  
0.3V to (VCC + 0.3V)  
0V to 1.0V  
LVDS Differential Output Voltage  
LVDS Output Short Circuit Current Duration  
Junction Temperature  
5 ms  
+150°C  
Storage Temperature Range  
Lead Temperature Range  
Soldering (4 sec.)  
65°C to +150°C  
+260°C  
Maximum Package Power Dissipation at 25°C  
RGH0016A Package  
2.99W  
Derate RGH0016A Package  
Package Thermal Resistance  
θJA  
23.9 mW/°C above +25°C  
+41.8°C/W  
+6.9°C/W  
θJC  
ESD Susceptibility  
(3)  
HBM  
8 kV  
250V  
(4)  
MM  
(5)  
CDM  
1250V  
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of  
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or  
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating  
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.  
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.  
(3) Human Body Model, applicable std. JESD22-A114C  
(4) Machine Model, applicable std. JESD22-A115-A  
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C  
Recommended Operating Conditions  
Min  
3.0  
0
Typ  
Max  
3.6  
1
Units  
V
Supply Voltage (VCC  
)
3.3  
Receiver Differential Input Voltage (VID  
)
V
Operating Free Air Temperature (TA)  
40  
+25  
+85  
°C  
DC Electrical Characteristics  
Over recommended operating supply and temperature ranges unless otherwise specified.(1)  
(2) (3)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
LVCMOS DC SPECIFICATIONS  
VIH  
VIL  
IIH  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
2.0  
GND  
40  
VCC  
0.8  
V
V
VIN = 3.6V  
VCC = 3.6V  
175  
0
250  
μA  
IIL  
Low Level Input Current  
VIN = GND  
VCC = 3.6V  
±10  
μA  
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as  
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and  
are not ensured.  
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground  
except VOD and ΔVOD  
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions  
at the time of product characterization and are not ensured.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: DS25CP152  
DS25CP152  
SNLS274D JANUARY 2008REVISED APRIL 2013  
www.ti.com  
DC Electrical Characteristics (continued)  
Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
VCL  
Input Clamp Voltage  
ICL = 18 mA, VCC = 0V  
0.9  
1.5  
V
LVDS INPUT DC SPECIFICATIONS  
VID  
Input Differential Voltage  
0
1
V
mV  
mV  
V
VTH  
VTL  
Differential Input High Threshold  
Differential Input Low Threshold  
Common Mode Voltage Range  
VCM = +0.05V or VCC-0.05V  
VID = 100 mV  
0
0
+100  
100  
VCMR  
0.05  
VCC -  
0.05  
VIN = +3.6V or 0V  
VCC = 3.6V or 0V  
±1  
±10  
μA  
IIN  
Input Current  
CIN  
RIN  
Input Capacitance  
Any LVDS Input Pin to GND  
Between IN+ and IN-  
1.7  
pF  
Input Termination Resistor  
100  
Ω
LVDS OUTPUT DC SPECIFICATIONS  
VOD  
Differential Output Voltage  
250  
-35  
350  
1.2  
450  
35  
mV  
mV  
V
RL = 100Ω  
RL = 100Ω  
ΔVOD  
Change in Magnitude of VOD for Complimentary  
Output States  
VOS  
Offset Voltage  
1.05  
-35  
1.375  
35  
ΔVOS  
Change in Magnitude of VOS for Complimentary  
Output States  
mV  
(4)  
IOS  
Output Short Circuit Current  
OUT to GND  
-35  
7
-55  
55  
mA  
mA  
pF  
Ω
OUT to VCC  
COUT  
ROUT  
Output Capacitance  
Any LVDS Output Pin to GND  
Between OUT+ and OUT-  
1.2  
100  
Output Termination Resistor  
SUPPLY CURRENT  
ICC  
Supply Current  
Supply Current with Outputs Disabled  
EN0 = EN1 = High  
EN0 = EN1 = Low  
64  
23  
77  
29  
mA  
mA  
ICCZ  
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.  
AC Electrical Characteristics  
Over recommended operating supply and temperature ranges unless otherwise specified  
(1) (2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
LVDS OUTPUT AC SPECIFICATIONS  
tPLHD  
tPHLD  
tSKD1  
tSKD2  
tSKD3  
Differential Propagation Delay Low to  
High  
340  
344  
4
500  
500  
35  
ps  
ps  
ps  
ps  
ps  
(3)  
RL = 100Ω  
Differential Propagation Delay High to  
(3)  
Low  
Pulse Skew |tPLHD tPHLD  
|
(3) (4)  
Channel to Channel Skew  
12  
50  
40  
(3) (5)  
Part to Part Skew  
150  
(3) (6)  
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as  
otherwise modified or specified by the Electrical Characteristics Conditions and/or notes. Typical specifications are estimations only and  
are not ensured.  
(2) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions  
at the time of product characterization and are not ensured.  
(3) Specification is ensured by characterization and is not tested in production.  
(4) tSKD1, |tPLHD tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and  
the negative going edge of the same channel.  
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode  
(any one input to all outputs).  
(6) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This  
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.  
4
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Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: DS25CP152  
 
DS25CP152  
www.ti.com  
SNLS274D JANUARY 2008REVISED APRIL 2013  
AC Electrical Characteristics (continued)  
Over recommended operating supply and temperature ranges unless otherwise specified (1) (2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
65  
65  
7
Max  
120  
120  
20  
Units  
ps  
(3)  
tLHT  
tHLT  
tON  
Rise Time  
Fall Time  
RL = 100Ω  
(3)  
ps  
Output Enable Time  
Output Disable Time  
ENn = LH to output active  
ENn = HL to output inactive  
SELn LH or HL to output  
μs  
tOFF  
tSEL  
5
12  
ns  
Select Time  
3.5  
12  
ns  
(3)  
JITTER PERFORMANCE  
tRJ1  
VID = 350 mV  
VCM = 1.2V  
Clock (RZ)  
2.5 Gbps  
0.5  
0.5  
8
1
1
ps  
ps  
Random Jitter (RMS Value)  
(7)  
tRJ2  
3.125 Gbps  
2.5 Gbps  
tDJ1  
tDJ2  
VID = 350 mV  
VCM = 1.2V  
K28.5 (NRZ)  
25  
ps  
Deterministic Jitter (Peak to Peak)  
(8)  
3.125 Gbps  
2.5 Gbps  
3
19  
ps  
tTJ1  
tTJ2  
VID = 350 mV  
VCM = 1.2V  
PRBS-23 (NRZ)  
0.04  
0.03  
0.08  
0.09  
UIP-P  
UIP-P  
Total Jitter (Peak to Peak)  
(9)  
3.125 Gbps  
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.  
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is  
subtracted algebraically.  
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.  
DC Test Circuits  
V
OH  
OUT+  
OUT-  
IN+  
IN-  
Power Supply  
Power Supply  
R
L
R
D
V
OL  
Figure 4. Differential Driver DC Test Circuit  
AC Test Circuits and Timing Diagrams  
OUT+  
OUT-  
IN+  
IN-  
Signal Generator  
R
L
R
D
Figure 5. Differential Driver AC Test Circuit  
Figure 6. Propagation Delay Timing Diagram  
Copyright © 2008–2013, Texas Instruments Incorporated  
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5
Product Folder Links: DS25CP152  
 
DS25CP152  
SNLS274D JANUARY 2008REVISED APRIL 2013  
www.ti.com  
Figure 7. LVDS Output Transition Times  
Functional Description  
The DS25CP152 is a 3.125 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing and  
switching over lossy FR-4 printed circuit board backplanes and balanced cables.  
Table 1. Switch Configuration Truth Table  
S1  
0
S0  
0
OUT1  
IN0  
OUT0  
IN0  
0
1
IN0  
IN1  
1
0
IN1  
IN0  
1
1
IN1  
IN1  
Table 2. Output Enable Truth Table  
EN1  
EN0  
OUT1  
OUT0  
0
0
1
1
0
1
0
1
Disabled  
Disabled  
Enabled  
Enabled  
Disabled  
Enabled  
Disabled  
Enabled  
Input Interfacing  
The DS25CP152 accepts differential signals and allows simple AC or DC coupling. With a wide common mode  
range, the DS25CP152 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The  
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the  
DS25CP152 inputs are internally terminated with a 100Ω resistor.  
LVDS  
Driver  
DS25CP152  
Receiver  
100W Differential T-Line  
OUT+  
IN+  
100W  
IN-  
OUT-  
Figure 8. Typical LVDS Driver DC-Coupled Interface to DS25CP152 Input  
6
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Product Folder Links: DS25CP152  
DS25CP152  
www.ti.com  
SNLS274D JANUARY 2008REVISED APRIL 2013  
CML3.3V or CML2.5V  
Driver  
V
CC  
DS25CP152  
Receiver  
50W  
50W  
100W Differential T-Line  
OUT+  
OUT-  
IN+  
IN-  
100W  
Figure 9. Typical CML Driver DC-Coupled Interface to DS25CP152 Input  
LVPECL  
Driver  
LVDS  
Receiver  
100W Differential T-Line  
IN+  
IN-  
OUT+  
100W  
OUT-  
150-250W  
150-250W  
Figure 10. Typical LVPECL Driver DC-Coupled Interface to DS25CP152 Input  
Output Interfacing  
The DS25CP152 outputs signals that are compliant to the LVDS standard. Its outputs can be DC-coupled to  
most common differential receivers. The following figure illustrates typical DC-coupled interface to common  
differential receivers and assumes that the receivers have high impedance inputs. While most differential  
receivers have a common mode input range that can accommodate LVDS compliant signals, it is recommended  
to check the respective receiver's data sheet prior to implementing the suggested interface implementation.  
DS25CP152  
Driver  
Differential  
Receiver  
100W Differential T-Line  
IN+  
OUT+  
CML or  
LVPECL or  
LVDS  
100W  
100W  
OUT-  
IN-  
Figure 11. Typical DS25CP152 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver  
Copyright © 2008–2013, Texas Instruments Incorporated  
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Product Folder Links: DS25CP152  
DS25CP152  
SNLS274D JANUARY 2008REVISED APRIL 2013  
www.ti.com  
Typical Performance Characteristics  
Figure 12. A 3.125 Gbps NRZ PRBS-7 After 2"  
Figure 13. A 2.5 Gbps NRZ PRBS-7 After 2"  
Differential FR-4 Stripline  
Differential FR-4 Stripline  
V:100 mV / DIV, H:50 ps / DIV  
V:100 mV / DIV, H:75 ps / DIV  
60  
60  
V
CC  
= 3.3V  
V
CC  
= 3.3V  
T
= 25°C  
50  
40  
50  
40  
A
T
= 25°C  
A
NRZ PRBS-7  
3.125 Gbps  
NRZ PRBS-7  
VID = 350 mV  
30  
30  
20  
10  
20  
10  
0
0
0
0.66  
1.32  
1.98  
2.64  
3.3  
0
0.8  
1.6  
2.4  
3.2  
4.0  
INPUT COMMON MODE VOLTAGE (V)  
DATA RATE (Gbps)  
Figure 14. Total Jitter as a Function of Input Common Mode  
Voltage  
Figure 15. Total Jitter as a Function of Data Rate  
8
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Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: DS25CP152  
 
DS25CP152  
www.ti.com  
SNLS274D JANUARY 2008REVISED APRIL 2013  
REVISION HISTORY  
Changes from Revision C (April 2013) to Revision D  
Page  
Changed layout of National Data Sheet to TI format ............................................................................................................ 8  
Copyright © 2008–2013, Texas Instruments Incorporated  
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9
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PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
DS25CP152TSQ/NOPB  
ACTIVE  
WQFN  
RGH  
16  
1000 RoHS & Green  
SN  
Level-1-260C-UNLIM  
-40 to 85  
2C152SQ  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
DS25CP152TSQ/NOPB WQFN  
RGH  
16  
1000  
178.0  
12.4  
4.3  
4.3  
1.3  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
WQFN RGH 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
210.0 185.0 35.0  
DS25CP152TSQ/NOPB  
1000  
Pack Materials-Page 2  
IMPORTANT NOTICE AND DISCLAIMER  
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