DS280DF810ABVR [TI]
28Gbps 多速率 8 通道重定时器 | ABV | 135 | -40 to 85;
| 型号： | DS280DF810ABVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 28Gbps 多速率 8 通道重定时器 | ABV | 135 | -40 to 85 |
| 文件： | 总54页 (文件大小：2170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS280DF810
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
DS280DF810 28Gbps 多速率 8 通道重定时器
1 特性
3 说明
1
•
•
具有集成信号调节功能的八通道多速率重定时器
DS280DF810 是一款具有集成信号调节功能的八通道
多速率重定时器。该器件用于扩展有损且存在串扰的远
距离高速串行链路的延伸长度并提升稳定性，同时实现
不高于 10-15 的比特误码率 (BER)。
所有通道均可独立锁定在 20.2Gbps 至 28.4Gbps
的范围内（包括 10.1376Gbps、10.3125Gbps、
12.5Gbps 等子速率）
•
•
超低延迟：28.4Gbps 数据速率下的典型延迟
< 500ps
DS280DF810 各通道的串行数据速率均可独立锁定在
20.2Gbps 至 28.4Gbps 的连续范围内或者支持的任意
子速率（速率的一半和四分之一），包括
10.1376Gbps、10.3125Gbps 和 12.5Gbps 等关键数
据速率，因此该器件支持独立通道前向纠错 (FEC) 直
通。
单电源，无需低抖动基准时钟，集成了交流耦合电
容以降低电路板布线复杂程度并节省物料清单
(BOM) 成本
•
•
•
•
集成 2×2 交叉点
自适应性连续时间线性均衡器 (CTLE)
自适应判决反馈均衡器 (DFE)
器件信息(1)
封装
带有 3 抽头有限冲激响应 (FIR) 滤波器的低抖动发
射器
器件型号
封装尺寸（标称值）
135 引脚 FCBGA
(135)
DS280DF810
8.0mm x 13.0mm
•
•
•
•
组合式均衡，在 12.9GHz 频率下支持 35dB 以上的
通道损耗；14GHz 时的通道损耗超过 30dB
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
可调节发送幅值：205 mVppd 至 1225 mVppd（典
型值）
片上眼图监视器 (EOM)，伪随机二进制序列
(PRBS) 模式校验器/发生器
简化原理图
RX0P
RX0N
TX0P
TX0N
小型 8mm x 13mm 小型球状引脚栅格阵列 (BGA)
封装，可轻松实现直通布线
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2.5 V or 3.3 V
RX1P
RX1N
TX1P
TX1N
•
•
•
独特的引脚分配支持在封装下对高速信号进行路由
提供引脚兼容的中继器
To other open-drain
interrupt pins
VDD
SDA(1)
SDC(1)
1 kΩ
SMBus
Slave mode
工作温度范围：-40°C 至 85°C
To system SMBus
EN_SMB
TEST
ADDR0
ADDR1
Address straps
(pull-up, pull-down, or float)
25 MHz
2 应用
CAL_CLK_IN
CAL_CLK_OUT
ALL_DONE_N
GND
•
•
•
背板和中板长度延长
SMBus Slave
mode
Float for SMBus Slave
READ_EN_N
VDD
mode, or connect to next
device‘s READ_EN_N for
SMBus Master mode
针对前端口光学模块的抖动消除
2.5 V
IEEE802.3bj 100GbE、无线带宽增强型数据速率
1 ꢀF
(2x)
0.1 ꢀF
(4x)
(EDR) 以及 OIF-CEI-25G-LR/MR/SR/VSR 电气接
口
(1) SMBus signals need to be pulled up elsewhere in the system.
•
SFP28、QSFP28、CFP2/CFP4、CDFP
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS538
DS280DF810
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Electrical Characteristics........................................... 8
8
9
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 29
8.5 Programming........................................................... 30
8.6 Register Maps......................................................... 31
Application and Implementation ........................ 32
9.1 Application Information............................................ 32
9.2 Typical Application ................................................. 32
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Example .................................................... 41
12 器件和文档支持 ..................................................... 43
12.1 文档支持................................................................ 43
12.2 接收文档更新通知 ................................................. 43
12.3 支持资源................................................................ 43
12.4 商标....................................................................... 43
12.5 静电放电警告......................................................... 43
12.6 Glossary................................................................ 43
7.6 Timing Requirements, Retimer Jitter
Specifications........................................................... 12
7.7 Timing Requirements, Retimer Specifications........ 13
7.8 Timing Requirements, Recommended Calibration
Clock Specifications................................................. 14
7.9 Recommended SMBus Switching Characteristics
(Slave Mode)............................................................ 14
7.10 Recommended SMBus Switching Characteristics
(Master Mode).......................................................... 14
7.11 Typical Characteristics ......................................... 15
4 修订历史记录
Changes from Original (February 2019) to Revision A
Page
•
首次公开发布 .......................................................................................................................................................................... 1
2
版权 © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
5 说明 （续）
印刷电路板 (PCB) 上集成了物理交流耦合电容（TX 与 RX），无需使用外部电容。DS280DF810 具有单电源，且
可将对外部组件的需求降至最低。这些 特性 可降低 PCB 布线的复杂程度并节省 BOM 成本。
DS280DF810 的高级均衡 特性 包括：一个低抖动 3 抽头发送有限冲激响应 (FIR) 滤波器、一个自适应连续时间线
性均衡器 (CTLE) 以及一个自适应判决反馈均衡器 (DFE)。支持针对具有多个连接器且存在串扰的有损互连和背板
进行扩展。集成的时钟和数据恢复 (CDR) 功能可重置抖动预算并对高速串行数据进行重定时， 非常适用于前端口
光学模块 应用。DS280DF810 对每个通道对采用 2x2 交叉点，可为主机同时提供通道交叉和扇出选项。
DS280DF810 可通过 SMBus 或外部 EEPROM 进行配置。单个 EEPROM 最多可由 16 个器件共享。非破坏性片
上眼图监视器以及 PRBS 发生器和校验器为系统内诊断提供支持。
Copyright © 2016–2019, Texas Instruments Incorporated
3
DS280DF810
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
www.ti.com.cn
6 Pin Configuration and Functions
135-pin fcBGA, 0.8 mm BGA pin pitch
Top View
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Legend
J
H
G
F
GND
GND
TX1N
GND
TX2N
GND
TX3N
GND
TX4N
GND
GND
GND
VDD
VDD
VDD
GND
GND
TX5N
TX5P
GND
GND
VDD
GND
GND
RX5P
GND
TX6N
GND
GND
J
H
G
F
Control/Status
TX0N
TX0P
GND
GND
GND
TX1P
GND
GND
GND
SDC
SDA
TX2P
GND
GND
GND
GND
GND
RX2P
GND
GND
VDD
VDD
VDD
GND
GND
TX3P
GND
GND
VDD
GND
GND
RX3P
GND
GND
VDD
VDD
VDD
GND
GND
TX4P
GND
GND
VDD
GND
GND
RX4P
GND
GND
TX6P
GND
GND
GND
GND
TEST0
GND
GND
GND
TX7N
TX7P
GND
High-Speed
Ground
READ_E
N_N
GND
TEST4 INT_N
Power
CAL_
EN_
TEST5
SMB
CAL_
TI test pins /
Reserved
E
D
C
B
A
CLK_ TEST1 ADDR1
OUT
E
D
C
B
A
CLK_IN
ALL_
TEST6 DONE_
N
GND
RX0P
RX0N
GND
GND
GND
ADDR0 TEST7
GND
RX7P
RX7N
GND
GND
GND
GND
GND
GND
RX1P
RX6P
GND
GND
RX1N
GND
RX2N
GND
RX3N
GND
RX4N
GND
RX5N
GND
RX6N
GND
GND
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Pin Functions
PIN
INTERNAL
TYPE
PULL-UP/
PULL-DOWN
DESCRIPTION
NAME
NO.
HIGH SPEED DIFFERENTIAL I/Os
RX0P
RX0N
C15
B15
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
RX1P
RX1N
B13
A13
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
RX2P
RX2N
B11
A11
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
RX3P
RX3N
B9
A9
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
RX4P
RX4N
B7
A7
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
RX5P
RX5N
B5
A5
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
RX6P
RX6N
B3
A3
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
RX7P
RX7N
C1
B1
Inverting and non-inverting differential inputs to the equalizer. An
on-chip 100-Ω termination resistor connects RXP to RXN. These
inputs are AC coupled on-chip with physical 220 nF capacitors.
TX0P
TX0N
G15
H15
Output
Output
None
None
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
4
Copyright © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
Pin Functions (continued)
PIN
INTERNAL
PULL-UP/
PULL-DOWN
TYPE
DESCRIPTION
NAME
NO.
TX1P
TX1N
TX2P
TX2N
TX3P
TX3N
TX4P
TX4N
TX5P
TX5N
TX6P
TX6N
TX7P
TX7N
H13
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
J13
H11
J11
H9
J9
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
H7
J7
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
H5
J5
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
H3
J3
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
G1
H1
Inverting and non-inverting 50 Ω driver outputs. These outputs are
AC coupled on-chip with physical 220 nF capacitors.
CALIBRATION CLOCK PINS
25 MHz (±100 PPM) 2.5 V single-ended clock from external
oscillator. No stringent phase noise or jitter requirements on this
clock. Used to calibrate VCO frequency range. This clock is not
used to recover data.
Input, 2.5 V
CMOS
CAL_CLK_IN
E1
Weak pull-down
None
Output, 2.5 V
CMOS
2.5 V buffered replica of calibration clock input (pin E1) for
connecting multiple devices in a daisy-chained fashion.
CAL_CLK_OUT E15
SYSTEM MANAGEMENT BUS (SMBUS) PINS
ADDR0
D13
Input, 4-level
None
4-level strap pins used to set the SMBus address of the device.
The pin state is read on power-up. The multi-level nature of these
pins allows for 16 unique device addresses. The four strap options
include:
0: 1 kΩ to GND
R: 10 kΩ to GND
F: Float
1: 1 kΩ to VDD
ADDR1
E13
Input, 4-level
None
None
Refer to Device SMBus Address for more information.
Four-level 2.5 V input used to select between SMBus master mode
(float) and SMBus slave mode (high). The four defined levels are:
0: 1 kΩ to GND - RESERVED, TI test mode.
R: 10 kΩ to GND - RESERVED, TI test mode
F: Float - SMBus Master Mode
EN_SMB
E3
Input, 4-level
1: 1 kΩ to VDD - SMBus Slave Mode
I/O, 3.3 V
LVCMOS, Open
Drain
SMBus data input and open drain output. External 2 kΩ to 5 kΩ
pull-up resistor is required as per SMBus interface standard. This
pin is 3.3 V LVCMOS tolerant.
SDA
SDC
E12
F12
None
None
I/O, 3.3 V
LVCMOS, Open
Drain
SMBus clock input and open drain clock output. External 2 kΩ to 5
kΩ pull-up resistor is required as per SMBus interface standard.
This pin is 3.3 V LVCMOS tolerant.
Copyright © 2016–2019, Texas Instruments Incorporated
5
DS280DF810
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
www.ti.com.cn
Pin Functions (continued)
PIN
INTERNAL
PULL-UP/
PULL-DOWN
TYPE
DESCRIPTION
NAME
NO.
SMBUS MASTER MODE PINS
SMBus Master Mode (EN_SMB=Float): When asserted low,
initiates the SMBus master mode EEPROM read function. Once
EEPROM read is complete (indicated by assertion of
ALL_DONE_N low), this pin can be held low for normal device
Weak pull-up operation. This pin is 3.3 V tolerant.
Input, 3.3 V
LVCMOS
READ_EN_N
ALL_DONE_N
F13
SMBus Slave Mode (EN_SMB=1): When asserted low, this causes
the device to be held in reset (I2C state machine reset and register
reset). This pin should be pulled high or left floating for normal
operation in SMBus Slave Mode. This pin is 3.3 V tolerant.
Indicates the completion of a valid EEPROM register load operation
when in SMBus Master Mode (EN_SMB=Float):
High = External EEPROM load failed or incomplete
Low = External EEPROM load successful and complete
When in SMBus slave mode (EN_SMB=1), this output reflects the
status of READ_EN_N input..
Output,
LVCMOS
D3
None
None
MISCELLANEOUS PINS
Open-drain 3.3 V tolerant active-low interrupt output. It pulls low
when an interrupt occurs. The events which trigger an interrupt are
programmable through SMBus registers. This pin can be
connected in a wired-OR fashion with other device's interrupt pin. A
single pull-up resistor in the 2 kΩ to 5 kΩ range is adequate for the
entire INT_N net.
Output,
LVCMOS,
Open-Drain
INT_N
F3
TEST0
TEST1
E2
Input, LVCMOS
Input, LVCMOS
Weak pull-up Reserved TI test pins. During normal (non-test-mode) operation,
these pins are configured as inputs and therefore they are not
affected by the presence of a signal. These pins may be left
floating, tied to GND, or connected to a 2.5-V (max) output.
E14
Weak pull-up
Reserved TI test pin. During normal (non-test-mode) operation, this
TEST4
F4
Input, LVCMOS
Weak pull-up pin is configured as an input and therefore is not affected by the
presence of a signal. This pin should be tied to GND or left floating.
TEST5
TEST6
TEST7
POWER
E4
Input, LVCMOS
Input, LVCMOS
Input, LVCMOS
Weak pull-up Reserved TI test pin. During normal (non-test-mode) operation, this
pin is configured as an input and therefore is not affected by the
presence of a signal. This pin may be left floating, tied to GND, or
D4
Weak pull-up
D12
Weak pull-up
connected to a 2.5 V (max) output.
Power supply, VDD = 2.5 V ±5%. TI recommends connecting at
least six de-coupling capacitors between the Retimer’s VDD plane
and GND as close to the Retimer as possible. For example, four
0.1 μF capacitors and two 1 μF capacitors directly beneath the
device or as close to the VDD pins as possible.
D6, D8, D10,
E5, E6, E7, E8,
E9, E10, F6,
F8, F10
VDD
Power
None
The VDD pins on this device should be connected through a low-
resistance path to the board VDD plane.
6
Copyright © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
Pin Functions (continued)
PIN
INTERNAL
PULL-UP/
PULL-DOWN
TYPE
DESCRIPTION
NAME
NO.
A1, A2, A4, A6,
A8, A10, A12,
A14, A15, B2,
B4, B6, B8,
B10, B12, B14,
C2, C3, C4, C5,
C6, C7, C8, C9,
C10, C11, C12,
C13, C14, D1,
D2, D5, D7, D9,
D11, D14, D15,
E11, F1, F2,
Ground reference. The GND pins on this device should be
connected through a low-resistance path to the board GND plane.
GND
Power
None
F5, F7, F9, F11,
F14, F15, G2,
G3, G4, G5,
G6, G7, G8,
G9, G10, G11,
G12, G13, G14,
H2, H4, H6, H8,
H10, H12, H14,
J1, J2, J4, J6,
J8, J10, J12,
J14, J15
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).
(1)
MIN
-0.5
-0.5
-0.5
-0.5
-0.5
MAX
2.75
2.75
4.0
UNIT
V
VDDABSMAX
VIO2.5V,ABSMAX
VIO3.3V,ABSMAX
VINABSMAX
VOUTABSMAX
TJABSMAX
Supply voltage (VDD)
2.5 V I/O voltage (LVCMOS, CMOS and Analog)
Open Drain Voltage (SDA, SDC, INT_N) and LVCMOS Input Voltage (READ_EN_N)
Signal input voltage (RXnP, RXnN)
Signal output voltage (TXnP, TXnN)
Junction temperature
V
V
2.75
2.75
150
V
V
ºC
ºC
Tstg
Storage temperature
-40
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2,000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1,000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2,000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1,000 V may actually have higher performance.
Copyright © 2016–2019, Texas Instruments Incorporated
7
DS280DF810
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
www.ti.com.cn
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
MAX
UNIT
V
VDD
Supply voltage, VDD to GND. DC plus AC power should not exceed these limits.
Supply noise, DC to < 50 Hz, sinusoidal(1)
Supply noise, 50 Hz to 10 MHz, sinusoidal(1)
Supply noise, >10 MHz, sinusoidal(1)
2.375
2.625
250
20
NVDD
NVDD
NVDD
TrampVDD
TJ
mVpp
mVpp
mVpp
μs
10
VDD supply ramp time, from 0 V to 2.375 V
Operating junction temperature
150
-40
110
85(2)
2.625
3.6
ºC
TA
Operating ambient temperature
-40
ºC
VIO2.5V
VIO3.3V,INT_N
VIO3.3V
2.5 V I/O voltage (LVCMOS, CMOS and Analog)
Open Drain LVCMOS I/O voltage (INT_N)
Open Drain LVCMOS I/O voltage (SDA, SDC)
2.375
V
V
2.375
3.6
V
(1) Steps must be taken to ensure the combined AC plus DC supply noise meets the specified VDD supply voltage limits.
(2) Steps must be taken to ensure the operating junction temperature range and ambient temperature stay-in-lock range (TEMPLOCK+
,
TEMPLOCK-) are met. Refer to Timing Requirements, Retimer Jitter Specifications for more details concerning TEMPLOCK+ and
TEMPLOCK-
.
7.4 Thermal Information
DS280DF810
THERMAL METRIC(1)
CONDITIONS/ASSUMPTIONS(2)
FC/CSP (ABV)
UNIT
135 PINS
26.4
9.3
4-Layer JEDEC Board
10-Layer 8-in x 6-in Board
20-Layer 8-in x 6-in Board
30-Layer 8-in x 6-in Board
4-Layer JEDEC Board
RθJA
Junction-to-ambient thermal resistance
°C/W
8.5
8.2
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
1.6
°C/W
°C/W
4-Layer JEDEC Board
9.3
4-Layer JEDEC Board
0.1
10-Layer 8-in x 6-in Board
20-Layer 8-in x 6-in Board
30-Layer 8-in x 6-in Board
4-Layer JEDEC Board
0.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
0.1
0.1
9.3
10-Layer 8-in x 6-in Board
20-Layer 8-in x 6-in Board
30-Layer 8-in x 6-in Board
5.0
ΨJB
4.9
4.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, or reduced ambient
temperature (<85 C) may be required in order to meet the maximum junction temperature specification per the Recommended
Operating Conditions.
7.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Full-rate
MIN
20.2
10.1
5.05
TYP
MAX
28.4
14.2
7.1
UNIT
Gbps
Gbps
Gbps
Rbaud
Input data rate
Half-rate
Quarter-rate
8
Copyright © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Single device reading its
configuration from an EEPROM.
Common channel configuration. This
time scales with the number of
devices reading from the same
EEPROM.
tEEPROM
tEEPROM
tPOR
EEPROM configuration load time
15(1)
ms
Single device reading its
configuration from an EEPROM.
Unique channel configuration. This
time scales with the number of
devices reading from the same
EEPROM.
EEPROM configuration load time
Power-on reset assertion time
40(1)
ms
ms
Internal power-on reset (PoR)
stretch between stable power supply
and de-assertion of internal PoR.
The SMBus address is latched on
the completion of the PoR stretch,
and SMBus accesses are permitted.
50
POWER SUPPLY
With CTLE, full DFE, Tx FIR,
Driver, and Cross-point enabled. Idle
power consumption is not included.
241
233
305
mW
mW
With CTLE, full DFE, Tx FIR, and
Driver enabled; Cross-point
disabled. Idle power consumption is
not included.
With CTLE, partial DFE (taps 1-2
only), Tx FIR, and Driver enabled;
Cross-point and DFE taps 3-5
disabled. Idle power consumption is
not included.
220
mW
With CTLE, Tx FIR, Driver, and
Cross-point enabled; DFE disabled.
Idle power consumption is not
included.
Power consumption per active
211
365
318
290
430
393
mW
mW
mW
Wchannel
channel
Assuming CDR acquiring lock with
CTLE, full DFE, Tx FIR, Driver, and
Cross-point enabled. Idle power
consumption is not included.
Assuming CDR acquiring lock with
CTLE, Tx FIR, Driver, and Cross-
point enabled; DFE disabled. Idle
power consumption is not included.
PRBS checker power consumption
only(2)
220
230
302
315
mW
mW
PRBS generator power power
consumption only(2)
Wstatic_total
Total idle power consumption
Idle or static mode, power supplied,
no high-speed data present at
inputs, all channels automatically
powered down.
658
1050
mW
(1) From low assertion of READ_EN_N to low assertion of ALL_DONE_N. Does not include Power-On Reset time.
(2) To ensure optimal performance, it is recommended to not enable more than two PRBS blocks (checker or generator) per channel quad.
Copyright © 2016–2019, Texas Instruments Incorporated
9
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www.ti.com.cn
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
With CTLE, full DFE, Tx FIR, Driver,
and Cross-point enabled.
1036
1330
mA
With CTLE, full DFE, Tx FIR, and
Driver enabled; Cross-point
disabled.
1010
mA
Active mode total device supply
current consumption
Itotal
With CTLE, partial DFE (taps 1-2
only), Tx FIR, and Driver enabled;
Cross-point and DFE taps 3-5
disabled.
970
940
263
mA
mA
mA
With CTLE, Tx FIR, Driver, and
Cross-point enabled. DFE disabled.
1278
400
Idle or static mode. Power supplied,
no high-speed data present at
inputs, all channels automatically
powered down.
Idle mode total device supply current
consumption
Istatic_total
LVCMOS DC SPECIFICATIONS
2.5 V LVCMOS pins
1.75
1.75
GND
GND
VDD
3.6
V
V
V
V
V
VIH
Input high level voltage
3.3 V LVCMOS pin (READ_EN_N)
2.5 V LVCMOS pins
0.7
VIL
Input low level voltage
3.3 V LVCMOS pin (READ_EN_N)
0.8
VTH
High level (1) input voltage
4-level pins ADDR0, ADDR1, and
EN_SMB
0.95 *
VDD
Float level input voltage
10 K to GND input voltage
Low level (0) input voltage
4-level pins ADDR0, ADDR1, and
EN_SMB
0.67 *
VDD
V
V
V
4-level pins ADDR0, ADDR1, and
EN_SMB
0.33 *
VDD
4-level pins ADDR0, ADDR1, and
EN_SMB
0.1
VOH
VOL
IIH
High level output voltage
Low level output voltage
Input high leakage current
Input high leakage current
IOH = 4 mA
2
V
V
IOL = -4 mA
0.4
70
65
Vinput = VDD, Open drain pins
Vinput = VDD and CAL_CLK_IN pin
μA
μA
IIH
Vinput = VDD, ADDR[1:0] and
EN_SMB pins
IIH
Input high leakage current
120
75
μA
IIH
IIL
IIL
Input high leakage current
Input low leakage current
Input low leakage current
Vinput = VDD, READ_EN_N
Vinput = 0 V, Open drain pins
Vinput = 0 V, CAL_CLK_IN pins
μA
μA
μA
-15
-45
Vinput = 0 V, ADDR[1:0],
READ_EN_N, and EN_SMB pins
IIL
Input low leakage current
-230
μA
RECEIVER INPUTS (RXnP, RXnN)
VIDMax
Maximum input differential voltage
For normal operation
1225
<-16
<-12
mVppd
dB
RLSDD11
RLSDD11
Differential input return loss, SDD11 Between 50 MHz and 3.69 GHz
Differential input return loss, SDD11 Between 3.69 GHz and 12.9 GHz
dB
Differential to common-mode input
Between 50 MHz and 12.9 GHz
return loss, SDC11
RLSDC11
RLSCD11
RLSCC11
RLSCC11
<-23
<-24
<-10
<-10
dB
dB
dB
dB
Differential to common-mode input
Between 50 MHz and 12.9 GHz
return loss, SCD11
Common-mode input return loss,
Between 150 MHz and 10 GHz
SCC11
Common-mode input return loss,
Between 10 GHz and 12.9 GHz
SCC11
10
Copyright © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum input peak-to-peak
amplitude level at device pins
required to assert signal detect.
25.78125 Gbps with PRBS7 pattern
and 20 dB loss channel
AC signal detect assert (ON)
threshold level
VSDAT
196
mVppd
Maximum input peak-to-peak
amplitude level at device pins which
causes signal detect to de-assert.
25.78125 Gbps with PRBS7 pattern
and 20 dB loss channel
AC signal detect de-assert (OFF)
threshold level
VSDDT
147
525
mVppd
mVppd
mVppd
TRANSMITTER OUTPUTS (TXnP, TXnN)
Measured with c(0)=7 setting
(Reg_0x3D[6:0]=0x07,
Reg_0x3E[6:0]=0x40,
REG_0x3F[6:0]=0x40). Differential
measurement using an 8T pattern
(eight 1 s followed by eight 0 s) at
25.78125 Gbps with TXPn and
TXNn terminated by 50 Ω to GND.
VOD
VOD
Output differential voltage amplitude
Measured with c(0)=31 setting
(Reg_0x3D[6:0]=0x1F,
Reg_0x3E[6:0]=0x40,
REG_0x3F[6:0]=0x40). Differential
measurement using an 8T pattern
(eight 1 s followed by eight 0 s) at
25.78125 Gbps with TXPn and
TXNn terminated by 50 Ω to GND.
Output differential voltage amplitude
1225
Differential output amplitude with TX
disabled
VODidle
VODres
< 11
< 50
mVppd
mVppd
Difference in VOD between two
adjacent c(0) settings. Applies to
VOD in the 525 mVppd to 1225
mVppd range [c(0)>4].
Output VOD resolution
With respect to signal ground.
Measured with PRBS9 data pattern.
Measured with a 33 GHz (-3 dB)
low-pass filter.
Vcm-TX-AC
Common-mode AC output noise
6.5
17
mV, RMS
20%-to-80% rise time and 80%-to-
20% fall time on a clock-like {11111
00000} data pattern at 25.78125
Gbps. Measured for ~800 mVppd
output amplitude and no
tr, tf
Output transition time
ps
equalization: Reg_0x3D=+13,
Reg_0x3E=0, REG_0x3F=0
Differential output return loss,
SDD22
RLSDD22
RLSDD22
RLSCD22
RLSDC22
RLSCC22
RLSCC22
Between 50 MHz and 5 GHz
Between 5 GHz and 12.9 GHz
Between 50 MHz and 12.9 GHz
Between 50 MHz and 12.9 GHz
Between 50 MHz and 10 GHz
Between 10 GHz and 12.9 GHz
<-12
<-9
dB
dB
dB
dB
dB
dB
Differential output return loss,
SDD22
Common-mode to differential output
return loss, SCD22
<-22
<-22
<-9
Differential-to-common-mode output
return loss, SDC22
Common-mode output return loss,
SCC22
Common-mode output return loss,
SCC22
<-9
SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)
VIH
VIL
Input high level voltage
Input low level voltage
SDA and SDC
SDA and SDC
1.75
3.6
0.8
V
V
GND
Copyright © 2016–2019, Texas Instruments Incorporated
11
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www.ti.com.cn
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
pF
CIN
Input pin capacitance
Low level output voltage
15
VOL
SDA or SDC, IOL = 1.25 mA
0.4
15
V
SDA or SDC, VINPUT = VIN, VDD,
GND
IIN
Input current
-15
μA
TR
TF
SDA rise time, read operation
SDA fall time, read operation
Pull-up resistor = 1 kΩ, Cb = 50 pF
Pull-up resistor = 1 kΩ, Cb = 50 pF
150
4.5
ns
ns
7.6 Timing Requirements, Retimer Jitter Specifications
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured at 28.4 Gbps to a
probability level of 1E-15 with
PRBS9 data pattern an evaluation
board traces de-embedded.
UIpp @
1E-12
JTJ
Output Total jitter (TJ)
0.24
Measured at 28.4 Gbps to a
probability level of 1E-15 with
PRBS9 data pattern an evaluation
board traces de-embedded
JRJ
Output Random Jitter (RJ)
Output Duty Cycle Distortion (DCD)
Output Total jitter (TJ)
8
15
0.17
6
mUI RMS
mUIpp
Measured at 28.4 Gbps to a
probability level of 1E-15 with
PRBS9 data pattern an evaluation
board traces de-embedded
JDCD
Measured at 25.78125 Gbps to a
probability level of 1E-12 with
PRBS11 data pattern an evaluation
board traces de-embedded.
UIpp @
1E-12
JTJ
Measured at 25.78125 Gbps to a
probability level of 1E-12 with
PRBS11 data pattern an evaluation
board traces de-embedded
JRJ
Output Random Jitter (RJ)
Output Duty Cycle Distortion (DCD)
Jitter peaking
mUI RMS
mUIpp
dB
Measured at 25.78125 Gbps to a
probability level of 1E-12 with
PRBS11 data pattern an evaluation
board traces de-embedded
JDCD
4
Measured at 10.3125 Gbps with
PRBS7 data pattern. Peaking
frequency in the range of 1 to 6
MHz.
JPEAK
0.8
Measured at 25.78125 Gbps with
PRBS7 data pattern. Peaking
frequency in the range of 1 to 17
MHz.
JPEAK
Jitter peaking
Jitter peaking
0.4
0.4
dB
dB
Measured at 28.4 Gbps with PRBS7
data pattern. Peaking frequency in
the range of 1 to 17 MHz.
JPEAK
Data rate of 10.3125 Gbps with
PRBS7 pattern
BWPLL
BWPLL
BWPLL
PLL bandwidth
PLL bandwidth
PLL bandwidth
5
5.5
5
MHz
MHz
MHz
Data rate of 25.78125 Gbps with
PRBS7 pattern
Data rate of 28.4 Gbps with PRBS7
pattern
12
Copyright © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
Timing Requirements, Retimer Jitter Specifications (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured at 28.4 Gbps with SJ
frequency > 10 MHz, 29 dB input
channel loss, PRBS31 data pattern,
800 mVppd launch amplitude, and
0.078 UIpp total uncorrelated output
jitter in addition to the applied SJ.
BER < 1E-12.
JTOL
JTOL
JTOL
JTOL
Input jitter tolerance
0.32
UIpp
Measured at 25.78125 Gbps with
SJ frequency = 190 KHz, 30 dB
input channel loss, PRBS31 data
pattern, 800 mVppd launch
amplitude, and 0.078 UIpp total
uncorrelated output jitter in addition
to the applied SJ. BER < 1E-12.
Input jitter tolerance
Input jitter tolerance
Input jitter tolerance
9
1
UIpp
UIpp
UIpp
Measured at 25.78125 Gbps with
SJ frequency = 940 KHz, 30 dB
input channel loss, PRBS31 data
pattern, 800 mVppd launch
amplitude, and 0.078 UIpp total
uncorrelated output jitter in addition
to the applied SJ. BER < 1E-12.
Measured at 25.78125 Gbps with
SJ frequency > 10 MHz, 32 dB input
channel loss, PRBS31 data pattern,
800 mVppd launch amplitude, and
0.078 UIpp total uncorrelated output
jitter in addition to the applied SJ.
BER < 1E-12.
0.38
CDR stay-in-lock ambient
temperature range, negative ramp.
85 °C starting ambient temperature,
ramp rate -3 °C/minute, 1.7
liters/sec airflow, 12 layer PCB.
TEMPLOCK- Maximum temperature change
below initial CDR lock acquisition
temperature.
115
125
°C
°C
CDR stay-in-lock ambient
temperature range, positive ramp.
TEMPLOCK+ Maximum temperature change
above initial CDR lock acquisition
temperature.
-40 °C starting ambient
temperature, ramp rate +3
°C/minute, 1.7 liters/sec airflow, 12
layer PCB.
7.7 Timing Requirements, Retimer Specifications
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
Input-to-output latency (propagation No cross-point; CDR enabled and
delay) through a channel locked.
Input-to-output latency (propagation Cross-point enabled; CDR enabled
delay) through a channel and locked.
Input-to-output latency (propagation No cross-point; CDR in raw mode.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.5UI +
125ps
tD
tD
tD
ps
3.5UI +
145ps
ps
ps
< 145
delay) through a channel
25.78125 Gbps data rate.
Latency difference between
channels at full-rate. 25.78125 Gbps
data rate
tSK
Channel-to-channel inter-pair skew
< 30
ps
Measured at 25.78125 Gbps, Adapt
Mode = 1 (Reg_0x31[6:5]=0x1),
EOM timer = 0x5
tlock
CDR lock acquisition time
CDR lock acquisition time
< 100
< 100
ms
(Reg_0x2A[7:4]=0x5).
Measured at 10.3125 Gbps, Adapt
Mode = 1 (Reg_0x31[6:5]=0x1),
EOM timer = 0x5
tlock
ms
(Reg_0x2A[7:4]=0x5).
Copyright © 2016–2019, Texas Instruments Incorporated
13
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www.ti.com.cn
7.8 Timing Requirements, Recommended Calibration Clock Specifications
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
PPM
CLKf
Calibration clock frequency
Calibration clock PPM tolerance
25
CLKPPM
-100
40%
100
Recommended/tolerable input duty
cycle
CLKIDC
50%
60%
Intrinsic duty cycle distortion of chip
calibration clock output at the
CAL_CLK_OUT pin, assuming 50%
duty cycle on CAL_CLK_IN pin.
Intrinsic calibration clock duty cycle
distortion
CLKODC
45%
55%
Assumes worst-case 60% and 40%
input duty cycle on the first device.
CAL_CLK_OUT from first device
connects to CAL_CLK_IN of second
device, and so on until the last
device.
Number of devices which can be
cascaded from CAL_CLK_OUT to
CAL_CLK_IN
CLKnum
20
N/A
7.9 Recommended SMBus Switching Characteristics (Slave Mode)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
SDC clock frequency
Data hold time
TEST CONDITIONS
MIN
TYP
100
0.75
100
MAX
UNIT
kHz
ns
fSDC
10
400
tHD-DAT
tSU-DAT
Data setup time
ns
7.10 Recommended SMBus Switching Characteristics (Master Mode)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
SDC clock frequency
SDC low period
TEST CONDITIONS
MIN
260
TYP
303
1.90
1.40
0.6
MAX
346
UNIT
kHz
μs
fSDC
TLOW
1.66
1.22
2.21
1.63
THIGH
THD-STA
TSU-STA
THD-DAT
TSD-DAT
TSU-STO
TBUF
SDC high period
μs
Hold time start operation
Setup time start operation
Data hold time
μs
0.6
μs
0.6
μs
Data setup time
0.1
μs
Stop condition setup time
Bus free time between Stop-Start
SDC rise time
0.6
μs
1.3
μs
TR
Pull-up resistor = 1 kΩ
Pull-up resistor = 1 kΩ
300
300
ns
TF
SDC fall time
ns
14
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DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
7.11 Typical Characteristics
1.6
1.6
1.4
1.2
1
c(0)=7
c(0)=7
c(0)=16
c(0)=16
c(0)=31
1.4
c(0)=31
1.2
1
0.8
0.6
0.4
0.8
0.6
0.4
2.325
2.395
2.465
2.535
2.605
2.675
-40
-15
10
35
60
85
VDD Supply Voltage (V)
Ambient Temperature (°C)
C001
C002
图 1. Typical VOD versus Supply Voltage
图 2. Typical VOD versus Temperature
0.25
0.2
0.15
0.1
0.05
0
0.25
0.2
0.15
0.1
0.05
0
TJ, VDD = 2.35 V
TJ, VDD = 2.65 V
DJ, VDD = 2.35 V
DJ, VDD = 2.65 V
TJ, VDD = 2.35 V
TJ, VDD = 2.65 V
DJ, VDD = 2.35 V
DJ, VDD = 2.65 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature (°C)
Temperature (°C)
C001
C001
图 3. Typical VOD versus FIR Main-Cursor
图 4. Typical Output Jitter versus Temperature at 25.78125
Gbps
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15
DS280DF810
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www.ti.com.cn
8 Detailed Description
8.1 Overview
The DS280DF810 is an eight-channel multi-rate retimer with integrated signal conditioning. Each of the eight
channels operates independently. Each channel includes a continuous-time linear equalizer (CTLE) and a
Decision Feedback Equalizer (DFE), which together compensate for the presence of a dispersive transmission
channel between the source transmitter and the DS280DF810 receiver. The CTLE and DFE are self-adaptive.
Each channel includes an independent voltage-controlled oscillator (VCO) and phase-locked loop (PLL) which
produce a clean clock that is frequency-locked to the clock embedded in the input data stream. The high-
frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially-reduced
jitter. This clean clock is used to re-time the incoming data, removing high-frequency jitter from the data stream
and reproducing the data on the output with significantly-reduced jitter.
Each channel of the DS280DF810 features an output driver with adjustable differential output voltage and output
equalization in the form of a three-tap finite impulse response (FIR) filter. The output FIR compensates for
dispersion in the transmission channel at the output of the DS280DF810.
All transmit and receive channels on the DS280DF810 are AC-coupled with physical AC-coupling capacitors (220
nF +/- 20%) on the package substrate. This ensures common mode voltage compatibility with all link partners
and eliminates the need for AC coupling capacitors on the system PCB, thereby saving cost and greatly reducing
PCB routing complexity.
Between each group of two adjacent channels (e.g. between channels 0–1, 2–3, 4–5, and 6–7) is a full 2x2
cross-point switch. This allows multiplexing and de-multiplexing and fanout applications for fail-over redundancy,
as well as cross-over applications to aid PCB routing.
Each channel also includes diagnostic features such as a Pseudo Random Bit Sequence (PRBS) pattern
generator and checker, as well as a non-destructive eye opening monitor (EOM). The EOM can be used to plot
the post-equalized eye at the input to the decision slicer or simply to read the horizontal eye opening (HEO) and
vertical eye opening (VEO).
The DS280DF810 is configurable through a single SMBus port. The DS280DF810 can also act as an SMBus
master to configure itself from an EEPROM. Up to sixteen DS280DF810 devices can share a single SMBus.
The sections which follow describe the functionality of various circuits and features within the DS280DF810. For
more information about how to program or operate these features, consult the DS280DF810 Programming
Guide.
16
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DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
8.2 Functional Block Diagram
One of Eight Channels
To adjacent
channel
DFE
Term
Raw
RXnP
RXnN
TXnP
Retimed
Sampler
TX FIR
Driver
X-point
CTLE+VGA
220 nF
220 nF
+
TXnN
PRBS
PRBS
Gen
Voltage
Regulator
Signal
Detect
PRBS
Gen
PRBS
Checker
Voltage
Regulator
PFD, CDR,
And Divider
VCO
Channel Digital Core
Buffer
CAL
CAL_CLK_IN
ADDRn
SCL
Power-On
Reset
Shared Digital Core
Always-On 10 MHz
SDA
READ_EN_N
EN_SMB
ALL_
INT_
Shared Digital Core
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8.3 Feature Description
8.3.1 Device Data Path Operation
The DS280DF810 data path consists of several key blocks as shown in the functional block diagram. These key
circuits are:
•
•
•
•
•
•
•
•
•
•
AC-Coupled Receiver and Transmitter
Signal Detect
Continuous Time Linear Equalizer (CTLE)
Variable Gain Amplifier (VGA)
2x2 Cross-point Switch
Decision Feedback Equalizer (DFE)
Clock and Data Recovery (CDR)
Calibration Clock
Differential Driver with FIR Filter
Differential Driver with FIR Filter
8.3.1.1 AC-Coupled Receiver and Transmitter
The differential receiver for each DS280DF810 channel contains on-package AC coupling capacitors. The
differential transmitter for each DS280DF810 channel also implement on-package AC coupling capacitors. The
AC coupling capacitors have a value of 220nF +/- 20%.
8.3.1.2 Signal Detect
The DS280DF810 receiver contains a signal detect circuit. The signal detect circuit monitors the energy level on
the receiver inputs and powers on or off the rest of the high-speed data path if a signal is detected or not. By
default, each channel allows the signal detect circuit to automatically power on or off the rest of the high speed
data path depending on the presence of an input signal. The signal detect block can be manually controlled in
the SMBus channel registers. This can be useful if it is desired to manually force channels to be disabled. For
information on how to manually operate the signal detect circuit refer to the DS280DF810 Programming Guide.
8.3.1.3 Continuous Time Linear Equalizer (CTLE)
The CTLE in the DS280DF810 is a fully-adaptive equalizer. The CTLE adapts according to a Figure of Merit
(FOM) calculation during the lock acquisition process. The FOM calculation is based upon the horizontal eye
opening (HEO) and vertical eye opening (VEO). Once the CDR locks and the CTLE adapts, the CTLE boost
level is frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state.
The CTLE can be re-adapted by resetting the CDR.
The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different boost
combinations. The CTLE adaption algorithm allows the CTLE to adapt through 16 of these boost combinations.
These 16 boost combinations comprise the EQ Table in the channel registers. See channel registers 0x40
through 0x4F. This EQ Table can be reprogrammed to support up to 16 of the 256 boost settings.
The boost levels can be set between 8 dB and 25 dB (at 14 GHz).
8.3.1.4 Variable Gain Amplifier (VGA)
The DS280DF810 receiver implements a VGA. The VGA assists in the recovery of extremely small signals,
working in conjunction with the CTLE to equalize and scale amplitude. The VGA has 1-bit control via Register
0x8E[0], and the VGA is enabled by default. In addition to the VGA, the CTLE implements its own gain control
via register 0x13[5] to adjust the DC amplitude similar to the VGA. For more information on how to configure the
VGA refer to the DS280DF810 Programming Guide.
8.3.1.5 2x2 Cross-point Switch
Between each group of two adjacent channels (i.e between channels 0–1, 2–3, 4–5, and 6–7) is a full 2×2 cross-
point switch. The cross-point can be configured through SMBus registers to operate as follows:
•
•
Straigh-thru mode
Multiplex two inputs to one output
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Feature Description (接下页)
•
•
Fanout one input to two outputs
Cross two inputs to two outputs
图 5 shows the four 2x2 cross-points available in the DS280DF810, and 图 6 shows how each cross-point can be
configured for straight-thru, multiplex, de-multiplex, or cross-over applications. Refer to the DS280DF810
Programming Guide for details on how to program the cross-point through SMBus registers.
RX0P
RX0N
TX0P
TX0N
CDR
X
X
X
X
RX1P
RX1N
TX1P
TX1N
CDR
CDR
RX2P
RX2N
TX2P
TX2N
RX3P
RX3N
TX3P
TX3N
CDR
CDR
RX4P
RX4N
TX4P
TX4N
RX5P
RX5N
TX5P
TX5N
CDR
CDR
RX6P
RX6N
TX6P
TX6N
RX7P
RX7N
TX7P
TX7N
CDR
图 5. Block diagram showing all four 2x2 cross-points in the DS280DF810
Straight Thru
Mux / Fanout
RXAP
RXAN
TXAP
TXAN
RXAP
RXAN
TXAP
TXAN
CDR
CDR
RXBP
RXBN
TXBP
TXBN
RXBP
RXBN
TXBP
TXBN
CDR
CDR
Cross-over
Mux / Fanout
RXAP
RXAN
TXAP
TXAN
RXAP
RXAN
TXAP
TXAN
CDR
CDR
RXBP
RXBN
TXBP
TXBN
RXBP
RXBN
TXBP
TXBN
CDR
CDR
图 6. Signal distribution options available in each 2x2 cross-point
(channel A can be 0, 2, 4, or 6; channel B can be 1, 3, 5, or 7)
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Feature Description (接下页)
8.3.1.6 Decision Feedback Equalizer (DFE)
A 5-tap DFE can be enabled within the data path of each channel to assist with reducing the effects of cross talk,
reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the
selected adapt mode. Once the DFE has been enabled it can be configured to adapt only during lock acquisition
or to adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights.
However, when the DFE is configured manually the DFE auto-adaption should be disabled. For many
applications with lower insertion loss (i.e. < 30 dB) lower crosstalk, or lower reflections, part or all of the DFE can
be disabled to reduce power consumption. The DFE can either be fully enabled (taps 1-5), partially enabled (taps
1-2 only), or fully disabled (no taps).
The DFE taps are all feedback taps with 1 UI spacing. Each tap has a specified boost weight range and polarity
bit.
表 1. DFE Tap Weights
DFE PARAMETER
Tap 1 Weight Range
Tap 2-5 Weight Range
Tap Weight Step Size
DECIMAL (REGISTER VALUE)
VALUE (mV) (TYP)
0 - 31
0 - 15
NA
0 – 217
0 – 105
7
0: (+) positive; feedback value creates a low-pass filter response, thus providing attenuation to
correct for negative-sign post-cursor ISI
Polarity
1: (-) negative; Feedback value creates a high-pass filter response, thus providing boost to correct
for positive-sign post-cursor ISI.
8.3.1.7 Clock and Data Recovery (CDR)
The CDR consists of a Phase Locked Loop (PLL), PPM counter, and Input and Output Data Multiplexers (mux)
allowing for retimed data, un-retimed data, PRBS generator and output muted modes.
By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output
to the FIR filter and differential driver together with the recovered clock which has been cleaned of any high-
frequency jitter outside the bandwidth of the CDR clock recovery loop. The bandwidth of the CDR defaults to 5.5
MHz (typical) in full-rate (divide-by-1) mode and 5.3 MHz (typical) in sub-rate mode. The CDR bandwidth is
adjustable. Refer to the DS280DF810 Programming Guide for more information on adjusting the CDR bandwidth.
Users can configure the CDR data to route the recovered clock and data to the PRBS checker. Users also have
the option of configuring the output of the CDR to send raw non-retimed data, or data from the pattern generator.
The CDR requires the following in order to be properly configured:
•
•
25 MHz calibration clock to run the PPM counter (CAL_CLK_IN).
Expected data rates must be programmed into the CDR either through the rate table or entered manually with
the corrected divider settings. Refer to the Programming Guide for more information on configuring the CDR
for different data rates.
8.3.1.8 Calibration Clock
The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The
calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable
lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates.
The host should provide an input calibration clock signal of 25 MHz frequency. Because this clock is not used for
clock and data recovery, there are no stringent jitter requirements placed on this 25 MHz calibration clock.
8.3.1.9 Differential Driver with FIR Filter
The DS280DF810 output driver has a three-tap finite impulse response (FIR) filter which allows for pre- and post-
cursor equalization to compensate for a wide variety of output channel media. The filter consists of a weighted
sum of three consecutive retimed bits as shown in the following diagram. C[0] can take on values in the range [-
31, +31]. C[-1] and C[+1] can take on values in the range [-15, 15].
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Retimed
Data
FIR filter
output
x
+
1 UI
Delay
C[-1]
Pre-cursor
x
+
1 UI
Delay
C[0]
Main-curosr
x
C[+1]
Post-cursor
图 7. FIR filter functional model
When utilizing the FIR filter, it is important to abide by the following general rules:
•
•
|C[-1]| + |C[0]| + |C[+1]| ≤ 31; the FIR tap coefficients absolute sum must be less or equal to 31).
sgn(C[-1]) = sgn(C[+1]) ≠ sgn(C[0]), for high-pass filter effect; the sign for the pre-cursor or post-cursor tap
must be different from main-cursor tap to realize boost effect.
•
sgn(C[-1]) = sgn(C[+1]) = sgn(C[0]), for low-pass filter effect; the sign for the pre-cursor or post-cursor tap
must be equal to the main-cursor tap to realize attenuation effect.
The FIR filter is used to pre-distort the transmitted waveform in order to compensate for frequency-dependant
loss in the output channel. The most common way of pre-distorting the signal is to accentuate the transitions and
de-emphasize the non-transitions. The bit before a transition is accentuated via the pre-cursor tap, and the bit
after the transition is accentuated via the post-cursor tap. The figures below give a conceptual illustration of how
the FIR filter affects the output waveform. The following characteristics can be derived from the example
waveforms.
•
•
•
•
VODpk-pk=v7 - v8
VODlow-frequency = v2 - v5
RpredB = 20 * log10 (v3 ⁄v2 )
RpstdB = 20 * log10 (v1 ⁄v2 )
Transmitted
Bits: 0
0
1
1
1
1
0
0
0
0
1
0
1
Differential
Voltage
v7
v1
v3
v2
0 V
Time [UI]
v5
v6
v4
v8
图 8. Conceptual FIR Waveform With Post-Cursor Only
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Transmitted
Bits: 0
0
1
1
1
1
0
0
0
0
1
0
1
Differential
Voltage
v3
v7
v1
v2
0 V
Time [UI]
v4
v5
v6
v8
图 9. Conceptual FIR Waveform With Pre-Cursor Only
Transmitted
Bits: 0
0
1
1
1
1
0
0
0
0
1
0
1
Differential
Voltage
v7
v1
v3
v2
0 V
Time [UI]
v5
v6
v4
v8
图 10. Conceptual FIR Waveform With Both Pre-Cursor and Post-Cursor
8.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
The output differential voltage (VOD) of the driver is controlled by manipulating the FIR tap settings. The main
cursor tap is the primary knob for amplitude adjustment. The pre and post cursor FIR tap settings can then be
adjusted to provide equalization. To maintain a constant peak-to-peak VOD, the user should adjust the main
cursor tap value relative to the pre tap or post tap changes so as to maintain a constant absolute sum of the FIR
tap values. The table below shows various settings for VOD settings ranging from 205 mVpp to 1225 mVpp
(typical). Note that the output peak-to-peak amplitude is a function of the sum of the absolute values of the taps,
whereas the low-frequency amplitude is purely a function of the main-cursor value.
表 2. Typical VOD and FIR Values
FIR SETTINGS
PEAK-TO PEAK
RPRE(dB)
RPST(dB)
PRE-CURSOR:
REG_0x3E[6:0]
MAIN-CURSOR:
REG_0x3D[6:0]
POST-CURSOR:
REG_0x3F[6:0]
VOD(V)
0
0
0
0
0
0
0
0
0
0.205
0.260
0.305
0.355
NA
NA
NA
NA
NA
NA
NA
NA
+1
+2
+3
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表 2. Typical VOD and FIR Values (接下页)
FIR SETTINGS
PEAK-TO PEAK
VOD(V)
RPRE(dB)
RPST(dB)
PRE-CURSOR:
MAIN-CURSOR:
REG_0x3D[6:0]
POST-CURSOR:
REG_0x3F[6:0]
REG_0x3E[6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
-2
-3
-4
0
0
0
0
0
+4
+5
0
0
0.395
0.440
0.490
0.525
0.565
0.610
0.650
0.685
0.720
0.760
0.790
0.825
0.860
0.890
0.925
0.960
0.985
1.010
1.040
1.075
1.095
1.125
1.150
1.165
1.190
1.205
1.220
1.225
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
1.165
1.165
1.165
1.165
1.165
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
1.0
1.6
2.4
3.3
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
2.1
2.5
3.1
3.8
4.7
5.8
7.2
9.0
11.6
NA
NA
NA
NA
1.1
1.3
1.8
2.2
2.7
+6
0
+7
0
+8
0
+9
0
+10
+11
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+18
+17
+16
+15
+14
+13
+12
+11
+10
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
17
0
16
0
15
0
26
-1
-2
-3
-4
-5
25
24
23
22
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RPST(dB)
表 2. Typical VOD and FIR Values (接下页)
FIR SETTINGS
PEAK-TO PEAK
VOD(V)
RPRE(dB)
PRE-CURSOR:
REG_0x3E[6:0]
MAIN-CURSOR:
REG_0x3D[6:0]
POST-CURSOR:
REG_0x3F[6:0]
0
0
21
20
19
18
17
16
15
26
25
24
23
22
21
20
-6
-7
-8
-9
-10
-11
-12
0
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
NA
NA
NA
NA
NA
NA
NA
0.7
1.2
1.5
2.0
2.6
3.2
4.0
3.3
3.9
4.7
5.7
6.9
8.4
10.1
NA
NA
NA
NA
NA
NA
NA
0
0
0
0
0
-1
-2
-3
-4
-5
-6
-7
0
0
0
0
0
0
The recommended pre-cursor and post-cursor settings for a given channel will depend on the channel
characteristics (mainly insertion loss) as well as the equalization capabilities of the downstream receiver. The
DS280DF810 receiver, with its highly-capable CTLE and DFE, does not require a significant amount of pre-
cursor or post-cursor. The figures below give general recommendations for pre- and post-cursor for different
channel loss conditions. The insertion loss (IL) in these plots refers to the total loss between the link partner
transmitter and the DS280DF810 receiver.
图 11. Guideline for Link partner FIR Settings When IL ≤ 15 dB
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图 12. Guideline for Link partner FIR Settings When IL ≤ 25 dB
图 13. Guideline for Link partner FIR Settings When IL ≤ 35 dB
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8.3.1.9.2 Output Driver Polarity Inversion
In some applications, it may be necessary to invert the polarity of the data transmitted from the retimer. To invert
the polarity of the data, read back the FIR polarity settings for the pre-cursor, main-cursor, and post-cursor taps
and then invert all of these polarities. Refer to the DS280DF810 Programming Guide for more details.
8.3.2 Debug Features
The DS280DF810 has multiple features to aid diagnostics, board manufacturing, and system debug. These key
features are:
•
•
•
•
Pattern Generator
Pattern Checker
Eye Opening Monitor
Interrupt Signals
8.3.2.1 Pattern Generator
Each channel in the DS280DF810 can be configured to generate a 16-bit user-defined data pattern or a pseudo
random bit sequence (PRBS). The user defined pattern can also be set to automatically invert every other 16-bit
symbol for DC balancing purposes. The DS280DF810 pattern generator supports the following PRBS
sequences:
•
•
•
•
•
•
•
•
PRBS – 27 - 1
PRBS – 29 - 1
PRBS – 211 - 1
PRBS – 215 - 1
PRBS – 223 - 1
PRBS – 231 - 1
PRBS – 258 - 1
PRBS – 263 - 1
8.3.2.2 Pattern Checker
The pattern checker can be manually set to look for specific PRBS sequences and polarities or it can be set to
automatically detect the incoming pattern and polarity. The PRBS checker supports the same set of PRBS
patterns as the PRBS generator.
The pattern checker consists of an 11-bit error counter. The pattern checker uses 32- bit words, but every bit in
the word is checked for error, so the error count represents the count of single bit errors.
In order to read out the bit and error counters, the pattern checker must first be frozen. Continuous operation with
simultaneous read out of the bit and error counters is not supported in this implementation. Once the bit and
error counter is read, they can be un-frozen to continue counting.
8.3.2.3 Eye Opening Monitor
The DS280DF810’s Eye Opening Monitor (EOM) measures the internal data eye at the input of the decision
slicer and can be used for 2 functions:
1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement
2. Full Eye Diagram Capture
The HEO measurement is made at the 0 V crossing and is read in channel register 0x27. The VEO
measurement is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can
be read from channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are
used to convert the contents of channel registers 0x27 and 0x28 into their appropriate units:
•
•
HEO [UI] = Reg_0x27 ÷ 32
VEO [mV] = Reg_0x28 x 3.125
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A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a
64 x 64 array, where each cell in the matrix consists of an 16-bit word representing the total number of hits
recorded at that particular phase and voltage offset. Users can manually adjust the vertical scaling of the EOM or
allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the
state machine and is always directly proportional to the data rate.
When a full eye diagram plot is captured, the retimer will shift out four 16-bit words of junk data that should be
discarded followed by 4096 16-bit words that make up the 64 × 64 eye plot. The first actual word of the eye plot
from the retimer is for (X, Y) position (0,0), which is the earliest position in time and the most negative position in
voltage. Each time the eye plot data is read out the voltage position is incremented. Once the voltage position
has incremented to position 63 (the most positive voltage), the next read will cause the voltage position to reset
to 0 (the most negative voltage) and the phase position to increment. This process will continue until the entire
64 × 64 matrix is read out. 图 14 below shows the EOM read out sequence overlaid on top of a simple eye
opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO
and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output
data.
63
127
4095
63
0
64
4032
63
图 14. EOM Full Eye Capture Readout
To manually control the EOM vertical range, remove scaling control from the state machine then select the
desired range:
Channel Reg 0x2C[6] → 0 (see 表 3).
表 3. Eye Opening Monitor Vertical Range Settings
CH REG 0x11[7:6] VALUE
EOM VERTICAL RANGE [mV]
2’b00
2'b01
2'b10
2'b11
±100
±200
±300
±400
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The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over
equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit
error rate.
The EOM can be accessed in two ways to read out the entire eye plot:
•
•
Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this
mode, the device must be addressed each time a new byte is read.
To perform a full eye capture with the EOM, follow these steps below within the desired channel register set:
表 4. Eye Opening Monitor Full Eye Capture Instructions
STEP
REGISTER [bits]
0x67[5]
OPERATION
Write
VALUE
DESCRIPTION
Disable lock EOM lock monitoring
1
0
0
0x2C[6]
Write
Set the desired EOM vertical range
2
0x11[7:6]
0x11[5]
Write
2'b--
0
3
4
Write
Power on the EOM
Enable fast EOM
0x24[7]
Write
1
Begin read out of the 64 x 64 array, discard first 4 words
Ch reg 0x24[0] is self-clearing.
0x24[0]
0x25
0x26
5
6
Read
1
0x25 is the MSB of the 16-bit word
0x26 is the LSB of the 16-bit word
0x25
0x26
Continue reading information until the 64 x 64 array is
complete.
Read
0x67[5]
0x2C[6]
0x11[5]
0x24[7]
Write
Write
Write
Write
1
1
1
0
Return the EOM to its original state. Undo steps 1-4
7
8.3.2.4 Interrupt Signals
The DS280DF810 can be configured to report different events as interrupt signals. These interrupt signals do not
impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits in
the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that
interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once
the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The
DS280DF810 will report the occurrence of an interrupt through the INT_N pin. The INT_N pin is an open drain
output that will pull the line low when an interrupt signal is triggered.
Note that all available interrupts are disabled by default. Users must activate the various interrupts before they
can be used.
The interrupts available in the DS280DF810 are:
•
•
•
•
•
•
CDR loss of lock
CDR locked
Signal detect loss
Signal detected
PRBS pattern checker bit error detected
HEO/VEO threshold violation
When an interrupt occurs, share register 0x08 reports which channel generated the interrupt request. Users can
then select the channels that generated the interrupt request and service the interrupt by reading the appropriate
interrupt status bits in the corresponding channel registers. For more information on reading interrupt status, refer
to the DS280DF810 Programming Guide.
28
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8.4 Device Functional Modes
8.4.1 Supported Data Rates
The DS280DF810 supports a wide range of input data rates, including divide-by-2 and divide-by-4 sub-rates. The
supported data rates are listed in 表 5. Refer to the DS280DF810 Programming Guide for information on
configuring the DS280DF810 for different data rates.
表 5. Supported Data Rates
DATA RATE RANGE
DIVIDER
CDR MODE
COMMENT
MIN
MAX
≥ 20.2 Gbps
≥ 10.1 Gbps
> 7.1 Gbps
≤ 28.4 Gbps
≤ 14.2 Gbps
< 10.1 Gbps
1
2
Enabled
Enabled
Disabled
N/A
Output jitter will be higher
with CDR disabled.
≥ 5.05 Gbps
≥ 1.25 Gbps
≤ 7.1 Gbps
4
Enabled
Disabled
< 5.05 Gbps
N/A
Output jitter will be higher
with CDR disabled.
8.4.2 SMBus Master Mode
SMBus master mode allows the DS280DF810 to program itself by reading directly from an external EEPROM.
When using the SMBus master mode, the DS280DF810 will read directly from specific location in the external
EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific
guidelines:
•
•
Maximum EEPROM size is 2048 Bytes
Minimum EEPROM size for a single DS280DF810 with individual channel configuration is 595 Bytes (3 base
header bytes + 12 address map bytes + 8 x 72 channel register bytes + 2x2 share register bytes; bytes are
defined to be 8-bits)
•
•
•
•
Set ENSMB = Float, for SMBus master mode
The external EEPROM device address byte must be 0xA0
The external EEPROM device must support 400 kHz operation at 2.5 V or 3.3 V supply
Set the SMBus address of the DS280DF810 by configuring the ADDR0 and ADDR1 pins
When loading multiple DS280DF810 devices from the same EEPROM, use these guidelines to configure the
devices:
•
•
•
Configure the SMBus addresses for each DS280DF810 to be sequential. The first device in the sequence
must have an address of 0x30
Daisy chain READ_EN_N and ALL_DONE_N from one device to the next device in the sequence so that they
do not compete for the EEPROM at the same time.
If all of the DS280DF810 devices share the same EEPROM channel and share register settings, configure
the common channel bit in the base header to 1. With common channel configuration enabled, each
DS280DF810 device will configure all 8 channels with the same settings.
When loading a single DS280DF810 from an EEPROM, use these guidelines to configure the device:
•
Set the common channel bit to 0 to allow for individual channel configuration, or set the common channel bit
to 1 to load the same configuration settings to all channels.
•
•
When configuring individual channels, a 1024 Byte or 2048 Byte EEPROM must be used.
If there are more than three DS280DF810 devices on a PCB that require individual channel configuration,
then each device must have its own EEPROM.
8.4.3 Device SMBus Address
The DS280DF810’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is
read on power up, after the internal power-on reset signal is de-asserted. The ADDR[1:0] pins are four-level
LVCMOS IOs, which provides for 16 unique SMBus addresses. The four levels are achieved by pin strap options
as follows:
•
0: 1 kΩ to GND
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•
•
•
R: 10 kΩ to GND
F: Float
1: 1 kΩ to VDD
表 6. SMBus Address Map
REQUIRED ADDRESS PIN STRAP VALUE
8-BIT WRITE ADDRESS [HEX]
ADDR1
ADDR0
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
0
0
0
R
F
1
0
0
R
R
R
R
F
F
F
F
1
0
R
F
1
0
R
F
1
0
1
R
F
1
1
1
8.5 Programming
8.5.1 Bit Fields in the Register Set
Many of the registers in the DS280DF810 are divided into bit fields. This allows a single register to serve multiple
purposes which may be unrelated. Often, configuring the DS280DF810 requires writing a bit field that makes up
only part of a register value while leaving the remainder of the register value unchanged. The procedure for
accomplishing this task is to read in the current value of the register to be written, modify only the desired bits in
this value, and write the modified value back to the register. Of course, if the entire register is to be changed,
rather than just a bit field within the register, it is not necessary to read in the current value of the register first. In
all register configuration procedures described in the following sections, this procedure should be kept in mind. In
some cases, the entire register is to be modified. When only a part of the register is to be changed, however, the
procedure described above should be used.
Each bit or field within a register has one of the following access properties:
•
•
•
R: Read-only
RW: Read or Write
RWSC: Read or Write, self-clearing
8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
The DS280DF810 has 3 types of registers:
1) Global Registers – These registers can be accessed at any time and are used to select individual channel
registers, the shared registers or to read back the TI ID and version information.
2) Shared Registers – These registers are used for device-level configuration, status read back or control.
3) Channel Registers – These registers are used to control and configure specific features for each individual
channel. All channels have the same channel register set and can be configured independent of each other.
The global registers can be accessed at any time, regardless of whether the shared or channel register set is
selected. The DS280DF810 global registers are located on addresses 0xEF-0xFF. The function of the global
registers falls into the following categories:
30
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Programming (接下页)
•
•
•
Channel selection and share enabling – Registers 0xFC and 0xFF
Device and version information – Registers 0xEF-0xF3
Reserved or unused registers – all other addresses
Register 0xFF[5:4] selects the share registers of either Quad 0 (channels 0-3) or Quad 1 (channels 4-7).
Register 0xFC is used to select the channel registers to be written to. To select a channel, write a 1 to its
corresponding bit in register 0xFC. Note that more than one channel may be written to by setting multiple bits in
register 0xFC. However, when performing an SMBus read transaction only one channel can be selected at a
time. If multiple channels are selected when attempting to perform an SMBus read, the device will return 0xFF.
Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read-
modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a
single channel in register 0xFC. This type of configuration allows for the reading of a single channel's register
information and then writing to all channels with the modified value. Register 0xFF bit 0 is used to select the
shared register page or the channel register page for the channels selected in register 0xFC.
TI repeaters and retimers have a vendor ID register (0xFE) which will always read back 0x03. In addition, there
are three device ID registers (0xF0, 0xF1, and 0xF3). These are useful to verify that there is a good SMBus
connection between the SMBus master and the DS280DF810.
8.6 Register Maps
Refer to the DS280DF810 Programming Guide (SNLU182) for the complete register map and example
programming sequences.
The DS280DF810 has a vendor ID register (0xFE), which will always read back 0x03. In addition, there are four
device ID registers (0xEF, 0xF0, 0xF1, and 0xF3). Reading these five registers and confirming the expected
value is a good way to verify SMBus communications between the SMBus Master and the DS280DF810. In
addition, writing a value to channel select Reg_0xFC and confirming the correct value is read back is a good way
to verify SMBus write communications with the DS280DF810.
表 7. Device and Vendor ID Registers
Global Register Description
0xEF
0xF0
0xF1
TI device ID (Quad count).
DS280DF810: 0x0C
TI version ID.
DS280DF810: 0x31
TI device ID.
DS280DF810: 0x13
0xF3
0xFE
TI channel and share version ID. Contains 0x00.
TI vendor ID. Contains 0x03.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS280DF810 is a high-speed retimer which extends the reach of differential channels and cleans jitter and
other signal impairments in the process. It can be deployed in a variety of different systems from backplanes to
front ports to active cable assemblies. The following sections outline typical applications and their associated
design considerations.
9.2 Typical Application
The DS280DF810 is typically used in the following application scenarios:
1. Backplane and Mid-Plane Reach Extension Application
2. Front-Port Jitter Cleaning Application
Line Card
Switch Fabric
25 G / 28 G - LR
25 G / 28 G - VSR
DS280DF810
Optical
x8
x8
X8
25 G / 28 G - LR
DS280DF810
CFP-2/QSFP28
ASIC
ASIC
FPGA
FPGA
Active Copper
DS280DF810
X8
25 G / 28 G-LR
x8 25 G / 28 G
DS280DF810
CFP-2/QSFP28
Backplane /
Midplane
图 15. Typical uses for the DS280DF810 in a system
32
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Typical Application (接下页)
9.2.1 Backplane and Mid-Plane Reach Extension Application
The DS280DF810 has strong equalization capabilities that allow it to recover data over channels up to 35 dB
insertion loss (at 12.9 GHz). As a result, the optimum placement for the DS280DF810 in a backplane and mid-
plane application is with the higher-loss channel segment at the input and the lower-loss channel segment at the
output. This reduces the equalization burden on the downstream ASIC/FPGA, as the DS280DF810 is equalizing
a majority of the overall channel. This type of asymmetric placement is not a requirement, but when an
asymmetric placement is required due to the presence of a passive backplane or mid-plane, then this becomes
the recommended placement.
Passive Backplane/
Midplane
Line Card
Switch Fabric Card
x8 25 G / 28 G
ASIC
ASIC
FPGA
FPGA
x8 25 G / 28 G
图 16. Backplane and Mid-Plane Application Block Diagram
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Typical Application (接下页)
Retimer
No AC coupling
capacitors needed
No AC coupling
capacitors needed
RX0P
TX0P
TX0N
RX0N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
RX1P
RX1N
TX1P
TX1N
TX6P
TX6N
RX6P
RX6N
RX7P
RX7N
TX7P
TX7N
2.5 V or 3.3 V
VDD
To other
open-drain
interrupt pins
SMBus
Slave mode
1 kΩ
INT_N
SDA
To
system
SMBus(1)
EN_SMB
TEST
SDC
25 MHz
Address
straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
CAL_CLK_IN
READ_EN_N
CAL_CLK_OUT
SMBus Slave
mode
Float for SMBus
Slave mode
ALL_DONE_N
GND
2.5 V
VDD
Minimum
recommended
decoupling
1 ꢀF
(2x)
0.1 ꢀF
(4x)
Backplane /
Mid-plane
Connector
ASIC / FPGA
Retimer
No AC coupling
capacitors needed
No AC coupling
capacitors needed
RX0P
RX0N
TX0P
TX0N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
RX1P
RX1N
TX1P
TX1N
RX6P
RX6N
TX6P
TX6N
RX7P
RX7N
TX7P
TX7N
VDD
INT_N
SMBus
Slave mode
1 kΩ
SDA
SDC
EN_SMB
TEST
ADDR0
ADDR1
Address straps
(pull-up, pull-
down, or float)
CAL_CLK_IN
READ_EN_N
CAL_CLK_OUT
SMBus Slave
mode
ALL_DONE_N
GND
2.5 V
VDD
Minimum
recommended
decoupling
1 ꢀF
(2x)
0.1 ꢀF
(4x)
(1) SMBus signals need to be pulled up elsewhere in the system.
图 17. Backplane and Mid-Plane Application Schematic
34
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Typical Application (接下页)
9.2.1.1 Design Requirements
For this design example, the following guidelines outlined in 表 8 apply.
表 8. Backplane and Mid-Plane Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
Not required. AC coupling capacitors are included in the device
package.
AC coupling capacitors
≤ 35 dB at 25.78125 Gbps Nyquist frequency
≤ 30 dB at 28 Gbps Nyquist frequency
Input channel insertion loss
Depends on downstream ASIC and FPGA capabilities. The
DS280DF810 has a low-jitter output driver with 3-tap FIR filter for
equalizing a portion of the output channel.
Output channel insertion loss
Link partner TX launch amplitude
Link partner TX FIR filter
800 mVppd to 1200 mVppd
Depends on channel loss
9.2.1.2 Detailed Design Procedure
The design procedure for backplane and mid-plane applications is as follows:
1. Determine the total number of channels on the board which require a DS280DF810 for signal conditioning.
This will dictate the total number of DS280DF810 devices required for the board. It is generally
recommended that channels with similar total insertion loss on the board be grouped together in the same
DS280DF810 device. This will simplify the device settings, as similar loss channels generally utilize similar
settings.
2. Determine the maximum current draw required for all DS280DF810 retimers. This may impact the selection
of the regulator for the 2.5 V supply rail. To calculate the maximum current draw, multiply the maximum
transient power supply current by the total number of DS280DF810 devices.
3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and
retransmitting the data which is received. PRBS pattern checkers and generators are not used in this
mode since normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the
worst-case power consumption in mission mode by the total number of DS280DF810 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and
retransmitting the data which is received. At the same time, some channels’ PRBS checkers or
generators may be enabled. For this calculation, multiply the worst-case power consumption in debug
mode by the total number of DS280DF810 devices.
4. Determine the SMBus address scheme needed to uniquely address each DS280DF810 device on the board.
Each DS280DF810 can be strapped with one of 16 unique SMBus addresses. If there are more
DS280DF810 devices on the board than the number of unique SMBus addresses which can be assigned,
then use an I2C expander like the TCA/PCA family of I2C/SMBus switches and multiplexers to split up the
SMBus into multiple busses.
5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions should be made for an EEPROM on the board with 8-bit
SMBus address 0xA0.
b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.
6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
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DS280DF810
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7. Make provisions in the schematic and layout for a 25 MHz (±100 ppm) single-ended CMOS clock. Each
DS280DF810 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the
CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid
the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5 V CMOS output,
then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or
resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN
input. The final retimer’s CAL_CLK_OUT output can be left floating.
8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that
multiple retimers’ INT_N outputs can be connected together since this is an open-drain output. The common
INT_N net should be pulled high.
9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Timing
Requirements, Retimer Jitter Specifications, then care should be taken to ensure the operating junction
temperature is met as well as the CDR stay-in-lock ambient temperature range defined in Timing
Requirements, Retimer Jitter Specifications. For example, if initial CDR lock acquisition occurs at an ambient
temperature of 85 ºC, then maintaining CDR lock would require the ambient temperature surrounding the
DS280DF810 to be kept above (85 ºC - TEMPLOCK-).
36
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DS280DF810
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ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
9.2.2 Front-Port Jitter Cleaning Application
The DS280DF810 has strong equalization capabilities that allow it to equalize insertion loss, reduce jitter, and
extend the reach of front-port interfaces. A single DS280DF810 can be used to support all eight egress channels
for a stacked QSFP cage. Another DS280DF810 can be used to support all eight ingress channels for the same
stacked QSFP cage. Alternatively, a single DS280DF810 can be used to support all egress and ingress channels
for a single QSFP port.
For applications which require IEEE802.3 100GBASE-CR4 or 25GBASE-CR auto-negotiation and link training, a
linear repeater device such as the DS280BR820 (or similar) is recommended.
图 18 illustrates this configuration, and Timing Requirements, Retimer Jitter Specifications shows an example
simplified schematic for a typical front-port application.
Line Card
DS280DF810
x8 25 G / 28 G - LR
25 G / 28 G
VSR
Optical
DS280DF810
ASIC
FPGA
Mezzanine
DS280DF810
Optical or Copper
25 G / 28 G
VSR
x8 25 G SR / 28 G - LR
DS280DF810
图 18. Front-Port Application Block Diagram
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DS280DF810
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www.ti.com.cn
Egress Retimer
No AC coupling
capacitors needed
No AC coupling
capacitors needed
TX0P
TX0N
RX0P
RX0N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
RX1P
RX1N
TX1P
TX1N
TX6P
TX6N
RX6P
RX6N
RX7P
RX7N
TX7P
TX7N
2.5 V or 3.3 V
VDD
SMBus
Slave mode
1 kΩ
INT_N
SDA
SDC
To
system
SMBus(1)
EN_SMB
TEST
ADDR0
ADDR1
25 MHz
Address
straps
(pull-up, pull-
down, or float)
CAL_CLK_IN
READ_EN_N
CAL_CLK_OUT
SMBus Slave
mode
Float for SMBus
Slave mode
ALL_DONE_N
GND
2.5 V
VDD
Minimum
recommended
decoupling
1 ꢀF
(2x)
0.1 ꢀF
(4x)
Front Port Connector
(e.g. stacked QSFP28)
ASIC / FPGA
Ingress Retimer
No AC coupling
capacitors needed
No AC coupling
capacitors needed
RX0P
RX0N
TX0P
TX0N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
RX1P
RX1N
TX1P
TX1N
RX6P
RX6N
TX6P
TX6N
RX7P
RX7N
TX7P
TX7N
VDD
INT_N
SMBus
Slave mode
1 kΩ
SDA
SDC
EN_SMB
TEST
ADDR0
ADDR1
Address straps
(pull-up, pull-
down, or float)
CAL_CLK_IN
READ_EN_N
CAL_CLK_OUT
SMBus Slave
mode
ALL_DONE_N
GND
2.5 V
VDD
Minimum
recommended
decoupling
1 ꢀF
(2x)
0.1 ꢀF
(4x)
(1) SMBus signals need to be pulled up elsewhere in the system.
图 19. Front-Port Application Schematic
38
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DS280DF810
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ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
9.2.2.1 Design Requirements
For this design example, the following guidelines outlined in 表 9 apply.
表 9. Front-Port Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
Not required. AC coupling capacitors are included in the device
package.
AC coupling capacitors
≤ 35 dB at 25.78125 Gbps Nyquist frequency.
≤ 30 dB at 28 Gbps Nyquist frequency.
Input channel insertion loss
Output channel insertion loss
Egress (ASIC-to-module) direction: Follow CAUI-4 / CEI-25G-VSR
host channel requirements (approximately 7 dB at 12.9 GHz).
Ingress (module-to-ASIC) direction: Depends on downstream ASIC
and FPGA capabilities. The DS280DF810 has a low-jitter output
driver with 3-tap FIR filter for equalizing a portion of the output
channel.
Host ASIC TX launch amplitude
Hos ASIC TX FIR filter
800 mVppd to 1200 mVppd
Depends on channel loss. Refer to Setting the Output VOD, Pre-
Cursor, and Post-Cursor Equalization.
9.2.2.2 Detailed Design Procedure
The design procedure for front-port applications is as follows:
1. Determine the total number of channels on the board which require a DS280DF810 for signal conditioning.
This will dictate the total number of DS280DF810 devices required for the board. It is generally
recommended that channels with similar total insertion loss on the board be grouped together in the same
DS280DF810 device. This will simplify the device settings, as similar loss channels generally utilize similar
settings.
2. Determine the maximum current draw required for all DS280DF810 retimers. This may impact the selection
of the regulator for the 2.5 V supply rail. To calculate the maximum current draw, multiply the maximum
transient power supply current by the total number of DS280DF810 devices.
3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and
retransmitting the data which is received. PRBS pattern checkers and generators are not used in this
mode since normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the
worst-case power consumption in mission mode by the total number of DS280DF810 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and
retransmitting the data which is received. At the same time, some channels’ PRBS checkers or
generators may be enabled. For this calculation, multiply the worst-case power consumption in debug
mode by the total number of DS280DF810 devices.
4. Determine the SMBus address scheme needed to uniquely address each DS280DF810 device on the board.
Each DS280DF810 can be strapped with one of 16 unique SMBus addresses. If there are more
DS280DF810 devices on the board than the number of unique SMBus addresses which can be assigned,
then use an I2C expander like the TCA/PCA family of I2C/SMBus switches and multiplexers to split up the
SMBus into multiple busses.
5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions should be made for an EEPROM on the board with 8-bit
SMBus address 0xA0.
b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.
6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
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ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
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7. Make provisions in the schematic and layout for a 25 MHz (±100 ppm) single-ended CMOS clock. Each
DS280DF810 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the
CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid
the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5 V CMOS output,
then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or
resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN
input. The final retimer’s CAL_CLK_OUT output can be left floating.
8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that
multiple retimers’ INT_N outputs can be connected together since this is an open-drain output. The common
INT_N net should be pulled high.
9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Timing
Requirements, Retimer Jitter Specifications, care should be taken to ensure the operating junction
temperature is met as well as the CDR stay-in-lock ambient temperature range defined in Timing
Requirements, Retimer Jitter Specifications. For example, if initial CDR lock acquisition occurs at an ambient
temperature of 85 ºC, then maintaining CDR lock would require the ambient temperature surrounding the
DS280DF810 to be kept above (85 ºC - TEMPLOCK-).
9.2.3 Application Curves
图 20. DS280DF810 Operating at 25.78125 Gbps
图 21. DS280DF810 FIR Transmit Equalization while
Operating at 25.78125 Gbps
图 20 shows a typical output eye diagram for the DS280DF810 operating at 25.78125 Gbps with PRBS9 pattern
using FIR main-cursor of +18, pre-cursor of -1 and post-cursor of +2. All other device settings are left at default.
图 21 shows an example of DS280DF810 FIR transmit equalization while operating at 25.78125 Gbps. In this
example, the Tx FIR filter main-cursor is set to +15, post-cursor to -3 and pre-cursor to -3. An 8T pattern is used
to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.
40
版权 © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
10 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the recommended operating conditions outlined in
Specifications in terms of DC voltage, AC noise, and start-up ramp time.
2. The maximum current draw for the DS280DF810 is provided in Specifications . This figure can be used to
calculate the maximum current the supply must provide. Typical mission-mode current draw can be inferred
from the typical power consumption in Specifications.
3. The DS280DF810 does not require any special power supply filtering (that is, ferrite bead) provided the
recommended operating conditions are met. Only standard supply decoupling is required. Refer to Pin
Configuration and Functions for details concerning the recommended supply decoupling.
11 Layout
11.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing them directly
underneath the device is one option if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care
should be taken to minimize the via stub, either by transitioning through most or all layers, or by back drilling.
4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by
counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board
6. BGA landing pads for a 0.8 mm pitch flip-chip BGA are typically 0.4 mm in diameter (exposed). The actual
size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined
solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) References
at http://focus.ti.com/quality/docs under the "Quality and Lead (Pb)-Free Data" menu.
7. If vias are used for the high-speed signals, ground via should be implemented adjacent to the signal via to
provide return path and isolation. For differential pair, the typical via configuration is "ground-signal-signal-
ground."
11.2 Layout Example
The following example layout demonstrates how all signals can be escaped from the BGA array using stripline
routing on a generic 28-layer stackup. This example layout assumes the following:
•
•
•
•
•
•
Trace width: 0.127 mm (5 mil)
Trace edge-to-edge spacing: 0.152 mm (6 mil)
VIA finished hole size (diameter): 0.203 mm (8 mil)
VIA drilled hole size: 0.254 mm (10 mil)
VIA-to-VIA spacing: 1.0 mm (39 mil), to enhance PCB manufacturability
No VIA-in-pad used
Note that many other escape routing options exist using different trace width and spacing combinations. The
optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.
版权 © 2016–2019, Texas Instruments Incorporated
41
DS280DF810
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
www.ti.com.cn
Layout Example (接下页)
图 23. Internal Signal Layer 1
图 22. Top Layer
图 25. Bottom Layer
图 24. Internal Signal Layer 2
42
版权 © 2016–2019, Texas Instruments Incorporated
DS280DF810
www.ti.com.cn
ZHCSKG3A –SEPTEMBER 2016–REVISED OCTOBER 2019
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《25G/28G 重定时器程序员指南》
德州仪器 (TI)，《DS280DF810EVM 用户指南》
德州仪器 (TI)，《了解 25G 和 28G 中继器和重定时器的 EEPROM 编程》 应用报告
德州仪器 (TI)， 《在 CPRI-7 应用中使用 TI 25G/28G 重定时器》 应用报告
德州仪器 (TI)，《DS2X0DF810 自适应参数优化进程》应用报告
德州仪器 (TI)，《DS2X0DFX10 25Gbps/28Gbps 重定时器功能指南》应用报告
德州仪器 (TI)，《25G/28G 重定时器针对异常值数据速率 PPM 校验场景进行 CDR 锁定优化》应用报告
德州仪器 (TI)， 《在 OTU4 应用中使用 TI 25G/28G 重定时器》 应用报告
德州仪器 (TI)，《TI 25G 和 28G 重定时器和中继器的选择指南》 应用报告
请单击此处，以请求对 DS280DF810 MySecure 文件夹中的程序员指南进行访问。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016–2019, Texas Instruments Incorporated
43
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS280DF810ABVR
DS280DF810ABVT
DS280DF810ABWR
DS280DF810ABWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FCCSP
FCCSP
FCCSP
FCCSP
ABV
ABV
ABW
ABW
135
135
135
135
1000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DS280DF8
Samples
Samples
Samples
Samples
SNAGCU
SNAGCU
SNAGCU
DS280DF8
DS280DF8W
DS280DF8W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS280DF810ABVR
DS280DF810ABVT
DS280DF810ABWR
DS280DF810ABWT
FCCSP
FCCSP
FCCSP
FCCSP
ABV
ABV
ABW
ABW
135
135
135
135
1000
250
330.0
178.0
330.0
178.0
24.4
24.4
24.4
24.4
8.4
8.4
8.4
8.4
13.4
13.4
13.4
13.4
3.0
3.0
3.0
3.0
12.0
12.0
12.0
12.0
24.0
24.0
24.0
24.0
Q2
Q2
Q2
Q2
1000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS280DF810ABVR
DS280DF810ABVT
DS280DF810ABWR
DS280DF810ABWT
FCCSP
FCCSP
FCCSP
FCCSP
ABV
ABV
ABW
ABW
135
135
135
135
1000
250
367.0
213.0
367.0
213.0
367.0
191.0
367.0
191.0
45.0
55.0
45.0
55.0
1000
250
Pack Materials-Page 2
PACKAGE OUTLINE
ABV0135A
FCBGA - 2.51 mm max height
SCALE 1.300
BALL GRID ARRAY
13.2
12.9
B
A
(11)
BALL A1 CORNER
2X (1)
8.2
7.9
(6)
2X (2.8)
2X (2.6)
(0.5)
C
2.51 MAX
(0.58)
SEATING PLANE
0.2 C
BALL TYP
0.405
TYP
0.325
11.2 TYP
SYMM
(0.9) TYP
J
H
G
F
(0.8) TYP
SYMM
135X
6.4
E
D
C
TYP
0.51
0.41
0.2
C A
C
B
B
A
0.08
0.8 TYP
1
2
3
4
5
6
8
9
10 11 12 13 14 15
7
0.8 TYP
BALL A1 CORNER
4221740/B 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ABV0135A
FCBGA - 2.51 mm max height
BALL GRID ARRAY
(0.8) TYP
135X ( 0.4)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
(0.8) TYP
D
SYMM
E
F
G
H
J
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
(
0.4)
0.05 MAX
0.05 MIN
(
0.4)
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221740/B 02/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ABV0135A
FCBGA - 2.51 mm max height
BALL GRID ARRAY
(
0.4) TYP
(0.8) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
(0.8) TYP
D
SYMM
E
F
G
H
J
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4221740/B 02/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
ABW0135A
FCBGA - 2.51 mm max height
SCALE 1.300
BALL GRID ARRAY
13.2
12.9
B
A
(11)
BALL A1 CORNER
8.2
7.9
(6)
(0.5)
C
2.51 MAX
(0.58)
SEATING PLANE
0.2 C
BALL TYP
0.405
TYP
0.325
11.2 TYP
SYMM
(0.9) TYP
J
H
G
F
(0.8) TYP
SYMM
6.4
E
D
C
TYP
0.51
135X
0.41
0.2
C A B
C
B
A
0.08
0.8 TYP
1
2
3
4
5
6
8
9
10 11 12 13 14 15
7
0.8 TYP
BALL A1 CORNER
4223026/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ABW0135A
FCBGA - 2.51 mm max height
BALL GRID ARRAY
(0.8) TYP
135X ( 0.4)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
(0.8) TYP
D
SYMM
E
F
G
H
J
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
(
0.4)
0.05 MAX
0.05 MIN
(
0.4)
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223026/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ABW0135A
FCBGA - 2.51 mm max height
BALL GRID ARRAY
(
0.4) TYP
(0.8) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
(0.8) TYP
D
SYMM
E
F
G
H
J
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4223026/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
DS2890P-000+
Digital Potentiometer, 1 Func, 100000ohm, 1-wire Serial Control Interface, 256 Positions, TSOC-6
MAXIM
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