DS32EV100SD/NOPB [TI]
可编程单式均衡器 | NHK | 14 | -40 to 85;
| 型号： | DS32EV100SD/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 可编程单式均衡器 | NHK | 14 | -40 to 85 电信 光电二极管 电信集成电路 |
| 文件： | 总14页 (文件大小：1061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS32EV100
www.ti.com
SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
DS32EV100 Programmable Single Equalizer
Check for Samples: DS32EV100
1
FEATURES
DESCRIPTION
The DS32EV100 programmable equalizer provides
compensation for transmission medium losses and
reduces the medium-induced deterministic jitter for
NRZ data channel. The DS32EV100 is optimized for
operation up to 3.2 Gbps for both cables and FR4
traces. The equalizer channel has eight levels of
input equalization that can be programmed by three
control pins.
2
•
•
•
•
Equalizes Up to 14 dB loss at 3.2 Gbps
8 levels of Programmable Equalization
Operates up to 3.2 Gbps with 40” FR4 Traces
0.12 UI Residual Deterministic Jitter at 3.2
Gbps with 40” FR4 Traces
•
•
Single 2.5V or 3.3V Power Supply
Supports AC or DC-Coupling with Wide Input
Common-Mode
The equalizer supports both AC and DC-coupled data
paths for long run length data patterns such as
PRBS-31, and balanced codes such as 8b/10b. The
device uses differential current-mode logic (CML)
inputs and outputs. The DS32EV100 is available in a
3 mm x 4 mm 14-pin WSON package. Power is
supplied from either a 2.5V or 3.3V supply.
•
•
•
•
Low power Consumption: 100 mW Typ at 2.5V
Small 3 mm x 4 mm 14-pin WSON Package
> 8 kV HBM ESD Rating
-40 to 85°C Operating Temperature Range
Simplified Application Diagram
Tx
ASIC/FPGA
High Speed
I/O
DS32EV100
OUT IN
Rx
Switch Fabric Card
Line Card
Backplane/Cable
Sub-system
Tx
ASIC/FPGA
High Speed
I/O
DS32EV100
Rx
OUT
IN
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS32EV100
SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
www.ti.com
Pin Diagram
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
BST_2
GND
GND
OUT_+
OUT_-
GND
IN+
IN-
DS32EV100
TOP VIEW
DAP = GND
VDD
GND
GND
BST_1
8
BST_0
Figure 1. 14-Pin WSON Package
(3 mm x 4 mm x 0.8 mm, 0.5 mm pitch)
See Package Number NHK0014A
PIN DESCRIPTIONS(1)
I/O,
Type
Pin Name
Pin #
Description
HIGH SPEED DIFFERENTIAL I/O
IN−
IN+
4
3
I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating
resistor is connected between IN+ and IN−. Refer to Figure 5.
OUT−
OUT+
11
12
O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT+ to VDD and OUT− to VDD.
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
14
7
8
I,
BST_2, BST_1, and BST_0 select the equalizer strength. BST_2 is internally pulled high. BST_1
LVCMOS and BST_0 are internally pulled low.
POWER
VDD
5
Power VDD = 2.5V ±5% or 3.3V ±10%. VDD pins should be tied to VDD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.
GND
DAP
2, 6, 9, 10,
13
Power Ground reference. GND should be tied to a solid ground plane through a low impedance path.
PAD
Power Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board.
OTHER
NC
1
Reserved. Leave no Connect.
(1) I = Input, O = Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
Absolute Maximum Ratings(1)(2)
Supply Voltage (VDD
)
−0.5V to +4.0V
−0.5V to +4.0V
–0.5V to +4.0V
–0.5V to +4.0V
+150°C
CMOS Input Voltage
CMOS Output Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
Lead Temperature
Soldering, 4 sec
+260°C
ESD Rating
HBM, 1.5 kΩ, 100 pF
EIAJ, 0Ω, 200 pF
> 8 kV
> 250 V
Thermal Resistance, θJA
,
No Airflow
40 °C/W
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Min
Typ
Max
Units
(1)
Supply Voltage
VDD2.5 to GND
VDD3.3 to GND
2.375
3.0
2.5
3.3
25
2.625
3.6
V
V
Ambient Temperature
−40
+85
°C
(1) The VDD2.5 is VDD = 2.5V ± 5% and VDD3.3 is VDD = 3.3V ± 10%.
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(1)
POWER
P
Power Supply
Consumption
VDD2.5
VDD3.3
100
140
150
200
mW
mW
N
Supply Noise
Tolerance
50 Hz – 100 Hz
100 Hz – 10 MHz
10 MHz – 1.6GHz
100
40
10
mVP-P
mVP-P
mVP-P
(3)
LVTTL DC SPECIFICATIONS
VIH
High Level Input
Voltage
VDD2.5
VDD3.3
1.6
2.0
VDD2.5
VDD3.3
V
V
VIL
Low Level Input
Voltage
−0.3
0.8
V
(1) Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation
Conditions at the time of product characterization and are not guaranteed.
(2) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(3) Allowed supply noise (mVP-P sine wave) under typical conditions.
Copyright © 2006–2013, Texas Instruments Incorporated
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SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Typ
Symbol
VOH
Parameter
Conditions
Min
Max
Units
(1)
High Level Output
Voltage
IOH = –3mA, VDD2.5
IOH = –3mA, VDD3.3
IOL = 3mA
2.0
2.4
V
V
VOL
IIN
Low Level Output
Voltage
0.4
V
Input Current
VIN = VDD
+1.8
0
+15
µA
µA
µA
VIN = GND
−15
IIN-P
Input Leakage Current VIN = VDD, with internal pull-down resistors
+95
with Internal Pull-
VIN = GND, with internal pull-up resistors
Down/Up Resistors
–20
µA
CML RECEIVER INPUTS (IN+, IN−)
VTX
Source Transmit
Launch Signal Level
(IN diff)
AC-Coupled or DC-Coupled Requirement,
Differential measurement at point A.
(Figure 2)
400
1600
mVP-P
VINTRE
VDDTX
VICMDC
Input Threshold
Voltage
Differential measurement at point B.
(Figure 2)
120
mVP-P
V
Supply Voltage of
Transmitter to EQ
DC-Coupled Requirement
1.6
VDD
Input Common-Mode
Voltage
DC-Coupled Requirement
Differential measurement at point A.
VDDTX-0.8
VDDTX-0.2
V
(4)
(Figure 2),
RLI
RIN
Differential Input
Return Loss
100 MHz – 1.6 GHz, with fixture’s effect de-
embedded
10
dB
Input Resistance
Differential Across IN+ and IN-. (Figure 5)
85
100
115
Ω
CML OUTPUTS (OUT+, OUT−)
VOD
Output Differential
Voltage Level (OUT
diff)
Differential measurement with OUT+ and OUT-
terminated by 50Ω to GND, AC-Coupled
(Figure 3)
550
620
725
mVP-P
VOCM
Output Common-Mode Single-ended measurement DC-Coupled with
Voltage
50Ω terminations
VDD-0.2
VDD-0.1
V
(4)
tR, tF
Transition Time
20% to 80% of differential output voltage,
measured within 1” from output pins.
20
42
60
58
ps
(Figure 3)
(4)
RO
Output Resistance
Single-ended to VDD
50
10
Ω
RLO
Differential Output
Return Loss
100 MHz – 1.6 GHz, with fixture’s effect de-
embedded. IN+ = static high.
dB
tPLHD
Differential Low to
High Propagation
Delay
Propagation delay measurement at 50% VOD
between input to output, 100 Mbps
(Figure 4),
240
240
ps
ps
(4)
tPHLD
Differential High to
Low Propagation
Delay
EQUALIZATION
DJ1
Residual Deterministic 40” of 6 mil microstrip FR4, EQ Setting 0x06,
Jitter at 3.2 Gbps
PRBS-7 (27-1) pattern
0.12
0.1
0.2
UIP-P
(5)
DJ2
Residual Deterministic 40” of 6 mil microstrip FR4, EQ Setting 0x06,
Jitter at 2.5 Gbps
PRBS-7 (27-1) pattern
0.16
UIP-P
(5) (6)
(4) Measured with clock-like {11111 00000} pattern.
(5) Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
(6) Deterministic jitter is measured at the differential outputs (point C of Figure 2), minus the deterministic jitter before the test channel (point
A of Figure 2). Random jitter is removed through the use of averaging or similar means.
4
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SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Typ
Symbol
DJ3
Parameter
Conditions
Min
Max
Units
(1)
Residual Deterministic 40” of 6 mil microstrip FR4, EQ Setting 0x06,
Jitter at 1 Gbps
PRBS-7 (27-1) pattern
0.05
0.5
UIP-P
psrms
(5) (6)
(4) (7)
RJ
Random Jitter
(7) Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in psrms, see
point C of Figure 2; JIN is the random jitter at the input of the equalizer in psrms, see Figure 2.
B
C
A
6 mils Trace Width,
FR4 Microstrip Test Channel
DS32EV100
INPUT OUTPUT
Signal Source
SMA
Connector
SMA
Connector
Figure 2. Test Setup Diagram
80%
80%
0V
OUT diff = (OUT+) œ (OUT-)
20%
20%
t
t
R
F
Figure 3. CML Output Transition Times
IN diff
0V
t
t
PHLD
PLHD
OUT diff
0V
Figure 4. Propagation Delay Timing Diagram
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SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
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V
DD
10k
IN+
IN -
V
50
50
DD
10k
6k
6k
EQ
Figure 5. Simplified Receiver Input Termination Circuit
DS32EV100 FUNCTIONAL DESCRIPTIONS AND APPLICATIONS INFORMATION
The DS32EV100 is a programmable equalizer optimized for operation up to 3.2 Gbps for backplane and cable
applications. The equalizer channel consists of an equalizer stage, a limiting amplifier, a DC offset correction
block, and a CML driver as shown in Figure 6.
DC Offset Correction
Input
Limiting
Amplifier
OUT
OUT
+
-
IN+
Equalizer
-
IN
Termination
BST CNTL
BST_0 : BST_2
3
3
Figure 6. Simplified Block Diagram
EQUALIZER BOOST CONTROL
The equalizer channel supports eight programmable levels of equalization boost, and is controlled by the Boost
Set pins (BST_[2:0]) in accordance with Table 1. The eight levels of boost settings enables the DS32EV100 to
address a wide range of media loss and data rates.
Table 1. EQ Boost Control Table
6 mil Microstrip FR4 Trace
Length (in)
24 AWG Twin-AX Cable Length
(m)
Channel Loss 1.6 GHz (dB)
BST_N
[2, 1, 0]
0
0
2
0
3
0 0 0
0 0 1
5
10
15
20
25
30
40
3
6
0 1 0
4
7
0 1 1
5
8
1 0 0 (Default)
1 0 1
6
10
12
14
7
1 1 0
10
1 1 1
6
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SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
GENERAL RECOMMENDATIONS
The DS32EV100 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner’s Manual for more detailed information on high-speed design tips to address signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML
lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of
a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit
board. See AN-1187 for additional information on WSON packages.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS32EV100 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS32EV100. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as
possible to the DS32EV100.
DC COUPLING
The DS32EV100 supports both AC coupling with external ac coupling capacitor, and DC coupling to its upstream
driver, or downstream receiver. With DC coupling, users must ensure the input signal common mode is within the
range of the electrical specification VICMDC and the device output is terminated with 50 Ω to VDD. When power-up
and power-down the device, both the DS32EV100 and the downstream receiver should be power-up and power-
down together. This is to avoid the internal ESD structures at the output of the DS32EV100 at power-down from
being turned on by the downstream receiver.
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SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
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Typical Performance Eye Diagrams and Curves
Figure 7. Equalized Signal
(40 in FR4, 1 Gbps, PRBS 7, 0x07 Setting)
Figure 8. Equalized Signal
(40 in FR4, 2.5 Gbps, PRBS 7, 0x07 Setting)
Figure 9. Equalized Signal
(40 in FR4, 3.2Gbps, PRBS 7, 0x07 Setting)
Figure 10. Equalized Signal
(10m 24 AWG Twin-AX Cable, 3.2 Gbps, PRBS 7, 0x07
Setting)
Figure 11. Equalized Signal
(32 in Tyco XAUI Backplane, 3.125 Gbps, PRBS 7, 0x07
Setting
Figure 12. DJ vs. EQ Setting (3.2 Gbps)
8
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SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
REVISION HISTORY
Changes from Revision C (February 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS32EV100SD/NOPB
ACTIVE
WSON
NHK
14
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
D32E1SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS32EV100SD/NOPB
WSON
NHK
14
1000
178.0
12.4
3.3
4.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON NHK 14
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
DS32EV100SD/NOPB
1000
Pack Materials-Page 2
MECHANICAL DATA
NHK0014A
SDA14A (Rev A)
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