DS36C200M/NOPB [TI]

双路高速双向差动收发器 | D | 14 | 0 to 70;
DS36C200M/NOPB
型号: DS36C200M/NOPB
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

双路高速双向差动收发器 | D | 14 | 0 to 70

驱动 光电二极管 接口集成电路 驱动器
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DS36C200  
www.ti.com  
SNLS111D JUNE 1998REVISED APRIL 2013  
DS36C200 Dual High Speed Bi-Directional Differential Transceiver  
Check for Samples: DS36C200  
1
FEATURES  
DESCRIPTION  
The DS36C200 is a dual transceiver device optimized  
for high data rate and low power applications. This  
device provides a single chip solution for a dual high  
speed bi-directional interface. Also, both control pins  
may be routed together for single bit control of  
datastreams. Both control pins are adjacent to each  
other for ease of routing them together. The  
DS36C200 is compatible with IEEE 1394 physical  
layer and may be used as an economical solution  
with some considerations. Please reference the  
application information on 1394 for more information.  
The device is in a 14-lead small outline package. The  
differential driver outputs provides low EMI with its  
low output swings typically 210 mV. The receiver  
offers ±100 mV threshold sensitivity, in addition to  
common-mode noise protection.  
2
Optimized for DSS to DVHS Interface Link  
Compatible IEEE 1394 Signaling Voltage  
Levels  
Operates Above 100 Mbps  
Bi-directional Transceivers  
14-lead SOIC Package  
Ultra Low Power Dissipation  
±100 mV Receiver Sensitivity  
Low Differential Output Swing Typical 210 mV  
High Impedance During Power Off  
Connection Diagram  
Note: * denotes active LOW pin  
Figure 1. SOIC Package  
See Package Number D (R-PDSO-G14)  
Functional Diagram  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1998–2013, Texas Instruments Incorporated  
DS36C200  
SNLS111D JUNE 1998REVISED APRIL 2013  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Absolute Maximum Ratings(1)(2)  
Supply Voltage (VCC  
)
0.3V to +6V  
Enable Input Voltage  
(DE, RE*)  
0.3V to (VCC + 0.3V)  
0.3V to +5.9V  
Voltage (DI/RO)  
Voltage (DO/RI±)  
0.3V to +5.9V  
Maximum Package Power Dissipation @+25°C  
M Package  
1255 mW  
10.04 mW/°C above +25°C  
65°C to +150°C  
Derate M Package  
Storage Temperature Range  
Lead Temperature Range  
(Soldering, 4 sec.)  
+260°C  
(3)  
ESD Rating  
(HBM, 1.5 kΩ, 100 pF)  
(EIAJ, 0 Ω, 200 pF)  
3.5 kV  
300V  
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply  
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.  
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.  
(3) ESD Rating: HBM (1.5 kΩ, 100 pF) 3.5 kV  
EIAJ (0Ω, 200 pF) 300V  
Recommended Operating Conditions  
Min  
+4.5  
0
Typ  
Max  
+5.5  
2.4  
Units  
Supply Voltage (VCC  
)
+5.0  
V
V
Receiver Input Voltage  
Operating Free Air  
Temperature (TA)  
0
25  
70  
°C  
2
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DS36C200  
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SNLS111D JUNE 1998REVISED APRIL 2013  
Electrical Characteristics(1)(2)(3)  
Over supply voltage and operating temperature ranges, unless otherwise specified  
Symbol  
Parameter  
Conditions  
Pin  
Min  
Typ  
Max  
Units  
DIFFERENTIAL DRIVER CHARACTERISTICS (RE* = VCC  
)
VOD  
ΔVOD  
VOH  
VOL  
Output Differential Voltage  
VOD Magnitude Change  
Output High Voltage  
Output Low Voltage  
RL = 55Ω, (Figure 2)  
DO+,  
DO−  
172  
0
210  
4
285  
35  
mV  
mV  
V
1.36  
1.15  
1.25  
5
V
VOS  
Offset Voltage  
1.0  
0
1.6  
25  
V
ΔVOS  
IOZD  
IOXD  
IOSD  
Offset Magnitude Change  
TRI-STATE Leakage  
Power-Off Leakage  
mV  
μA  
μA  
mA  
VOUT = VCC or GND  
VOUT = 5.5V or GND, VCC = 0V  
VOUT = 0V  
10  
10  
±1  
+10  
+10  
9  
±1  
Output Short Circuit Current  
4  
DIFFERENTIAL RECEIVER CHARACTERISTICS (DE = GND)  
VTH  
VTL  
IIN  
Input Threshold High  
Input Threshold Low  
Input Current  
VCM = 0V to 2.3V  
RI+,  
RI−  
+100  
+10  
mV  
mV  
μA  
V
100  
10  
3.8  
VIN = +2.4V or 0V  
IOH = 400 μA  
±1  
4.9  
4.9  
4.9  
4.9  
0.1  
60  
VOH  
Output High Voltage  
RO  
Inputs Open  
3.8  
V
Inputs Terminated, Rt = 55Ω  
Inputs Shorted, VID = 0V  
IOL = 2.0 mA, VID = 200 mV  
VOUT = 0V  
3.8  
V
V
VOL  
Output Low Voltage  
0.4  
V
IOSR  
Output Short Circuit Current  
15  
100  
mA  
DEVICE CHARACTERISTICS  
VIH  
VIL  
IIH  
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
Input Clamp Voltage  
Power Supply Current  
DI, DE  
RE*  
2.0  
VCC  
0.8  
V
V
GND  
VIN = VCC or 2.4V  
±1  
±1  
0.8  
3
±10  
±10  
μA  
μA  
V
IIL  
VIN = GND or 0.4V  
ICL = 18 mA  
VCL  
ICCD  
1.5  
No Load, DE = RE* = VCC  
RL = 55Ω, DE = RE* = VCC  
DE = RE* = 0V  
VCC  
7
mA  
mA  
mA  
11  
6
17  
10  
ICCR  
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground  
except VOD and VID  
.
(2) All typicals are given for VCC = +5.0V and TA = +25°C.  
(3) The DS36C200 is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers  
outputs.  
Copyright © 1998–2013, Texas Instruments Incorporated  
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DS36C200  
SNLS111D JUNE 1998REVISED APRIL 2013  
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Units  
Switching Characteristics  
Over supply voltage and operating temperature ranges, unless otherwise specified.  
(1) (2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
DIFFERENTIAL DRIVER CHARACTERISTICS  
tPHLD  
tPLHD  
tSKD  
tTLH  
tTHL  
tPHZ  
tPLZ  
Differential Propagation Delay High to Low  
Differential Propagation Delay Low to High  
RL = 55Ω, CL = 10 pF  
(Figure 3 and Figure 4)  
1.0  
1.0  
0
2.5  
2.6  
0.1  
0.5  
0.5  
5
5.5  
5.5  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Differential Skew |tPHLD – tPLHD  
Transition Time Low to High  
Transition Time High to Low  
Disable Time High to Z  
|
0
2
0
2
RL = 55Ω  
(Figure 5 and Figure 6)  
0.3  
0.3  
0.3  
0.3  
20  
20  
30  
30  
Disable Time Low to Z  
5
tPZH  
tPZL  
Enable Time Z to High  
10  
10  
Enable Time Z to Low  
DIFFERENTIAL RECEIVER CHARACTERISTICS  
tPHLD  
tPLHD  
tSKD  
tr  
Differential Propagation Delay High to Low  
Differential Propagation Delay Low to High  
CL = 10 pF, VID = 200 mV  
(Figure 7 and Figure 8)  
1.5  
1.5  
0
5
9
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4.6  
0.4  
1.5  
1.5  
5
Differential Skew |tPHLD – tPLHD  
|
3
Rise Time  
0
5
tf  
Fall Time  
0
5
tPHZ  
tPLZ  
tPZH  
tPZL  
Disable Time High to Z  
Disable Time Low to Z  
Enable Time Z to High  
Enable Time Z to Low  
CL = 10 pF  
(Figure 9 and Figure 10)  
1
20  
20  
30  
30  
1
5
0.3  
0.3  
10  
10  
(1) CL includes probe and fixture capacitance.  
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr 1 ns, tf 1 ns (0%–100%).  
4
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DS36C200  
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SNLS111D JUNE 1998REVISED APRIL 2013  
PARAMETER MEASUREMENT INFORMATION  
Figure 2. Differential Driver DC Test Circuit  
Figure 3. Differential Driver Propagation Delay and Transition Time Test Circuit  
Figure 4. Differential Driver Propagation Delay and Transition Time Waveforms  
Figure 5. Driver TRI-STATE Delay Test Circuit  
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SNLS111D JUNE 1998REVISED APRIL 2013  
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Figure 6. Driver TRI-STATE Delay Waveforms  
Figure 7. Receiver Propagation Delay and Transition Time Test Circuit  
Figure 8. Receiver Propagation Delay and Transition Time Waveforms  
Figure 9. Receiver TRI-STATE Delay Test Circuit  
Figure 10. Receiver TRI-STATE Delay Waveforms  
6
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Product Folder Links: DS36C200  
 
DS36C200  
www.ti.com  
SNLS111D JUNE 1998REVISED APRIL 2013  
APPLICATION INFORMATION  
TRUTH TABLES  
The DS36C200 has two enable pins DE and RE*, however, the driver and receiver should never be enabled  
simultaneously. Enabling both could cause multiple channel contention between the receiver output and the  
driving logic. It is recommended to route the enables together on the PC board. This will allow a single bit  
[DE/RE*] to control the chip. This DE/RE* bit toggles the DS36C200 between Receive mode and Transmit mode.  
When the bit is asserted HIGH the device is in Transmit mode. When the bit is asserted LOW the device is in  
Receive mode. The mode determines the function of the I/O pins: DI/RO, DO/RI+, and DO/RI. Please note that  
some of the pins have been identified by its function in the corresponding mode in the three tables below. For  
example, in Transmit mode the DO/RI+ pin is identified as DO+. This was done for clarity in the tables only and  
should not be confused with the pin identification throughout the rest of this document. Also note that a logic low  
on the DE/RE* bit corresponds to a logic low on both the DE pin and the RE* pin. Similarly, a logic high on the  
DE/RE* bit corresponds to a logic high on both the DE pin and the RE* pin.  
Table 1. Receive Mode(1)  
Input(s)  
Input/Output  
[RI+] [RI]  
DE  
L
RE*  
L
RO  
H
> +100 mV  
< 100 mV  
L
L
L
L
L
100 mV > & > 100 mV  
X
X
L
H
Z
(1) H = Logic high level  
L = Logic low level  
X = Indeterminate state  
Z = High impedance state  
Table 2. Transmit Mode(1)  
Input(s)  
Input/Output  
DE  
H
RE*  
H
DI  
DO+  
L
DO−  
H
L
H
H
H
2 > & > 0.8  
X
H
L
H
H
X
X
L
H
Z
Z
(1) H = Logic high level  
L = Logic low level  
X = Indeterminate state  
Z = High impedance state  
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SNLS111D JUNE 1998REVISED APRIL 2013  
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DEVICE PIN DESCRIPTIONS  
Pin#  
Name  
(In mode only)  
DE  
Mode  
Description  
3
Transmit  
Driver Enable: When asserted low driver is disabled. And when asserted  
high driver is enabled.  
1, 7  
10, 13  
11, 12  
4
DI  
TTL/CMOS driver input pins  
Non-inverting driver output pin  
Inverting driver output pin  
DO+  
DO−  
RE*  
Receive  
Receiver Enable: When asserted low receiver is enabled. And when  
asserted high receiver is disabled.  
1, 7  
10, 13  
11, 12  
5
RO  
RI+  
RI−  
GND  
VCC  
NC  
Receiver output pin  
Positive receiver input pin  
Negative receiver input pin  
Ground pin  
Transmit and  
Receive  
2
Positive power supply pin, +5V ± 10%  
No Connect  
6, 8, 9, 14  
IEEE 1394  
The DS36C200 drives and receives IEEE 1394 physical layer signal levels. The current mode driver is capable of  
driving a 55Ω load with VOD between 172 mV and 285 mV. The DS36C200 is not designed to work with a link  
layer controller IC requiring full 1394 physical layer compliancy to the standard. No clock generator, no  
arbitration, and no encode/decode logic is provided with this device. For a 1394 link where speed sensing, bus  
arbitration, and other functions are not required, a controller and the DS36C200 will provide a cost effective, high  
speed dedicated link. This is shown in Figure 11. In applications that require fully compliant 1394 protocol, a link  
layer controller and physical layer controller will be required as shown in Figure 11. The physical layer controller  
supports up to three DC36C200 devices (not shown).  
The DS36C200 drivers are current mode drivers and intended to work with a two 110Ω termination resistors in  
parallel with each other. The termination resistors should match the characteristic impedance of the transmission  
media. The drivers are current mode devices therefore the resistors are required. Both resistors are required for  
half duplex operation and should be placed as close to the DO/RI+ and DO/RIpins as possible at opposite  
ends of the bus. However, if your application only requires simplex operation, only one termination resistor is  
required. In addition, note the voltage levels will vary from those in the datasheet due to different loading. Also,  
AC or unterminated configurations are not used with this device. Multiple node configurations are possible as  
long as transmission line effects are taken into account. Discontinuities are caused by mid-bus stubs,  
connectors, and devices that affect signal integrity.  
The differential line driver is a balanced current source design. A current mode driver, generally speaking has a  
high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other  
hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to  
produce a logic state and in the other direction to produce the other logic state. The typical output current is mere  
3.8 mA, a minimum of 3.1 mA, and a maximum of 5.2 mA. The current mode requires that a resistive  
termination be employed to terminate the signal and to complete the loop as shown in Figure 12. The 3.8 mA  
loop current will develop a differential voltage of 210 mV across the 55Ω termination resistor which the receiver  
detects with a 110 mV minimum differential noise margin neglecting resistive line losses (driven signal minus  
receiver threshold (210 mV – 100 mV = 110 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with  
respect to ground as shown in Figure 8.  
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its  
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver  
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows  
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed  
current between its output without any substantial overlap current. This is similar to some ECL and PECL  
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less  
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing  
RS-422 drivers.  
8
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Fail-safe Feature:  
The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS  
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from  
appearing as a valid signal.  
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe  
protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.  
1. Open Input Pins. The DS36C200 is a dual transceiver device, and if an application requires only one  
receiver, the unused channel inputs should be left OPEN. Do not tie the receiver inputs to ground or any  
other voltages. The input is biased by internal high value pull up or pull down resistors to set the output to a  
HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs.  
2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or  
power-off condition, the receiver output will again be in a HIGH state, even with the end of the cable 100Ω  
termination resistor across the input pins. The unplugged cable can become a floating antenna which can  
pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a  
valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced  
interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable.  
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V  
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not  
supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs  
shorted and no external common-mode voltage applied.  
If there is more than 10mV of differential noise, the receiver may switch or oscillate. If this condition can happen  
in your application, you may wish to add external fail-safe resistors to create a larger noise margin. External  
lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of  
higher noise levels. The pull up and pull down resistors should be in the 5kto 15krange to minimize loading  
and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less  
than 1.75V) to be compatible with the internal circuitry.  
Additional information on fail-safe biasing of LVDS devices may be found in AN-1194 (SNLA051).  
Figure 11. (A) Dedicated IEEE 1394 Link  
(B) Full IEEE 1394 Compliant Link  
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Figure 12. Typical in Home Application  
(1)  
Figure 13. Typical Interface Connection  
(1) The DS36C200 is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers  
outputs.  
10  
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SNLS111D JUNE 1998REVISED APRIL 2013  
REVISION HISTORY  
Changes from Revision C (April 2013) to Revision D  
Page  
Changed layout of National Data Sheet to TI format .......................................................................................................... 10  
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PACKAGE OPTION ADDENDUM  
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10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
DS36C200M/NOPB  
DS36C200MX/NOPB  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
14  
14  
55  
RoHS & Green  
SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
0 to 70  
0 to 70  
DS36C200M  
DS36C200M  
2500 RoHS & Green  
SN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
DS36C200MX/NOPB  
SOIC  
D
14  
2500  
330.0  
16.4  
6.5  
9.35  
2.3  
8.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOIC 14  
SPQ  
Length (mm) Width (mm) Height (mm)  
367.0 367.0 35.0  
DS36C200MX/NOPB  
D
2500  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
TUBE  
*All dimensions are nominal  
Device  
Package Name Package Type  
SOIC  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
DS36C200M/NOPB  
D
14  
55  
495  
8
4064  
3.05  
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