DS50PCI401SQ/NOPB [TI]
具有均衡和去加重功能的 5.0Gbps 4 通道转接驱动器 | NJY | 54 | -10 to 85;
| 型号： | DS50PCI401SQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有均衡和去加重功能的 5.0Gbps 4 通道转接驱动器 | NJY | 54 | -10 to 85 驱动 接口集成电路 驱动器 |
| 文件： | 总37页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS50PCI401
www.ti.com
SNLS292J –JUNE 2009–REVISED APRIL 2013
DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with
Equalization and De-Emphasis
Check for Samples: DS50PCI401
1
FEATURES
DESCRIPTION
The DS50PCI401 is a low power, 4 lane bidirectional
2
•
Input and Output signal conditioning
increases PCIe reach in backplanes and
cables
buffer/equalizer designed specifically for PCI Express
Gen1 and Gen2 applications. The device performs
both receive equalization and transmit de-emphasis,
allowing maximum flexibility of physical placement
within a system. The receiver is capable of opening
an input eye that is completely closed due to inter-
symbol interference (ISI) induced by the interconnect
medium.
•
•
•
•
0.09 UI of residual deterministic jitter at 5Gbps
after 42” of FR4 (with Input EQ)
0.11 UI of residual deterministic jitter at 5Gbps
after 7m of PCIe Cable (with Input EQ)
0.09 UI of residual deterministic jitter at 5Gbps
with 28” of FR4 (with Output DE)
The transmitter de-emphasis level can be set by the
user depending on the distance from the
DS50PCI401 to the PCI Express endpoint. The
DS50PCI401 contains PCI Express specific functions
such as Transmit Idle, RX Detection, and Beacon
signal pass through.
0.13 UI of residual deterministic jitter at 5Gbps
with 7m of PCIe Cable (with Output DE)
•
•
Adjustable Transmit VOD 800 to 1200mVp-p
Automatic power management on an
individual lane basis via SMBus
The device will change the load impedance on its
input pins based on the state of RXDETA/B inputs
detection. An internal rate detection circuit is included
to detect if an incoming data stream is at Gen2 data
rates, and adjusts the de-emphasis on it's output
accordingly. The signal conditioning provided by the
device allows systems to upgrade from Gen1 data
rates to Gen2 without reducing their physical reach.
This is true for FR4 applications such as backplanes,
as well as cable interconnect.
•
•
Adjustable electrical idle detect threshold.
Data rate optimized 3-stage equalization to 26
dB gain
•
•
Data rate optimized 6-level 0 to 12 dB transmit
de-emphasis
Flow-thru pinout in 10mmx5.5mm 54-pin
leadless WQFN package
•
•
•
Single supply operation at 2.5V
>6kV HBM ESD rating
-10 to 85°C operating temperature range
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
DS50PCI401
SNLS292J –JUNE 2009–REVISED APRIL 2013
www.ti.com
Typical Application
PCI401
Slice 1 of 4
PCI Express Interconnect
Cable or Backplane
PCI Express
Root
Complex or
Bridge
PCI401
Slice 1 of 4
PCI Express
Endpoint
Block Diagram - Detail View Of Channel (1 Of 8)
VOD/ DeEMPHASIS
CONTROL
VDD
DEMA/B
SMBus
RATE
DET
RXDETA/B
EQ
LIMITER
Ix_n+
Ix_n-
OUTBUF
Ox_n+
Ox_n-
TX Idle Enable
IDLE
DET
EQA/B
SMBus
TXIDLEx
SMBus
2
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SNLS292J –JUNE 2009–REVISED APRIL 2013
Pin Diagram
SMBUS AND CONTROL
OB_0+
OB_0-
OB_1+
OB_1-
OB_2+
OB_2-
OB_3+
OB_3-
1
2
3
4
IB_0+
IB_0-
IB_1+
IB_1-
45
44
43
42
5
6
7
8
41
40
39
38
VDD
IB_2+
IB_2-
IB_3+
9
DAP = GND
IB_3-
VDD
37
36
35
34
33
32
31
10
11
12
13
14
15
16
17
VDD
IA_0+
IA_0-
IA_1+
OA_0+
OA_0-
OA_1+
OA_1-
OA_2+
OA_2-
OA_3+
OA_3-
IA_1-
VDD
IA_2+
IA_2-
30
29
28
IA_3+
IA_3-
18
DS50PCI401 Pin Diagram 54 lead
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Table 1. Pin Descriptions
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
IA_0+, IA_0- ,
IA_1+, IA_1-,
IA_2+, IA_2-,
IA_3+, IA_3-
10, 11
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INA_0+ to VDD and
INA_0- to VDD when enabled.
12, 13
15, 16
17, 18
OA_0+, OA_0-,
OA_1+, OA_1-,
OA_2+, OA_2-,
OA_3+, OA_3-
35, 34
33, 32
31, 30
29, 28
O,LPDS
I, CML
Inverting and non-inverting low power differential signal (LPDS) 50Ω
driver outputs with de-emphasis. Compatible with AC coupled CML
inputs.
IB_0+, IB_0- ,
IB_1+, IB_1-,
IB_2+, IB_2-,
IB_3+, IB_3-
45, 44
43, 42
40, 39
38, 37
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INB_0+ to VDD and
INB_0- to VDD when enabled.
OB_0+, OB_0-,
OB_1+, OB_1-,
OB_2+, OB_2-,
OB_3+, OB_3-
1, 2
3, 4
5, 6
7, 8
O,LPDS
Inverting and non-inverting low power differential signal (LPDS) 50Ω
driver outputs with de-emphasis. Compatible with AC coupled CML
inputs.
Control Pins — Shared (LVCMOS)
ENSMB 48
I, LVCMOS
w/internal
pulldown
System Management Bus (SMBus) enable pin.
When pulled high provide access internal digital registers that are a
means of auxiliary control for such functions as equalization, de-
emphasis, VOD, rate, and idle detection threshold.
When pulled low, access to the SMBus registers are disabled and
SMBus function pins are used to control the Equalizer and De-Emphasis.
Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND
CONFIGURATION REGISTERS and Electrical Characteristics — Serial
Management Bus Interface for detail information.
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS
ENSMB = 1
SMBUS clock input pin is enabled. External pull-up resistor maybe
needed. Refer to RTERM in the SMBus specification.
SDA
49
I, LVCMOS,
ENSMB = 1
O, Open Drain
The SMBus bi-directional SDA pin is enabled. Data input or open drain
output. External pull-up resistor is required.
Refer to RTERM in the SMBus specification.
AD0-AD3
54, 53, 47, 46
I, LVCMOS
w/internal
pulldown
ENSMB = 1
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs. See section — SYSTEM
MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
for additional information.
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I,FLOAT,
LVCMOS
EQA/B ,0/1 controls the level of equalization of the A/B sides as shown in
Table 2. The EQA/B pins are active only when ENSMB is de-asserted
(Low). Each of the 4 A/B channels have the same level unless controlled
by the SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane, and the EQB0/B1
pins are converted to SMBUS AD2/AD3 inputs.
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I,FLOAT,
LVCMOS
DEMA/B ,0/1 controls the level of de-emphasis of the A/B sides as
shown in Table 3. The DEMA/B pins are only active when ENSMB is de-
asserted (Low). Each of the 4 A/B channels have the same level unless
controlled by the SMBus control registers. When ENSMB goes High the
SMBus registers provide independent control of each lane and the DEM
pins are converted to SMBUS AD0/AD1 and SCL/SDA inputs.
RATE
21
I,FLOAT,
LVCMOS
RATE control pin controls the pulse width of de-emphasis of the output.
A Low forces Gen1 (2.5Gbps), High forces Gen 2 (5Gbps),
Open/Floating the rate is internally detected after each exit from idle and
the pulse width is set appropriately. When ENSMBUS= 1 this pin is
disabled and the RATE function is controlled internally by the SMBUS
registers. Refer to Table 3.
4
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Pin Name
SNLS292J –JUNE 2009–REVISED APRIL 2013
Table 1. Pin Descriptions (continued)
Pin Number
I/O, Type
Pin Description
Control Pins — Both Modes (LVCMOS)
RXDETA,RXDETB
PRSNT
22,23
I, LVCMOS
w/internal
pulldown
The RXDET pins in combination with the ENRXDET pin controls the
receiver detect function. Depending on the input level, a 50Ω or >50KΩ
termination to the power rail is enabled. Refer to Table 6.
52
I, LVCMOS
Cable Present Detect input. High when a cable is not present per PCIe
Cabling Spec. 1.0. Puts part into low power mode. When low (normal
operation) part is enabled.
ENRXDET
26
I, LVCMOS
w/internal
pulldown
Enables pin control of receiver detect function. Pin must be pulled high
externally for RXDETA/B to function. Controls both A and B sides. Refer
to Table 6.
TXIDLEA,TXIDLEB
24,25
I, FLOAT,
LVCMOS
Controls the electrical idle function on corresponding outputs when
enabled. H= electrical Idle, Float=autodetect (Idle on input passed to
output), L=Idle squelch disabled as shown in Table 4.
Analog
SD_TH
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for
default 130mV DIFF p-p, otherwise connect resistor from SD_TH to GND
to set threshold voltage as shown in Table 5.
Power
VDD
9, 14,36, 41, 51
DAP
Power
Power
Power supply pins CML/analog.
GND
Ground pad (DAP - die attach pad).
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FUNCTIONAL DESCRIPTION
The DS50PCI401 is a low power media compensation 4 lane repeater optimized for PCI Express Gen 1 and Gen
2 media including lossy FR-4 printed circuit board backplanes and balanced cables. The DS50PCI401 operates
in two modes: Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically
increased per the De-Emphasis table below for improved performance over lossy media. The receiver detect
pins RXDETA/B provide manual control for input termination (50Ω or >50KΩ). Rate optimization is also pin
controllable, with pin selections for 2.5Gbps, 5Gbps, and auto detect. The receiver electrical idle detect threshold
is also programmable via an optional external resistor on the SD_TH pin.
SMBUS Mode:
When in SMBus mode the equalization, de-emphasis, and termination disable features are all programmable on
a individual lane basis, instead of grouped by sides as in the pin mode case. Upon assertion of ENSMB the
RATE, EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to
AD0-AD3 SMBus address inputs. The other external control pins remain active unless their respective registers
are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low.
On powerup and when ENSMB is driven low all registers are reset to their default state. If PRSNT is asserted
while ENSMB is high, the registers retain their current state.
Table 2. Equalization Input Select Pins for A and B ports (3–Level Input)
EQ1(1)
EQ0(1)
Equalization Level
Off
Suggested Use
F
1
0
F
1
F
0
0
1
F
1
0
0
0
1
1
F
F
Bypass
Approx. 4 dB at 2.5Ghz
Approx. 9.6 dB at 2.5GHz
Approx. 11.4 dB at 2.5Ghz
Approx. 15.5 dB at 2.5Ghz
Approx. 17 dB at 2.5Ghz
Approx.19.1 dB at 2.5Ghz
Approx. 20.6 dB at 2.5Ghz
Approx. 26.3 dB at 2.5Ghz
8 inches FR4 (6-mil trace) or less than 1 meter (28 AWG) PCIe cable
14 inches FR4 (6-mil trace) or 1 meter (28 AWG) PCIe cable
20 inches FR4 (6-mil trace) or 5 meters (26 AWG) PCIe cable
30 inches FR4 (6-mil trace) or 7 meters (24 AWG) PCIe cable
40 inches FR4 (6-mil trace) or 9 meters (24 AWG) PCIe cable
50 inches FR4 (6-mil trace) or 10 meters (24 AWG) PCIe cable
15 meters (24 AWG) PCIe cable
>15 meters (24 AWG) PCIe cable
(1) F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
Table 3. De-Emphasis Input Select Pins for A and B ports (3–Level Input)
RATE
DEM1 DEM0(1
Typical De-
Emphasis Level
Typical DE Pulse
Width
Typical VOD
Suggested Use
(1)
)
0/F
0/F
0
0
0
1
0dB
0ps
1000mV
1000mV
-3.5dB
400ps
8 inches FR4 (6-mil trace) or less than 1
meter (28 AWG) PCIe cable
0/F
0/F
0/F
0/F
0/F
0/F
0/F
1
1
0
1
F
F
F
0
1
F
F
0
1
F
-6dB
-6dB
400ps
1000mV
1000mV
1000mV
1000mV
1200mV
1400mV
400ps enhanced
400ps enhanced
400ps enhanced
400ps enhanced
400ps enhanced
15 inches FR4 (6-mil trace)
-9dB
-12dB
-9dB
30 inches FR4 (6-mil trace)
40 inches FR4 (6-mil trace)
-12dB
Reserved, don't
use
1/F
1/F
0
0
0
1
0dB
0ps
1000mV
1000mV
-3.5dB
200ps
(1) F=Float (don't drive pin - (each float pin has an internal 50K Ohm resistor to VDD and GND). Enhanced DE Pulse width provides
additional de-emphasis on second bit. VOD = Voltage Output Differential amplitude. When RATE is floated (F=Auto Rate Detection
Active) DE Level and Pulse Width settings follow detected RATE. RATE=0 is 2.5GBps, RATE=1 is 5 GBps
6
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RATE
SNLS292J –JUNE 2009–REVISED APRIL 2013
Table 3. De-Emphasis Input Select Pins for A and B ports (3–Level Input) (continued)
DEM1 DEM0(1
Typical De-
Emphasis Level
Typical DE Pulse
Width
Typical VOD
Suggested Use
(1)
)
1/F
1/F
1/F
1/F
1/F
1/F
1/F
1
1
0
1
F
F
F
0
1
F
F
0
1
F
-6dB
-6dB
200ps
1000mV
1000mV
1000mV
1000mV
1200mV
1400mV
200ps enhanced
200ps enhanced
200ps enhanced
200ps enhanced
200ps enhanced
10 inches FR4 (6-mil trace)
-9dB
-12dB
-9dB
20 inches FR4 (6-mil trace)
30 inches FR4 (6-mil trace)
-12dB
Reserved, don't
use
Table 4. Idle Control (3–Level Input)
TXIDLEA/B
Function
0
This state is for lossy media, dedicated Idle threshold detect circuit disabled,
output follows input based on EQ settings. Idle state not guaranteed.
Float
1
Float enables automatic idle detection. Idle on the input is passed to the
output. This is the recommended default state. Output driven to Idle if diff input
signal less than value set by SD_TH pin.
Manual override, output forced to Idle. Diff inputs are ignored.
Table 5. Receiver Electrical Idle Detect Threshold Adjust (Analog input - connect Resistor to GND or
Float)
SD_TH resistor value (Ω) (connect from pin to GND)(1)
Typical Receiver Electrical Idle Detect Threshold (DIFF p-p)
Float (no resistor required)
130mV (default condition)
0
225mV
20mV
80K
(1) SD_TH resistor value can be set from 0 through 80K Ohms to achieve desired idle detect threshold, see Figure 1. 8K Ohm is approx
130mV.
250
V
= 2.5V
= 25°C
DD
T
A
200
150
100
50
0
0
10k 20k 30k 40k 50k 60k 70k 80k
SD_TH RESISTOR VALUE (W)
Figure 1. Typical Idle threshold vs SD_TH resistor value
Table 6. Receiver Detect Pins for A and B ports (LVCMOS inputs)
PRSNT#
ENRXDET
RXDETA/B
Function
0
1
0
Disable RXDETA termination mode: Rx detection state machine disabled. Input
termination >50KΩ. Associated output channels in low power idle mode.
0
1
1
Force RXDETA termination mode: Rx detection state machine disabled. Input termination
50Ω. Associated output channels set to active.
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Table 6. Receiver Detect Pins for A and B ports (LVCMOS inputs) (continued)
PRSNT#
ENRXDET
RXDETA/B
Function
1
X
X
Power down mode: Input termination 50Ω. Associated output channels off. Part in power
saving mode.
USING RXDETA/B IN A PCIe ENVIRONMENT
In order for upstream and downstream PCIe subsystems to communicate in a cabling environment, the PCIe
specification includes several auxiliary or sideband signals to manage system-level functionality or
implementation. Similar methods are used in backplane applications, but the exact implementation falls outside
the PCIe standard. Initial communication from the downstream subsystem to the upstream subsystem is done
with the CPRSNT# auxiliary signal. The CPRSNT# signal is asserted Low by the downstream componentry after
the "Power Good" condition has been established. This mechanism allows for the upstream subsystem to
determine whether the power is good within the downstream subsystem, enable the reference clock, and initiate
the Link Training Sequence.
CPWRON
0V
CPRSNT# to RESET Removal
5 ms (min)
CPERST#
0V
RESET Removed and
REFCLK Stable
CPRSNT#
CREFCLK
0V
Figure 2. Typical PCIe System Timing
The signals shown in the graphic could be easily replicated within the downstream subsystem and used to
control the RXDETA/B inputs on the DS50PCI401. Often an onboard microcontroller will be used to handle
events like power-up, power-down, power saving modes, and hot insertion. The microcontroller would use the
same information to determine when to enable and disable the DS50PCI401 input termination. In applications
that require SMBus control, the microcontroller could also delay any response to the upstream subsystem to
allow sufficient time to correctly program the DS50PCI401 and other devices on the board.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8
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SNLS292J –JUNE 2009–REVISED APRIL 2013
(1)(2)
Absolute Maximum Ratings
Supply Voltage (VDD)
LVCMOS Input/Output Voltage
CML Input Voltage
-0.5V to +3.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5V)
-30 to +30 mA
CML Input Current
LPDS Output Voltage
Analog (SD_TH)
-0.5V to (VDD+0.5V)
-0.5V to (VDD+0.5V)
+125°C
Junction Temperature
Storage Temperature
Lead Temperature Range
Soldering (4 sec.)
-40°C to +125°C
+260°C
Maximum Package Power Dissipation at 25°C
NJY Package
4.21 W
Derate NJY Package
52.6mW/°C above +25°C
ESD Rating
HBM, STD - JESD22-A114C
MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-C
Thermal Resistance
≥6 kV
≥250 V
≥1250 V
θJC
11.5°C/W
19.1°C/W
θJA, No Airflow, 4 layer JEDEC
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage
VDD to GND
2.375
-10
2.5
25
2.625
+85
3.6
V
°C
Ambient Temperature
SMBus (SDA, SCL)
Supply Noise Tolerance up to 50Mhz
V
(1)
100
mV pp
(1) Allowed supply noise (mVP-P sine wave) under typical conditions.
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Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
(1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(3)
POWER
EQX=Float, DEX=0, VOD=1Vpp
,PRSNT=0
758
950
mW
mW
PD
Power Dissipation
PRSNT=1, ENSMB=0
0.92
1.125
LVCMOS / LVTTL DC SPECIFICATIONS
(4)
(4)
VIH
High Level Input
Voltage
2
0
3.6
0.8
V
V
V
V
VIL
Low Level Input
Voltage
VOH
VOL
IIH
High Level Output
Voltage
SMBUS open drain VOH set by
pullup Resistor
Low Level Output
Voltage
IOL = 4mA
0.4
Input High Current
Input Low Current
VIN = 3.6V , LVCMOS
-15
-15
+15
μA
μA
VIN = 3.6V , w/
FLOAT,PULLDOWN input
+120
IIL
VIN = 0V
-15
-80
+15
+15
VIN = 0V, w/FLOAT input
CML RECEIVER INPUTS (IN_n+, IN_n-)
(5)
RLRX-DIFF
Rx package plus Si
differential return loss
0.05GHz – 1.25GHz
-21
-20
dB
(5)
1.25GHz – 2.5GHz
(5)
RLRX-CM
Common mode Rx
return loss
0.05GHz - 2.5GHz
-11.5
50
dB
Ω
ZRX-DC
Rx DC common mode Tested at VDD=0
impedance
40
85
60
115
1.2
ZRX-DIFF-DC
VRX-DIFF-DC
ZRX-HIGH-IMP-DC -POS
Rx DC differential
impedance
Tested at VDD=0
100
Ω
Differential Rx peak to Tested at DC, TXIDLEx=0
peak voltage
0.10
V
DC Input CM
impedance for V>0
Vin = 0 to 200 mV,
RXDETA/B = 0,
50
40
KΩ
ENSMB = 0, VDD=2.625
VRX-IDLE-DET-DIFF-PP
Electrical Idle detect
threshold
SD_TH = float, see Table 5,
175
mVP-P
(6)
LPDS OUTPUTS (OUT_n+, OUT_n-)
VTX-DIFF-PP
Output Voltage Swing
Differential measurement with
OUT_n+ and OUT_n- terminated
by 50Ω to GND AC-Coupled,
800
1000
1200
mVP-P
(3)
Figure 4,
VOCM
Output Common-Mode Single-ended measurement DC-
VDD - 1.4
3.5
V
(1)
Voltage
Coupled with 50Ω termination,
VTX-DE-RATIO-3.5
Tx de-emphasis level
ratio
VOD = 1000 mV, DEM1 = GND,
dB
(1) (7)
DEM0 = VDD,
,
(1) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not guaranteed.
(2) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(3) Measured with DEM Select pins configured for 1000mV VOD, see De-emphasis table.
(4) Input edge rate for LVCMOS/FLOAT inputs must be 50ns minimum from 10-90%.
(5) Input Return Loss also uses the setup shown in Figure 6. The blocking / biasing circuit is replaced with a simple AC coupling capacitor
for each input to emulate a typical PCIe application.
(6) Measured at package pins of receiver. Less than 40mV is IDLE, greater than 175mV is ACTIVE. SD_TH pin connected with resistor to
GND overrides this default setting.
(7) Measured with a repeating K28.5 pattern at a data rate of 2.5 Gbps and 5.0 Gbps.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) (2)
Symbol
VTX-DE-RATIO-6
Parameter
Conditions
Min
Typ
Max
Units
Tx de-emphasis level
ratio
VOD = 1000 mV, DEM1 = VDD,
6
dB
(1) (7)
DEM0 = GND,
,
(8)
TTX-HF-DJ-DD
TTX-LF-RMS
Tx Dj > 1.5 Mhz
0.15
3.0
UI
(8)
Tx RMS jitter < 1.5Mhz
ps RMS
TTX-RISE-FALL
Transmitter Rise/ Fall
Time
20% to 80% of differential output
voltage, Figure 3
50
67
ps
(1) (9)
TRF-MISMATCH
RLTX-DIFF
Tx rise/fall mismatch
20% to 80% of differential output
voltage
0.01
0.1
UI
(1) (9)
Differential Output
Return Loss
0.05- 1.25 Ghz, See Figure 6
1.25- 2.5 Ghz, See Figure 6
-23
-20
dB
dB
RLTX-CM
Common Mode Return 0.05- 2.5 Ghz, See Figure 6
Loss
-11
dB
Ω
ZTX-DIFF-DC
VTX-CM-AC-PP
ITX-SHORT
DC differential Tx
impedance
100
Tx AC common mode
voltage
100
90
mVpp
transmitter short circuit Total current transmitter can
current limit
supply when shorted to VDD or
GND
mA
mV
mV
nS
VTX-CM-DC- ACTIVE-IDLE-
DELTA
Absolute Delta of DC
Common Mode Voltage
during L0 and electrical
Idle
40
25
VTX-CM-DC- LINE-DELTA
Absolute Delta of DC
Common Mode Voltage
between Tx+ and Tx-
TTX-IDLE-SET-TO -IDLE
Max time to transition
to valid diff signaling
after leaving Electrical
Idle
VIN = 800 mVp-p, 5 Gbps,
Figure 5
6.5
5.5
9.5
TTX-IDLE-TO -DIFF-DATA
Max time to transition
to valid diff signaling
after leaving Electrical
Idle
VIN = 800 mVp-p, 5 Gbps,
Figure 5
8
nS
ps
TPDEQ
Differential Propagation EQ = 11,
Delay +4.0 dB @ 2.5 GHz , Figure 4
150
120
200
170
250
(10)
TPD
Differential Propagation EQ = FF,
Delay Equalizer Bypass, Figure 4
220
27
ps
ps
ps
(10) (11)
TLSK
Lane to Lane Skew in a TA = 25C,VDD = 2.5V
(12) (11)
Single Part
TPPSK
Part to Part
Propagation Delay
Skew
TA = 25C,VDD = 2.5V
35
(8) PCIe 2.0 transmit jitter specifications - actual device jitter is much less. Actual device Rj and Dj has been characterized and specified
with test loads outlined in the EQUALIZATION and DE-EMPHASIS sections of the Electrical Characteristics table.
(9) Guaranteed by device characterization
(10) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ Bypass will result in the shortest
propagation delays.
(11) Propagation Delay measurements for Part to Part skew are all based on devices operating under indentical temperature and supply
voltage conditions.
(12) Guaranteed by device characterization
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) (2)
Symbol
EQUALIZATION
DJE1
Parameter
Conditions
Min
Typ
0.02
0.02
0.02
Max
0.09
0.04
0.11
0.07
Units
UIP-P
UIP-P
UIP-P
Residual Deterministic 42” of 5 mil stripline FR4,
Jitter at 5 Gbps
EQ1,0=F,1; K28.5 pattern,
DEMx=0, Tx Launch Amplitude 1.0
(13) (14)
Vp-p, SD_TH=F.
Residual Deterministic 42” of 5 mil stripline FR4,
Jitter at 2.5 Gbps
EQ1,0=F,1; K28.5 pattern,
DJE2
DJE3
DEMx=0, Tx Launch Amplitude 1.0
(13) (14)
Vp-p, SD_TH=F.
Residual Deterministic 7 meters of 24 AWG PCIe cable,
Jitter at 5 Gbps
EQ1,0=1,0; K28.5 pattern,
DEMx=0, Tx Launch Amplitude 1.0
(13) (14)
Vp-p, SD_TH=F.
Residual Deterministic 7 meters of 24 AWG PCIe cable,
Jitter at 2.5 Gbps
EQ1,0=1,0; K28.5 pattern,
DJE4
RJ
0.03
<0.5
UIP-P
DEMx=0, Tx Launch Amplitude 1.0
(13) (14)
Vp-p, SD_TH=F.
Random Jitter
Tx Launch Amplitude 1.0 Vp-p,
SD_TH=F, Repeating 1100b
psrms
(13)
(D24.3) pattern.
DE-EMPHASIS
Residual Deterministic 28” of 5 mil stripline FR4,
Jitter at 5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,1; Tx Launch
DJD1
0.02
0.03
0.03
0.04
0.09
0.05
0.13
0.06
UIP-P
UIP-P
UIP-P
UIP-P
(13)
(13)
Amplitude 1.0 Vp-p, SD_TH=F.
(14)
Residual Deterministic 28” of 5 mil microstrip FR4,
Jitter at 2.5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,0; Tx Launch
DJD2
DJD3
DJD4
Amplitude 1.0 Vp-p, SD_TH=F.
(14)
Residual Deterministic 7 meters of 24 AWG PCIe cable,
Jitter at 5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,1; Tx Launch
(13)
Amplitude 1.0 Vp-p, SD_TH=F.
(14)
Residual Deterministic 7 meters of 24 AWG PCIe cable,
Jitter at 2.5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,0; Tx Launch
(13)
Amplitude 1.0 Vp-p, SD_TH=F.
(14)
(13) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not guaranteed.
(14) Residual DJ measurements subtract out deterministic jitter present at the generator outputs. For 2.5 Gbps generator Dj = 0.0275 UI and
for 5.0 Gbps generator Dj = 0.035 UI.
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Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
0.8
3.6
V
V
VIH
2.1
4
IPULLUP
Current Through Pull-Up Resistor
or Current Source
High Power Specification
mA
VDD
Nominal Bus Voltage
2.375
-200
3.6
V
(1)
ILEAK-Bus
ILEAK-Pin
CI
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SCL
+200
µA
µA
pF
-15
(1) (2)
10
RTERM
External Termination Resistance
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
Pullup VDD = 3.3V,
2000
1000
Ω
Ω
(1) (2) (3)
Pullup VDD = 2.5V,
(1) (2) (3)
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 7
(4)
FSMB
TBUF
Bus Operating Frequency
10
100
kHz
µs
Bus Free Time Between Stop and
Start Condition
4.7
THD:STA
TSU:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
At IPULLUP, Max
4.0
4.7
µs
µs
Repeated Start Condition Setup
Time
TSU:STO
THD:DAT
TSU:DAT
TTIMEOUT
TLOW
Stop Condition Setup Time
Data Hold Time
4.0
300
250
25
µs
ns
ns
ms
µs
µs
Data Setup Time
(4)
Detect Clock Low Timeout
Clock Low Period
35
4.7
4.0
(4)
(4)
THIGH
Clock High Period
50
2
TLOW:SEXT
Cumulative Clock Low Extend Time
(Slave Device)
ms
(4)
(4)
(4)
tF
Clock/Data Fall Time
Clock/Data Rise Time
300
ns
ns
tR
1000
tPOR
Time in which a device must be
operational after power-on reset
500
ms
(1) Recommended value. Parameter not tested in production.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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TIMING DIAGRAMS
Figure 3. CML Output Transition Times
Figure 4. Propagation Delay Timing Diagram
Figure 5. Idle Timing Diagram
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Supply
Iconnect/PC
Biasing/blocking Circuit
Rt + 2Rl = 98W
Gnd
2.5V
Rl
Bias T
OUT+
OUT-
PCIe EVK board
PCI401
Rt
Biasing/
blocking
CSA8000B w/TDR module
Bias T
Rl
Figure 6. Input and Output Return Loss Setup
t
LOW
t
R
t
HIGH
SCL
SDA
t
t
t
t
SU:STA
HD:STA
F
HD:DAT
t
t
BUF
SU:STO
t
SU:DAT
ST
SP
SP
ST
Figure 7. SMBus Timing Parameters
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SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be
pulled high to enable SMBus mode and allow access to the configuration registers.
The DS50PCI401 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBus slave address
inputs. The AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is A0'h. Based on the SMBus 2.0 specification, the DS50PCI401 has a 7-bit slave address
of 1010000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The device
address byte can be set with the use of the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pull-up resistor and it depends on the Host that drives the bus.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
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6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Please see Table 7 for more information.
SMBus REGISTER WRITES:
The DS50PCI401 outputs will NOT be PCIe compliant with the SMBus registers enabled (ENSMB = 1) until the
VOD levels have been set. Below is an example to configure the VOD level to a PCIe compliant amplitude and
adjust the DE and EQ signal conditioning to work with a 7m PCIe cable interconnect on the input B-side / output
A-side of the device
1. Reset the SMBus registers to default values:
–
Write 01'h to address 0x00.
2. Set VOD = 1.0V for all channels (OA[3:0] and OB[3:0]):
Write 0F'h to address 0x10, 0x17, 0x1E, 0x25, 0x2D, 0x34, 0x3B, 0x42.
3. Set equalization to external pin level EQ[1:0] = 10 (~15.5 dB at 2.5 GHz) for all channels (IB[3:0]):
Write 39'h to address 0x0F, 0x16, 0x1D, 0x24.
4. Set de-emphasis to DE[1:0] = F1 or -12 dB enhanced for all A channels (OA[3:0]):
Write A0'h to address 0x2E, 0x35, 0x3C, 0x43.
–
–
–
IDLE AND RATE DETECTION TO EXTERNAL PINS
The functions of IDLE and RATE detection to external pins for monitoring can be supported in SMBus mode. The
external GPIO pins of 19, 20, 46 and 47 will be changed and they will serve as outputs for IDLE and RATE
detect signals.
The following external pins should be set to auto detection:
RATE = F (FLOAT) – auto RATE detect enabled
TXIDLEA/B = F (FLOAT) – auto IDLE detect enabled
There are 4 GPIO pins that can be configured as outputs with reg_4E[0].
To disable the external SMBus address pins, so pin 46 and 47 can be used as outputs:
Write 01'h to address 0x4E.
Care must be taken to ensure that only the desired status block is enabled and attached to the external pin as
the status blocks can be OR’ed together internally. Register bits reg_47[5:4] and bits reg_4C[7:6] are used to
enable each of the status block outputs to the external pins. The channel status blocks can be internally OR’ed
together to monitor more than one channel at a time. This allows more information to be presented on the status
outputs and later if desired, a diagnosis of the channel identity can be made with additional SMBus writes to
register bits reg_47[5:4] and bits reg_4C[7:6].
Below are examples to configure the device and bring the internal IDLE and RATE status to pins 19, 20, 46, 47.
To monitor the IDLE detect with two channels ORed (CH0 with CH2, CH1 with CH3, CH4 with CH6, CH5 with
CH7):
Write 32'h to address 0x47.
The following IDLE status should be observable on the external pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
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pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means IDLE is detected (no signal present).
Pin = LOW (GND) means ACTIVE (data signal present).
To monitor the RATE detect with two channels ORed (CH0 with CH2, CH1 with CH3, CH4 with CH6, CH5 with
CH7):
Write C0'h to address 0x4C.
The following RATE status should be observable on the external pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means high data rate is detected (6 Gbps).
Pin = LOW (GND) means low rate is detected (3 Gbps).
Table 7. SMBus Register Map
Address
Register Name
Bit (s) Field
Type Default
Description
0x00
Reset
7:1
0
Reserved
R/W
0x00
Set bits to 0.
Reset
SMBus Reset
1: Reset registers to default value
0x01
PWDN Channels
7:0
PWDN CHx
R/W
0x00
Power Down per Channel
[7]: CHA_3
[6]: CHA_2
[5]: CHA_1
[4]: CHA_0
[3]: CHB_3
[2]: CHB_2
[1]: CHB_1
[0]: CHB_0
00'h = all channels enabled
FF'h = all channels disabled
0x02
0x08
PWDN Control
7:1
0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
Override PWDN
0: Allow PWDN pin control
1: Block PWDN pin control
Pin Control Override
7:5
4
Reserved
Set bits to 0.
Override IDLE
0: Allow IDLE pin control
1: Block IDLE pin control
3
2
Reserved
Set bit to 0.
Override RATE
0: Allow RATE pin control
1: Block RATE pin control
1:0
7:6
5
Reserved
Reserved
IDLE auto
Set bits to 0.
Set bits to 0.
0x0E
CH0 - CHB0
IDLE RATE Select
R/W
0x00
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
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Table 7. SMBus Register Map (continued)
0x0F
CH0 - CHB0
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH0 IB0 EQ
IB0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x10
0x11
CH0 - CHB0
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH0 OB0 VOD
OB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH0 - CHB0
DE Control
7:0
CH0 OB0 DEM
OB0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x12
0x15
CH0 - CHB0
IDLE Threshold
7:4
3:0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
CH1 - CHB1
IDLE RATE Select
7:6
5
Reserved
IDLE auto
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
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Table 7. SMBus Register Map (continued)
0x16
CH1 - CHB1
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH1 IB1 EQ
IB1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x17
0x18
CH1 - CHB1
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH1 OB1 VOD
OB1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH1 - CHB1
DE Control
7:0
CH1 OB1 DEM
OB1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x19
0x1C
CH1 - CHB1
IDLE Threshold
7:4
3:0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
CH2 - CHB2
IDLE RATE Select
7:6
5
Reserved
IDLE auto
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
20
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Table 7. SMBus Register Map (continued)
0x1D
CH2 - CHB2
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH2 IB2 EQ
IB2 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x1E
0x1F
CH2 - CHB2
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH2 OB2 VOD
OB2 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH2 - CHB2
DE Control
7:0
CH2 OB2 DEM
OB2 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x20
0x23
CH2 - CHB2
IDLE Threshold
7:4
3:0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
CH3 - CHB3
IDLE RATE Select
7:6
5
Reserved
IDLE auto
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
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Table 7. SMBus Register Map (continued)
0x24
CH3 - CHB3
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH3 IB3 EQ
IB3 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x25
0x26
CH3 - CHB3
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH3 OB3 VOD
OB3 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH3 - CHB3
DE Control
7:0
CH3 OB3 DEM
OB3 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x27
0x2B
CH3 - CHB3
IDLE Threshold
7:4
3:0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
CH4 - CHA0
IDLE RATE Select
7:6
5
Reserved
IDLE auto
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
22
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Table 7. SMBus Register Map (continued)
0x2C
CH4 - CHA0
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH4 IA0 EQ
IA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x2D
0x2E
CH4 - CHA0
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH4 OA0 VOD
OA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH4 - CHA0
DE Control
7:0
CH4 OA0 DEM
OA0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x2F
0x32
CH4 - CHA0
IDLE Threshold
7:4
3:0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
CH5 - CHA1
IDLE RATE Select
7:6
5
Reserved
IDLE auto
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
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Table 7. SMBus Register Map (continued)
0x33
CH5 - CHA1
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH5 IA1 EQ
IA1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ0 EQ1] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x34
0x35
CH5 - CHA1
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH5 OA1 VOD
OA1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH5 - CHA1
DE Control
7:0
CH5 OA1 DEM
OA1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x36
0x39
CH5 - CHA1
IDLE Threshold
7:4
3:0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
CH6 - CHA2
IDLE RATE Select
7:6
5
Reserved
IDLE auto
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
24
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Table 7. SMBus Register Map (continued)
0x3A
CH6 - CHA2
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH6 IA2 EQ
IA2 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x3B
0x3C
CH6 - CHA2
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH6 OA2 VOD
OA2 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH6 - CHA2
DE Control
7:0
CH6 OA2 DEM
OA2 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x3D
0x40
CH6 - CHA2
IDLE Threshold
7:4
3:0
Reserved
R/W
R/W
0x00
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
CH7 - CHA3
IDLE RATE Select
7:6
5
Reserved
IDLE auto
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
1
Reserved
Set bits to 0.
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: Gbps
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Table 7. SMBus Register Map (continued)
0x41
CH7 - CHA3
EQ Control
7:6
5:0
Reserved
R/W
0x20
Set bits to 0.
CH7 IA3 EQ
IA3 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ0 EQ1] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x42
0x43
CH7 - CHA3
VOD Control
7
Reserved
R/W
R/W
0x03
0x03
Set bit to 0.
6:0
CH7 OA3 VOD
OA3 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
CH7 - CHA3
DE Control
7:0
CH7 OA3 DEM
OA3 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x44
CH7 - CHA3
IDLE Threshold
7:4
3:0
Reserved
R/W
0x00
Set bits to 0.
IDLE threshold
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
26
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SNLS292J –JUNE 2009–REVISED APRIL 2013
APPLICATION INFORMATION
GENERAL RECOMMENDATIONS
The DS50PCI401 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and the latest version of the LVDS Owner's Manual for more detailed information on
high speed design tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 100Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for
the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used
sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias
are used the layout must also provide for a low inductance path for the return currents as well. Route the
differential signals away from other signals and noise sources on the printed circuit board. See AN-1187
(SNOA401) for additional information on WQFN packages.
20 mils
EXTERNAL MICROSTRIP
100 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
1
2
12
10
8
6
5
4
3
18
16
14 13
15
11
9
7
17
54
53
52
19
20
21
22
23
24
25
26
27
51
50
49
BOTTOM OF PKG
GND
48
47
46
VDD
44
29
32
36 37
39 40 41 42
38
43
45
28
30 31
33 34
35
VDD
VDD
Figure 8. Typical Routing Options
The graphic shown above depicts different transmission line topologies which can be used in various
combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be
minimized or eliminated by increasing the swell around each hole and providing for a low inductance return
current path. When the via structure is associated with thick backplane PCB, further optimization such as back
drilling is often used to reduce the deterimential high frequency effects of stubs on the signal path.
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POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS50PCI401 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01 μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS50PCI401. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
Typical Performance Eye Diagrams and Curves
DS50PCI401 Return Loss
0
-RL
(S11)
RX-CM
-5
-10
-15
-20
-25
-30
-35
-40
-RL
(SDD11)
RX-DIFF
S11
SDD11
0.50
0.00
1.00
1.50
2.00
2.50
Frequency (GHz)
Figure 9. Receiver Return Loss Mask for 5.0 Gbps
0
-5
-RL
-RL
(S11)
TX-CM
-10
-15
-20
-25
-30
-35
-40
(SDD11)
TX-DIFF
S11
SDD11
0.50
0.00
1.00
1.50
2.00
2.50
Frequency (GHz)
Figure 10. Transmitter Return Loss Mask for 5.0 Gbps
28
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SNLS292J –JUNE 2009–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision I (April 2013) to Revision J
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 28
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS50PCI401SQ/NOPB
DS50PCI401SQE/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
NJY
NJY
54
54
2000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-10 to 85
-10 to 85
DS50PCI401SQ
DS50PCI401SQ
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS50PCI401SQ/NOPB
WQFN
NJY
NJY
54
54
2000
250
330.0
178.0
16.4
16.4
5.8
5.8
10.3
10.3
1.0
1.0
12.0
12.0
16.0
16.0
Q1
Q1
DS50PCI401SQE/NOPB WQFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS50PCI401SQ/NOPB
DS50PCI401SQE/NOPB
WQFN
WQFN
NJY
NJY
54
54
2000
250
356.0
208.0
356.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
3.51±0.1
(0.1)
SEE TERMINAL
DETAIL
19
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
46
0.3
54X
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
54X
0.1
C A
C
B
0.05
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54X (0.25)
SEE DETAILS
54
46
1
45
50X (0.5)
(7.5)
(9.8)
SYMM
(1.17)
TYP
2X
(1.16)
28
18
(
0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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