DS80EP100SDX [TI]
IC,CABLE EQUALIZER,LLCC,6PIN,PLASTIC;
| 型号： | DS80EP100SDX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,CABLE EQUALIZER,LLCC,6PIN,PLASTIC 光电二极管 |
| 文件： | 总15页 (文件大小：4139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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May 20, 2008
DS80EP100
5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and
Cables
General Description
Features
National’s Power-saver equalizer compensates for transmis-
sion medium losses and minimizes medium-induced deter-
ministic jitter. Performance is guaranteed over the full range
of 5 to 12.5 Gbps. The DS80EP100 requires no power to op-
erate. The equalizer operates anywhere in the data path to
minimize media-induced deterministic jitter in both FR4 traces
and cable applications. Symmetric I/O structures support full
duplex or half duplex applications. Linear compensation is
provided independent of line coding or protocol. The device
is ideal for both bi-level and multi-level signaling.
5 to 12.5 Gbps Operation
■
■
■
■
No Power or Ground Required
Equalization effective anywhere in data path
Equalizes CML, LV-PECL, LVDS signals
Symmetric I/O structures provide equal boost for bi-
directional operation
■
7 dB Maximum Boost
■
■
■
■
■
■
■
■
Code independent, 8b/10b or Scrambled
Supports both bi-level and multi-level signaling
The equalizer is available in a 6 pin leadless LLP package
with a space saving 2.2 mm X 2.5 mm footprint. This tiny
package provides maximum flexibility in placement and rout-
ing of the Power-saver equalizer.
Extends reach over backplanes and cables
Compatible with PCI-Express Gen1 and Gen2
Compatible with XAUI
Will operate in series with existing active Equalizer
Easy to handle 6 pin LLP
Simplified Application Diagram
30029401
Note:
The DS80EP100 provides the flexibility of passing the data from either side of the device. It can be placed anywhere in the data path.
© 2008 National Semiconductor Corporation
300294
www.national.com
Pin Descriptions
Pin Name
Pin Number
I/O Type
Description
High speed differential I/O
IOA-
IOA+
3
1
I/O
I/O
N/A
Symmetric
differential I/O
IOB-
IOB+
4
6
Symmetric
differential I/O
NC
2, 5
Reserved.
Exposed
Pad
DAP
Do not connect.
Note:
I = Input / O = Output
Connection Diagram
30029405
Bottom View Shown
2.2mm x 2.5mm 6-Pin LLP Package
Order Number DS80EP100
See NS Package Number SDA14A
www.national.com
2
Lead Temperature
Soldering, 4 sec
ESD Rating
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+260°C
1.3kV
HBM, 1.5 kΩ, 100 pF
INPUT/OUTPUT
Recommended Operating
Conditions
(IOA+ and IOB+) or (IOA- and IOB-)
(IOA+ and IOA-) or (IOB+ and IOB-)
(IOA+ and IOB-) or (IOA- and IOB+)
Junction Temperature
+2V
+4V
+4V
Min Typ Max Units
+150°C
−65°C to +150°C
Ambient Temperature
Bit Rate
−40 25
5
+85
°C
Storage Temperature
12.5 Gbps
Electrical Characteristics (Note 6) Over recommended operating conditions unless other specified. All
parameters are guaranteed by test, statistical analysis or design.
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 2)
1000
6
VIN
(Note 3)
mVp-p
dB
Input voltage swing
Equalization
3600
6.25 GHz relative to 100MHz
Differential input return
loss
100 MHz – 6.25 GHz, with fixture's effect de-
embedded
RLI
RLO
RIN
RO
15
15
dB
dB
Differential output return 100 MHz – 6.25 GHz, with fixture's effect de-
loss
embedded IOA+, or IOB+ = static high.
Differential across IOA+ and IOA-, or IOB+ and
IOB-, ZLOAD = 100Ω
Differential across IOA+ and IOA-, or IOB+ and
IOB-, ZSOURCE = 100Ω
100
Ω
Ω
Input Impedance
Output Impedance
Through Response
100
Relative to ideal load, see Figure 2 for setup
See Figure 3 and Table 1 for limits
Resistance IOA+ to IOA-
and IOB+ to IOB-
R1
R2
R3
150
Ω
Ω
Ω
No load, high impedance on all ports
Resistance IOA+ to IOB+
and IOA- to IOB-
50
150
0.4
No load, high impedance on all ports
No load, high impedance on all ports
Resistance IOA+ to IOB-
and IOA- to IOB+
DC Gain
ZLOAD = 100Ω
(IOA/IOB or IOB/IOA)
5 Gbps, 20 in of 6mil microstrip FR4
See (Note 4)
Residual deterministic
jitter
DJ1
DJ2
0.15
UIp-p
UIp-p
6.25 Gbps, 20 in of 6mil microstrip FR4
See (Notes 4, 5)
Residual deterministic
jitter
0.15
0.20
0.20
8 Gbps, 20 in of 6mil microstrip FR4
See (Notes 4, 5)
Residual deterministic
jitter
DJ3
DJ4
DJ5
0.15
0.15
0.15
UIp-p
UIp-p
UIp-p
Residual deterministic
jitter
10 Gbps, 20 in of 6mil microstrip FR4
See (Note 4)
Residual deterministic
jitter
12.5 Gbps, 14 in of 6mil microstrip FR4
See (Note 4)
3
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Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: Typical values represent most likely parametric norms, TA = +25 degC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: Differential signal to Equalizer, measured at the input to a transmission line, see point A of Figure 1. The transmission line is Z0 = 100Ω, 6-mil, microstrip
in FR4 material.
Note 4: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Test pattern: PRBS- 7 .
Note 5: Specification is guaranteed by characterization and is not tested in production.
Note 6: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
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4
Test Setup Diagrams
30029403
FIGURE 1. Transient Test Setup Diagram
30029404
FIGURE 2. Frequency Response Test Circuit
Typical Equalizer Transfer Function
30029406
FIGURE 3. Typical Equalizer Transfer Function
5
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Table 1. Typical Through Response
Frequency (GHz)
DS80EP100 Attenuation Typ
(dB)
0.1
0.5
1
-8.25
-7.64
-6.12
-4.68
-3.57
-2.22
-1.66
-1.53
-1.77
-2.28
-2.8
1.5
2
3
4
5
6
7
8
9
-3.47
-3.91
10
Block Diagram
30029402
FIGURE 4. Simplified Block Diagram
path and will provide the same compensation at the receiving
circuit. (See Simplified Application Diagram)
Application Information
DS80EP100 DEVICE DESCRIPTION
SYMMETRIC I/O STRUCTURES
The DS80EP100 Power-Saver equalizer is a passive network
circuit composed of resistive, capacitive, and inductive com-
ponents (See Figure 4). A Differential bridged T-network com-
pensates for the transmission medium losses and minimizes
medium-induced deterministic jitter with FR4 and cables. The
equalizer attenuates low frequency signals and is a bandpass
filter at the resonant frequency. The response is linear and
symmetric.
The symmetry of the passive equalization network allows bi-
directional operation. Signals receive equal compensation
regardless of the direction of data flow. (See Simplified Block
Diagram).
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS AND NO CONNECT PADS
The differential I/Os must have a controlled differential
impedance of 100Ω. It is preferable to route all differential
lines exclusively on one layer of the board. The use of vias
should be avoided if possible. If vias must be used, they
should be used sparingly and must be placed symmetrically
for each side of a given differential pair. Differential signals
should be routed away from other signals and noise sources
on the printed circuit board. Pin 2, Pin 5, and the center DAP
have to be left as no connect. Therefore, do not connect the
landing pads of these pins to the power or ground plane. See
AN-1187 for additional information on the LLP package.
I/O TERMINATIONS
The DS80EP100 I/O impedance is 100Ω differential. The
equalizer is designed for 100Ω-balanced differential signals
and is not intended for single-ended transmission.
LINEAR COMPENSATION
The unique linear compensation feature of the DS80EP100
combined with the tiny package allows maximum flexibility in
placement. The equalizer can be placed anywhere in the data
www.national.com
6
Typical Performance Characteristics
30029407
30029408
Residual Deterministic Jitter vs. FR4 Length
Residual Deterministic Jitter vs. FR4 Length
30029409
30029410
Eye Height vs. FR4 Length
Eye Height vs. FR4 Length
7
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Typical Eye Diagrams — Includes Transmitter Setup, Interconnect, and
Device Total Jitter
30029411
30029414
FIGURE 5. Unequalized Signal (20in FR4, 5Gbps, PRBS7)
FIGURE 8. Unequalized Signal (20in FR4, 6.25Gbps,
PRBS7)
30029412
30029415
FIGURE 6. Equalized Signal (20in FR4, 5Gbps, PRBS7)
FIGURE 9. Equalized Signal (20in FR4, 6.25Gbps, PRBS7)
30029413
30029416
FIGURE 7. Equalized Signal (Zoom) (20in FR4, 5Gbps,
PRBS7)
FIGURE 10. Equalized Signal (Zoom) (20in FR4,
6.26Gbps, PRBS7)
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8
30029417
30029420
FIGURE 11. Unequalized Signal (20in FR4, 8Gbps,
PRBS7)
FIGURE 14. Unequalized Signal (20in FR4, 10Gbps,
PRBS7)
30029418
30029421
FIGURE 12. Equalized Signal (20in FR4, 8Gbps, PRBS7)
FIGURE 15. Equalized Signal (20in FR4, 10Gbps, PRBS7)
30029419
30029422
FIGURE 13. Equalized Signal (Zoom) (20in FR4, 8Gbps,
PRBS7)
FIGURE 16. Equalized Signal (Zoom) (20in FR4, 10Gbps,
PRBS7)
9
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30029423
30029426
FIGURE 17. Unequalized Signal (14in FR4, 12.5Gbps,
PRBS7)
FIGURE 20. Unequalized Signal (5m 26AWG Twin-AX
Cable, 5Gbps, PRBS7)
30029424
30029427
FIGURE 18. Equalized Signal (14in FR4, 12.5Gbps,
PRBS7)
FIGURE 21. Equalized Signal (5m 26AWG Twin-AX Cable,
5Gbps, PRBS7)
30029425
30029428
FIGURE 19. Equalized Signal (Zoom) (14in FR4,
12.5Gbps, PRBS7)
FIGURE 22. Equalized Signal (Zoom) (5m 26AWG Twin-
AX Cable, 5Gbps, PRBS7)
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10
30029429
30029432
FIGURE 23. Unequalized Signal (5m 26AWG Twin-AX
Cable, 8Gbps, PRBS7)
FIGURE 26. Unequalized Signal (5m 26AWG Twin-AX
Cable, 10Gbps, PRBS7)
30029430
30029433
FIGURE 24. Equalized Signal (5m 26AWG Twin-AX Cable,
8Gbps, PRBS7)
FIGURE 27. Equalized Signal (5m 26AWG Twin-AX Cable,
10Gbps, PRBS7)
30029431
30029434
FIGURE 25. Equalized Signal (Zoom) (5m 26AWG Twin-
AX Cable, 8Gbps, PRBS7)
FIGURE 28. Equalized Signal (Zoom) (5m 26AWG Twin-
AX Cable, 10Gbps, PRBS7)
11
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS80EP100
See NS Package SDB06A
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12
Notes
13
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Notes
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