DS80PCI402SQE [TI]
2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis; 2.5 Gbps的/ 5.0 Gbps的/ 8.0 Gbps的4通道PCI Express中继器,具有均衡和去加重型号: | DS80PCI402SQE |
厂家: | TEXAS INSTRUMENTS |
描述: | 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis |
文件: | 总39页 (文件大小:1681K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
March 22, 2012
DS80PCI402
2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express
Repeater with Equalization and De-Emphasis
With a low power consumption and control to turn-off unused
channels, the DS80PCI402 is part of PowerWise family of
energy efficient devices.
General Description
The DS80PCI402 is a low power, 4 lane repeater with 4-stage
input equalization, and output de-emphasis driver to enhance
the reach of PCI express serial links in board-to-board or ca-
ble interconnects. Ideal for x4 (or lower) PCI express config-
uration, the DS80PCI402 automatically detects and adapts to
Gen-1, Gen-2 and Gen-3 data rates for easy system upgrade.
Features
Comprehensive family, proven system inter-operability
■
DS80PCI102 : x1 PCIe Gen-1/2/3
DS80PCI402 : x4 PCIe Gen-1/2/3
DS80PCI800 : x8/x16 PCIe Gen-1/2/3
Each channel supports seamless detection and management
of the new Gen-3 transmit equalizer coefficients (FIR tap)
handshake protocol and PCIe control signals such as transmit
idle, beacon etc. without external system intervention. An au-
tomatic receive detection circuitry controls the input termina-
tion impedance based upon endpoint insertion (hot-plug
events). These features guarantee PCIe interoperability at
both the electrical and system level, while reducing design
complexity.
Automatic rate detect and adaptation to Gen-1/2/3 speeds
■
■
■
Seamless support for Gen-3 transmit FIR handshake
Rate adaptive receive EQ (up to 36 dB), transmit
deemphasis (up to 12 dB) only Gen-1/2
Adjustable Transmit VOD: 0.8 to 1.3 Vp-p (pin mode)
■
■
0.2 UI of residual deterministic jitter at 8 Gbps after 40” of
FR4 or 10m 30awg PCIe Cable
Powered by National’s SiGe BiCMOS process, DS80PCI402
offers programmable transmit de-emphasis (up to 12 dB),
transmit VoD (up to 1300 mVp-p) and receive equalization (up
to 36 dB) to enable longer distance transmission in lossy cop-
per cables (10m+), or backplanes (40”+) with multiple con-
nectors. The receiver is capable of opening an input eye that
is completely closed due to inter-symbol interference (ISI) in-
troduced by the interconnect medium.
Low power dissipation with ability to turnoff unused
channels: 65 mW/channel
Automatic receiver detect (hot-plug)
■
■
■
Multiple configuration modes: Pins/SMbus/Direct-
EEPROM load
Flow-thru pinout: 54-pin LLP (10 mm x 5.5 mm, 0.5 mm
pitch)
■
Single supply voltage: 2.5V or 3.3V (selectable)
■
■
■
The programmable settings can be applied easily via pins,
software (SMBus/I2C) or loaded via an external EEPROM.
When operating in the EEPROM mode, the configuration in-
formation is automatically loaded on power up, which elimi-
nates the need for an external microprocessor or software
driver.
5 kV HBM ESD rating
−40 to 85°C operating temperature range
Typical Application
30119880
© 2012 Texas Instruments Incorporated
301198 SNLS324C
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Block Diagram - Detail View Of
Channel (1 Of 8)
30119886
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2
Pin Diagram
30119892
DS80PCI402 Pin Diagram 54 lead
Ordering Information
NSID
Qty
Spec
Package
SQA54A
SQA54A
DS80PCI402SQ
DS80PCI402SQE
Tape & Reel Supplied As 2,000 Units
Tape & Reel Supplied As 250 Units
NOPB
NOPB
3
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Pin Descriptions
Pin Name
Pin Number I/O, Type
Pin Description
Differential High Speed I/O's
INB_0+, INB_0- ,
INB_1+, INB_1-,
INB_2+, INB_2-,
INB_3+, INB_3-
45, 44, 43, 42
40, 39, 38, 37
I
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INB_n+ to VDD and INB_n- to VDD when enabled.
OUTB_0+, OUTB_0-, 1, 2, 3, 4
OUTB_1+, OUTB_1-, 5, 6, 7, 8
OUTB_2+, OUTB_2-,
O
I
Inverting and non-inverting 50Ω driver outputs with de-
emphasis. Compatible with AC coupled CML inputs.
OUTB_3+, OUTB_3-
INA_0+, INA_0- ,
INA_1+, INA_1-,
INA_2+, INA_2-,
INA_3+, INA_3-
10, 11, 12, 13
15, 16, 17, 18
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INA_n+ to VDD and INA_n- to VDD when enabled.
OUTA_0+, OUTA_0-, 35, 34, 33, 32
OUTA_1+, OUTA_1-, 31, 30, 29, 28
OUTA_2+, OUTA_2-,
O
Inverting and non-inverting 50Ω driver outputs with de-
emphasis. Compatible with AC coupled CML inputs.
OUTA_3+, OUTA_3-
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS, ENSMB Master or Slave mode
O, OPEN
Drain
SMBUS clock input pin is enabled (slave mode).
Clock output when loading EEPROM configuration (master
mode).
SDA
49
I, LVCMOS, ENSMB Master or Slave mode
O, OPEN
Drain
The SMBus bi-directional SDA pin is enabled. Data input or
open drain (pull-down only) output.
AD0-AD3
READ_EN
54, 53, 47, 46 I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are
the user set SMBus slave address inputs.
26
I, LVCMOS
When using an External EEPROM, a transition from high to
low starts the load from the external EEPROM
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization of the
A/B sides as shown in . The pins are active only when ENSMB
is de-asserted (low). Each of the 4 A/B channels have the
same level unless controlled by the SMBus control registers.
When ENSMB goes high the SMBus registers provide
independent control of each lane. The EQB[1:0] pins are
converted to SMBUS AD2, AD3 inputs. See Table 2:
Equalizer Settings.
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4
Pin Name
Pin Number I/O, Type
Pin Description
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis
of the A/B sides as shown in . The pins are only active when
ENSMB is de-asserted (low). Each of the 4 A/B channels have
the same level unless controlled by the SMBus control
registers. When ENSMB goes high the SMBus registers
provide independent control of each lane. The DEMA[1:0]
pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins
are converted to AD0, AD1 inputs. See Table 3: Output
Voltage and De-emphasis Settings.
RATE
21
26
I, 4-LEVEL,
LVCMOS
RATE control pin selects GEN 1,2 and GEN 3 operating
modes.
Tie 1kΩ to GND = GEN 1,2
Float = Auto Rate select
Tie 20kΩ to GND = GEN 3 without De-emphasis
Tie 1kΩ to VDD = GEN 3 with De-emphasis
Controls the internal Signal Detect Threshold.
SD_TH
I, 4-LEVEL,
LVCMOS
See Table 5: Signal Detect Threshold Level.
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
The RXDET pin controls the receiver detect function.
Depending on the input level, a 50Ω or >50KΩ termination to
the power rail is enabled.
See Table 4: RX-Detect Settings.
LPBK
23
I, 4-LEVEL,
LVCMOS
Controls the loopback function
Tie 1kΩ to GND = Root Complex Loopback (INA_n to
OUTB_n
Float = Normal Operation
Tie 1kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
Controls the internal regulator
VDD_SEL
PRSNT
25
52
I, FLOAT
Float = 2.5V mode
Tie GND = 3.3V mode
I, LVCMOS
Cable Present Detect input. high when a cable is not present
per PCIe Cabling Spec. 1.0. Puts part into low power mode.
When low (normal operation) part is enabled. See Table 4:
RX-Detect Settings.
Outputs
ALL_DONE
27
24
O, LVCMOS Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
Power
VIN
Power
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating.
VDD
9, 14,36, 41,
51
Power supply pins CML/analog
2.5V mode, connect to 2.5V
3.3V mode, connect 0.1 uF cap to each VDD pin
GND
DAP
Power
Ground pad (DAP - die attach pad).
Notes:
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not
guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
5
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ESD Rating
Absolute Maximum Ratings (Note 1)
HBM, STD - JESD22-A114F
MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-D
Thermal Resistance
θJC
θJA, No Airflow, 4 layer JEDEC
For soldering specifications: see product folder at
www.national.com/ms/MS/MS-SOLDERING.pdf
5 kV
150 V
1000 V
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD - 2.5V)
Supply Voltage (VIN - 3.3V)
LVCMOS Input/Output Voltage
CML Input Voltage
CML Input Current
Junction Temperature
Storage Temperature
-0.5V to +2.75V
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5)
-30 to +30 mA
125°C
11.5°C/W
19.1°C/W
Min
Typ Max Units
Supply Voltage (2.5V mode) 2.375 2.5 2.625
Supply Voltgae (3.3V mode) 3.0
Ambient Temperature
SMBus (SDA, SCL)
V
V
-40°C to +125°C
+260°C
3.3 3.6
25 +85
3.6
Lead Temperature Range Soldering
(4 sec.)
-40
°C
SQA54A Package
V
Derate SQA54A Package
52.6mW/°C above
+25°C
Supply Noise up to 50 MHz
(Note 4)
100
mVp-p
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Power
PD
Power Dissipation
VDD = 2.5 V supply,
EQ Enabled,
500
700
mW
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0
VIN = 3.3 V supply,
EQ Enabled,
660
900
mW
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0
LVCMOS / LVTTL DC Specifications
Vih
High Level Input
Voltage
2.0
3.6
0.8
V
Vil
Low Level Input Voltage
0
V
V
Voh
High Level Output
Voltage
(ALL_DONE pin)
Ioh = −4mA
Iol = 4mA
2.0
Vol
Low Level Output
Voltage
0.4
V
(ALL_DONE pin)
Iih
Input High Current
(PRSNT pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
-15
+15
uA
uA
Input High Current
with internal resistors
(4–level input pin)
+20
+150
Iil
Input Low Current
(PRSNT pin)
VIN = 3.6 V,
LVCMOS = 0 V
-15
+15
-40
uA
uA
Input Low Current
with internal resistors
(4–level input pin)
-160
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6
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CML Receiver Inputs (IN_n+, IN_n-)
RLrx-diff
RX Differential return
loss
0.05 - 1.25 GHz
1.2 - 2.5 GHz
2.5 - 4.0 GHz
0.05 - 2.5 GHz
2.5 - 4.0 GHz
-16
-16
-14
-12
-8
dB
dB
dB
dB
dB
Ω
RLrx-cm
RX Common mode
return loss
Zrx-dc
RX DC common mode Tested at VDD = 2.5 V
impedance
40
80
50
60
120
1.2
Zrx-diff-dc
Vrx-diff-dc
RX DC differntial mode Tested at VDD = 2.5 V
impedance
100
1.0
50
Ω
Differential RX peak to Tested at pins
peak voltage (VID)
0.6
V
Zrx-high-imp-
dc-pos
DC Input common
mode impedance for
V>0
VID = 0 to 200mV,
ENSMB = 0, RXDET = 0,
VDD = 2.5 V
KΩ
Vrx-signal-det- Signal detect assert
SD_TH = F (float),
0101 pattern at 8 Gbps
180
110
mVp-p
mVp-p
diff-pp
level for active data
signal
Vrx-idle-det-
diff-pp
Signal detect de-assert SD_TH = F (float),
level for electrical idle 0101 pattern at 8 Gbps
7
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
High Speed Outputs
Vtx-diff-pp
Output Voltage
Differential Swing
Differential measurement
with Out_n+ and OUT_n-,
terminated by 50Ω to GND,
AC-Coupled, VID = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0
(Note 7)
0.8
1.0
1.2
mVp-p
Vtx-de-ratio_3.5
TX de-emphasis ratio VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R,
Gen 1 & 2 modes only
TX de-emphasis ratio VOD = 1.0 Vp-p,
−3.5
−6
dB
dB
Vtx-de-ratio_6
DEM0 = R, DEM1 = R,
Gen 1 & 2 modes only
TTX-HF-DJ-DD
TTX-HF-DJ-DD
TTX-RISE-FALL
TX Dj > 1.5 MHz
0.15
3.0
UI
ps RMS
ps
TX RMS jitter < 1.5 MHz
Transmitter rise/fall
time
20% to 80% of differential
output voltage
35
45
TRF-MISMATCH
RLTX-DIFF
Transmitter rise/fall
mismatch
20% to 80% of differential
output voltage
0.01
0.1
UI
TX Differential return
loss
0.05 - 1.25 GHz
1.25 - 2.5 GHz
2.5 - 4 GHz
-16
-12
-11
-12
-8
dB
dB
dB
dB
dB
Ω
RLTX-CM
TX Common mode
return loss
0.05 - 2.5 GHz
2.5 - 4 GHz
ZTX-DIFF-DC
VTX-CM-AC-PP
ITX-SHORT
DC differential TX
impedance
100
TX AC common mode VOD = 1.0 Vp-p,
voltage DEM0 = 1, DEM1 = 0
Transmitter short circuit Total current the transmitter
100
mVp-p
mA
20
current limit
can supply when shorted to
VDD or GND
VTX-CM-DC-
Absolute delta of DC
common mode voltage
during L0 and electrical
idle
100
25
mV
ACTIVE-IDLE-DELTA
VTX-CM-DC-LINE- Absolute delta of DC
mV
ns
common mode voltgae
between TX+ and TX-
DELTA
TTX-IDLE-DATA
TTX-DATA-IDLE
TPDEQ
Max time to transition to VID = 1.0 Vp-p, 8 Gbps
valid differential signal
after idle
3.5
6.2
Max time to transition to VID = 1.0 Vp-p, 8 Gbps
idle after differential
signal
ns
Differential propagation EQ = 00, (Note 6)
200
ps
delay
TLSK
Lane to lane skew
T = 25C, VDD = 2.5V
25
40
ps
ps
TPPSK
Part to part propagation T = 25C, VDD = 2.5V
delay skew
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8
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Equalization
DJE1
Residual deterministic 35” 4mils FR4,
0.14
UI
jitter at 8 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
DJE2
DJE3
DJE4
DJE5
DJE6
Residual deterministic 35” 4mils FR4,
0.1
0.05
0.16
0.1
UI
UI
UI
UI
UI
jitter at 5 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
Residual deterministic 35” 4mils FR4,
jitter at 2.5 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
Residual deterministic 10 meters 30 awg cable,
jitter at 8 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
Residual deterministic 10 meters 30 awg cable,
jitter at 5 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
Residual deterministic 10 meters 30 awg cable,
0.05
jitter at 2.5 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
De-emphasis (Gen 1&2 mode only)
DJD1
Residual deterministic 10” 4mils FR4,
jitter at 2.5 Gbps AND VID = 0.8 Vp-p,
0.1
0.1
UI
UI
5.0 Gbps
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = −3.5 dB,
DJD2
Residual deterministic 20” 4mils FR4,
jitter at 2.5 Gbps AND VID = 0.8 Vp-p,
5.0 Gbps
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = −9 dB,
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mVp-p sine wave) under typical conditions.
Note 5: Guaranteed by device characterization.
Note 6: Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation delays.
Note 7: In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by
DEMA/B[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS80PCI800 repeater in GEN3 mode is designed to be transparent,
so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake negotiation link training.
9
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Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
0.8
3.6
V
V
VIH
2.1
4
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
mA
VDD
Nominal Bus Voltage
2.375
-200
3.6
V
ILEAK-Bus
ILEAK-Pin
CI
Input Leakage Per Bus Segment (Note 8)
Input Leakage Per Device Pin
+200
µA
µA
pF
-15
Capacitance for SDA and SCL
(Note 8, Note 9)
10
RTERM
External Termination Resistance Pullup VDD = 3.3V,
2000
1000
Ω
Ω
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
(Note 8, Note 9, Note 10)
Pullup VDD = 2.5V,
(Note 8, Note 9, Note 10)
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
400
520
kHz
kHz
ENSMB = FLOAT (Master Mode)
280
1.3
400
TBUF
Bus Free Time Between Stop and
Start Condition
µs
µs
µs
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
At IPULLUP, Max
0.6
0.6
TSU:STA
Repeated Start Condition Setup
Time
TSU:STO
THD:DAT
TSU:DAT
TLOW
Stop Condition Setup Time
Data Hold Time
0.6
0
µs
ns
ns
µs
µs
ns
ns
Data Setup Time
100
1.3
0.6
Clock Low Period
THIGH
tF
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
(Note 11)
50
(Note 11)
300
300
tR
(Note 11)
tPOR
Time in which a device must be
operational after power-on reset
(Note 11, Note 12)
500
ms
Note 8: Recommended value.
Note 9: Recommended maximum capacitance load per bus segment is 400pF.
Note 10: Maximum termination voltage should be identical to the device supply voltage.
Note 11: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
Note 12: Guaranteed by Design. Parameter not tested in production.
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10
Timing Diagrams
30119802
FIGURE 1. CML Output and Rise and FALL Transition Time
30119803
FIGURE 2. Propagation Delay Timing Diagram
30119804
FIGURE 3. Transmit IDLE-DATA and DATA-IDLE Response Time
30119894
FIGURE 4. SMBus Timing Parameters
11
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ization settings can be accessed via the SMBus registers.
Each input has a total of 256 possible equalization settings.
The tables show the 16 setting when the device is in pin mode.
When using SMBus mode, the equalization, VOD and de-
Emphasis levels are set by registers.
Functional Descriptions
The DS80PCI402 is a low power media compensation 4 lane
repeater optimized for PCI Express Gen 1/2 and 3. The
DS80PCI402 compensates for lossy FR-4 printed circuit
board backplanes and balanced cables. The DS80PCI402
operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus
Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB
= float) to load register informations from external EEPROM;
please refer to SMBUS Master Mode for additional informa-
tion.
The input control pins have been enhanced to have 4 different
levels and provide a wider range of control settings when EN-
SMB=0.
Table 1: 4–Level Control Pin
Settings
Pin Control Mode:
Pin Setting Description
Voltage at Pin
0.03 x VDD
1/3 x VDD
When in pin mode (ENSMB = 0), equalization and de-em-
phasis can be selected via pin for each side independently.
When de-emphasis is asserted VOD is automatically adjust-
ed per the De- Emphasis table below. The RXDET pins
provides automatic and manual control for input termination
(50Ω or >50KΩ). RATE setting is also pin controllable with pin
selections (Gen 1/2, auto detect and Gen 3). The receiver
electrical idle detect threshold is also adjustable via the
SD_TH pin.
0
Tie 1kΩ to GND
Tie 20kΩ to GND
R
Float
1
Float (leave pin open) 2/3 x VDD
0.98 x VDD
Tie 1kΩ to VDD
Note: The above required resistor value is for a single
device. When there are multiple devices connected to the
pull-up / pull-down resistor, the value must scale with the
number of devices. If 4 devices are connected to a single
pull-up or pull-down, the 1kΩ resistor value should be
250Ω. For the 20kΩ to GND, this should also scale to 5kΩ.
SMBUS Mode:
When in SMBus mode (ENSMB = 1), the VOD (output ampli-
tude), equalization, de-emphasis, and termination disable
features are all programmable on a individual lane basis, in-
stead of grouped by A or B as in the pin mode case. Upon
assertion of ENSMB, the EQx and DEMx functions revert to
register control immediately. The EQx and DEMx pins are
converted to AD0-AD3 SMBus address inputs. The other ex-
ternal control pins (RATE, RXDET and SD_TH) remain active
unless their respective registers are written to and the appro-
priate override bit is set, in which case they are ignored until
ENSMB is driven low (pin mode). On power-up and when
ENSMB is driven low all registers are reset to their default
state. If PRSNT is asserted while ENSMB is high, the regis-
ters retain their current state.
3.3V or 2.5V Supply Mode Operation
The DS80PCI402 has an optional internal voltage regulator
to provide the 2.5V supply to the device. In 3.3V mode oper-
ation, the VIN pin = 3.3V is used to supply power to the device.
The internal regulator will provide the 2.5V to the VDD pins of
the device and a 0.1 uF cap is needed at each of the 5 VDD
pins for power supply de-coupling (total capacitance should
be ≤0.5 uF), and the VDD pins should be left open. The
VDD_SEL pin must be tied to GND to enable the internal reg-
ulator. In 2.5V mode operation, the VIN pin should be left open
and 2.5V supply must be applied to the 5 VDD pins to power
the device. The VDD_SEL pin must be left open (no connect)
to disable the internal regulator.
Equalization settings accessible via the pin controls were
chosen to meet the needs of most PCIe applications. If addi-
tional fine tuning or adjustment is needed, additional equal-
30119806
FIGURE 5. 3.3V or 2.5V Supply Connection Diagram
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12
•
•
De-Emphasis: use the guidelines outlined in table 3.
VOD: use the guidelines outlined in table 3.
System Information
When using the DS80PCI402 in CPU systems, there are spe-
cific signal integrity settings to ensure signal integrity margin.
The settings were achieved with completing extensive test-
ing. Please contact your field representative for more infor-
mation regarding the testing completed to achieve these
settings.
For tuning in the upstream direction (from EP to CPU).
•
•
EQ: use the guidelines outlined in table 2.
De-Emphasis:
For trace lengths < 15” set to -3.5 dB
For trace lengths > 15” set to -6 dB
—
—
For tuning the in the downstream direction (from CPU to EP).
•
VOD: set to 900 mV
•
EQ: use the guidelines outlined in table 2.
Table 2: Equalizer Settings
Level EQA1 EQA0
EQB1 EQB0
EQ – 8 bits [7:0]
dB at
1.25 GHz 2.5 GHz
dB at
dB at
4 GHz
Suggested Use
1
2
0
0
0000 0000 = 0x00
0000 0001 = 0x01
0000 0010 = 0x02
0000 0011 = 0x03
0000 0111 = 0x07
0001 0101 = 0x15
0000 1011 = 0x0B
0000 1111 = 0x0F
0101 0101 = 0x55
0001 1111 = 0x1F
0010 1111 = 0x2F
0011 1111 = 0x3F
1010 1010 = 0xAA
0111 1111 = 0x7F
1011 1111 = 0xBF
1111 1111 = 0xFF
2.1
3.4
3.7
5.8
4.9
FR4 < 5 inch trace
FR4 5 inch 5–mil trace
FR4 5 inch 4–mil trace
FR4 10 inch 5–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 20 inch 4–mil trace
FR4 25 to 30 inch 4–mil trace
FR4 30 inch 4–mil trace
FR4 35 inch 4–mil trace
10m, 30awg cable
0
0
R
7.9
3
Float
4.8
7.7
9.9
4
0
1
5.9
8.9
11.0
14.3
14.6
17.0
18.5
18.0
22.0
24.4
25.8
27.4
29.0
31.4
32.7
5
R
0
R
7.2
11.2
11.4
13.5
15.0
12.8
17.4
19.7
21.1
21.7
23.5
25.8
27.3
6
R
6.1
7
R
Float
1
8.8
8
R
10.2
7.5
9
Float
Float
Float
Float
1
0
10
11
12
13
14
15
16
R
11.4
13.0
14.2
13.8
15.6
17.2
18.4
Float
1
10m – 12m cable
0
1
R
1
Float
1
1
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Table 3: Output Voltage and De-emphasis Settings
Level
DEMA1
DEMB1
DEMA0
DEMB0
VOD Vp-p
DEM dB
(see note below)
Inner Amplitude
Vp-p
Suggested Use
1
2
0
0
0.8
0.9
0.9
1.0
1.0
1.0
1.1
1.1
1.1
1.2
1.2
1.2
1.3
1.3
1.3
1.3
0
0
0.8
0.9
0.6
1.0
0.7
0.5
1.1
0.7
0.6
1.2
0.8
0.6
1.3
0.9
0.7
0.5
FR4 <5 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 20 inch 4–mil trace
0
0
R
3
Float
- 3.5
0
4
0
1
5
R
0
R
- 3.5
- 6
0
6
R
7
R
Float
1
8
R
- 3.5
- 6
0
9
Float
Float
Float
Float
1
0
10
11
12
13
14
15
16
R
Float
1
- 3.5
- 6
0
0
1
R
- 3.5
- 6
- 9
1
Float
1
1
Note: The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are also available in GEN 3 mode when RATE = 1 (tied to VDD).
Table 4: RX-Detect Settings
PRSNT#
RXDET
SMBus REG Input Termination Termination sensed Comments
bit[3:2]
00
on output pins
X
0
0
0
High Impedance
Manual RX-Detect, input is high
impedance mode
01
High Impedance High Z until receiver Auto RX-Detect, outputs test every 12
Tie 20kΩ
to GND
is detected
msec for 600 msec then stops; termination
is high-z until detection; once detected
input termination is 50 Ω
50 Ω
Reset function by pulsing PRSNT# high for
5 usec then low again
0
Float
(Default)
10
11
High Impedance High Z until recevier Auto RX-Detect, outputs test every 12
is detected
msec until detection occurs; termination is
high-z until detection; once detected input
termination is 50 Ω
50 Ω
0
1
1
X
X
50 Ω
High Impedance
Manual RX-Detect, input is 50 Ω
Power down mode, input is high
X
impedance, output drivers are disabled
Used to reset RX-Detect State Machine
when held high for 5 usec
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14
Table 5: Signal Detect Threshold Level
SD_TH
SMBus REG bit [3:2] and [1:0]
Assert Level (typ)
210 mVp-p
De-assert Level (typ)
150 mVp-p
0
10
01
00
11
R
160 mVp-p
100 mVp-p
F (default)
1
180 mVp-p
110 mVp-p
190 mVp-p
130 mVp-p
Note: VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps
SMBUS Master Mode
The DS80PCI402 device supports reading directly from an external EEPROM device by implementing SMBus Master mode. When
using the SMBus master mode, the DS80PCI402 will read directly from specific location in the external EEPROM. When designing
a system for using the external EEPROM, the user needs to follow these specific guidelines.
•
•
•
Set ENSMB = Float — enable the SMBUS master mode.
The external EEPROM device address byte must be 0xA0'h and capable of 400 kHz operation at 2.5V and 3.3V supply.
Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
When tying multiple DS80PCI402 devices to the SDA and SCL bus, use these guidelines to configure the devices.
•
Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM. Example below is for 4
device.
U1: AD[3:0] = 0000 = 0xB0'h,
U2: AD[3:0] = 0001 = 0xB2'h,
U3: AD[3:0] = 0010 = 0xB4'h,
U4: AD[3:0] = 0011 = 0xB6'h
•
•
Use a pull-up resistor on SDA and SCL; value = 2k ohms
Daisy-chain READEN# (pin 26) and ALL_DONE# (pin 27) from one device to the next device in the sequence so that they do
not compete for the EEPROM at the same time.
1. Tie READEN# of the 1st device in the chain (U1) to GND
2. Tie ALL_DONE# of U1 to READEN# of U2
3. Tie ALL_DONE# of U2 to READEN# of U3
4. Tie ALL_DONE# of U3 to READEN# of U4
5. Optional: Tie ALL_DONE# output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS80PCI402 device. The first 3 bytes of the EEPROM
always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag
to enable/disable CRC checking. If CRC checking is disabled, a fixed pattern (8’hA5) is written/read instead of the CRC byte from
the CRC location, to simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration
data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS80PCI402
address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the
EEPROM. There are 37 bytes of data size for each DS80PCI402 device.
:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
15
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16
17
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18
39
40
41
42
43
44
45
46
47
27
28
29
2A
2B
2C
2D
2E
2F
0x56
0x00
0x00
0x15
0x60
0x00
0x00
0x54
0x54
VOD CHA2 = 1.0V
DEM CHA2 = 0 (0dB)
EQ CHA3 = 00
Table 7: Example of EEPROM for 4
Devices using 2 Address Maps
EEPROM Address EEPROM Comments
Address (Hex)
Data
VOD CHA3 = 1.0V
DEM CHA3 = 0 (0dB)
0
00
0x43
CRC_EN = 0, Address
Map = 1, >256 bytes = 0,
Device Count[3:0] = 3
1
2
3
4
01
02
03
04
0x00
0x08
0x00
0x0B
EEPROM Burst Size
CRC not used
End Device 0, 1 - Address
Offset 39
Device 0 Address
Location
48
30
0x00
Begin Device 2, 3 -
Address Offset 3
5
6
05
06
0x00
0x0B
CRC not used
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
0x00
0x04
0x07
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x01
0x80
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x00
0x54
0x54
Device 1 Address
Location
7
8
07
08
0x00
0x30
CRC not used
Device 2 Address
Location
EQ CHB0 = 00
VOD CHB0 = 1.0V
DEM CHB0 = 0 (0dB)
EQ CHB1 = 00
9
09
0A
0x00
0x30
CRC not used
10
Device 3 Address
Location
VOD CHB1 = 1.0V
DEM CHB1 = 0 (0dB)
11
0B
0x00
Begin Device 0, 1 -
Address Offset 3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
0x00
0x04
0x07
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x01
0x80
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x01
EQ CHB2 = 00
VOD CHB2 = 1.0V
DEM CHB2 = 0 (0dB)
EQ CHB3 = 00
EQ CHB0 = 00
VOD CHB3 = 1.0V
DEM CHB3 = 0 (0dB)
VOD CHB0 = 1.0V
DEM CHB0 = 0 (0dB)
EQ CHB1 = 00
VOD CHB1 = 1.0V
DEM CHB1 = 0 (0dB)
EQ CHA0 = 00
VOD CHA0 = 1.0V
DEM CHA0 = 0 (0dB)
EQ CHA1 = 00
EQ CHB2 = 00
VOD CHB2 = 1.0V
DEM CHB2 = 0 (0dB)
EQ CHB3 = 00
VOD CHA1 = 1.0V
DEM CHA1 = 0 (0dB)
VOD CHB3 = 1.0V
DEM CHB3 = 0 (0dB)
EQ CHA2 = 00
VOD CHA2 = 1.0V
DEM CHA2 = 0 (0dB)
EQ CHA3 = 00
EQ CHA0 = 00
VOD CHA3 = 1.0V
DEM CHA3 = 0 (0dB)
VOD CHA0 = 1.0V
DEM CHA0 = 0 (0dB)
EQ CHA1 = 00
VOD CHA1 = 1.0V
DEM CHA1 = 0 (0dB)
End Device 2, 3 - Address
Offset 39
EQ CHA2 = 00
Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all 8–channels set to EQ = 00 (min
boost), VOD = 1.0V, DEM = 0 (0dB) and multiple device can point to the same address map.
19
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START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
System Management Bus (SMBus)
and Configuration Registers
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. ENSMB = 1kΩ to VDD to
enable SMBus slave mode and allow access to the configu-
ration registers.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
The DS80PCI402 has the AD[3:0] inputs in SMBus mode.
These pins are the user set SMBUS slave address inputs. The
AD[3:0] pins have internal pull-down. When left floating or
pulled low the AD[3:0] = 0000'b, the device default address
byte is B0'h. Based on the SMBus 2.0 specification, the
DS80PCI402 has a 7-bit slave address. The LSB is set to 0'b
(for a WRITE). The device supports up to 16 address byte,
which can be set with the AD[3:0] inputs. Below are the 16
addresses.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
Table 8: Device Slave Address Bytes
AD[3:0] Settings
0000
Address Bytes (HEX)
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
B0
B2
B4
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
CA
CC
CE
0001
0010
0011
6. The Device drives an ACK bit (“0”).
0100
7.
The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
0101
0110
0111
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1000
1001
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
1010
1011
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
1100
1101
5. The Host drives a START condition.
1110
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
1111
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant.
External pull-up resistor is required on the SDA. The resistor
value can be from 1 kΩ to 5 kΩ depending on the voltage,
loading and speed. The SCL may also require an external
pull-up resistor and it depends on the Host that drives the bus.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
TRANSFER OF DATA VIA THE SMBus
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
During normal operation the data on SDA must be stable dur-
ing the time when SCL is High.
Please see SMBus Register Map Table for more information.
There are three unique states for the SMBus:
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20
Table 9: SMBUS Slave Mode Register Map
Address Register Name
Bit (s) Field
Type Default Description
0x00
Observation,
Reset
7
Reserved
R/W 0x00
R
Set bit to 0.
6:3
Address Bit
AD[3:0]
Observation of AD[3:0] bits
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
2
EEPROM Read
Done
R
1: Device completed the read from external
EEPROM.
1
Block Reset
R/W
1: Block bit 0 from resettting the registers; self
clearing.
0
Reset
R/W
SMBus Reset
1: Reset registers to default value; self clearing.
0x01
PWDN Channels
7:0
PWDN CHx
R/W 0x00
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Note: override PRSNT pin.
0x02
Override PRSNT,
LPBK Control
7:6
5:4
Reserved
R/W 0x00
Set bits to 0.
LPBK
00: Use LPBK pin control
Control
01: INA_n to OUTB_n loopback
10: INB_n to OUTA_n loopback
11: Disable loopback and ignore LPBK pin.
3:1
0
Reserved
Set bits to 0.
Override PRSNT
pin
1: Block PRSNT pin control
0: Allow PRSNT pin control
0x05
0x06
Slave Mode CRC bits 7:0
CRC bits
Reserved
Reserved
Slave CRC
R/W 0x00
R/W 0x10
CRC bits [7:0]
Set bits to 0.
Set bit to 1.
Slave CRC Control 7:5
4
3
1: Disables the slave CRC mode
0: Enables the slave CRC mode
Note: In order to change VOD, DEM and EQ of
the channels in slave mode, set bit to 1 to disable
the CRC.
2:0
Reserved
Set bits to 0.
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0x08
Override
Pin Control
R/W 0x00
7
6
Reserved
Set bit to 0.
Override SD_TH
1: Block SD_TH pin control
0: Allow SD_TH pin control
5
4
Reserved
Set bit to 0.
Override IDLE
1: IDLE control by registers
0: IDLE control by signal detect
3
2
Override RXDET
Override RATE
1: Block RXDET pin control
0: Allow RXDET pin control
1: Block RATE pin control
0: Allow RATE pin control
1
Reserved
Reserved
Reserved
IDLE_AUTO
Set bit to 0.
Set bit to 0.
Set bits to 0.
0
0x0E
CH0 - CHB0
7:6
5
R/W 0x00
IDLE, RXDET
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x0F
0x10
CH0 - CHB0
EQ
EQ Control
R/W 0x2F
R/W 0xAD
IB0 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
CH0 - CHB0
VOD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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22
0x11
CH0 - CHB0
DEM
0x02
7
RXDET STATUS
R
R
Observation bit for RXDET CH0 - CHB0.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH0 - CHB0.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x12
CH0 - CHB0
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W 0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x15
CH1 - CHB1
IDLE, RXDET
7:6
5
Reserved
R/W 0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x16
CH1 - CHB1
EQ
EQ Control
R/W 0x2F
IB1 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
23
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0x17
CH1 - CHB1
VOD
R/W 0xAD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x18
CH1 - CHB1
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH1 - CHB1.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH1 - CHB1.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x19
CH1 - CHB1
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W 0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
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24
0x1C
CH2 - CHB2
IDLE, RXDET
R/W 0x00
7:6
5
Reserved
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x1D
0x1E
CH2 - CHB2
EQ
EQ Control
R/W 0x2F
R/W 0xAD
IB2 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
CH2 - CHB2
VOD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x1F
CH2 - CHB2
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH2 - CHB2.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH2 - CHB2.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
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0x20
CH2 - CHB2
IDLE Threshold
R/W 0x00
7:4
3:2
Reserved
IDLE thd
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x23
CH3 - CHB3
IDLE, RXDET
7:6
5
Reserved
R/W 0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x24
0x25
CH3 - CHB3
EQ
EQ Control
R/W 0x2F
R/W 0xAD
IB3 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
CH3 - CHB3
VOD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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26
0x26
CH3 - CHB3
DEM
0x02
7
RXDET STATUS
R
R
Observation bit for RXDET CH3 - CHB3.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH3 - CHB3.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x27
CH3 - CHB3
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W 0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x2B
CH4 - CHA0
IDLE, RXDET
7:6
5
Reserved
R/W 0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x2C
CH4 - CHA0
EQ
EQ Control
R/W 0x2F
IA0 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
27
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0x2D
CH4 - CHA0
VOD
R/W 0xAD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x2E
CH4 - CHA0
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH4 - CHA0.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH4 - CHA0.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x2F
CH4 - CHA0
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W 0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
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28
0x32
CH5 - CHA1
IDLE, RXDET
R/W 0x00
7:6
5
Reserved
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x33
0x34
CH5 - CHA1
EQ
EQ Control
R/W 0x2F
R/W 0xAD
IA1 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
CH5 - CHA1
VOD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x35
CH5 - CHA1
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH5 - CHA1.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH5 - CHA1.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
29
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0x36
CH5 - CHA1
IDLE Threshold
R/W 0x00
7:4
3:2
Reserved
IDLE thd
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x39
CH6 - CHA2
IDLE, RXDET
7:6
5
Reserved
R/W 0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x3A
0x3B
CH6 - CHA2
EQ
EQ Control
R/W 0x2F
R/W 0xAD
IA2 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
CH6 - CHA2
VOD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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30
0x3C
CH6 - CHA2
DEM
0x02
7
RXDET STATUS
R
R
Observation bit for RXDET CH6 - CHA2.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH6 - CHA2.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x3D
CH6 - CHA2
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W 0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x40
CH7 - CHA3
IDLE, RXDET
7:6
5
Reserved
R/W 0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x41
CH7 - CHA3
EQ
EQ Control
R/W 0x2F
IA3 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
31
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0x42
CH7 - CHA3
VOD
R/W 0xAD
7
6
Short Circuit
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x43
CH7 - CHA3
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH7 - CHA3.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH7 - CHA3.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x44
CH7 - CHA3
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W 0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x51
Device ID
7:5
4:0
VERSION
ID
R
0x44
010'b
00100'b
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32
impedance of 85 - 100Ω. It is preferable to route differential
lines exclusively on one layer of the board, particularly for the
input traces. The use of vias should be avoided if possible. If
vias must be used, they should be used sparingly and must
be placed symmetrically for each side of a given differential
pair. Whenever differential vias are used the layout must also
provide for a low inductance path for the return currents as
well. Route the differential signals away from other signals
and noise sources on the printed circuit board. See AN-1187
for additional information on LLP packages.
Applications Information
The DS80PCI402 is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the information
below and Revision 4 of the LVDS Owner's Manual for more
detailed information on high speed design tips to address sig-
nal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and LPDS outputs have been optimized to
work with interconnects using
a controlled differential
30119810
FIGURE 6. Typical Routing Options
The graphic shown above depicts different transmission line
topologies which can be used in various combinations to
achieve the optimal system performance. Impedance discon-
tinuities at the differential via can be minimized or eliminated
by increasing the swell around each hole and providing for a
low inductance return current path. When the via structure is
associated with thick backplane PCB, further optimization
such as back drilling is often used to reduce the deterimential
high frequency effects of stubs on the signal path.
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1 μF bypass capac-
itor should be connected to each VDD pin such that the ca-
pacitor is placed as close as possible to the DS80PCI402.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, capacitor with capacitance in
the range of 1 μF to 10 μF should be incorporated in the power
supply bypassing design as well. These capacitors can be
either tantalum or an ultra-low ESR ceramic.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS80PCI402 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
33
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Typical Performance Curves Characteristics
30119827
FIGURE 7. Power Dissipation (PD) vs. Output Differential Voltage (VOD)
30119828
FIGURE 8. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Supply Voltage (VDD)
30119829
FIGURE 9. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Temperature
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34
Typical Performance Eye Diagrams Characteristics
30119830
FIGURE 10. Test Setup Connections Diagram
30119831
FIGURE 11. TL = 20 inch 4–mil FR4 trace,
DS80PCI402 settings: EQ[1:0] = R, R = 15'h, DEM[1:0] = float, float
30119832
FIGURE 12. TL = 35 inch 4–mil FR4 trace,
DS80PCI402 settings: EQ[1:0] = float, R = 1F'h, DEM[1:0] = float, float
35
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30119833
FIGURE 13. Test Setup Connections Diagram
30119834
FIGURE 14. TL1 = 20 inch 4–mil FR4 trace, TL2 = 15 inch 4–mil FR4 trace,
DS80PCI402 settings: EQ[1:0] = R, R = 15'h, DEM[1:0] = float, float
30119835
FIGURE 15. TL1 = 30 inch 4–mil FR4 trace, TL2 = 15 inch 4–mil FR4 trace,
DS80PCI402 settings: EQ[1:0] = R, 1 = 0F'h, DEM[1:0] = float, float
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36
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS80PCI402SQ (Tape and Reel 2,000 units)
Order Number DS80PCI402SQE (Tape and Reel 250 units)
Package Number SQA54A
(See AN-1187 for PCB Design and Assembly Recommendations)
37
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Notes
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microcontroller.ti.com
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