DS90C031QML-SP [TI]
LVDS 四路 CMOS 差动线路驱动器;
| 型号： | DS90C031QML-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVDS 四路 CMOS 差动线路驱动器 驱动 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总21页 (文件大小：657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C031QML
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SNLS202B –MARCH 2006–REVISED MARCH 2013
DS90C031QML LVDS Quad CMOS Differential Line Driver
Check for Samples: DS90C031QML
1
FEATURES
DESCRIPTION
The DS90C031 is a quad CMOS differential line
driver designed for applications requiring ultra low
power dissipation and high data rates.
2
•
•
•
•
•
•
•
•
Radiation guaranteed 100 krad(Si)
High impedance LVDS outputs with power-off
±350 mV differential signaling
Low power dissipation
The DS90C031 accepts TTL/CMOS input levels and
translates them to low voltage (350 mV) differential
output signals. In addition the driver supports a TRI-
STATE function that may be used to disable the
output stage, thus dropping the device to a low idle
power state of 11 mW typical.
Low differential skew
Low propagation delay
Pin compatible with DS26C31
Compatible with IEEE 1596.3 SCI LVDS
standard
In addition, the DS90C031 provides power-off high
impedance LVDS outputs. This feature assures
minimal loading effect on the LVDS bus lines when
VCC is not present. The DS90C031 and companion
line receiver (DS90C032) provide a new alternative to
high power psuedo-ECL devices for high speed point-
to-point interface applications.
•
•
Compatible with proposed TIA LVDS standard
Fail safe logic for floating inputs
Connection Diagram
Figure 1. Dual-In-Line
See Package Number NAD0016A & NAC0016A
Figure 2. LCCC Package
See Pacakage Number NAJ0020A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS90C031QML
SNLS202B –MARCH 2006–REVISED MARCH 2013
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Functional Block Diagram
Truth Table
Enables
Input
Outputs
EN
EN*
DI
X
L
DO+
Z
DO−
Z
L
H
L
H
All other combinations of
ENABLE inputs
H
H
L
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage (VCC
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to + 5.8V
Input Voltage (DI)
Enable Input Voltage (EN, EN*)
Output Voltage (DO+, DO−
)
Storage Temperature Range
−65°C ≤ TA ≤ +150°C
+260°C
Lead Temperature Range, Soldering (4 seconds)
(2)
Maximum Package Power Dissipation at +25°C
20 Pin LCCC Package
16 Pin CLGA (NAD)
16 Pin CLGA (NAC)
Thermal Resistance
θJA
1900 mW
1450 mW
1450 mW
20 Pin LCCC Package
16 Pin CLGA (NAD)
16 Pin CLGA (NAC)
θJC
78°C/W
145°C/W
145°C/W
20 Pin LCCC Package
16 Pin CLGA (NAD)
16 Pin CLGA (NAC)
18°C/W
14°C/W
14°C/W
3.5KV
(3)
ESD Rating
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) Derate LCCC at 12.8mW/°C above +25°C. Derate CLGA at 6.9mW/°C above +25°C.
(3) Human body model, 1.5 kΩ in series with 100 pF.
Recommended Operating Conditions
Min
+4.5
−55
Typ
+5.0
+25
Max
+5.5
+125
Unit
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
°C
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Quality Conformance Inspection
Table 1. Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp (°C)
+25
1
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
5
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
12
13
14
+125
-55
+25
+125
-55
(1)
DC Parameters
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Units
VOD1
Differential Ouput Voltage
RL = 100Ω
250
450
35
mV
mV
1, 2, 3
1, 2, 3
DVOD1
Change in Magnitude of Vod1 for RL = 100Ω
complementary output States
VOS
Offset Voltage
RL = 100Ω
RL = 100Ω
1.12 1.37
V
1, 2, 3
1, 2, 3
5
5
DVOS
Change in Magnitude of Vos for
Complementary Output States
25
mV
VOH
VOL
VIH
VIL
II
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Input Current
RL = 100Ω
RL = 100Ω
1.6
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0.9
2.0
(2)
(2)
VCC
0.8
V
Gnd
V
VI = VCC, Gnd, 2.5, or 0.4V
ICl = -18mA
±10
-1.5
-5.0
±10
µA
V
VCl
IOS
IOff
Input Clamp Voltage
Output Short Circuit Current
Power-off Leakage
VO = 0V
mA
µA
VO = 0V or 2.4V,
VCC-= 0V or Open
IOZ
Output TRI-STATE Current
EN = 0.8V and EN* = 2.0V
VO = 0V or VCC
±10
µA
1, 2, 3
ICC
Drivers Enabled Supply Current
Drivers Disabled Supply Current
DI = Hi or Low
25
10
mA
mA
1, 2, 3
1, 2, 3
ICCZ
DI = Hi or Low, En = Gnd,
En* = VCC
(1) Pre and Post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post
Radiation Limits” table. Radiation end point limits for the noted parameters are guaranteed only for the conditions, as specified.
(2) Tested during VOH / VOL tests.
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AC Parameters
The following conditions apply, unless otherwise specified.
AC:
VCC = 4.5V / 5.0V / 5.5V, RL = 100Ω (between outputs), CL = 20pF (each output to Gnd)
Sub-
groups
Symbol
tPHLD
tPLHD
Parameter
Conditions
Notes
Min Max
Units
Differential Propagation Delay
High to Low
0.5
0.5
5.0
5.0
ns
9, 10, 11
Differential Propagation Delay
Low to High
ns
9, 10, 11
tSkD
tSk1
tSk2
tPHZ
tPLZ
tPZH
tPZL
Differential Skew |tPHLD-tPLHD|
Channel to Channel Skew
Chip to Chip Skew
3.0
3.0
4.5
20
ns
ns
ns
ns
ns
ns
ns
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
(1)
(2)
(3)
(3)
(3)
(3)
Disable Time High to Z
Disable Time Low To Z
Enable Time Z to High
Enable Time Z to Low
20
20
20
(1) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
(2) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
(3) Parameter guaranteed, not tested 100%
(1)
AC/DC Parameters - Post Radiation Limits
Sub-
groups
Symbol
ICC
ICCZ
Parameter
Conditions
Notes
Min Max
Units
Drivers Enabled Supply Current
DI - Hi or Low, En = Gnd,
En* = VCC
30
mA
1
Drivers Disabled Supply Current
DI - Hi or Low, En = Gnd,
En* = VCC
30
mA
1
(1) Pre and Post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post
Radiation Limits” table. Radiation end point limits for the noted parameters are guaranteed only for the conditions, as specified.
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Parameter Measurement Information
Figure 3. Driver VOD and VOS Test Circuit
Figure 4. Driver Propagation Delay and Transition Time Test Circuit
Figure 5. Driver Propagation Delay and Transition Time Waveforms
Figure 6. Driver TRI-STATE Delay Test Circuit
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Parameter Measurement Information (continued)
Figure 7. Driver TRI-STATE Delay Waveform
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Typical Performance Characteristics
Power Supply Current vs Power Supply Voltage
Power Supply Current vs Temperature
Figure 8.
Figure 9.
Power Supply Current vs Power Supply Voltage
Power Supply Current vs Temperature
Figure 10.
Figure 11.
Output TRI-STATE Current vs Power Supply Voltage
Output Short Circuit Current vs Power Supply Voltage
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Differential Output Voltage vs Power Supply Voltage
Differential Output Voltage vs Ambient Temperature
Figure 14.
Figure 15.
Output Voltage High vs Power Supply Voltage
Output Voltage High vs Ambient Temperature
Figure 16.
Figure 17.
Output Voltage Low vs Power Supply Voltage
Output Voltage Low vs Ambient Temperature
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Offset Voltage vs Power Supply Voltage
Offset Voltage vs Ambient Temperature
Figure 20.
Figure 21.
Power Supply Current vs Frequency
Power Supply Current vs Frequency
Figure 22.
Figure 23.
Differential Output Voltage vs Load Resistor
Differential Propagation Delay vs Power Supply Voltage
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
Differential Propagation Delay vs Ambient Temperature
Differential Skew vs Power Supply Voltage
Figure 26.
Figure 27.
Differential Skew vs Ambient Temperature
Differential Transition Time vs Power Supply Voltage
Figure 28.
Figure 29.
Differential Transition Time vs Ambient Temperature
Figure 30.
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TYPICAL APPLICATION
Figure 31. Point-to-Point Application
APPLICATIONS INFORMATION
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 31. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C031differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The typical
output current is mere 3.4 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as
discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as
shown in Figure 31. AC or unterminated configurations are not allowed. The 3.4 mA loop current will develop a
differential voltage of 340 mV across the 100Ω termination resistor which the receiver detects with a 240 mV
minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (340
mV – 100 mV = 240 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as
shown in Figure 32. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 680 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required. The LVDS outputs are high impedance under power-off condition. This
allows for multiple or redundant drivers to be used in certain applications.
The footprint of the DS90C031 is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver.
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Figure 32. Driver Output Levels
Pin Descriptions
Pin No. (SOIC)
Name
DI
Description
1, 7, 9, 15
Driver input pin, TTL/CMOS compatible
Non-inverting driver output pin, LVDS levels
Inverting driver output pin, LVDS levels
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
2, 6, 10, 14
DO+
DO−
EN
3, 5, 11, 13
4
12
16
8
EN*
VCC
Gnd
Ground pin
Radiation Environments
Careful consideration should be given to environmental conditions when using a product in a radiation
environment.
Total Ionizing Dose
Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level
specified in the Ordering Information table on the front page. Testing and qualification of these products is done
on a wafer level according to MIL-STD-883G, Test Method 1019.7, Condition A and the “Extended room
temperature anneal test” described in section 3.11 for application environment dose rates less than 0.16
rad(Si)/s. Wafer level TID data is available with lot shipments.
Single Event Latch-Up
One time single event latch-up (SEL) testing was preformed showing SEL immunity to 103 MeV-cm2/mg. A test
report is available upon request.
Single Event Upset
Single event upset (SEU) data are available upon request.
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REVISION HISTORY
Released
Revision
Section
Changes
03/01/06
New
New Release, Corporate format
1 MDS data sheet converted into Corp. data sheet
format. MNDS90C031-X-RH Rev 2A1 will be
archived.
10/12/2010
03/04/2013
A
B
Features, Ordering Table, Absolute Maximum Added reference to Radiation and Fail safe. Removed
Ratings, Applications Information
reference to EOL NSID, Output Voltage changed limit
from −0.3V to (VCC + 0.3V) to −0.3V to +5.8V, Added
paragraph to Applications Information section and
New Radiation Environment section. Revision A will
be Archived.
All
Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
5962-9583301Q2A
ACTIVE
LCCC
CFP
CFP
CFP
LCCC
CFP
CFP
CFP
NAJ
20
16
16
16
20
16
16
16
50
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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-55 to 125
DS90C031E
-QML Q
5962-95833
01Q2A ACO
01Q2A >T
5962-9583301VFA
5962R9583301VFA
5962R9583301VZA
DS90C031E-QML
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NAD
NAD
NAC
NAJ
19
19
42
50
19
42
19
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
DS90C031W-
QMLV Q
5962-95833
01VFA ACO
01VFA >T
DS90C031WR
QMLV Q
5962R95833
01VFA ACO
01VFA >T
DS90C031WGR
QMLV Q
5962R95833
01VZA ACO
01VZA >T
DS90C031E
-QML Q
5962-95833
01Q2A ACO
01Q2A >T
DS90C031W-QMLV
DS90C031WGRQMLV
DS90C031WRQMLV
NAD
NAC
NAD
DS90C031W-
QMLV Q
5962-95833
01VFA ACO
01VFA >T
DS90C031WGR
QMLV Q
5962R95833
01VZA ACO
01VZA >T
DS90C031WR
QMLV Q
5962R95833
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Drawing Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
(1)
(2)
(3)
(4)
01VFA ACO
01VFA >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS90C031QML, DS90C031QML-SP :
Military: DS90C031QML
•
Space: DS90C031QML-SP
•
Addendum-Page 2
PACKAGE OPTION ADDENDUM
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11-Apr-2013
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 3
MECHANICAL DATA
NAJ0020A
E20A (Rev F)
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MECHANICAL DATA
NAD0016A
W16A (Rev T)
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MECHANICAL DATA
NAC0016A
WG16A (RevG)
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相关型号：
DS90C031TM/NOPB
IC QUAD LINE DRIVER, PDSO16, 0.150 INCH, LEAD FREE, PLASTIC, SOIC-16, Line Driver or Receiver
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DS90C031TMX/NOPB
IC QUAD LINE DRIVER, PDSO16, 0.150 INCH, PLASTIC, SOIC-16, Line Driver or Receiver
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