DS90C124 [TI]
5MHz 至 35MHz 直流平衡 24 位 FPD-Link II 解串器;型号: | DS90C124 |
厂家: | TEXAS INSTRUMENTS |
描述: | 5MHz 至 35MHz 直流平衡 24 位 FPD-Link II 解串器 光电二极管 |
文件: | 总41页 (文件大小:1802K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit
FPD-Link II Serializer and Deserializer
1 Features
2 Applications
1
•
5-MHz to 35-MHz Clock Embedded and DC-
Balancing 24:1 and 1:24 Data Transmissions
•
•
•
•
Automotive Central Information Displays
Automotive Instrument Cluster Displays
Automotive Heads-Up Displays
•
User Defined Pre-Emphasis Driving Ability
Through External Resistor on LVDS Outputs and
Capable to Drive Up to 10-Meter Shielded
Twisted-Pair Cable
Remote Camera-Based Driver Assistance
Systems
•
•
User-Selectable Clock Edge for Parallel Data on
Both Transmitter and Receiver
3 Description
The DS90C241 and DS90C124 chipset translates a
24-bit parallel bus into a fully transparent data and
control LVDS serial stream with embedded clock
information. This single serial stream simplifies
transferring a 24-bit bus over PCB traces or over
cable by eliminating the skew problems between
parallel data and clock paths. It saves system cost by
narrowing data paths, which in turn reduces PCB
layers, cable width, and connector size and pins.
Internal DC Balancing Encode and Decode
(Supports AC-Coupling Interface With No External
Coding Required)
•
•
Individual Power-Down Controls for Both
Transmitter and Receiver
Embedded Clock CDR (Clock and Data Recovery)
on Receiver and No External Source of Reference
Clock Required
The DS90C241 and DS90C124 incorporate LVDS
signaling on the high-speed I/O. LVDS provides a
low-power and low-noise environment for reliably
transferring data over a serial transmission path. By
optimizing the serializer output edge rate for the
operating frequency range, EMI is further reduced.
•
•
•
•
•
•
All Codes RDL (Random Data Lock) to Support
Live-Pluggable Applications
LOCK Output Flag to Ensure Data Integrity at
Receiver Side
Balanced TSETUP and THOLD Between RCLK and
RDATA on Receiver Side
In addition, the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding and decoding
supports AC-coupled interconnects.
PTO (Progressive Turnon) LVCMOS Outputs to
Reduce EMI and Minimize SSO Effects
All LVCMOS Inputs and Control Pins Have
Internal Pulldown
Device Information(1)
On-Chip Filters for PLLs on Transmitter and
Receiver
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90C124
DS90C241
TQFP (48)
7.00 mm x 7.00 mm
•
•
•
•
•
Temperature Range: –40°C to 105°C
Greater Than 8-kV HBM ESD Tolerant
Meets AEC-Q100 Compliance
Power Supply Range: 3.3 V ± 10%
48-Pin TQFP Package
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
PRE
DEN
VODSEL
REN
D
OUT
+
R
+
IN
24
24
R
D
OUT
IN
R -
IN
D
OUT
-
TRFB
TCLK
Timing
and
Control
PLL
PLL
LOCK
RCLK
RRFB
RPWDNB
Timing
and
Clock
Recovery
TPWDNB
Control
SERIALIZER œ DS90C241
DESERIALIZER œ DS90C124
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Table of Contents
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 20
Applications and Implementation ...................... 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ..................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 8
6.5 Electrical Characteristics........................................... 8
6.6 Timing Requirements – Serializer............................. 9
6.7 Switching Characteristics – Serializer..................... 10
6.8 Switching Characteristics – Deserializer................. 10
6.9 Typical Characteristics............................................ 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
9
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 32
12.1 Documentation Support ........................................ 32
12.2 Related Links ........................................................ 32
12.3 Receiving Notification of Documentation Updates 32
12.4 Community Resources.......................................... 32
12.5 Trademarks........................................................... 32
12.6 Electrostatic Discharge Caution............................ 32
12.7 Glossary................................................................ 32
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (April 2013) to Revision M
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Deleted Lead temperature, soldering (260°C maximum) from Absolute Maximum Ratings.................................................. 7
Added Thermal Information table ........................................................................................................................................... 8
Added Typical Characteristics (PCLK = 5 MHz and PCLK = 25 MHz plus pre-emphasis).................................................. 11
•
•
•
Changes from Revision K (April 2013) to Revision L
Page
•
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
2
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
5 Pin Configuration and Functions
DS90C241 Serializer PFB Package
48-Pin TQFP
Top View
DIN[10]
DIN[11]
DIN[12]
DIN[13]
DIN[14]
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
V
SS
PRE
V
V
DR
DD
DR
SS
DOUT+
DOUT-
DEN
V
IT
IT
ꢀ{90/241
48 tLb ÇvCt
DD
V
SS
DIN[15]
DIN[16]
DIN[17]
DIN[18]
DIN[19]
V
V
V
V
PT0
SS
PT0
PT1
DD
SS
DD
PT1
RESRVD
Pin Functions – DS90C241 Serializer
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
LVCMOS PARALLEL INTERFACE PINS
4-1, 48-44,
41-32, 29-25
DIN[23:0]
TCLK
I
I
LVCMOS, Transmitter parallel interface data input pins. Tie LOW if unused, do not float.
LVCMOS, Transmitter parallel interface clock input pin. Strobe edge set by TRFB
configuration pin.
10
CONTROL AND CONFIGURATION PINS
DCAOFF
DCBOFF
5
8
I
I
LVCMOS, Reserved. This pin must be tied LOW.
LVCMOS, Reserved. This pin must be tied LOW.
LVCMOS, Transmitter data enable.
DEN = H; LVDS driver outputs are enabled (ON).
DEN = L; LVDS driver outputs are disabled (OFF), Transmitter LVDS driver DOUT (±) outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
DEN
18
I
LVCMOS, Pre-emphasis level select.
PRE = NC (No Connect); Pre-emphasis is disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor
value determines pre-emphasis level. Recommended value RPRE ≥ 3 kΩ; Imax = [(1.2/R) ×
20], Rmin = 3 kΩ
PRE
23
I
RESRVD
TPWDNB
13
9
I
I
LVCMOS, Reserved. This pin must be tied LOW.
LVCMOS, Transmitter power down bar.
TPWDNB = H; Transmitter is enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS driver DOUT (±) outputs are
in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
(1) G = Ground, I = Input, O = Output, P = Power
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Pin Functions – DS90C241 Serializer (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
LVCMOS, Transmitter clock edge select pin.
TRFB
11
I
TRFB = H; Parallel interface data is strobed on the rising clock edge.
TRFB = L; Parallel interface data is strobed on the falling clock edge.
LVCMOS, VOD Level select
VODSEL = L; LVDS driver output is approximately ± 400 mV (RL = 100 Ω)
VODSEL = H; LVDS driver output is approximately ± 750 mV (RL = 100 Ω)
VODSEL
12
I
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
LVDS SERIAL INTERFACE PINS
LVDS, Transmitter LVDS inverted (-) output
DOUT−
19
20
O
O
This output is intended to be loaded with a 100-Ω load to the DOUT- pin. The interconnect
must be AC-coupled to this pin with a 100-nF capacitor.
LVDS, Transmitter LVDS true (+) output.
This output is intended to be loaded with a 100-Ω load to the DOUT+ pin. The interconnect
must be AC-coupled to this pin with a 100-nF capacitor.
DOUT+
POWER OR GROUND PINS
VDDDR
VDDIT
VDDL
22
42
7
P
P
P
P
P
P
G
G
G
G
G
G
G
VDD, Analog voltage supply, LVDS output power
VDD, Digital voltage supply, Tx input power
VDD, Digital voltage supply, Tx logic power
VDD, Analog voltage supply, VCO power
VDD, Analog voltage supply, PLL power
VDD, Digital voltage supply, Tx serializer power
ESD ground
VDDPT0
VDDPT1
VDDT
16
14
30
24
21
43
6
VSS
VSSDR
VSSIT
VSSL
Analog ground, LVDS output ground
Digital ground, Tx input ground
Digital ground, Tx logic ground
VSSPT0
VSSPT1
VSST
17
15
31
Analog ground, VCO ground
Analog ground, PLL ground
Digital ground, Tx serializer ground
4
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
DS90C124 Deserializer PFB Package
48-Pin TQFP
Top View
PTO GROUP 1
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
ROUT[8]
ROUT[9]
ROUT[10]
ROUT[11]
V
R1
R1
DD
V
SS
V
IR
IR
DD
V
SS
RIN+
RIN-
V
V
OR2
DD
OR2
ꢀ{90/124
48 tLb ÇvCt
SS
RRFB
RCLK
LOCK
V
SS
PR1
PR1
PR0
PR0
ROUT[12]
ROUT[13]
ROUT[14]
ROUT[15]
V
DD
V
SS
V
DD
REN
PTO GROUP 3
Pin Functions – DS90C124 Deserializer
PIN
TYPE(1)
DESCRIPTION
NAME
LVCMOS PARALLEL INTERFACE PINS
NO.
RCLK
18
O
O
O
O
LVCMOS, Parallel interface clock output pin. Strobe edge set by RRFB configuration pin.
LVCMOS, Receiver LVCMOS level outputs – Group 1
ROUT[7:0]
ROUT[15:8]
ROUT[23:16]
25-28, 31-34
13-16, 21-24
3-6, 9-12
LVCMOS, Receiver LVCMOS level outputs – Group 2
LVCMOS, Receiver LVCMOS level outputs – Group 3
CONTROL AND CONFIGURATION PINS
LVCMOS, Receiver data enable
REN = H; ROUT[23:0] and RCLK are enabled (ON).
REN = L; ROUT[23:0] and RCLK are disabled (OFF), receiver ROUT[23:0] and RCLK outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
REN
48
I
LVCMOS, LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23:0] and RCLK are TRI-STATED
LOCK
17
2
O
I
RESRVD
LVCMOS, Reserved. This pin must be tied LOW.
LVCMOS, Receiver power down bar.
RPWDNB = H; Receiver is enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), ROUT[23:0], RCLK, and LOCK are in
TRI-STATE standby mode, PLL is shutdown to minimize power consumption.
RPWDNB
RRFB
1
I
I
LVCMOS, Receiver clock edge select pin.
RRFB = H; ROUT LVCMOS outputs strobed on the rising clock edge.
RRFB = L; ROUT LVCMOS outputs strobed on the falling clock edge.
43
(1) G = Ground, I = Input, O = Output, P = Power
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Pin Functions – DS90C124 Deserializer (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
LVDS SERIAL INTERFACE PINS
Receiver LVDS Inverted (−) Input
RIN−
42
41
I
I
This input is intended to be terminated with a 100-Ω load to the RIN- pin. The interconnect
must be AC-coupled to this pin with a 100-nF capacitor.
Receiver LVDS True (+) input
This input is intended to be terminated with a 100-Ω load to the RIN+ pin. The interconnect
must be AC-coupled to this pin with a 100-nF capacitor.
RIN+
POWER OR GROUND PINS
VDDIR
39
30
20
7
P
P
P
P
P
P
P
P
G
G
G
G
G
G
G
G
VDD, Analog LVDS voltage supply, power
VDD, Digital voltage supply, LVCMOS output power
VDD, Digital voltage supply, LVCMOS output power
VDD, Digital voltage supply, LVCMOS output power
VDD, Analog voltage supply, PLL power
VDD, Analog voltage supply, PLL VCO power
VDD, Digital voltage supply, Logic power
VDD, Digital voltage supply, Logic power
Analog LVDS ground
VDDOR1
VDDOR2
VDDOR3
VDDPR0
VDDPR1
VDDR0
47
45
36
37
40
29
19
8
VDDR1
VSSIR
VSSOR1
VSSOR2
VSSOR3
VSSPR0
VSSPR1
VSSR0
Digital ground, LVCMOS output ground
Digital ground, LVCMOS output ground
Digital ground, LVCMOS output ground
Analog ground, PLL ground
46
44
35
38
Analog ground, PLL VCO ground
Digital ground, Logic ground
VSSR1
Digital ground, Logic ground
6
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
4
UNIT
V
VCC
Supply voltage
LVCMOS/LVTTL input voltage
LVCMOS/LVTTL output voltage
LVDS receiver input voltage
LVDS driver output voltage
LVDS output short circuit duration
Junction temperature
VCC + 0.3
VCC + 0.3
3.9
V
V
V
3.9
V
10
ms
°C
°C
TJ
150
Tstg
Storage temperature
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±8000
±1250
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
IEC, powered-up only contact
discharge (RIN0+, RIN0-, RIN1+, RIN1-
±8000
±15000
±8000
)
)
RD = 330 Ω, CS = 150 pF
IEC, powered-up only air-gap
discharge (RIN0+, RIN0-, RIN1+, RIN1-
ISO10605 contact discharge
V(ESD) Electrostatic discharge
V
(RIN0+, RIN0-, RIN1+, RIN1-
ISO10605 air-gap discharge
(RIN0+, RIN0-, RIN1+, RIN1-
ISO10605 contact discharge
(RIN0+, RIN0-, RIN1+, RIN1-
ISO10605 air-gap discharge
(RIN0+, RIN0-, RIN1+, RIN1-
)
RD = 330 Ω, CS = 150 and 330 pF
RD = 2 kΩ, CS = 150 and 330 pF
±15000
±8000
)
)
±15000
)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
UNIT
VCC
Supply voltage
3.3
V
Clock rate
5
35
MHz
mVP-P
°C
Supply noise
±100
105
TA
Operating free-air temperature
−40
25
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
6.4 Thermal Information
DS90C241-Q1
DS90C124-Q1
THERMAL METRIC(1)
UNIT
TFB (TQFP)
48 PINS
67.5
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.1
33.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
ψJB
33
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS AND LVTTL DC SPECIFICATIONS
Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF, and VODSEL; and
Rx: RPWDNB, RRFB, and REN
VIH
VIL
High-level voltage
2
VCC
0.8
V
V
V
Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF, and VODSEL; and
Rx: RPWDNB, RRFB, and REN
Low-level input voltage
Input clamp voltage
GND
ICL = −18 mA, Tx: DIN[23:0], TCLK, TPWDNB, DEN,
TRFB, DCAOFF, DCBOFF, and VODSEL; and
Rx: RPWDNB, RRFB, and REN(1)
VCL
−0.8
−1.5
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
−10
−20
±5
±5
10
20
IIN
Input current
VIN = 0 V or 3.6 V
and VODSEL
µA
Rx: RPWDNB, RRFB,
and REN
VOH
VOL
IOS
High-level output voltage
Low-level output voltage
Output short circuit current
IOH = −4 mA, Rx: ROUT[23:0], RCLK, and LOCK
IOL = 4 mA, Rx: ROUT[23:0], RCLK, and LOCK
VOUT = 0 V, Rx: ROUT[23:0], RCLK, and LOCK(1)
2.3
GND
−40
3
0.33
−70
VCC
0.5
V
V
−110
mA
RPWDNB, REN = 0 V, VOUT = 0 V or 2.4 V,
Rx: ROUT[23:0], RCLK, and LOCK
IOZ
TRI-STATE output current
−30
±0.4
30
50
µA
LVDS DC SPECIFICATIONS
Differential threshold high
voltage
VTH
VCM = 1.2 V, Rx: RIN+ and RIN−
Rx: RIN+ and RIN−
mV
mV
Differential threshold low
voltage
VTL
−50
VIN = 2.4 V, VCC = 3.6 V or 0 V, Rx: RIN+ and RIN−
VIN = 0 V, VCC = 3.6 V, Rx: RIN+ and RIN−
±200
±200
600
IIN
Input current
µA
RL = 100 Ω, without pre-
emphasis, Tx: DOUT+ and
DOUT− (see Figure 12)
VODSEL = L
VODSEL = H
250
450
400
750
Output differential voltage
(DOUT+) – (DOUT−
VOD
mV
)
1200
50
Output differential voltage
unbalance
RL = 100 Ω, without pre-emphasis, Tx: DOUT+ and
DOUT−
ΔVOD
VOS
10
1.25
1
mV
V
RL = 100 Ω, without pre-emphasis, Tx: DOUT+ and
DOUT−
Offset voltage
1
1.5
50
RL = 100 Ω, without pre-emphasis, Tx: DOUT+ and
DOUT−
ΔVOS
Offset voltage unbalance
mV
(1) Specification is ensured by characterization and is not tested in production.
Submit Documentation Feedback
8
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DOUT = 0 V, DIN = H,
TPWDNB, DEN = 2.4 V,
Tx: DOUT+ and DOUT−
VODSEL = L
VODSEL = H
−2
−8
IOS
Output short circuit current
mA
DOUT = 0 V, DIN = H,
TPWDNB, DEN = 2.4 V,
Tx: DOUT+ and DOUT−
−7
−13
TPWDNB, DEN = 0 V, DOUT = 0 V or 2.4 V,
Tx: DOUT+ and DOUT−
IOZ
TRI-STATE output current
−15
±1
15
µA
SERIALIZER OR DESERIALIZER SUPPLY CURRENT – DVDDx, PVDDx, AND AVDDx PINS (Digital, PLL, and Analog VDDs)
RL = 100 Ω, RPRE = OFF, VODSEL = H/L, f = 35 MHz,
40
45
40
45
65
mA
mA
mA
mA
µA
and checker-board pattern (see Figure 3)
Serializer (Tx) total supply
current (includes load current)
RL = 100 Ω, RPRE = 6 kΩ, VODSEL = H/L, f = 35 MHz,
and checker-board pattern (see Figure 3)
70
ICCT
f = 35 MHz, RL = 100 Ω, RPRE = OFF,
65
and VODSEL = H/L
Serializer (Tx) total supply
current (includes load current)
f = 35 MHz, RL = 100 Ω, RPRE = 6 kΩ, VODSEL = H/L,
and random pattern
70
Serializer (Tx) supply current
power-down
ICCTZ
TPWDNB = 0 V (all other LVCMOS inputs = 0 V)
800
85
Deserializer (Rx) total supply
current (includes load current)
CL = 8-pF LVCMOS output, f = 35 MHz, and checker-
board pattern (see Figure 4)
mA
mA
µA
ICCR
Deserializer (Rx) total supply
current (includes load current)
CL = 8-pF LVCMOS output, f = 35 MHz, and random
pattern
80
Deserializer (Rx) supply current RPWDNB = 0 V (all other LVCMOS inputs = 0 V,
power-down RIN+/ RIN– = 0 V)
ICCRZ
50
6.6 Timing Requirements – Serializer
over recommended operating supply and temperature ranges (unless otherwise noted)
MIN
TYP
T
MAX
200
0.6T
0.6T
6
UNIT
tTCP
tTCIH
tTCIL
tCLKT
tJIT
Transmit clock period (see Figure 7)
Transmit clock high time
28.6
0.4T
0.4T
ns
ns
ns
ns
0.5T
0.5T
3
Transmit clock low time
TCLK input transition time (see Figure 6)
TCLK input jitter(1)
33
ps (RMS)
(1) tJIT (at BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
6.7 Switching Characteristics – Serializer
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVDS Low-to-High transition
time
RL = 100 Ω, CL = 10 pF to GND, and
VODSEL = L (see Figure 5)
tLLHT
tLHLT
0.6
ns
LVDS High-to-Low transition
time
RL = 100 Ω, CL = 10 pF to GND, and
VODSEL = L (see Figure 5)
0.6
ns
tDIS
tDIH
DIN[23:0] setup to TCLK
DIN[23:0] hold from TCLK
RL = 100 Ω and CL = 10 pF to GND(1)
RL = 100 Ω and CL = 10 pF to GND(1)
5
5
ns
ns
DOUT± HIGH to TRI-STATE
delay
RL = 100 Ω and CL = 10 pF to GND
tHZD
tLZD
tZHD
15
15
ns
ns
ns
(see Figure 8)(2)
DOUT± LOW to TRI-STATE
delay
RL = 100 Ω and CL = 10 pF to GND
(see Figure 8)(2)
DOUT± TRI-STATE to HIGH
delay
RL = 100 Ω and CL = 10 pF to GND
200
(see Figure 8)(2)
DOUT± TRI-STATE to LOW
delay
RL = 100 Ω and CL = 10 pF to GND
tZLD
tPLD
200
10
ns
ms
ns
(see Figure 8)(2)
Serializer PLL lock time
RL = 100 Ω (see Figure 9)
RL = 100 Ω, VODSEL = L, and TRFB = H
(see Figure 10)
3.5T + 2.85
3.5T + 2.85
3.5T + 10
tSD
Serializer delay
RL = 100 Ω, VODSEL = L, and TRFB = L
(see Figure 10)
3.5T + 10
ns
TxOUT_Eye_Opening
(respect to ideal)
TxOUT_E_O
5 MHz to 35 MHz (see Figure 11)(1)(3)(4)
0.75
UI(5)
(1) Specification is ensured by characterization and is not tested in production.
(2) When the serializer output is tri-stated, the deserializer loses PLL lock. Resynchronization must occur before data transfer.
(3) tJIT (at BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
(4) TxOUT_E_O is affected by pre-emphasis value.
(5) UI – Unit Interval; equivalent to one ideal serialized data bit width. The UI scales with frequency.
6.8 Switching Characteristics – Deserializer
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
Receiver out clock period tRCP = tTCP and RCLK pin(1)
TEST CONDITIONS
MIN
28.6
45%
TYP
MAX
200
UNIT
tRCP
tRDC
ns
RCLK duty cycle
RCLK pin
50%
2.5
55%
CL = 8 pF (lumped load);
ROUT[23:0], LOCK, and RCLK
pins (see Figure 13)(1)
LVCMOS low-to-high
transition time
tCLH
3.5
3.5
ns
ns
CL = 8 pF (lumped load);
ROUT[23:0], LOCK, and RCLK
pins (see Figure 13)(1)
LVCMOS high-to-low
transition time
tCHL
2.5
ROUT[7:0] setup data to
RCLK (Group 1)
tROS
tROH
tROS
tROH
tROS
tROH
tHZR
ROUT[7:0] pins (see Figure 17)
ROUT[7:0] pins (see Figure 17)
0.4 × tRCP
0.4 × tRCP
0.4 × tRCP
0.4 × tRCP
0.4 × tRCP
0.4 × tRCP
(29/56) × tRCP
(27/56) × tRCP
0.5 × tRCP
ns
ns
ns
ns
ns
ns
ns
ROUT[7:0] hold data to
RCLK (Group 1)
ROUT[15:8] setup data
to RCLK (Group 2)
ROUT[15:8] and LOCK pins
(see Figure 17)
ROUT[15:8] hold data to ROUT[15:8] and LOCK pins
RCLK (Group 2) (see Figure 17)
0.5 × tRCP
ROUT[23:16] setup data ROUT[23:16] pins
to RCLK (Group 3)
(27/56) × tRCP
(29/56) × tRCP
3
(see Figure 17)
ROUT[23:16] hold data
to RCLK (Group 3)
ROUT[23:16] pins
(see Figure 17)
HIGH to TRI-STATE
delay
ROUT[23:0], RCLK, and LOCK
pins (see Figure 15)
10
(1) Specification is ensured by characterization and is not tested in production.
10 Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Switching Characteristics – Deserializer (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW to TRI-STATE
delay
ROUT[23:0], RCLK, and LOCK
pins
tLZR
tZHR
tZLR
tDD
3
10
ns
TRI-STATE to HIGH
delay
ROUT[23:0], RCLK, and LOCK
pins
3
3
10
10
ns
TRI-STATE to LOW
delay
ROUT[23:0], RCLK, and LOCK
pins
ns
ns
Deserializer delay
RCLK pin (see Figure 14)
[4+(3/56)]T + 5.9 [4+(3/56)]T + 14
5 MHz
See Figure 16(1)(2)
35 MHz
5
5
50
50
Deserializer PLL lock
time from power down
tDRDL
ms
Receiver input tolerance 5 MHz to 35 MHz
(left)
(see Figure 18)(1)(3)
RxIN_TOL_L
RxIN_TOL_R
0.25
0.25
UI(4)
UI(4)
Receiver input tolerance 5 MHz to 35 MHz
(right)
(see Figure 18)(1)(3)
(2) The deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.
(3) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position. See AN-1217 How to Validate BLVDS SER/DES Signal Integrity
Using an Eye Mask (SNLA053) for details.
(4) UI – Unit Interval; equivalent to one ideal serialized data bit width. The UI scales with frequency.
6.9 Typical Characteristics
Figure 1 and Figure 2 are scope shots with PCLK = 5 MHz measured out of the DS90C241 DOUT± with pre-emphasis OFF
and pre-emphasis ON using a 1010... pattern on the DIN[23:0] inputs. The scope was triggered on the input PCLK.
Figure 2. DS90C241 DOUT± Eye Diagram at 5 MHz
With Pre-Emphasis ON
Figure 1. DS90C241 DOUT± Eye Diagram at 5 MHz
Without Pre-Emphasis
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
7 Parameter Measurement Information
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 3. Serializer Input Checkerboard Pattern
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 4. Deserializer Output Checkerboard Pattern
10 pF
DOUT+
DOUT-
80%
20%
80%
Differential
Signal
100W
Vdiff = 0V
20%
10 pF
Vdiff = (DOUT+) - (DOUT-)
t
t
LHLT
LLHT
Figure 5. Serializer LVDS Output Load and Transition Times
V
DD
80%
80%
TCLK
20%
20%
0V
t
t
CLKT
CLKT
Figure 6. Serializer Input Clock Transition Times
t
TCP
TCLK
V
DD
/2
V
DD
/2
V
/2
DD
t
t
DIH
DIS
V
DD
DIN [0:23]
Setup
Hold
V
/2
V
DD
/2
DD
0V
Figure 7. Serializer Setup and Hold Times
12
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Parameter Measurement Information (continued)
Parasitic package and
Trace capcitance
DOUT+
DOUT-
5 pF
100W
DEN
t
LZD
V
/2
V
/2
CC
DEN
CC
(single-ended)
0V
0V
CLK1
CLK1
t
t
TCP
TCP
DOUT±
(differential)
200 mV
200 mV
DCA
DCA
DCA
t
ZLD
DCA
DCA DCA DCA DCA
All data —0“s
All data —1“s
t
HZD
V
/2
V
/2
CC
DEN
CC
(single-ended)
0V
0V
DCA
DCA DCA DCA DCA
t
ZHD
DCA
DCA
DCA
200 mV
200 mV
DOUT±
(differential)
t
t
TCP
TCP
CLK0
CLK0
Figure 8. Serializer TRI-STATE Test Circuit and Delay
2.0V
PWDWN
TCLK
0.8V
t
or
HZD
t
LZD
t
or
ZHD
t
PLD
t
ZLD
Output
Active
ÇwL-{Ç!Ç9
ÇwL-{Ç!Ç9
DOUT±
Figure 9. Serializer PLL Lock Time and TPWDNB TRI-STATE Delays
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Parameter Measurement Information (continued)
DIN
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
t
SD
TCLK
{Çht {Ç!wÇ
.LÇ .LÇ
{Çht {Ç!wÇ
.LÇ .LÇ
{Çht {Ç!wÇ
.LÇ .LÇ
{Çht {Ç!wÇ
.LÇ .LÇ
{Çht
.LÇ
{òa.h[ b-4
{òa.h[ b-3
{òa.h[ b-2
{òa.h[ b-1
{òa.h[ b
DOUT0-23
DCA, DCB
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
23
Figure 10. Serializer Delay
Ideal Data Bit
End
Ideal Data Bit
Beginning
TxOUT_E_O
t (1/2UI)
BIT
t
(1/2UI)
BIT
Ideal Center Position (t /2)
BIT
t
(1UI)
BIT
Figure 11. Transmitter Output Eye Opening (TxOUT_E_O)
DOUT+
24
R
L
DIN
DOUT-
TCLK
VOD = (DOUT+) – (DOUT -
)
Differential output signal is shown as (DOUT+) – (DOUT -) with the device in data transfer mode.
Figure 12. Serializer VOD Diagram
Single-ended
Signal
80%
20%
80%
20%
Deserializer
8 pF
lumped
t
t
CHL
CLH
Figure 13. Deserializer LVCMOS/LVTTL Output Load and Transition Times
14
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Parameter Measurement Information (continued)
{Ç!wÇ
.LÇ
{Çht {Ç!wÇ
.LÇ .LÇ
{Çht {Ç!wÇ
.LÇ .LÇ
{Çht {Ç!wÇ
.LÇ .LÇ
{òa.h[ b+3
{Çht
.LÇ
{òa.h[ b
{òa.h[ b+1
{òa.h[ b+2
RIN0-23
DCA, DCB
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
23
t
DD
RCLK
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
ROUT0-23
Figure 14. Deserializer Delay
500W
VREF = V /2 for t
or t ,
LZR
DD
ZLR
or t
VREF
+
-
VREF = 0V for t
C
= 8pF
ZHR
HZR
L
REN
VOH
V
DD
/2
V /2
DD
REN
VOL
t
t
ZLR
LZR
VOL + 0.5V
VOH + 0.5V
VOL + 0.5V
VOH - 0.5V
VOL
t
t
ZHR
HZR
ROUT [23:0]
VOH
CL includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0].
Figure 15. Deserializer TRI-STATE Test Circuit and Timing
2.0ë
tí5b
0.8ë
t
DRDL
RIN±
[h/Y
5}v[š /ꢀŒꢁ
ÇwL-{Ç!Ç9
ÇwL-{Ç!Ç9
t
or t
LZR
HZR
ROUT [0:23]
w/[Y
ÇwL-{Ç!Ç9
ÇwL-{Ç!Ç9
ÇwL-{Ç!Ç9
ÇwL-{Ç!Ç9
w9b
Figure 16. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Parameter Measurement Information (continued)
t
t
HIGH
LOW
RCLK
V
/2
V
DD
/2
DD
t
t
ROH
ROS
(group 1)
(group 1)
5ata ëalid
.efore w/[Y
5ata ëalid
!fter w/[Y
ROUT [7:0]
V
/2
V
DD
/2
DD
1/2 ÜL
1/2 ÜL
t
t
ROH
ROS
(group 2)
(group 2)
5ata ëalid
.efore w/[Y
5ata ëalid
!fter w/[Y
ROUT [15:8], LOCK
V
/2
V
DD
/2
DD
1/2 ÜL
1/2 ÜL
t
t
ROH
ROS
(group 3)
(group 3)
5ata ëalid
.efore w/[Y
5ata ëalid
!fter w/[Y
ROUT [23:16]
V
/2
V
DD
/2
DD
Figure 17. Deserializer Setup and Hold Times
Sampling
Window
Ideal Data Bit
End
Ideal Data Bit
Beginning
RxIN_TOL -L
RxIN_TOL -R
Ideal Sampling Position
t
BIT
( )
2
t
BIT
(1UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure with respect to ideal.
Figure 18. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
16
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
8 Detailed Description
8.1 Overview
The DS90C241 serializer and DS90C124 deserializer chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 840 Mbps throughput.
The DS90C241 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream
with embedded clock, and scrambles or DC balances the data to enhance signal quality to support AC coupling.
The DS90C124 receives the LVDS serial data stream and converts it back into a 24-bit wide parallel data and
recovered clock. The 24-bit serializer or deserializer chipset is designed to transmit data up to 10 meters over
shielded twisted pair (STP) at clock speeds from 5 MHz to 35 MHz.
The deserializer can attain lock to a data stream without the use of a separate reference clock source. This
greatly simplifies system complexity and overall cost. The deserializer synchronizes to the serializer regardless of
data pattern, delivering true automatic plug and lock performance. It locks to the incoming serial stream without
the requirement of special training patterns or sync characters. The deserializer recovers the clock and data by
extracting the embedded clock information and validating data integrity from the incoming data stream and then
deserializes the data. The deserializer monitors the incoming clock information, determines lock status, and
asserts the LOCK output high when lock occurs. Each has a power down control to enable efficient operation in
various applications.
8.2 Functional Block Diagram
PRE
DEN
VODSEL
REN
D
+
R
+
OUT
IN
-
24
24
R
D
OUT
IN
R
IN
D
-
OUT
TRFB
TCLK
Timing
and
Control
PLL
PLL
LOCK
RCLK
RRFB
RPWDNB
Timing
and
Control
Clock
Recovery
TPWDNB
SERIALIZER œ DS90C241
DESERIALIZER œ DS90C124
Copyright © 2017, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Initialization and Locking Mechanism
Initialization of the DS90C241 and DS90C124 must be established before each device sends or receives data.
Initialization refers to synchronizing the PLLS of the serializer and the deserializer together. After the serializers
locks to the input clock source, the deserializer synchronizes to the serializers as the second and final
initialization step.
1. When VCC is applied to both serializer or deserializer, the respective outputs are held in TRI-STATE and
internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.2 V) the PLL in
serializer begins locking to a clock input. For the serializer, the local clock is the transmit clock, TCLK. The
serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Feature Description (continued)
serializer block is now ready to send data patterns. The deserializer output remains in TRI-STATE while its
PLL locks to the embedded clock information in serial data stream. Also, the deserializer LOCK output
remains low until its PLL locks to incoming data and sync-pattern on the RIN± pins.
2. The deserializer PLL acquires lock to a data stream without requiring the serializer to send special patterns.
The serializer that is generating the stream to the deserializer automatically sends random (non-repetitive)
data patterns during this step of the Initialization State. The deserializer locks onto the embedded clock
within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the
incoming bit stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit
expects a coded input bit stream. In order for the deserializer to lock to a random data stream from the
serializer, it performs a series of operations to identify the rising clock edge and validates data integrity, then
locks to it. Because this locking procedure is independent on the data pattern, total random locking duration
may vary. At the point when the CDR of the deserializer locks to the embedded clock, the LOCK pin goes
high and valid RCLK/data appears on the outputs. Note that the LOCK signal is synchronous to valid data
appearing on the outputs. The deserializer’s LOCK pin is a convenient way to ensure data integrity is
achieved on receiver side.
8.3.2 Data Transfer
After serializer lock is established, the inputs DIN0 to DIN23 may be used to input data to the serializer. Data is
clocked into the serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable through the
TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The serializer
outputs (DOUT±) are intended to drive point-to-point connections as shown in Figure 19.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream. The CLK1
bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits
in the serial stream. DCB functions as the DC Balance control bit. It does not require any precoding of data on
transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This
bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data
integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically
performed within serializer and deserializer.
Serialized data and clock or control bits (24 +4 bits) are transmitted from the serial data output (DOUT±) at 28
times the TCLK frequency. For example, if TCLK is 35 MHz, the serial rate is 35 × 28 = 980 Mega bits per
second. Because only 24 bits are from input data, the serial payload rate is 24 times the TCLK frequency. For
example, if TCLK = 35 MHz, the payload data rate is 35 × 24 = 840 Mbps. TCLK is provided by the data source
and must be in the range of 5 MHz to 35 MHz nominal. The serializer outputs (DOUT±) can drive a point-to-point
connection. The outputs transmit data when the enable pin (DEN) is high, TPWDNB is high. The DEN pin may
be used to TRI-STATE the outputs when driven low.
When the deserializer channel attains lock to the input from a serializer, it drives its LOCK pin high and
synchronously delivers valid data and recovered clock on the output. The deserializer locks onto the embedded
clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin.
The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high,
data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the
RRFB input. ROUT[23:0], LOCK, and RCLK outputs each drive a maximum of 8-pF load with 35-MHz clock.
REN controls TRI-STATE for ROUTn and the RCLK pin on the deserializer.
8.3.3 Resynchronization
If the deserializer loses lock, it automatically tries to re-establish lock. For example, if the embedded clock edge
is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The deserializer then
enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock edge,
identifies it and then proceeds through the locking process. The logic state of the LOCK signal indicates whether
the data on ROUT is valid; when it is high, the data is valid. The system must monitor the LOCK pin to determine
whether data on the ROUT is valid.
18
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Feature Description (continued)
8.3.4 Pre-Emphasis
The DS90C241 features a pre-emphasis function used to compensate for long or lossy transmission media.
Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. The transmission distance is limited by the loss
characteristics and quality of the media. Pre-emphasis adds extra current during LVDS logic transition to reduce
the cable loading effects and increase driving distance. In addition, pre-emphasis helps provide faster transitions,
increased eye openings, and improved signal integrity. To enable the pre-emphasis function, the PRE pin
requires one external resistor (Rpre) to Vss to set the additional current level. Pre-emphasis strength is set
through an external resistor (Rpre) applied from min to max (floating to 3 kΩ) at the PRE pin. A lower input
resistor value on the PRE pin increases the magnitude of dynamic current during data transition. There is an
internal current source based on the following formula: PRE = (Rpre ≥ 3 kΩ); IMAX = [(1.2/Rpre) × 20]. The ability
of the DS90C241 to use the pre-emphasis feature extends the transmission distance up to 10 meters in most
cases.
The amount of pre-emphasis for a given media depends on the transmission distance of the application. In
general, too much pre-emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk and increased power dissipation. For short cables or distances, pre-emphasis may not
be required. Signal quality measurements are recommended to determine the proper amount of pre-emphasis for
each application.
8.3.5 AC-Coupling and Termination
The DS90C241 and DS90C124 supports AC-coupled interconnects through integrated DC balanced
encoding/decoding scheme. To use AC coupled connection between the serializer and deserializer, insert
external AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 19. The deserializer
input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to
1.2 V. With AC signal coupling, capacitors provide the AC-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package must be used for the AC-coupling
capacitor. This helps minimize degradation of signal quality due to package parasitics. The most common used
capacitor value for the interface is 100-nF (0.1-µF) capacitor. NPO class 1 or X7R class 2 type capacitors are
recommended. 50-WVDC must be the minimum used for the best system-level ESD performance.
The DS90C124 input stage is designed for AC-coupling by providing a built-in AC bias network which sets the
internal VCM to 1.2 V. Therefore multiple termination options are possible.
8.3.5.1 Receiver Termination Options
8.3.5.1.1 Option 1
A single, 100-Ω termination resistor is placed across the RIN± pins (see Figure 19). This provides the signal
termination at the receiver inputs. Other options may be used to increase noise tolerance.
DOUT+
RIN+
100 nF
100 nF
100W
DOUT-
100W
RIN-
100 nF
100 nF
Figure 19. AC Coupled Application
8.3.5.1.1.1 Option 2
For additional EMI tolerance, two 50-Ω resistors may be used in place of the single 100-Ω resistor. A small
capacitor is tied from the center point of the 50-Ω resistors to ground (see Figure 20). This provides a high-
frequency low impedance path for noise suppression. Value is not critical; 4.7 nF may be used with general
applications.
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Feature Description (continued)
0.1 mF
0.1 mF
RIN+
50W
100W
DS90C241
DS90C124
4.7 nF
50W
RIN-
0.1 mF
0.1 mF
Copyright © 2017, Texas Instruments Incorporated
Figure 20. Receiver Termination Option 2
8.3.5.1.1.2 Option 3
For high noise environments an additional voltage divider network may be connected to the center point. This
has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the
range of 75 Ω to 2 KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.2 V. For
example (see Figure 21), VDD = 3.3 V, Rpullup = 1.3 kΩ, Rpulldown = 750 Ω; or Rpullup = 130 Ω, Rpulldown =
75 Ω (strongest). The smaller values consume more bias current, but provide enhanced noise suppression.
VDD
0.1 mF
0.1 mF
RIN+
R
R
50W
PU
PD
100W
DS90C241
DS90C124
4.7 nF
50W
RIN-
0.1 mF
0.1 mF
Copyright © 2017, Texas Instruments Incorporated
Figure 21. Receiver Termination Option 3
8.4 Device Functional Modes
Table 1 and Table 2 list the truth tables for the serializer and deserializer.
Table 1. DS90C241 Serializer Truth Table
TPWDNB
(PIN 9)
DEN
(PIN 18)
Tx PLL STATUS
(INTERNAL)
LVDS OUTPUTS
(PINS 19 AND 20)
L
X
L
X
X
Hi Z
H
H
H
Hi Z
Hi Z
H
H
Not locked
Locked
Serialized data with embedded clock
Table 2. DS90C124 Deserializer Truth Table
RPWDNB
(PIN 1)
REN
(PIN 48)
Rx PLL STATUS
(INTERNAL)
ROUTn AND RCLK
(SEE PIN DIAGRAM)
LOCK
(PIN 17)
L
X
X
Hi Z
Hi Z
Hi Z
Hi Z
L = PLL unocked
H = PLL locked
H
H
L
X
H
Not locked
L
20
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Table 2. DS90C124 Deserializer Truth Table (continued)
RPWDNB
(PIN 1)
REN
(PIN 48)
Rx PLL STATUS
(INTERNAL)
ROUTn AND RCLK
(SEE PIN DIAGRAM)
LOCK
(PIN 17)
H
H
Locked
Data and RCLK active
H
8.4.1 Power Down
The power-down state is a low power sleep mode that the serializer and deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down
mode, which reduces supply current to the µA range. The serializer enters power down when the TPWDNB pin is
driven low. In power down, the PLL stops and the outputs go into TRI-STATE, disabling load current and
reducing supply. To exit power down, TPWDNB must be driven high. When the serializer exits power down, its
PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for
Initialization before data transfer can begin. The deserializer enters power down mode when RPWDNB is driven
low. In power down mode, the PLL stops and the outputs enter TRI-STATE. To bring the deserializer block out of
the power down state, the system drives RPWDNB high.
Both the serializer and deserializer must reinitialize and relock before data can be transferred. The deserializer
initializes and asserts LOCK high when it is locked to the input clock.
8.4.2 Tri-State
For the serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This does TRI-STATE
both driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer returns to the previous
state as long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the deserializer enters TRI-STATE. Consequently, the receiver
output pins (ROUT0 to ROUT23) and RCLK enters TRI-STATE. The LOCK output remains active, reflecting the
state of the PLL. The deserializer input pins are high impedance during receiver power down (RPWDNB low) and
power-off (VCC = 0 V).
8.4.3 Progressive Turn–On (PTO)
Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 0.5-UI
apart in phase to reduce EMI, simultaneous switching noise, and system ground bounce.
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Using the DS90C241 and DS90C124
The DS90C241/DS90C124 serializer or deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over
a serial LVDS link up to 840 Mbps. Serialization of the input data is accomplished using an on-board PLL at the
serializer which embeds clock with the data. The deserializer extracts the clock/control information from the
incoming data stream and deserializes the data. The deserializer monitors the incoming clockl information to
determine lock status and indicates lock by asserting the LOCK output high.
9.1.2 Display Application
The DS90C241/DS90C124 chipset is intended for interface between a host (graphics processor) and a display. It
supports an 18-bit color depth (RGB666) and up to 800 × 480 display formats. In a RGB666 configuration 18
color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS, and DE) along with three
spare bits are supported across the serial link with PCLK rates from 5 MHz to 35 MHz.
9.2 Typical Application
Figure 22 shows a typical application of the DS90C241 serializer (SER). The LVDS outputs use a 100-Ω
termination and 100-nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
A system General Purpose Output (GPO) controls the TPWDNB pin. In this application the TRFB pin is tied High
to latch data on the rising edge of the TCLK. The DEN signal is not used and is tied High also. In this application,
the link is short; therefore, the VODSEL pin is tied Low for the standard LVDS swing. The pre-emphasis input
uses a resistor to ground to set the amount of pre-emphasis desired by the application.
Figure 23 shows a typical application of the DS90C124 deserializer (DES). The LVDS inputs use a 100-Ω
termination and 100-nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
A system GPO controls the RPWDNB pin. In this application, the RRFB pin is tied high to strobe the data on the
rising edge of the RCLK. The REN signal is not used and is tied high also.
22
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Typical Application (continued)
DS90C241 (SER)
VDDDR
3.3V
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
C1
C2
C3
C4
VDDPT0
VDDPT1
C5
C6
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
VDDIT
VDDL
VDDT
LVCMOS
Parallel
Interface
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
DOUT+
DOUT-
C7
Serial
LVDS
Interface
R1
TCLK
GPO
3.3V
C8
TPWDNB
DEN
VSSDR
VSSPT0
VSSPT1
VSST
VSSL
VSSIT
VSS
TRFB
TPWDNB = System GPO
DEN = High (ON)
TRFB = High (Rising edge)
VODSEL = Low (400mV)
PRE = Rpre
RESRVD = Low
DCAOFF = Low
DCBOFF = Low
DCAOFF
DCBOFF
C1 to C3 = 0.1 mF
C4 to C6 = 0.01 mF
C7 = 100 nF; 50WVDC, NPO or X7R
C8 = 100 nF; 50WVDC, NPO or X7R
R1 = 100W
VODSEL
PRE
RESRVD
R2
R2 = Open (OFF) or Rpre í 3 kW (ON) (cable specific)
Copyright © 2017, Texas Instruments Incorporated
Figure 22. DS90C241 Typical Application Connection
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Typical Application (continued)
DS90C124 (DES)
3.3V
VDDIR
VDDPR0
VDDPR1
3.3V
C5
C6
C8
C1
C3
C2
C4
VDDOR1
VDDOR2
VDDOR3
VDDR0
VDDR1
C7
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
C1 to C8 = 0.1 mF to 0.01 mF
C9 = 100 nF; 50 WVDC, NPO or X7R
C10 = 100 nF; 50 WVDC, NPO or X7R
R1 = 100W
C9
RIN+
RIN-
Serial
LVDS
Interface
ROUT8
ROUT9
R1
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
LVCMOS
Parallel
Interface
C10
3.3V
GPO
RPWDNB
REN
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RRFB
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RESRVD = Low
RESRVD
RCLK
LOCK
Copyright © 2017, Texas Instruments Incorporated
Figure 23. DS90C124 Tyical Application Connection
9.2.1 Design Requirements
For the typical design application, use the following as input parameters:
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 22 and Figure 23.
24
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Typical Application (continued)
9.2.2 Detailed Design Procedure
Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide
low-noise power to the device. Good layout practice also separates high frequency or high-level inputs and
outputs to minimize unwanted stray noise, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mil) for power and ground sandwiches. This arrangement uses the
plane capacitance for the PCB power system and has low-inductance, which has proven effectiveness especially
at high frequencies, and makes the value and placement of external bypass capacitors less critical. External
bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use values
in the range of 0.01 µF to 10 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. The voltage rating of
the tantalum capacitors must be at least 5 times the power supply voltage being used.
MLCC surface mount capacitors are recommended due to their smaller parasitic properties. When using multiple
capacitors per supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommended at the
point of power entry. This is typically in the 50 µF to 100 µF range and smooth low frequency switching noise. TI
recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with through on both ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as
0603 or 0805, is recommended for external bypass. A small body sized capacitor has less inductance. The user
must pay attention to the resonance frequency of these external bypass capacitors, usually in the range from 20
MHz to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance
between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use
two vias from power and ground pins to the planes, reducing the impedance at high frequency. Use at least a
four layer board with a power and ground plane. Place LVCMOS signals away from the LVDS lines to prevent
coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω are typically
recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as
common mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
9.2.2.1 Noise Margin
The deserializer noise margin is the amount of input jitter (phase noise) that the deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
•
•
•
Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise)
Media: ISI, VCM noise
Deserializer: VCC noise
For a graphical representation of noise margin, see Figure 18.
9.2.2.2 Transmission Media
The serializer and deserializer can be used in point-to-point configuration, through a PCB trace, or through
twisted pair cable. In a point-to-point configuration, the transmission media requires termination at both ends of
the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ω. Use
cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most
applications that involve cables, the transmission distance is determined on data rates involved, acceptable bit
error rate and transmission medium.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver Input Tolerance in Switching Characteristics –
Deserializer and the Differential Threshold Voltage specifications in Electrical Characteristics define the
acceptable data eye opening. A differential probe must be used to measure across the termination resistor at the
DS90C124 inputs. Figure 24 illustrates the eye opening and relationship to the receiver input tolerance and
differential threshold voltage specifications.
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Typical Application (continued)
Ideal Data Bit
End
Ideal Data Bit
Beginning
Minimum Eye
Width
≥ V - V
TH TL
RxIN_TOL -L
RxIN_TOL -R
t
BIT
(1UI)
Figure 24. Receiver Input Eye Opening
9.2.2.3 Live Link Insertion
The serializer and deserializer devices support live pluggable applications. The automatic receiver lock to
random data plug and go hot insertion capability allows the DS90C124 to attain lock to the active data stream
during a live insertion event.
9.2.3 Application Curves
Figure 25, Figure 26, and Figure 27 are scope shots with PCLK = 25 MHz into the DS90C241 with a 1010...
pattern on the DIN[23:0] inputs. The scope was triggered on the input PCLK.
Figure 25. Input PCLK = 25 MHz and Associated DOUT
Serial Stream
Figure 26. Input PCLK = 25 MHz and Associated DOUT
Serial Stream With Pre-Emphasis
Figure 27. Input PCLK = 25 MHz and Associated DOUT Serial Stream With VODSEL = H
26
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Typical Application (continued)
Figure 28, Figure 29, and Figure 30 are scope shots with PCLK = 33 MHz into the DS90C241 with a 1010...
pattern on the DIN[23:0] inputs. The scope was triggered on the input PCLK.
Figure 28. Input PCLK = 33 MHz and Associated DOUT
Serial Stream
Figure 29. Input PCLK = 33 MHz and Associated DOUT
Serial Stream With Pre-Emphasis
t/[Y
5hÜÇ+ꢀ-
wꢀ ëh5=I
(differenꢁial)
Figure 30. Input PCLK = 33 MHz and Associated DOUT Serial Stream With VODSEL = H
10 Power Supply Recommendations
An all CMOS design of the serializer and deserializer makes them inherently low power devices. Additionally, the
constant current source nature of the LVDS outputs minimize the slope of the speed versus ICC curve of CMOS
designs.
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS SERDES devices must be designed to provide low-noise power
feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power and ground sandwiches. This arrangement provides
plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially
effective at high frequencies, and makes the value and placement of external bypass capacitors less critical.
External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use
values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage
rating of the tantalum capacitors must be at least 5 times the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50-µF to 100-µF range and smooth low frequency switching noise. TI recommends
connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to
the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass
capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 MHz to 30 MHz range. To provide effective
bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins
to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Configuration and Functions typically provide guidance on which circuit blocks are connected to
which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits
such as PLLs.
Use at least a four layer board with a power and ground plane. Place LVCMOS (LVTTL) signals away from the
LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of
100 Ω are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications, termination must be placed at
both ends of the devices. Nominal value is 100 Ω to match the line’s differential impedance. Place the resistor as
close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting stub
between the termination resistor and device.
11.1.1 LVDS Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER© Operation and Applications Guide (SNLA035) for full details.
•
•
Use 100-Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS/LVTTL signal
•
•
•
•
•
Minimize the number of vias
Use differential connectors when operating above 500-Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual available in PDF format from the TI web
site at: www.ti.com/lvds.
28
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
11.2 Layout Example
Figure 31 shows the input LVCMOS traces and output high-speed, 100-Ω differential traces from the DS90C241
EVM.
Figure 31. DS90C241 Layout Example from DS90C241 EVM
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
Layout Example (continued)
Figure 32 shows the input high-speed, 100-Ω differential traces and the output LVCMOS traces and from the
DS90C124 EVM.
Figure 32. DS90C124 Layout Example from DS90C124 EVM
30
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
Layout Example (continued)
Figure 33 shows the power decoupling from the DS90C241 EVM.
Figure 33. DS90C241 Example Layout of Power Decoupling from EVM
Figure 34 shows the power decoupling from the DS90C124 EVM.
Figure 34. DS90C124 Example Layout of Power Decoupling from EVM
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
AN-1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (SNLA053)
AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
AN-905 Transmission Line RAPIDESIGNER© Operation and Applications Guide (SNLA035)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DS90C124
DS90C241
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
DS90C124, DS90C241
www.ti.com
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2005–2017, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: DS90C124 DS90C241
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90C124IVS/NOPB
DS90C124IVSX/NOPB
DS90C124QVS/NOPB
DS90C124QVSX/NOPB
DS90C241IVS/NOPB
DS90C241IVSX/NOPB
DS90C241QVS/NOPB
DS90C241QVSX/NOPB
ACTIVE
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
PFB
48
48
48
48
48
48
48
48
250
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
DS90C124
IVS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PFB
1000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
SN
SN
SN
SN
SN
SN
SN
DS90C124
IVS
PFB
DS90C124
QVS
PFB
DS90C124
QVS
PFB
DS90C241
IVS
PFB
DS90C241
IVS
PFB
DS90C241
QVS
PFB
DS90C241
QVS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS90C124, DS90C124-Q1, DS90C241, DS90C241-Q1 :
Catalog: DS90C124, DS90C241
•
Automotive: DS90C124-Q1, DS90C241-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C124IVSX/NOPB
DS90C124QVSX/NOPB
DS90C241IVSX/NOPB
DS90C241QVSX/NOPB
TQFP
TQFP
TQFP
TQFP
PFB
PFB
PFB
PFB
48
48
48
48
1000
1000
1000
1000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
2.2
2.2
2.2
2.2
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90C124IVSX/NOPB
DS90C124QVSX/NOPB
DS90C241IVSX/NOPB
DS90C241QVSX/NOPB
TQFP
TQFP
TQFP
TQFP
PFB
PFB
PFB
PFB
48
48
48
48
1000
1000
1000
1000
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS90C124IVS/NOPB
DS90C124QVS/NOPB
DS90C241IVS/NOPB
DS90C241QVS/NOPB
PFB
PFB
PFB
PFB
TQFP
TQFP
TQFP
TQFP
48
48
48
48
250
250
250
250
10 x 25
10 x 25
10 x 25
10 x 25
150
150
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
Pack Materials-Page 3
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明