DS90C185SQ/NOPB [TI]
低功耗 FPD 链接 (LVDS) 串行器 | NJV | 48 | -10 to 70;
| 型号： | DS90C185SQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗 FPD 链接 (LVDS) 串行器 | NJV | 48 | -10 to 70 驱动 光电二极管 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总19页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 11, 2012
DS90C185
Low Power 1.8V FPD-Link (LVDS) Serializer
General Description
Features
The DS90C185 is a Low Power Serializer for portable battery
powered applications that reduces the size of the RGB inter-
face between the host GPU and the Display.
Typical power 50mW @ 75 MHz pclk
■
Drives up to 1400 x 1050 @ 60 Hz (SXGA+) Displays
2.94 Gbps of throughput
■
■
■
■
■
■
■
■
24 bit RGB plus three video control signals are serialized and
translated to LVDS compatible levels and sent as a 4 data +
clock (4D+C) reduced width LVDS compatible interface. The
LVDS Interface is compatible with FPD-Link (1) deserializers
and many LVDS based displays. These interfaces are com-
monly supported in LCD modules with “LVDS” or FPD-Link /
FlatLink single-pixel input interfaces.
Two operating modes: 24 bit and 18 bit RGB
25 to 105 MHz Pixel Clock support
Single 1.8V Supply
Sleep Mode
Spread Spectrum Clock compatibility
Small 6mm x 6mm x 0.8mm QFN package
Displays up to 1400 x 1050 @ 60 fps are supported with
24bpp in color depth. 18bpp may also be supported by a ded-
icated mode with a 3D+C output. Power Dissipation is mini-
mized by the full LVCMOS design and 1.8V powered core and
VDDIO rails.
Applications
eBooks
■
■
■
■
Media Tablet Devices
The DS90C185 is offered in the small 48 pin QFN package
and features single 1.8V supply operation for minimum power
dissipation (50mW typ).
Netbooks
Portable Display Monitors
System Diagram
30151590
Ordering Information
Order Number
Package Description
Package ID
Supplied As
DS90C185SQE/NOPB
48–pin LLP, 6.0 x 6.0 x 0.8 mm, 0.4 mm pitch
SQF48A
250 units on Tape and Reel
1000 units on Tape and
Reel
DS90C185SQ/NOPB
DS90C185SQX/NOPB
48–pin LLP, 6.0 x 6.0 x 0.8 mm, 0.4 mm pitch
48–pin LLP, 6.0 x 6.0 x 0.8 mm, 0.4 mm pitch
SQF48A
SQF48A
2500 units on Tape and
Reel
© 2012 Texas Instruments Incorporated
301515 SNLS402C
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Functional Block Diagram
30151501
Connection Diagram
30151591
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2
DS90C185 Pin Descriptions
Pin Name
I/O
No.
Description
1.8 V LVCMOS VIDEO INPUTS
D27 – D21,
D20,
I
22 – 16, Data input pins.
14, This includes: 8 Red, 8 Green, 8 Blue, and 3 video control lines and a general purpose or
D19 – D14,
D13 – D9,
D8 – D1,
D0
12 – 7, L/R control bit. Includes pull down.
5 – 1,
47 – 40,
38
CLK
I
6
Clock input.
Includes pull down.
LVDS VIDEO OUTPUTS
TxOUT0 –/+,
TxOUT1 –/+,
TxOUT2 –/+,
TxOUT3 –/+,
O
36, 35
34, 33
32, 31
28, 27
LVDS Output Data — Expects 100 Ω DC load.
TxCLK OUT -/+
O
30, 29
LVDS Output Clock — Expects 100 Ω DC load.
1.8 V LVCMOS CONTROL INPUTS
R_FB
I
I
I
23
26
39
LVCMOS Ievel programmable strobe select
1 = Rising Edge Clock
0 = Falling Edge Clock — default
Includes pull down.
18B_Mode
VOD_SEL
Mode Configuration Input
1 = 3D+C (18 bit RGB mode)
0 = 4D+C (24 bit RGB mode) — default
Includes pull down.
VOD Select Input
0 = Reduced VOD (lower power)
1 = Normal VOD — default
Includes pull down.
PDB
I
37
Power Down Bar(Sleep) Input
1 = ACTIVE
0 = Sleep State (low power idle) — default
Includes pull down.
POWER and GROUND
VDD
P
P
P
G
G
48
25
13
Digital power input
LVDS driver power input
PLL power input
VDDTX
VDDPLL
GND
15, 24 Ground pins
Connect DAP to ground plane
DAP
3
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ESD Ratings
HBM
CDM
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
>4kV
>1.25kV
>250V
MM
Supply Voltage (VDD
)
−0.3V to +2.5V
−0.5V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
Recommended Operating
Conditions
LVCMOS Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
Junction Temperature
Storage Temperature
Min Nom Max Units
Continuous
+150°C
−65°C to +150°C
Supply Voltage (VDD
Operating Free Air
Temperature (TA)
)
1.71 1.8 1.89
V
−10 +22 +70
°C
Lead Temperature
(Soldering, 4 sec)
Supply Noise Voltage
(VDD
<90 mVPP
+260°C
)
Package Derating: θJA
26.6 °C/W above +22°C
Differential Load
Impedance
Input Clock Frequency 25
80 100
120
105
Ω
MHz
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
0.65 *
VDD
VDD
GND
0.35*V
V
DD
VIN = 0V or VDD = 1.71 V to 1.89 V
–10
±1
+10
μA
mV
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
VODSEL = H
VODSEL = L
160
300
450
RL = 100Ω
Figure 3
(320) (600) (900) (mVP-P
115 180 300 mV
(230) (360) (600) (mVP-P
)
)
Change in VOD between complimentary
output states
50
mV
ΔVOD
RL = 100Ω
VOS
Offset Voltage
0.8
0.9
1.0
50
V
Change in VOS between complimentary
output states
mV
ΔVOS
IOS
IOZ
SERIALIZER SUPPLY CURRENT
Output Short Circuit Current
–45
−35
±1
−25
±10
mA
mA
VOUT = 0V, RL = 100Ω
Output LVDS Driver Power Down Current PDB = 0V
IDDT1
Serializer Supply Current
Worst Case
Checkerboard pattern,
RL = 100Ω,
f = 105 MHz
60
85
mA
18B_MODE = L,
VOD_SEL = H,
VDD = 1.89
Figure 1
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4
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDDTG
Serializer Supply Current
16 Grayscale
f = 75 MHz
31
mA
RL = 100Ω,
18B_MODE = L,
VOD_SEL = L,
VDD = 1.8
16 Grayscale Pattern
41
28
36
33
45
29
38
18
mA
mA
mA
mA
mA
mA
mA
μA
RL = 100Ω,
18B_MODE = L,
VOD_SEL = H,
VDD = 1.8
16 Grayscale Pattern
RL = 100Ω,
18B_MODE = H,
VOD_SEL = L,
VDD = 1.8
16 Grayscale Pattern
RL = 100Ω,
18B_MODE = H,
VOD_SEL = H,
VDD = 1.8
16 Grayscale Pattern
IDDTP
Serializer Supply Current
PRBS-7
f = 75 MHz
Figure 11
RL = 100Ω,
18B_MODE = L,
VOD_SEL = L,
VDD = 1.8
PRBS-7 Pattern
RL = 100Ω,
18B_MODE = L,
VOD_SEL = H,
VDD = 1.8
PRBS-7 Pattern
RL = 100Ω,
18B_MODE = H,
VOD_SEL = L,
VDD = 1.8
PRBS-7 Pattern
RL = 100Ω,
18B_MODE = H,
VOD_SEL = H,
VDD = 1.8
PRBS-7 Pattern
IDDZ
Serializer Power Down Current
200
5
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Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
Parameter
Min
1.0
Typ
Max
6.0
Units
ns
TxCLK IN Transition Time (Figure 5)
TxCLK IN Period (Figure 6)
TCIP
9.52
T
40
ns
TCIH
TxCLK IN High Time (Figure 6)
TxCLK IN Low Time (Figure 6)
0.35T 0.5T
0.35T 0.5T
0.65T
0.65T
ns
TCIL
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
Min
Typ
0.18
0.18
1
Max
Units
ns
LVDS Low-to-High Transition Time (Figure 4(Note 5))
LVDS High-to-Low Transition Time (Figure 4(Note 5))
Transmitter Output Pulse Positions Normalized for f = 105 MHz
0.5
0.5
LHLT
ns
TPPOS0
UI
Bit 0
Figure 10
TPPOS1
TPPOS2
TPPOS3
TPPOS4
TPPOS5
TPPOS6
ΔTPPOS
Transmitter Output Pulse Positions Normalized for
Bit 1
2
UI
UI
UI
UI
UI
UI
UI
Transmitter Output Pulse Positions Normalized for
Bit 2
3
Transmitter Output Pulse Positions Normalized for
Bit 3
4
Transmitter Output Pulse Positions Normalized for
Bit 4
5
6
Transmitter Output Pulse Positions Normalized for
Bit 5
Transmitter Output Pulse Positions Normalized for
Bit 6
7
Variation in Transmitter Pulse Position (Bit 6 — Bit
0)
±0.06
TSTC
THTC
TCCJ
Required TxIN Setup to TxCLK IN
Required TxIN Hold to TxCLK IN
Cycle to Cycle Jitter
Figure 6
0
ns
ns
UI
2.5
f = 105 Mhz
0.028
0.035
(Note 5)
TSD
f = 105 MHz
Figure 7
2*TCIP +
10.54
2*TCIP +
13.96
ns
Serializer Propagation Delay
TCCS
TPLLS
TPPD
TxOUT Channel to Channel Skew
Transmitter Phase Lock Loop Set
110
ps
ms
ns
Figure 8
1
Figure 9
(Note 6)
100
Transmitter Power Down Delay
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 1.8 V and TA = +22C unless specified otherwise.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ΔVOD).
Note 4: VOS previously referred as VCM
.
Note 5: Parameter is guaranteed by characterization and is not tested at final test.
Note 6: Parameter is guaranteed by design and is not tested at final test.
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6
AC Timing Diagrams
30151545
FIGURE 1. “Worst Case” Test Pattern (Note 7)
30151544
FIGURE 2. “16 Grayscale” Test Pattern - DS90C185 (Note 8, Note 9)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS I/O.
Note 8: Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16 grayscale test pattern tests device power
consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (CLK).
7
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30151530
FIGURE 3. DS90C185 (Transmitter) LVDS Output Load
30151506
FIGURE 4. DS90C185 (Transmitter) LVDS Transition Times
30151542
FIGURE 5. DS90C185 (Transmitter) Input Clock Transition Time
30151540
FIGURE 6. DS90C185 (Transmitter) Setup/Hold and High/Low Times with R_FB pin = GND (Falling Edge Strobe)
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8
30151512
FIGURE 7. DS90C185 Propagation Delay
30151551
FIGURE 8. DS90C185 (Transmitter) Phase Lock Loop Set Time
30151552
FIGURE 9. Transmitter Power Down Delay
9
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30151543
FIGURE 10. Transmitter LVDS Output Pulse Position Measurement - DS90C185
60
VODSEL = L, 18B = L
VODSEL = H, 18B = L
55
50
45
40
35
30
25
20
VODSEL = L, 18B = H
VODSEL = H, 18B = H
20
40
60
80
100
120
FREQUENCY (MHz)
30151556
FIGURE 11. Typ Current Draw — PRBS-7 Data Pattern
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10
28 bit interface typically assigns 24 bits to RGB color data, 3
bits to video control (HS, VS and DE) and one spare bit can
be ignored, used for L/R signaling or function as a general
purpose bit. The single pixel 24bpp 4D+C LVDS interface
mapping is shown Figure 13. A single pixel 18bpp mode is
also supported by utilizing the 18B_MODE pin. In this config-
uration the TxOUT3 output channel is place in TRI-STATE®
to save power. Its respective inputs are ignored. This mapping
is shown in Figure 12.
LVDS Interface / TFT Color Data
recommended Mapping
Different color mapping options exist. Check with the color
mapping of the Deserializer / TCON device that is used to
ensure compatible mapping for the application. The
DS90C185 supports single pixel interfaces with either 24bpp
or 18bpp color depths.
The DS90C185 provides four LVDS data lines along with an
LVDS clock line (4D+C) for the 28 LVCMOS data inputs. The
30151548
FIGURE 12. DS90C185 LVDS Map — 18B_MODE = H
30151549
FIGURE 13. DS90C185 LVDS Map — 18B_MODE = L
11
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COLOR MAPPING INFORMATION
DS90C187 Input
Color
Note
A defacto color mapping is shown next. Different color map-
ping options exist. Check with the color mapping of the De-
serializer / TCON device that is used to ensure compatible
mapping for the application.
Mapping
D21
D11
D10
D9
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
DE
VS
HS
GP
LSB
MSB
24bpp / MSB on CH3
DS90C187 Input
Color
Note
D8
Mapping
D7
D6
D22
D21
D5
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
DE
VS
HS
GP
MSB
D24
D23
D17
D16
D15
D14
D13
D12
D26
D25
D20
D19
D18
D27
LSB
MSB
D4
D3
D2
D1
D0
LSB
D24
D23
D11
D10
D9
MSB
Data Enable
Vertical Sync
Horizontal Sync
General Purpose
D8
D7
D6
LSB
18bpp
D26
D25
D17
D16
D15
D14
D13
D12
D20
D19
D18
D27
MSB
DS90C187 Input
Color
Mapping
Note
D5
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
DE
VS
HS
MSB
D4
D3
D2
D1
D0
LSB
Data Enable
D11
D10
D9
MSB
Vertical Sync
Horizontal Sync
General
Purpose
D8
D7
24bpp / LSB on CH3
D6
LSB
DS90C187 Input
Color
Note
D17
D16
D15
D14
D13
D12
D20
D19
D18
MSB
Mapping
D5
D4
D3
D2
D1
D0
D22
R7
R6
R5
R4
R3
R2
R1
MSB
Data Enable
Vertical Sync
Horizontal Sync
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12
TABLE 2. Power Down Select
Result
Functional Description
PDB
DS90C185 converts a wide parallel LVCMOS input bus into
FPD-Link LVDS data. The device can be configured to sup-
port RGB-888 (24 bit color) or RGB-666 (18 bit color). The
DS90C185 has several power saving features including: se-
lectable VOD, 18 bit / 24 bit mode select, and a power down
pin control.
0
1
SLEEP Mode (default)
ACTIVE (enabled)
LVDS Outputs
The DS90C185's LVDS drivers are compatible with ANSI/
TIA/EIA-644–A LVDS receivers. The LVDS drivers an output
a power saving low VOD or a higher VOD to enable longer trace
and cable lengths by configuring the VODSEL pin.
In each input pixel clock cycle, data from D[27:0] is serialized
and driven out on TxOUT[3:0] +/- with TxCLKOUT +/-. If
18B_MODE is LOW, then TxOUT3 +/- is powered down and
the corresponding LVCMOS input signals are ignored.
TABLE 3. VOD Select
VODSEL Result
The input pixel clock can range from 25 MHz to 105 MHz,
resulting in a total maximum payload of 700 Mbps (28 bits *
25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver
will operate at a speed of 7 bits per input clock cycle, resulting
in a serial line rate of 175 Mbps to 735 Mbps. TxCLKOUT +/-
will operate at the same rate as CLK with a duty cycle ratio of
57:43.
0
1
±180 mV (360mVpp)
±300 mV (600mVpp)
For more information regarding the electrical characteristics
of the LVDS outputs, refer to the LVDS DC Characteristics
and LVDS Switching Specifications.
Pixel Clock Edge Select (RFB)
18 bit / 24 bit Color Mode (18B)
The RFB pin determines the edge that the input LVCMOS
data is latched on. If RFB is HIGH, input data is latched on
the RISING EDGE of the pixel clock (CLK). If RFB is LOW,
the input data is latched on the FALLING EDGE of the pixel
clock. Note: This can be set independently of receiver’s output
clock strobe.
The 18B pin can be used to further save power by powering
down the 4th LVDS driver in each used bank when the appli-
cation requires only 18 bit color or 3D+C LVDS. Set the 18B
pin to logic HIGH to TRI-STATE® TxOUT3 +/-. For 24 bit color
applications this pin should be set to logic LOW. Note that the
power down function takes priority over the TRI-STATE®
function.
TABLE 1. Pixel Clock Edge
RFB
Result
TABLE 4. Color DepthConfigurations
0
1
FALLING edge
RISING edge
18B_Mode
Result
24bpp, LVDS 4D+C
18bpp, LVDS 3D+C
0
1
Power Management
The DS90C185 has several features to assist with managing
power consumption. The 18B_MODE pin allows the
DS90C185 to power down the unused LVDS driver for
RGB-666 (18 bit color) applications. If no clock is applied to
the CLK pin, the DS90C185 will enter a low power state. To
place the DS90C185 in its lowest power state, the device can
be powered down by driving the PDB pin to LOW.
LVCMOS Inputs
The DS90C185 has 28 data inputs. These inputs are typically
used for 24 or 18 bits of RGB video with 1, 2 or 3 video control
signal (HS, VS and DE) inputs and one spare bit that can be
used for L/R signaling or function as a general purpose bit. All
LVCMOS input pins are designed for 1.8V LVCMOS logic. All
LVCMOS inputs, including clock, data and configuration pins
have an internal pull down resistor to set a default state. If any
LVCMOS inputs are unused, they can be left as no connect
(NC) or connected to ground.
Sleep Mode (PDB)
The DS90C185 provides a power down feature. When the
device has been powered down, current draw through the
supply pins is minimized and the PLL is shut down. The LVDS
drivers are also powered down with their outputs pulled to
GND through 100Ω resistors.
13
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Applications Information
Power Up Sequence
and placement of external bypass capacitors less critical. This
practice is easier to implement in dense pcbs with many lay-
ers and may not be practical in simpler boards. External
bypass capacitors should include both RF ceramic and tan-
talum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the
2.2 uF to 10 uF range. Voltage rating of the tantalum capac-
itors should be at least 5X the power supply voltage being
used.
The VDD power supply pins do not require a specific power on
sequence and can be powered on in any order. However, the
PDB pin should only be set to logic HIGH once the power sent
to all supply pins is stable. Active clock and data inputs should
not be applied to the DS90C185 until all of the input power
pins have been powered on, settled to the recommended op-
erating voltage and the PDB pin has be set to logic HIGH.
The user experience can be impacted by the way a system
powers up and powers down an LCD screen. The following
sequence is recommended:
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. It is recom-
mended to connect power and ground pins directly to the
power and ground planes with bypass capacitors connected
to the plane with vias on both ends of the capacitor.
Power up sequence (DS90C185 PDB input initially LOW):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep
backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t
occur.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
3. Toggle DS90C185 power down pin to PDB = VIH.
4. Enable video source output; start sending black video
data.
5. Send >1ms of black video data; this allows the
DS90C185 to be phase locked, and the display to show
black data first.
6. Start sending true image data.
7. Enable backlight.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
Power Down sequence (DS90C185 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time
specified in the LCD data sheet for the backlight to go
low.
2. Video source output data switch from active video data
to black image data (all visible pixel turn black); drive this
for >2 frame times.
3. Set DS90C185 power down pin to PDB = GND.
4. Disable the video output of the video source.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the LVDS lines to prevent
coupling from the LVCMOS lines to the LVDS lines. Closely
coupled differential lines of 100 Ohms are typically recom-
mended for LVDS interconnect. The closely coupled lines
help to ensure that coupled noise will appear as common
mode and thus is rejected by the receivers. The tightly cou-
pled lines will also radiate less.
5. Remove power from the LCD panel for lowest system
power.
Power Supply Filtering
The DS90C185 has several power supply pins at 1.8V. It is
important that these pins all be connected and properly by-
passed. Bypassing should consist of at least one 0.1µF ca-
pacitor placed on each pin, with an additional 4.7µF – 22µF
capacitor placed on the PLL supply pin (VDDPLL). 0.01µF
capacitors are typically recommended for each pin. Additional
filtering including ferrite beads may be necessary for noisy
systems. It is recommended to place a 0 resistor at the bypass
capacitors that connect to each power pin to allow for addi-
tional filtering if needed. A large bulk capacitor is recommend-
ed at the point of power entry. This is typically in the 50µF —
100µF range.
Information on the QFN (LLP) style package is provided in
Application Note: AN-1187.
LVDS Interconnect Guidlines
See AN-1108 and AN-905 for full details.
•
•
•
•
Use 100Ω coupled differential pairs
Use differential connectors when above 500Mbps
Minimize skew within the pair
Use the S/2S/3S rule in spacings
S = space between the pairs
2S = space between pairs
—
—
—
Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer de-
vices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high fre-
quency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin di-
electrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven es-
pecially effective at high frequencies, and makes the value
3S = space to LVCMOS signals
•
•
Place ground vias next to signal vias when changing
between layers
When a signal changes reference planes, place a bypass
cap and vias between the new and old reference plane
For more tips and detailed suggestions regarding high speed
board layout principles, please consult the LVDS Owner's
Manual at: http://www.ti.com/lvds
www.ti.com
14
Revision
June 08, 2012
•
•
Fixed typo in Figure 12 for bits D14 and D15
Fixed typo in Pin Descriptions for VODSEL. VODSEL = 0
reduced swing and VODSEL = 1 normal LVDS swing now
match Functional Description explanation
15
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead LLP Quad Package
Dimensions in millimeters only
TI Package Number SQF48A
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16
Notes
17
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Notes
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