DS90C187LFE/NOPB [TI]
低功耗双像素 FPD 链接 (LVDS) 串行器 | NLA | 92 | -10 to 70;
| 型号： | DS90C187LFE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗双像素 FPD 链接 (LVDS) 串行器 | NLA | 92 | -10 to 70 驱动 光电二极管 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总21页 (文件大小：1372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 25, 2012
DS90C187
Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer
General Description
Features
The DS90C187 is a Low Power Serializer for portable battery
powered application that reduces the size of the RGB inter-
face between the host GPU and the Display.
100 mW typical power consumption at 185 MHz (SIDO
■
mode)
Drives QXGA/WQXGA class displays
■
■
The DS90C187 Serializer is designed to support dual pixel
data transmission between Host and Flat Panel Display up to
QXGA 2048x1536@60Hz resolutions. The transmitter con-
verts up to 48 bits (Dual Pixel 24 bit color) of 1.8V LVCMOS
data into two channels of 4 data + clock (4D+C) reduced width
interface LVDS compatible data streams.
Three operating modes:
Single Pixel In / Single Pixel Out (SISO), 105 MHz max
Single Pixel In / Dual Pixel Out (SIDO), 185 MHz
Dual Pixel In / Dual Pixel Out (DIDO), 105 MHz
—
—
—
Supports 24 bit RGB, 48 bit RGB
■
■
■
Optional low power mode supports 18 bit RGB, 36 bit RGB
DS90C187 supports 3 modes of operation. In single pixel
mode in/out mode, the device can drive up to SXGA+
1400x1050@60Hz. In this mode, the device converts one
bank of 24 bit RGB data to one channel of 4D+C LVDS data
stream. In single pixel in / dual pixel out mode, the device can
drive up to WUXGA+ 1920x1440@60Hz. In this configura-
tion, the device provides single-to-dual pixel conversion and
converts one bank of 24 bit RGB data into two channels of 4D
+C LVDS streams at half the pixel clock rate. In dual pixel in /
dual pixel out mode, the device can drive up to QXGA
2048x1536@60Hz or up to QSXGA 2560x2048@30Hz. In
this mode, the device converts 2 channels of 24 bit RGB data
into 2 channels of 4D+C LVDS streams. For all the modes,
the device supports 18bpp and 24bpp color.
Supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and 8D+2C
LVDS configurations
Compatible with FPD-Link, and FlatLink Deserializers
1.8V VDDIO & Core Supply
■
■
■
■
■
■
Interfaces directly with 1.8V LVCMOS
Less than 1mW power consumption in Sleep Mode
Spread Spectrum Clock Compatible
Small 7mm x 7mm x 0.9 mm 92–pin dual row QFN
package
Applications
Media Tablet Devices
■
■
■
The DS90C187 is offered in a small 92 pin dual row QFN
package and features single 1.8V supply for minimal power
dissipation.
eBook / Notebooks / Laptops
Portable Display Monitors
Typical Application Diagram
30151690
Single Pixel In Dual Pixel Out (SIDO) Mode
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated
301516 SNLS401A
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Functional Block Diagrams
30151694
30151695
30151696
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2
Connection Diagram
30151691
Ordering Information
Order Number
Package Description
Package ID Supplied As
DS90C187LFE/NOPB 92–pin dual row QFN, 7.0 X 7.0 X 0.9 mm, 0.5 mm pitch LFA92A
DS90C187LF/NOPB 92–pin dual row QFN, 7.0 X 7.0 X 0.9 mm, 0.5 mm pitch LFA92A
DS90C187LFX/NOPB 92–pin dual row QFN, 7.0 X 7.0 X 0.9 mm, 0.5 mm pitch LFA92A
250 units on Tape and Reel
1000 units on Tape and Reel
2500 units on Tape and Reel
3
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DS90C187 Pin Descriptions — Serializer
Pin Name
I/O
No.
Description
1.8V LVCMOS VIDEO INPUTS
INA_[27:21],
INA_[17:9],
INA_[8:0]
I
I
B19–B13,
B9–B1,
B40–B32
Channel A Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
Includes pull down.
INB_[27:21],
INB_[17:14],
INB_[13:9],
INB_[8:0]
A23–A17,
A10–A7,
A5–A1,
Channel B Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
A50–A42
Includes pull down.
HS (INA_18),
VS (INA_19),
DE (INA_20)
I
I
B10,
B11,
B12
Video Control Signal Inputs –
HS = Horizontal Sync, VS = Vertical SYNC, and DE = Data Enable
IN_CLK
A6
Pixel Input Clock
Includes pull down.
1.8V LVCMOS CONTROL INPUTS
MODE0,
MODE1
I
B20,
A25
Mode Control Inputs (MODE1, MODE0)
00 = Single In / Single Out
01 = Single In / Dual Out
10 = Dual In / Dual Out
11 = Reserved
Includes pull down.
RFB
I
I
I
I
A24
A40
A29
A41
Rising / Falling Clock Edge Select Input –
0 = Falling Edge, 1 = Rising Edge
Includes pull down.
PDB
Power Down (Sleep) Control Input –
0 = Sleep (Power Down mode), 1 = device active (enabled)
Includes pull down.
18B
18 bit / 24 bit Control Input –
0 = 24 bit mode, 1 = 18 bit mode
Includes pull down.
VODSEL
VOD Level Select Input –
0 = Low swing, 1 = Normal swing
Includes pull down.
N/C
I
I
A39
no connect pin — leave open
Reserved – Tie to Ground.
RSVD
A11, A12, A16
LVDS OUTPUTS
OA_C+,
OA_C-
O
O
O
O
B28,
A35
Channel A LVDS Output Clock —
Expects 100 Ω DC load.
Channel A LVDS Output Data —
Expects 100 Ω DC load.
Channel B LVDS Output Clock —
Expects 100 Ω DC load.
Channel B LVDS Output Data —
Expects 100 Ω DC load.
OA_[3:0]+,
OA_[3:0]-
B27, B29–B31
A34, A36–A38
OB_C+,
OB_C-
B23,
A30
OB_[3:0]+,
OB_[3:0]-
B21, B24–B26,
A28, A31–A33
POWER and GROUND
VDDTX
VDD
P
P
P
G
G
B22
A14, A26, A51
A13
Power supply for LVDS Drivers, 1.8V.
Power supply pin for core, 1.8V.
Power supply pin for PLL, 1.8V.
Ground pins.
VDDP
GND
DAP
A15, A27, A52
DAP
Connect DAP to Ground plane.
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4
ESD Ratings:
HBM
CDM
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
> ±8 kV
> ±1.25 kV
>±250 V
MM
Supply Voltage (VCC
)
−0.3V to +2.5V
−0.3V to VDD + 0.3V
Recommended Operating
Conditions
LVCMOS Input Voltage
LVDS Driver Output
Voltage
LVDS Output Short Circuit
Duration
Junction Temperature
Storage Temperature
Package Derating: θJA
−0.3V to +3.6V
Min Nom Max Units
Supply Voltage
1.71 1.80 1.89
V
Continuous
+150°C
−65°C to +150°C
Operating Free Air
Temperature (TA)
−10 +25 +70
°C
Differential Load Impedance
Supply Noise Voltage
100 120
80
Ω
35.1°C/W above +22°C
<90 mVp-p
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions
LVCMOS DC SPECIFICATIONS
Min
Typ
Max
Units
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
0.65VDD
GND
VDD
0.35VDD
+10
V
V
VIN = 0V or VDD
=
– 10
±1
µA
1.71 V to 1.89 V
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
VODSEL = VIH
VODSEL = VIL
160
(320)
300
(600)
450
(900)
mV
(mVP-P
RL = 100Ω
Figure 3
)
)
110
180
300
mV
(220)
(360)
(600)
(mVP-P
Change in VOD between
Complimentary Output States
Offset Voltage
50
mV
ΔVOD
VOS
0.8
0.9
1.0
50
V
Change in VOS between
mV
ΔVOS
Complimentary Output States
Output Short Circuit Current
IOS
VOUT = GND, VODSEL = VDD
–45
−35
60
−25
85
mA
mA
SUPPLY CURRENT
IDDT1
IDDT2
IDDT3
Serializer Worst Case Supply
Current
(includes load current)
Checkerboard
pattern,
f = 105 MHz,
MODE[1:0] = 00
(SISO)
RL = 100 Ω,
18B = VIL,
f = 185 MHz,
MODE[1:0] = 01
(SIDO)
95
140
150
mA
mA
VODSEL = VIH,
VDD = 1.89 V,
Figure 1
f = 105 MHz,
MODE[1:0] = 10
(DIDO)
100
5
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDDTP
Serializer Supply Current PRBS-7 MODE[1:0] = 01
18B = VIL,
55
mA
(SIDO)
VODSEL = VIL,
VDD = 1.8
f = 150 MHz,
RL = 100 Ω,
PRBS-7 Pattern
Figure 12
18B = VIL,
75
49
65
53
71
48
63
18
mA
mA
mA
mA
mA
mA
mA
µA
VODSEL = VIH,
VDD = 1.8
18B = VIH,
VODSEL = VIL,
VDD = 1.8
18B = VIH,
VODSEL = VIH,
VDD = 1.8
IDDTG
Serializer Supply Current 16
Grayscale
MODE[1:0] = 01
(SIDO)
f = 150 MHz,
RL = 100 Ω,
16 Grayscale
Pattern
18B = VIL,
VODSEL = VIL,
VDD = 1.8
18B = VIL,
VODSEL = VIH,
VDD = 1.8
18B = VIH,
VODSEL = VIL,
VDD = 1.8
18B = VIH,
VODSEL = VIH,
VDD = 1.8
IDDZ
Power Down Supply Current
PDB = GND
200
Recommended Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
TCIT
Parameter
Min
1.0
Typ
Max
Units
ns
IN_CLK Transition Time
Figure 5
MODE[1:0] = 00 or 10
MODE[1:0] = 01
MODE[1:0] = 00 or 10
MODE[1:0] = 01
Figure 6
T
4.0
2.0
1.0
ns
TCIP
IN_CLK Period
Figure 6
9.53
5.40
0.35T
0.35T
1.5
T
40
ns
T
20
ns
TCIH
TCIL
TXIT
IN_CLK High Time
IN_CLK Low Time
0.5T
0.5T
0.65T
0.65T
0.3T
ns
ns
INA_x & INB_x Transition Time
Figure 5
ns
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
TSTC
Parameter
Min
0
Typ
Max
Units
ns
INn_x Setup to IN_CLK
INn_x Hold from IN_CLK
Figure 6
THTC
2.5
ns
LLHT
LVDS Low-to-High Transition Time
Figure 4(Note 4)
0.18
0.18
0.5
0.5
ns
LHLT
TBIT
LVDS High-to-Low Transition Time
(Note 4)
ns
LVDS Output Bit Width
MODE[1:0] = 00, or 10
MODE[1:0] = 01
1/7 TCIP
2/7 TCIP
ns
ns
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6
Symbol
Parameter
Min
Typ
Max
Units
TPPOS0 Transmitter Output Pulse Positions Normalized Figure 9
1
UI
for Bit 0
TPPOS1 Transmitter Output Pulse Positions Normalized
for Bit 1
2
UI
UI
UI
UI
UI
UI
UI
TPPOS2 Transmitter Output Pulse Positions Normalized
for Bit 2
3
TPPOS3 Transmitter Output Pulse Positions Normalized
for Bit 3
4
TPPOS4 Transmitter Output Pulse Positions Normalized
for Bit 4
5
6
TPPOS5 Transmitter Output Pulse Positions Normalized
for Bit 5
TPPOS6 Transmitter Output Pulse Positions Normalized
for Bit 6
7
Variation in Transmitter Pulse Position (Bit 6 —
Bit 0)
±0.06
ΔTPPOS
TCCS
TJCC
LVDS Channel to Channel Skew
Jitter Cycle-to-Cycle
110
ps
UI
MODE0, MODE1 = 0,
f = 105 MHz,
0.028
0.035
(Note 4)
TPLLS
TPDD
Phase Lock Loop Set (Enable Time)
Powerdown Delay
Figure 7
1
ms
ns
Figure 8
100
(Note 5)
TSD
Latency Delay
MODE0 = 0,
MODE1 = 1 or 0
Figure 10
2*TCIP + 2*TCIP +
10.54 13.96
ns
(Note 4)
TLAT
Latency Delay for Single Pixel In / Dual Pixel MODE0 = 1,
9*TCIP + 9*TCIP +
4.19 6.36
ns
Out Mode
MODE1 = 0
Figure 10
(Note 4)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VDD, VDDTX and VDDP = 1.8V and T A = +25°C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ΔVOD).
Note 4: Parameter is guaranteed by characterization and is not tested at final test.
Note 5: Parameter is guaranteed by design and is not tested at final test.
7
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AC Timing Diagrams
30151675
FIGURE 1. Checker Board Test Pattern (Note 6, Note 8)
30151674
FIGURE 2. “16 Gray Scale” Test Pattern (Falling Edge Clock shown) (Note 7, Note 8)
Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
Note 7: Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16 grayscale test pattern tests device power
consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Note 8: Figures 1, 2 show a falling edge data strobe (IN_CLK).
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8
30151697
FIGURE 3. DS90C187 (Transmitter) LVDS Output Load
30151671
FIGURE 4. LVDS Output Transition Times
30151672
FIGURE 5. LVCMOS Input Transition Times
30151670
FIGURE 6. LVCMOS Input Setup/Hold and Clock High/Low Times (Falling Edge Strobe)
9
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30151681
FIGURE 7. Start Up / Phase Lock Loop Set Time
30151682
FIGURE 8. Sleep Mode / Power Down Delay
30151673
FIGURE 9. LVDS Serial Bit Positions
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10
30151680
FIGURE 10. Single In Dual Out Mode Timing and Latency
30151698
FIGURE 11. Single In Single Out / Dual In Dual Out Latency
11
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110
100
90
VODSEL = L, 18B = L
VODSEL = H, 18B = L
VODSEL = L, 18B = H
VODSEL = H, 18B = H
80
70
60
50
40
30
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
30151692
FIGURE 12. Typ Current Draw — Single In/Dual Out Mode — PRBS-7 Data Pattern
60
VODSEL = L, 18B = L
VODSEL = H, 18B = L
55
50
45
40
35
30
25
20
VODSEL = L, 18B = H
VODSEL = H, 18B = H
20
40
60
80
100
120
FREQUENCY (MHz)
30151693
FIGURE 13. Typ Current Draw — Single In/Single Out Mode — PRBS-7 Data Pattern
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12
LVDS Interface / TFT Color Data Recommended Mapping
Different color mapping options exist. Check with the color
mapping of the Deserializer / TCON device that is used to
ensure compatible mapping for the application. The
DS90C187 supports three modes of operation for single and
dual pixel applications supporting either 24bpp or 18bpp color
depths.
In the Dual Pixel / 24bpp mode, eight LVDS data lines are
provided along with two LVDS clock lines (8D+2C). The De-
serializer may utilize one or two clock lines. The 53 bit inter-
face typically assigns 24 bits to RGB for the odd pixel, 24 bits
to RGB for the even pixel, 3 bits for the video control signals
(HS, VS and DE), 1 bit for odd pixel and 1 bit for even pixel
which can be ignored or used for general purpose data, con-
trol or L/R signaling.
A reduced width input interface is also supported with a Sin-
gle-to-Dual Pixel conversion where the data is presented at
double rate (same clock edge, 2X speed, see Figure 10) and
the DE transition is used is flag the first pixel. Also note in both
8D+2C configurations, the three video control signals are sent
over both the A and B outputs. The DES / TCON may recover
one set, or both depending upon its implementation. The Dual
Pixel / 24bpp 8D+2C LVDS Interface Mapping is shown in
Figure 14.
30151677
A Dual Pixel / 18bpp mode is also supported. In this configu-
FIGURE 15. Dual Pixel / 18bpp LVDS Mapping
ration OA3 and OB3 LVDS output channels are placed in TRI-
STATE® to save power. Their respective inputs are ignored.
(Figure 15)
In the Single Pixel / 24bpp mode, four LVDS data lines are
provided along with a LVDS clock line (4D+C). The 28 bit in-
terface typically assigns 24 bits to RGB color data, 3 bits to
video control (HS, VS and DE) and one spare bit can be ig-
nored, used for L/R signaling or function as a general purpose
bit. The Single Pixel / 24bpp 4D+C LVDS Interface Mapping
is shown in Figure 16.
A Single Pixel / 18bpp mode is also supported. In this config-
uration the OA3 LVDS output channel is placed in TRI-
STATE® to save power. Its respective inputs are ignored.
(Figure 17)
30151679
FIGURE 16. Single Pixel / 24bpp LVDS Mapping
30151678
FIGURE 17. Single Pixel / 18bpp LVDS Mapping
30151676
FIGURE 14. Dual Pixel / 24bpp LVDS Mapping
13
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COLOR MAPPING INFORMATION
Single Pixel Input / 24bpp / LSB on
CH3
A defacto color mapping is shown next. Different color map-
ping options exist. Check with the color mapping of the De-
serializer / TCON device that is used to ensure compatible
mapping for the application.
DS90C187 Input
Color
Note
Mapping
Single Pixel Input / 24bpp / MSB on
CH3
INA_5
INA_4
INA_3
INA_2
INA_1
INA_0
INA_22
INA_21
INA_11
INA_10
INA_9
INA_8
INA_7
INA_6
INA_24
INA_23
INA_17
INA_16
INA_15
INA_14
INA_13
INA_12
INA_26
INA_25
DE
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
DE
VS
HS
GP
MSB
DS90C187 Input
Color
Note
Mapping
INA_22
INA_21
INA_5
INA_4
INA_3
INA_2
INA_1
INA_0
INA_24
INA_23
INA_11
INA_10
INA_9
INA_8
INA_7
INA_6
INA_26
INA_25
INA_17
INA_16
INA_15
INA_14
INA_13
INA_12
DE
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
DE
VS
HS
GP
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
Data Enable*
VS
Vertical Sync
HS
Horizontal Sync
General Purpose
INA_27
Data Enable*
Vertical Sync
Horizontal Sync
VS
HS
INA_27
General
Purpose
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14
DS90C187 Input
Color
Mapping
Note
Single Pixel Input / 18bpp
DS90C187 Input
Color
Note
Mapping
INA_8
INA_7
INA_6
INA_26
INA_25
INA_17
INA_16
INA_15
INA_14
INA_13
INA_12
INB_22
INB_21
INB_5
INB_4
INB_3
INB_2
INB_1
INB_0
INB_24
INB_23
INB_11
INB_10
INB_9
INB_8
INB_7
INB_6
INB_26
INB_25
INB_17
INB_16
INB_15
INB_14
INB_13
INB_12
DE
O_G2
O_G1
O_G0
O_B7
O_B6
O_B5
O_B4
O_B3
O_B2
O_B1
O_B0
E_R7
E_R6
E_R5
E_R4
E_R3
E_R2
E_R1
E_R0
E_G7
E_G6
E_G5
E_G4
E_G3
E_G2
E_G1
E_G0
E_B7
E_B6
E_B5
E_B4
E_B3
E_B2
E_B1
E_B0
DE
INA_5
INA_4
INA_3
INA_2
INA_1
INA_0
INA_11
INA_10
INA_9
INA_8
INA_7
INA_6
INA_17
INA_16
INA_15
INA_14
INA_13
INA_12
DE
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
DE
VS
HS
MSB
LSB
MSB
LSB
MSB
LSB
MSB
Data Enable*
Vertical Sync
Horizontal Sync
VS
HS
Dual Pixel Input / 24bpp
DS90C187 Input
Color
Note
Mapping
INA_22
INA_21
INA_5
INA_4
INA_3
INA_2
INA_1
INA_0
INA_24
INA_23
INA_11
INA_10
INA_9
O_R7
O_R6
O_R5
O_R4
O_R3
O_R2
O_R1
O_R0
O_G7
O_G6
O_G5
O_G4
O_G3
MSB
LSB
Data Enable*
MSB
VS
VS
Vertical Sync
HS
HS
Horizontal Sync
General Purpose
General Purpose
INA_27
INB_27
GP
GP
15
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Dual Pixel Input / Dual Pixel Output
Functional Description
When MODE0 is LOW and MODE1 is set to HIGH, data from
INA_[27:0], HS, VS and DE is serialized and driven out on
OA_[3:0]+/- with OA_C+/-, while data from INB_[27:0], HS,
VS and DE is serializer and driven out on OB_[3:0]+/- with
OB_C+/-. If 18B_MODE is LOW, then OA_3+/- and OB_3+/-
is powered down and the corresponding LVCMOS input sig-
nals are ignored.
DS90C187 converts a wide parallel LVCMOS input bus into
banks of FPD-Link LVDS data. The device can be configured
to support RGB-888 (24 bit color) or RGB-666 (18 bit color)
in three main configurations: single pixel in / single pixel out;
single pixel in / dual pixel out; dual pixel in / dual pixel out. The
DS90C187 has several power saving features including: se-
lectable VOD, 18 bit / 24 bit mode select, and a power down
pin control.
In this configuration IN_CLK can range from 25 MHz to 105
MHz, resulting in a total maximum payload of 1.325 Gbps (53
bits * 25 MHz) to 5.565 Gbps (53 bits * 105 MHz). Each LVDS
driver will operate at a speed of 7 bits per input clock cycle,
resulting in a serial line rate of 175 Mbps to 735 Mbps. OA_C
+/- and OB_C+/- will operate at the same rate as IN_CLK with
a duty cycle ratio of 57:43.
Device Configuration
The MODE0 and MODE1 pins are used to configure the
DS90C187 into the three main operation modes as shown in
the table below.
TABLE 1. Mode Configurations
Pixel Clock Edge Select (RFB)
MODE1
MODE0 CONFIGURATION
The RFB pin determines the edge that the input LVCMOS
data is latched on. If RFB is HIGH, input data is latched on
the RISING EDGE of the pixel clock (IN_CLK). If RFB is LOW,
the input data is latched on the FALLING EDGE of the pixel
clock. Note: This can be set independently of receiver’s output
clock strobe.
0
0
1
0
1
Single Pixel Input /
Single Pixel Output (SISO)
0
1
1
Single Pixel Input /
Dual Pixel Output (SIDO)
Dual Pixel Input /
Dual Pixel Output (DIDO)
TABLE 2. Pixel Clock Edge
RFB
Result
RESERVED
0
1
FALLING edge
RISING edge
Single Pixel Input / Single Pixel Output
When MODE0 and MODE1 are both set to low, data from
INA_[27:0], HS, VS and DE is serialized and driven out on
OA_[3:0]+/- with OA_C+/-. If 18B_MODE is LOW, then OA_3
+/- is powered down and the corresponding LVCMOS input
signals are ignored.
Power Management
The DS90C187 has several features to assist with managing
power consumption. The device can be configured through
the MODE0 and MODE1 control pins to enable only the re-
quired number of LVDS drivers for each application. The
18B_MODE pin allows the DS90C187 to power down the un-
used LVDS driver(s) for RGB-666 (18 bit color) applications
for an additional level of power management. If no clock is
applied to the IN_CLK pin, the DS90C187 will enter a low
power state. To place the DS90C187 in its lowest power state,
the device can be powered down by driving the PDB pin to
LOW.
In this configuration IN_CLK can range from 25 MHz to 105
MHz, resulting in a total maximum payload of 700 Mbps (28
bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS
driver will operate at a speed of 7 bits per input clock cycle,
resulting in a serial line rate of 175 Mbps to 735 Mbps. OA_C
+/- will operate at the same rate as IN_CLK with a duty cycle
ratio of 57:43.
Single Pixel Input / Dual Pixel Output
When MODE0 is HIGH and MODE1 is LOW, data from INA_
[27:0], HS, VS and DE is serialized and driven out on OA_
[3:0]+/- and OB_[3:0]+/- with OA_C+/- and OB_C+/-. If
18B_MODE is LOW, then OA_3+/- and OB_3+/- are powered
down and the corresponding LVCMOS input signals are ig-
nored. The input LVCMOS data is split into odd and even
pixels starting with the odd (first) pixel outputs OA_[3:0]+/-
and then the even (second) pixel outputs OB_[3:0]+/-. The
splitting of the data signals starts with DE (data enable) tran-
sitioning from logic LOW to HIGH indicating active data (see
Figure 10). The number of clock cycles during blanking
must be an EVEN number. This configuration will allow the
user to interface with two FPD-Link receivers or other dual
pixel inputs.
Sleep Mode (PDB)
The DS90C187 provides a power down feature. When the
device has been powered down, current draw through the
supply pins is minimized and the PLL is shut down. The LVDS
drivers are also powered down with their outputs pulled to
GND through 100Ω resistors (not TRI-STATE®).
TABLE 3. Power Down Select
PDB
Result
0
1
SLEEP Mode (default)
ACTIVE (enabled)
LVDS Outputs
The DS90C187's LVDS drivers are compatible with ANSI/
TIA/EIA-644–A LVDS receivers. The LVDS drivers can output
a power saving low VOD, or a high VOD to enable longer trace
and cable lengths by configuring the VODSEL pin.
In this configuration IN_CLK can range from 50 MHz to 185
MHz, resulting in a total maximum payload of 1.4 Gbps (28
bits * 50 MHz) to 5.18 Gbps (28 bits * 185 MHz). Each LVDS
driver will operate at a speed of 7 bits per 2 input clock cycles,
resulting in a serial line rate of 175 Mbps to 647.5 Mbps.
OA_C+/- and OA_B+/- will operate at ½ the rate as IN_CLK
with a duty cycle ratio of 57:43.
TABLE 4. VOD Select
VODSEL Result
0
1
±180 mV (360 mVpp)
±300 mV (600 mVpp)
www.ti.com
16
Any unused LVDS outputs that are not powered down or put
into TRI-STATE® due to the MODE0, MODE1, or 18B pins
should be externally terminated differentially with a 100 ohm
resistor. For example, when driving a timing controller
(TCON) that only requires an 8D + C LVDS interface, rather
than 8D + 2C, the unused clock line should be terminated near
the package of the DS90C187. For more information regard-
ing the output state of unused LVDS drivers, refer to the next
section, 18 bit / 24 bit Color Mode (18B). For more information
regarding the electrical characteristics of the LVDS outputs,
refer to the LVDS DC Characteristics and LVDS Switching
Specifications.
function. So if the device is configured for 18 bit color Single
Pixel In/Single Pixel Out, LVDS channel OB_3+/- will be pow-
ered down and not TRI-STATE®. If an LVDS driver is pow-
ered down, each output terminal is pulled low by a 100 ohm
resistor to ground.
TABLE 5. Color DepthConfigurations
18B
0
Result
24bpp, LVDS 4D+C or 8D+2C
18bpp, LVDS 3D+C or 6D+2C
1
LVCMOS Inputs
18 bit / 24 bit Color Mode (18B)
The DS90C187 has two banks of 24 data inputs, one set of
video control signal (HS, VS and DE) inputs and several de-
vice configuration LVCMOS pins. All LVCMOS input pins are
designed for 1.8V LVCMOS logic. All LVCMOS inputs, in-
cluding clock, data and configuration pins, have an internal
pull down resistor to set a default state. If any inputs are un-
used, they can be left as no connect (NC) or connected to
ground.
The 18B pin can be used to further save power by powering
down the 4th LVDS driver in each used bank when the appli-
cation requires only 18 bit color or 3D+C LVDS. Set the 18B
pin to logic HIGH to TRI-STATE® OA_3+/- and OB_3+/- (if
the device is configured for dual pixel output). For 24 bit color
applications this pin should be set to logic LOW. Note that the
power down function takes priority over the TRI-STATE®
17
www.ti.com
Applications Information
Power Up Sequence
and placement of external bypass capacitors less critical. This
practice is easier to implement in dense pcbs with many lay-
ers and may not be practical in simpler boards. External
bypass capacitors should include both RF ceramic and tan-
talum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the
2.2 uF to 10 uF range. Voltage rating of the tantalum capac-
itors should be at least 5X the power supply voltage being
used.
The VDD power supply pins do not require a specific power on
sequence and can be powered on in any order. However, the
PDB pin should only be set to logic HIGH once the power sent
to all supply pins is stable. Active clock and data inputs should
not be applied to the DS90C187 until all of the input power
pins have been powered on, settled to the recommended op-
erating voltage and the PDB pin has be set to logic HIGH..
The user experience can be impacted by the way a system
powers up and powers down an LCD screen. The following
sequence is recommended:
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. It is recom-
mended to connect power and ground pins directly to the
power and ground planes with bypass capacitors connected
to the plane with vias on both ends of the capacitor.
Power up sequence (DS90C187 PDB input initially LOW):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep
backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t
occur.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency. Some de-
vices provide separate power and ground pins for different
portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate
planes on the PCB are typically not required. Pin Description
tables typically provide guidance on which circuit blocks are
connected to which power pin pairs. In some cases, an ex-
ternal filter many be used to provide clean power to sensitive
circuits such as PLLs.
3. Toggle DS90C187 power down pin to PDB = VIH.
4. Enable video source output; start sending black video
data.
5. Send >1ms of black video data; this allows the
DS90C187 to be phase locked, and the display to show
black data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (DS90C187 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time
specified in the LCD data sheet for the backlight to go
low.
2. Video source output data switch from active video data
to black image data (all visible pixel turn black); drive this
for >2 frame times.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the LVDS lines to prevent
coupling from the LVCMOS lines to the LVDS lines. Closely
coupled differential lines of 100 Ohms are typically recom-
mended for LVDS interconnect. The closely coupled lines
help to ensure that coupled noise will appear as common
mode and thus is rejected by the receivers. The tightly cou-
pled lines will also radiate less.
3. Set DS90C187 power down pin to PDB = GND.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system
power.
Power Supply Filtering
The DS90C187 has several power supply pins at 1.8V. It is
important that these pins all be connected and properly by-
passed. Bypassing should consist of at least one 0.1μF ca-
pacitor placed on each pin, with an additional 4.7μF – 22μF
capacitor placed on the PLL supply pin (VDDPLL). 0.01μF
capacitors are typically recommended for each pin. Additional
filtering including ferrite beads may be necessary for noisy
systems. It is recommended to place a 0 ohm resistor at the
bypass capacitors that connect to each power pin to allow for
additional filtering if needed. A large bulk capacitor is recom-
mended at the point of power entry. This is typically in the
50μF — 100μF range.
Information on the QFN (LLP) style package is provided in
Application Note: AN-1187.
LVDS Interconnect Guidelines
See AN-1108 and AN-905 for full details.
•
•
•
•
Use 100Ω coupled differential pairs
Use differential connectors when above 500Mbps
Minimize skew within the pair
Use the S/2S/3S rule in spacings
S = space between the pairs
2S = space between pairs
—
—
—
Layout Guidelines
3S = space to LVCMOS signals
Circuit board layout and stack-up for the LVDS serializer de-
vices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high fre-
quency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin di-
electrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven es-
pecially effective at high frequencies, and makes the value
•
•
Place ground vias next to signal vias when changing
between layers
When a signal changes reference planes, place a bypass
cap and vias between the new and old reference plane
For more tips and detailed suggestions regarding high speed
board layout principles, please consult the LVDS Owner's
Manual at: http://www.ti.com/lvds
www.ti.com
18
Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions show in millimeters
TI Package Number LFA92A
19
www.ti.com
Notes
www.ti.com
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