DS90C3201 [TI]
3.3V 8MHz 至 135MHz 双路 FPD 链接发送器;
| 型号： | DS90C3201 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V 8MHz 至 135MHz 双路 FPD 链接发送器 光电二极管 |
| 文件： | 总23页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C3201
www.ti.com
SNLS192D –APRIL 2005–REVISED APRIL 2013
DS90C3201 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
Check for Samples: DS90C3201
1
FEATURES
DESCRIPTION
The DS90C3201 is a 3.3V single/dual FPD-Link 10-
bit color transmitter is designed to be used in Liquid
Crystal Display TVs, LCD Monitors, Digital TVs, and
Plasma Display Panel TVs. The DS90C3201 is
designed to interface between the digital video
processor and the display device using the low-
power, low-EMI LVDS (Low Voltage Differential
Signaling) interface. The DS90C3201 converts up to
70 bits of LVCMOS/LVTTL data into ten LVDS data
streams. The transmitter can be programmed
clocking data with rising edge or falling edge clock.
Optional two-wire serial programming allows fine
tuning in development and production environments.
At a transmitted clock frequency of 135 MHz, 70 bits
of LVCMOS/LVTTL data are transmitted at an
effective rate of 945 Mbps per LVDS channel. Using
a 135 MHz clock, the data throughput is 9.45Gbit/s
(945Mbytes/s). This allows the dual 10-bit LVDS
Transmitter to support HDTV resolutions.
2
•
•
•
•
Up to 9.45Gbit/s data throughput
8 MHz to 135 MHz input clock support
Supports up to QXGA panel resolutions
Supports HDTV resolutions and frame rates up
to 1920 x 1080p
•
•
•
•
•
LVDS 30-bit, 24-bit or 18-bit color data outputs
Supports single pixel and dual pixel interfaces
Supports spread spectrum clocking
Two-wire serial communication interface
Programmable clock edge and control strobe
select
•
•
•
•
Power down mode
+3.3V supply voltage
128-pin TQFP
Compliant to TIA/EIA-644-A-2001 LVDS
Standard
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
DS90C3201
SNLS192D –APRIL 2005–REVISED APRIL 2013
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Block Diagram
7
7
TXOA [6:0]
TXOB[6:0]
TXOC [6:0]
TXOD[6:0]
TXOE[6:0]
TXEA[6:0]
TXEB[6:0]
TXEC[6:0]
TXED[6:0]
TXEE[6:0]
TCLKIN
TXOA-/+
TXOB-/+
TXOC-/+
TXOD-/+
TXOE-/+
TXEA-/+
TXEB-/+
TXEC-/+
TXED-/+
TXEE-/+
TCLKOUT -/+
7
7
7
7
7
7
7
7
PLL
RFB
PWDNB
MODE0
MODE1
S2CLK
S2DAT
Figure 1. Transmitter Block Diagram
Typical Application Diagram
Host
(PC, Graphics Board, Video Processor)
Display
LVDS
(LCD Monitor, LCD TV, Digital TV)
5 Pairs
DE
DE
Pixel Data
Pixel Data
5 Pairs
DS90C3201
FPD-Link
Transmitter
DS90C3202
FPD-Link
Receiver
Clock
HSYNC
VSYNC
Clock
HSYNC
VSYNC
Digital
Display
Video
Source
LVDS Clock
2-Wire Serial
Interface
Figure 2. LCD Panel Application Diagram
Functional Description
The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to
transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface
between the digital video processor and the display using a LVDS interface. The DS90C3201 transmitter
serializes 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals
(HSYNC, VSYNC, DE and two user-defined signals) along with clock signal to 10 channels of LVDS signals and
transmits them. The DS90C3202 receiver converts 10 channels of LVDS signals into parallel signals and outputs
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SNLS192D –APRIL 2005–REVISED APRIL 2013
2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals (HSYNC,
VSYNC, DE and two user-defined signals) along with clock signal. The dual high speed LVDS channels supports
single pixel in-single pixel out and dual pixel in-dual pixel out transmission modes. The FPD-Link chipset is
suitable for a variety of display applications including LCD Monitors, LCD TV, Digital TV, and DLP TV, and
Plasma Display Panels.
Using a true 10-bit color depth system, the 30-bit RGB color produces over 1.07 billion colors to represent High
Definition (HD) displays in their most natural color, surpassing the maximum 16.7 million colors achieved by 6/8-
bit color conventionally used for large-scale LCD televisions and LCD monitors.
LVDS TRANSMITTER
The LVDS Transmitter serializes LVCMOS/LVTTL RGB video data and control signal timing into LVDS data
streams.
SINGLE PIXEL AND DUAL PIXEL INTERFACE
The DS90C3201 LVDS ports support two modes: Single Pixel mode (30-bit LVDS output) and Dual Pixel mode
(2 x 30-bit LVDS output). For Single Pixel mode, the Odd LVDS ports for 10-bit RGB data are utilized. For the
Dual Pixel mode, both Odd and Even LVDS ports are utilized for 10-bit RGB data.
SELECTABLE INPUT DATA STROBE
The Transmitter input data edge strobe can be latched on the rising or falling edges of input clock signal. The
dedicated RFB pin is used to program input strobe select on the rising edge of TCLK IN or the falling edge of
TCLK IN.
2-WIRE SERIAL COMMUNICATION INTERFACE
Optional Two-wire serial interface programming allows fine tuning in development and production environments.
The Two-wire serial interface provides several capabilities to reduce EMI and to customize output timing. These
capabilities are selectable/programmable via Two-wire serial interface: Programmable LVDS Swing Control,
Adjustable Input Setup/Hold Control, Input/Output Channel Control.
PROGRAMMABLE LVDS SWING CONTROL
Programmable LVDS amplitude (VOD) and LVDS offset voltage (VOS) of the differential signals can be adjusted
for better impedance matching for noise and EMI reduction. The low level LVDS swing mode and offset voltage
can be controlled via Two-wire serial interface.
ADJUSTABLE INPUT SETUP/HOLD CONTROL
Programmable LVCMOS/LVTTL Data Input Setup and Hold Times can be adjusted with respect to TCLK IN for
convenient interface with a variety of graphic controllers and video processors. Feature is controlled via Two-wire
serial interface.
INPUT/OUTPUT CHANNEL CONTROL
Full independent control for input/output channels can be disabled to minimize power supply line noise and
overall power dissipation. Feature is configured via Two-wire serial interface.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VDD
)
−0.3V to +4V
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
Continuous
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
LVDS Output Voltage
LVDS Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 10 seconds)
Maximum Package Power Dissipation Capacity at 25°C
Package Derating
128 TQFP Package
1.4W
25.6mW/°C above +25°C
> 2 kV
HBM, 1.5kΩ, 100pF
EIAJ, 0Ω, 200pF
ESD Rating
> 200 V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Min
3.15
0
Nom
3.3
Max
3.6
Unit
V
Supply Voltage (VDD
)
Operating Free Air Temperature (TA)
+25
+70
±100
VDD
135
125
°C
Supply Noise Voltage (VP-P
Transmitter Input Range
Input Clock Frequency (f)
)
mVP-P
V
0
8
MHz
ns
TCLKIN Period (TCIP
)
7.4
(1) (2) (3)
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LVCMOS/LVTTL DC SPECIFICATIONS (Tx inputs, control inputs)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
0
VDD
0.8
V
V
ICL = −18mA
0V ≤ VIN ≤ VDD
VIN = 0V
−0.8
0
−1.5
+10
V
µA
µA
−10
LVDS TRANSMITTER DC SPECIFICATIONS
VOD
Differential Output Voltage
(Programmable register)
RL = 100Ω, Register addr 28d/1ch
bit [5] (TXE) = 0b,
bit [4] (TXO) = 0b (Default)
200
400
620
400
50
mV
mV
mV
RL = 100Ω, Register addr 28d/1ch
bit [5] (TXE) = 1b,
bit [4] (TXO) = 1b
100
250
ΔVOD
Change in VOD between
RL = 100Ω
complimentary output states
(1) Typical values are given for VDD = 3.3V and T A = +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified.
(3) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage and temperature
ranges. This parameter is functional tested only on Automatic Test Equipment (ATE).
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Electrical Characteristics (1) (2) (3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
VOS
Parameter
Conditions
Min
Typ
Max
Unit
Offset Voltage (Programmable
register)
RL = 100Ω, Register addr 28d/1ch
bit [3:2] (TXE) = 00b,
1.0
1.2
1.5
V
bit [1:0] (TXO) = 00b, (Default)
RL = 100Ω, Register addr 28d/1ch
bit [3:2] (TXE) = 01b,
bit [1:0] (TXO) = 01b
0.8
0.6
1.0
0.8
1.2
1.0
V
V
RL = 100Ω, Register addr 28d/1ch
bit [3:2] (TXE) = 10b,
bit [1:0] (TXO) = 10b
ΔVOS
Change in VOS between
complimentary output states
50
mV
mA
IOS
Output Short Circuit Current
VOUT = 0V
−50
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
ICCTZ
Transmitter Supply Current, Worst
RL = 100Ω,
CL = 5pF,
Worst Case Pattern,
Default Register
Settings
f = 8 MHz
20
65
60
95
mA
mA
Case
(Figure 4, Figure 6)
f = 135 MHz
150
235
(4)
Transmitter Supply Current,
Incremental Test Pattern
RL = 100Ω,
CL = 5pF,
Worst Case Pattern,
Default Register
Settings
f = 8 MHz
15
40
55
90
mA
mA
f = 135 MHz
110
175
(5)
(Figure 5 Figure 6)
Transmitter Supply Current, Power
Down
PDWNB = Low,
RL = 100Ω, CL = 5pF,
2
mA
Default Register Settings
(4) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
(5) The incremental test pattern tests device power consumption for a “typical” LCD display pattern.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
TCIT
Parameter
TCLK IN Transition Time (Figure 8)
Min
Typ
Max
(1)
Unit
ns
TCIP
TCLK IN Period (Figure 9)
TCLK IN High Time (Figure 9)
TCLK IN Low Time (Figure 9)
TxIN Transition Time
7.4
T
125.0
ns
TCIH
0.30TCIP
0.50TCIP
0.50TCIP
0.70TCIP
ns
TCIL
0.30TCIP
0.70TCIP
ns
(1)
(1)
TXIT
ns
TJITRMS
TCLK IN Jitter (RMS)
±200
ps
(1) Less than 5ns or 30% of TCIP, whichever is less.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
LLHT
Parameter
Min
Typ
0.6
0.6
0
Max
1.5
Unit
ns
LVDS Low-to-High Transition Time (Figure 7)
LHLT
LVDS High-to-Low Transition Time (Figure 7)
1.5
ns
(1)
TPPos1
TPPos0
TPPos6
TPPos5
TPPos4
Transmitter Output Pulse Position for bit 1 (1st bit) (Figure 15)
Transmitter Output Pulse Position for bit 0 (2nd bit) (Figure 15)
Transmitter Output Pulse Position for bit 6 (3rd bit) (Figure 15)
Transmitter Output Pulse Position for bit 5 (4th bit) (Figure 15)
Transmitter Output Pulse Position for bit 4 (5th bit) (Figure 15)
−0.2
+0.2
UI
(1)
1 UI − 0.2
2 UI − 0.2
3 UI − 0.2
4 UI − 0.2
1
1 UI + 0.2
2 UI + 0.2
3 UI + 0.2
4 UI + 0.2
UI
(1)
2
UI
(1)
3
UI
(1)
4
UI
(1) A Unit Interval (UI) is defined as 1/7th of an ideal clock period (TCIP/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
(Figure 13)
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Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
TPPos3
TPPos2
TSTC
Parameter
Min
5 UI − 0.2
6 UI − 0.2
1.5
Typ
5
Max
Unit
(1)
Transmitter Output Pulse Position for bit 3 (6th bit) (Figure 15)
Transmitter Output Pulse Position for bit 2 (7th bit) (Figure 15)
5 UI + 0.2
6 UI + 0.2
UI
(1)
6
UI
Required TxIN Setup to TCLK IN (Figure 9)
Register addr 26d/19h bit [2:0] = 000b (Default)
0.69
ns
ns
ns
THTC
Required TxIN Hold to TCLK IN (Figure 9)
Register addr 26d/19h bit [2:0] = 000b (Default)
1.5
0.70
TSTC/THTC
Programmable
adjustment
Register addr 26d/19h bit [2:0] = 001b (Figure 14)
Decrease TSTC ~400ps from Default;
Increase THTC ~400ps from Default
0.5/
1.0
Register addr 26d/19h bit [2:0] = 010b,
Decrease TSTC ~800ps from default;
Increase THTC ~800ps from Default
0/
1.5
ns
ns
ns
ns
ns
ns
Register addr 26d/19h bit [2:0] = 011b,
Decrease TSTC ~1200ps from Default;
Increase THTC ~1200ps from Default
-0.5/
2.0
Register addr 26d/19h bit [2:0] = 111b,
Increase TSTC ~800ps from Default;
Decrease THTC ~800ps from Default
1.5/
0
Register addr 26d/19h bit [2:0] = 110b,
Increase TSTC ~600ps from Default;
Decrease THTC ~600ps from Default
1.4/
0
Register addr 26d/19h bit [2:0] = 101b,
Increase TSTC ~400ps from Default;
Decrease THTC ~400ps from Default
1.1/
0.3
Register addr 26d/19h bit [2:0] = 100b,
Increase TSTC ~200ps from Default;
Decrease THTC ~200ps from Default
0.9/
0.5
TCCD
Transmitter TCLKIN (LVTTL) to CLKOUT
(LVDS) Latency
(Figure 9)
f = 135 MHz
10
20
20
30
ns
ns
ns
ns
ns
ns
ms
ns
(3)
f = 85 MHz
f = 65 MHz
f = 40 MHz
f = 25 MHz
f = 8 MHz
(2)
(3)
(3)
(3)
25
40
40
50
60
70
180
200
10
TPPLS
TPDD
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Powerdown Delay (Figure 11)
100
(2) The typical transmitter TCCD latency is: 1.786*T + 4.19 ns – 2 UI, where T = TCLK IN period.
(3) Specification is ensured by characterization.
Two-Wire Serial Communication Interface
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
fSC
Parameter
Conditions
Min
Typ
Max
Unit
kHz
us
S2CLK Clock Frequency
Clock Low Period
400
SC:LOW
SC:HIGH
SCD:TR
SCD:TF
SU:STA
HD:STA
HD:STO
SC:SD
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
1.5
0.6
Clock High Period
us
S2CLK and S2DAT Rise Time
S2CLK and S2DAT Fall Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Clock Falling Edge to Data
Data to Clock Rising Edge
S2CLK Low to S2DAT Data Valid
0.3
0.3
us
us
0.6
0.6
0.6
0
us
us
us
us
SD:SC
0.1
0.1
us
SCL:SD
0.9
us
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Two-Wire Serial Communication Interface (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Bus Free Time
Conditions
Min
Typ
Max
Unit
BUF
RP = 4.7KΩ, CL = 50pF
13
us
AC Timing Diagrams
SCD:TF
SCD:TR
f
SC
SC:LOW
SC:HIGH
S2CLK
HD:STO
SU:STA
HD:STA
S2DAT
Data in
SD:SC
SC:SD
S2DAT
Data out
SCL:SD
Figure 3. Two-Wire Serial Communication Interface Timing Diagram
Figure 4. “Worst Case” Test Pattern
TCLKIN
TXOA, TXEA
TXOB, TXEB
TXOC, TXEC
TXOD, TXED
TXOE, TXEE
Figure 5. Incremental Test Pattern
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AC Timing Diagrams (continued)
250
Incr. Pattern
(max)
Worst Case
(max)
200
150
100
Worst Case
(typ)
50
Incr. Pattern
(typ)
0
0
20 40
60 80 100 120 140 160
FREQUENCY (MHz)
Figure 6. Typical and Max ICC with Worst Case and Incremental Test Pattern
Figure 7. LVDS Transition Times
80%
80%
20%
20%
TCIT
TCIT
Figure 8. Input Clock Transition Time
TCIP
TCIH
TCIL
TxCLK IN
V
/2
V
/2
DD
DD
TSTC
THTC
TxIN [69:0]
V
/2
V
DD
/2
DD
TCCD
TxCLK OUT-
TxCLK OUT+
0V
Figure 9. Input Setup/Hold Time, High/Low Time, and Clock In to Clock Out Latency
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AC Timing Diagrams (continued)
1.5V
PWDNB
3.15V
V
DD
TPLLS
TCLK IN
VDIFF
= 0V
TCLK OUT
Figure 10. Phase Lock Loop Set Time
1.5V
PWDNB
TxCLK IN
TPDD
VDIFF
TCLK OUT
= 0V
500 mV
GND
Figure 11. Transmitter Powerdown Delay
TxCLK IN
TxIN
RFB = 0
RFB = 1
Figure 12. LVTLL Input Programmable Strobe Select
Ideal Bit Start
Ideal Bit Stop
1 UI = T /7
CIP
Ideal Pulse Width
Figure 13. Serializer Ideal Pulse Width
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AC Timing Diagrams (continued)
RFB=0
RFB=1
Register addr 26d/1ah[2:0]=[000]
Default
V
DD
/2
V
DD
/2
V
DD
/2
V
/2
DD
Register addr 26d/1ah[2:0]=[111]
Increases Setup @ 800 ps
CLK
CLK
CLK
CLK
@ 800 ps
IDS
V
DD
/2
Register addr 26d/1ah[2:0]=[110]
V
/2
DD
Increases Setup @ 600 ps
@ 600 ps
IDS
IDS
IDS
V
DD
/2
V
/2
DD
Register addr 26d/1ah[2:0]=[101]
Increases Setup @ 400 ps
@ 400 ps
V
DD
/2
V
DD
/2
V
Register addr 26d/1ah[2:0]=[100]
Increases Setup @ 200 ps
@ 200 ps
V
/2
/2
DD
DD
Register addr 26d/1ah[2:0]=[001]
Increases Hold @ 400 ps
CLK
@ 400 ps
IDS
V
DD
/2
V
DD
/2
Register addr 26d/1ah[2:0]=[010]
Increases Hold @ 800 ps
CLK
@ 800 ps
IDS
V
DD
/2
V
DD
/2
Register addr 26d/1ah[2:0]=[011]
Increases Hold @ 1200 ps
CLK
@ 1200 ps
IDS
Figure 14. User Programmable Internal Clock Delay Adjustment for Input Data Setup/Hold Optimization
Input Data Sampling Clock (TCLKIDS
)
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AC Timing Diagrams (continued)
TCLK OUT
(Differential)
V
= 0V
V
DIFF
= 0V
DIFF
Previous
cycle
Current
Cycle
Next
cycle
OA1-1
OB1-1
OC1-1
OD1-1
OE1-1
EA1-1
EB1-1
EC1-1
ED1-1
EE1-1
OA0-1
OB0-1
OC0-1
OD0-1
OE0-1
EA0-1
EB0-1
EC0-1
ED0-1
EE0-1
OA6
OB6
OC6
OD6
OE6
EA6
EB6
EC6
ED6
EE6
OA5
OB5
OC5
OD5
OE5
EA5
EB5
EC5
ED5
EE5
OA4
OB4
OC4
OD4
OE4
EA4
EB4
EC4
ED4
EE4
OA3
OB3
OC3
OD3
OE3
EA3
EB3
EC3
ED3
EE3
OA2
OB2
OC2
OD2
OE2
EA2
EB2
EC2
ED2
EE2
OA1
OB1
OC1
OD1
OE1
EA1
EB1
EC1
ED1
EE1
OA0
OB0
OC0
OD0
OE0
EA0
EB0
EC0
ED0
EE0
TXOA+/-
TXOB+/-
TXOC+/-
TXOD+/-
TXOE+/-
TXEA+/-
TXEB+/-
TXEC+/-
TXED+/-
TXEE+/-
(1 UI)
(2 UI)
(3 UI)
(4 UI)
(5 UI)
(6 UI)
(7 UI)
TPPos1
TPPos0
TPPos6
TPPos5
TPPos4
TPPos3
TPPos2
Figure 15. LVDS Input Mapping and Ideal Transmitter Pulse Position
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PIN ASSIGNMENTS
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TXOB5
TXOB6
TXOA0
97
98
99
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RESRVD
MODE1
VSSL
A1
100
VDDL
TXO
TXOA2
TXOA3
TXOA4
TXOA5
TXOA6
VDDT2
VDDT3
VSST2
VSST3
TXEE0
TXEE1
TXEE2
TXEE3
TXEE4
TXEE5
TXEE6
VDDE0
101
102
103
TXOA-
TXOA+
TXOB-
TXOB+
TXOC-
TXOC+
TXOD-
TXOD+
TXOE-
TXOE+
VSSL
104
105
106
107
108
109
110
111
112
VDDL
1
DS90C320
11
3
4
TCLKOUT-
TCLKOUT+
TXEA-
TXEA+
TXEB-
TXEB+
TXEC-
TXEC+
TXED-
TXED+
TXEE-
TXEE+
VSSL
11
115
116
117
0
0
11
11
8
VSSE
9
TXED
TXED1
TXED2
TXED3
TXED4
TXED5
TXED6
TXEC0
TXEC1
120
121
122
123
124
125
126
127
128
VDDL
MODE0
RFB
TXEC
2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 16. DS90C3201 Transmitter
DS90C3201 PIN DESCRIPTIONS
Pin No.
Pin Name
TXEC3
TXEC4
TXEC5
TXEC6
TXEB0
TXEB1
TXEB2
TXEB3
TXEB4
TXEB5
I/O
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
Pin Type
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
Description
1
2
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
3
4
5
6
7
8
9
10
12
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DS90C3201 PIN DESCRIPTIONS (continued)
Pin No.
11
Pin Name
TXEB6
VDDE1
VSSE1
TXEA0
TXEA1
TXEA2
TXEA3
TXEA4
TXEA5
TXEA6
VDDP1
VSSP1
VSSP0
VDDP0
VDDT0
VSST0
TCLKIN
VDDI
I/O
I/P
Pin Type
LVTTL I/P (pulldown)
DIGITAL
Description
LVTTL level data input
12
VDD
GND
I/P
Power supply for digital circuitry
Ground pin for digital circuitry
LVTTL level data input
13
DIGITAL
14
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
PLL
15
I/P
LVTTL level data input
16
I/P
LVTTL level data input
17
I/P
LVTTL level data input
18
I/P
LVTTL level data input
19
I/P
LVTTL level data input
20
I/P
LVTTL level data input
21
VDD
GND
GND
VDD
VDD
GND
I/P
Power supply for PLL circuitry
Ground pin for PLL circuitry
Ground pin for PLL circuitry
Power supply for PLL circuitry
Power supply for logic
22
PLL
23
PLL
24
PLL
25
TX LOGIC
26
TX LOGIC
Ground pin for logic
27
LVTTL I/P (pulldown)
DIGITAL
LVTTL level data clock input
Power supply for digital circuitry
Ground pin for digital circuitry
28
VDD
GND
I/P
29
VSSI
DIGITAL
30
PWDNB
LVTTL I/P (pulldown)
Powerdown Bar (Active LOW)
0 = DEVICE DISABLED
1 = DEVICE ENABLED
31
32
33
S2CLK
S2DAT
RFB
I/P
DIGITAL
Two-wire Serial interface - clock
Two-wire Serial interface - data
I/OP
VDD
DIGITAL
LVTTL I/P (pulldown)
Rising Falling Bar (Figure 12)
0 = FALLING EDGE
1 = RISING EDGE
34
MODE0
I/P
LVTTL I/P (pulldown)
“EVEN” bank enable
0 = LVDS EVEN OUTPUTS DISABLED
1 = LVDS EVEN OUTPUTS ENABLED
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
VDDL
VSSL
VDD
GND
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
VDD
GND
O/P
O/P
O/P
ANALOG
ANALOG
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
ANALOG
ANALOG
LVDS O/P
LVDS O/P
LVDS O/P
Power supply for analog circuitry
Ground pin for analog circuitry
TXEE+
TXEE -
TXED+
TXED -
TXEC+
TXEC -
TXEB+
TXEB -
TXEA+
TXEA -
TCLKOUT+
TCLKOUT -
VDDL
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Power supply for analog circuitry
VSSL
Ground pin for analog circuitry
TXOE+
TXOE -
TXOD+
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
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DS90C3201 PIN DESCRIPTIONS (continued)
Pin No.
54
Pin Name
TXOD -
TXOC+
TXOC -
TXOB+
TXOB -
TXOA+
TXOA -
VDDL
I/O
O/P
O/P
O/P
O/P
O/P
O/P
O/P
VDD
GND
I/P
Pin Type
Description
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Power supply for analog circuitry
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
LVDS O/P
ANALOG
ANALOG
55
56
57
58
59
60
61
62
VSSL
Ground pin for analog circuitry
63
MODE1
LVTTL I/P (pulldown)
“ODD” bank enable
0 = LVDS ODD OUTPUTS DISABLED
1 = LVDS ODD OUTPUTS ENABLED
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
RESRVD
TXOE0
TXOE1
TXOE2
TXOE3
TXOE4
TXOE5
TXOE6
VDDO0
VSSO0
TXOD0
TXOD1
TXOD2
TXOD3
TXOD4
TXOD5
TXOD6
VDDT1
VSST1
TXOC0
TXOC1
TXOC2
TXOC3
TXOC4
TXOC5
TXOC6
VDDO1
VSSO1
TXOB0
TXOB1
TXOB2
TXOB3
TXOB4
TXOB5
TXOB6
TXOA0
I/P
I/P
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
DIGITAL
Tie to VSS for correct functionality
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
Power supply for digital circuitry
Ground pin for digital circuitry
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
Power supply for logic
Ground pin for logic
I/P
I/P
I/P
I/P
I/P
I/P
VDD
GND
I/P
DIGITAL
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
TX LOGIC
I/P
I/P
I/P
I/P
I/P
I/P
VDD
GND
I/P
TX LOGIC
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
DIGITAL
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
Power supply for digital circuitry
Ground pin for digital circuitry
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
I/P
I/P
I/P
I/P
I/P
I/P
VDD
GND
I/P
DIGITAL
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
I/P
I/P
I/P
I/P
I/P
I/P
I/P
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DS90C3201 PIN DESCRIPTIONS (continued)
Pin No.
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Pin Name
TXOA1
TXOA2
TXOA3
TXOA4
TXOA5
TXOA6
VDDT2
VDDT3
VSST2
VSST3
TXEE0
TXEE1
TXEE2
TXEE3
TXEE4
TXEE5
TXEE6
VDDE0
VSSE0
TXED0
TXED1
TXED2
TXED3
TXED4
TXED5
TXED6
TXEC0
TXEC1
TXEC2
I/O
I/P
Pin Type
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
TX LOGIC
Description
LVTTL level data input
I/P
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
Power supply for logic
Power supply for logic
Ground pin for logic
I/P
I/P
I/P
I/P
VDD
VDD
GND
GND
I/P
TX LOGIC
TX LOGIC
TX LOGIC
Ground pin for logic
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
DIGITAL
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
Power supply for digital circuitry
Ground pin for digital circuitry
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
I/P
I/P
I/P
I/P
I/P
I/P
VDD
GND
I/P
DIGITAL
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
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APPLICATION INFORMATION
Two-Wire Serial Communication Interface Description
The DS90C3201 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by
the DS90C3201) and the S2DAT line is bi-directional. DS90C3201 has a fixed 7bit slave address. The address is
not user configurable in anyway.
A zero in front of the register address is required. For example, to access register 0x0Fh, “0F” is the correct way
of accessing the register.
COMMUNICATING WITH THE DS90C3201 CONTROL REGISTERS
There are 32 data registers (one byte each) in the DS90C3201, and can be accessed through 32 addresses. All
registers are predefined as read only or read and write. The DS90C3201 slave state machine does not require
an internal clock and it supports only byte read and write. Page mode is not supported. The 7-bit binary address
is 0111111 All seven bits are hardwired internally.
Reading the DS90C3201 can take place either of three ways:
1. If the location latched in the data register addresses is correct, then the read can simply consist of a slave
address byte, followed by retrieving the data byte.
2. If the data register address needs to be set, then a slave address byte, data register address will be sent
first, then the master will repeat start, send the slave address byte and data byte to accomplish a read.
3. When performing continuous read operations, another write (or read) instruction in between reads needs to
be completed in order for the two-wire serial interface module to read repeatedly.
The data byte has the most significant bit first. At the end of a read, the DS90C3201 can accept either
Acknowledge or No Acknowledge from the Master (No Acknowledge is typically used as a signal for the slave
that the Master has read its last byte).
AC
K
Bus Activity:
Master
Register
Address
Slave Address
Slave Address
A
2
A
1
A
0
A
2
A
1
A
0
S
P
SDA Line
S
0
1
AC
K
AC
K
AC
K
Data
Bus Activity:
DS90C3201
Figure 17. Byte Read
The master must generate a Start by sending the 7-bit slave address plus a 0 first, and wait for acknowledge
from DS90C3201. When DS90C3201 acknowledges (the 1st ACK) that the master is calling, the master then
sends the data register address byte and waits for acknowledge from the slave. When the slave acknowledges
(the 2nd ACK), the master repeats the “Start” by sending the 7-bit slave address plus a 1 (indicating that READ
operation is in progress) and waits for acknowledge from DS90C3201. After the slave responds (the 3rd ACK),
the slave sends the data to the bus and waits for acknowledge from the master. When the master acknowledges
(the 4th ACK), it generates a “Stop”. This completes the “ READ”.
A Write to the DS90C3201 will always include the slave address, data register address byte, and a data byte.
Bus Activity:
Master
Register
Address
Slave
Address
Data
A
2
A
1
A
0
SDA Line
P
S
0
AC
K
AC
K
AC
K
Bus Activity:
DS90C3201
Figure 18. Byte Write
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The master must generate a “Start” by sending the 7-bit slave address plus a 0 and wait for acknowledge from
DS90C3201. When DS90C3201 acknowledges (the 1st ACK) that the master is calling, the master then sends
the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd
ACK), the master sends the data byte and wait for acknowledge from the slave. When the slave acknowledges
(the 3rd ACK), the master generates a “ Stop”. This completes the “WRITE”.
DS90C3201 Two-Wire Serial Interface Register Table
Table 1. DS90C3201 Two-Wire Serial Interface Register Table
Address
0d/0h
1d/1h
2d/2h
3d/3h
4d/4h
5d/5h
6d/6h
R/W
R
RESET
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
Bit #
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Description
Vender ID low byte[7:0] = 05h
Default Value
0000_0101
0001_0011
0010_0111
0110_0111
0000_0000
0000_1000
1000_0111
R
Vender ID high byte[15:8] =13h
Device ID low byte[7:0] = 27h
R
R
Device ID high byte 15:8] = 67h
Device revision [7:0] = 00h to begin with
Low frequency limit, 8Mhz = 8h
R
R
R
High frequency limit 135Mhz = 87h =
0000_0000_1000_0111
7d/7h
8d/8h
R
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:3]
[2:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
R
9d/9h
R
10d/ah
11d/bh
20d/14h
21d/15h
22d/16h
23d/17h
24d/18h
25d/19h
26d/1ah
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LVTTL input delay control for TCLK channel, 000 is Default
which means no delays add to TCLK, two buffer delay per
step adjustment for Tsetup; while single buffer step
adjustment for Thold
[111]: move internal clock early by 4 buffer delays
(increases setup time)
[110]: move internal clock early by 3 buffer delays
(increases setup time)
[101]: move internal clock early by 2 buffer delays
(increases setup time)
[100]: move internal clock early by 1 buffer delays
(increases setup time)
[001]: move internal clock late by 2 buffer delays (increases
hold time)
[010]: move internal clock late by 4 buffer delays (increases
hold time)
[011]: move internal clock late by 6 buffer delays (increases
hold time)
[000]: Default
Reserved
27d/1bh
R/W
PWDN
[7:0]
0000_0000
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Table 1. DS90C3201 Two-Wire Serial Interface Register Table (continued)
Address
R/W
RESET
Bit #
Description
Default Value
28d/1ch
R/W
PWDN
[7]
Vod adjustment for TCLK channel
0000_0000
0: TCLK Vod is the same as TXE EVEN BANK (Default)
1: TCLK Vod is the same as TXO ODD BANK
[6]
[5]
Vos adjustment for TCLK channel
0: TCLK Vos is the same as TXE EVEN BANK (Default)
1: TCLK Vos is the same as TXO ODD BANK
Vod adjustment for TXE EVEN BANK
0: Vod set at 400mV ( Default)
1: Vod set at 250mv
[4]
Vod adjustment for TXO ODD BANK
0: Vod set at 400mV ( Default)
1: Vod set at 250mv
[3:2]
Vos adjustment for TXE EVEN BANK
11: NA
10: LVDS DR O/P Vos set at 0.8V
01: LVDS DR O/P Vos set at 1.0V
00: LVDS DR O/P Vos set at 1.2V (Default)
[1:0]
Vos adjustment for TXO ODD BANK
11: NA
10: LVDS DR O/P Vos set at 0.8V
01: LVDS DR O/P Vos set at 1.0V
00: LVDS DR O/P Vos set at 1.2V (Default)
29d/1dh
30d/1eh
31d/1fh
R/W
R/W
R/W
PWDN
PWDN
PWDN
[7:5]
[4]
Reserved
0000_0000
0000_0000
0000_0000
I/O disable control for TXE EVEN BANK channel E,
1: Disable, 0: Enable (Default)
[3]
[2]
[1]
[0]
I/O disable control for TXE EVEN BANK channel D,
1: Disable, 0: Enable (Default)
I/O disable control for TXE EVEN BANK channel C,
1: Disable, 0: Enable (Default)
I/O disable control for TXE EVEN BANK channel B,
1: Disable, 0: Enable (Default)
I/O disable control for TXE EVEN BANK channel A,
1: Disable, 0: Enable (Default)
[7:5]
[4]
Reserved
I/O disable control for TXO ODD BANK channel E,
1: Disable, 0: Enable (Default)
[3]
[2]
I/O disable control for TXO ODD BANK channel D,
1: Disable, 0: Enable (Default)
I/O disable control for TXO ODD BANK channel C,
1: Disable, 0: Enable (Default)
[1]
I/O disable control for TXO ODD BANK channel B,
1 Disable, 0: Enable (Default)
[0]
I/O disable control for TXO ODD BANK channel A,
1: Disable, 0: Enable (Default)
[7:6]
11: LVDS O/Ps available as long as "NO CLK" is at HIGH
regardless PLL lock or not
10: LVDS O/Ps available after 1K of TCLK cycles detected
& PLL generated strobes are within 0.5UI respect to
REFCLK
01: LVDS O/Ps available after 2K of TCLK cycles detected
00: Default ; LVDS O/Ps available after 1K of TCLK cycles
detected
[5]
0: Default; to select the size of wait counter between 1K or
2K, Default is 1K
[0:4]
Reserved
18
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3201
DS90C3201
www.ti.com
SNLS192D –APRIL 2005–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DS90C3201
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90C3201VS/NOPB
ACTIVE
TQFP
PDT
128
90
RoHS & Green
SN
Level-3-260C-168 HR
0 to 70
DS90C3201VS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS90C3201VS/NOPB
PDT
TQFP
128
90
6 X 15
150
322.6 135.9 7620 20.3
15.4 15.45
Pack Materials-Page 1
MECHANICAL DATA
MPQF013 – NOVEMBER 1995
PDT (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,13
M
0,40
96
0,05
65
64
97
33
128
0,13 NOM
1
32
12,40 TYP
Gage Plane
14,05
SQ
13,95
0,25
16,10
SQ
0,05 MIN
15,90
0°–5°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4087726/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
1
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