DS90C387A [TI]
双像素 LVDS 显示接口/FPD 链接发送器;
| 型号： | DS90C387A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双像素 LVDS 显示接口/FPD 链接发送器 光电二极管 |
| 文件： | 总21页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C387A,DS90CF388A
DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link
Literature Number: SNLS065D
February 2006
DS90C387A/DS90CF388A
Dual Pixel LVDS Display Interface / FPD-Link
General Description
The DS90C387A/DS90CF388A transmitter/receiver pair is
designed to support dual pixel data transmission between
Host and Flat Panel Display up to QXGA resolutions. The
transmitter converts 48 bits (Dual Pixel 24-bit color) of
CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage
Differential Signalling) data streams. At a maximum dual
pixel rate of 112MHz, LVDS data line speed is 784Mbps,
providing a total throughput of 5.7Gbps (714 Megabytes per
second).
vides a reliable interface based on LVDS technology that
delivers the bandwidth needed for high-resolution panels
while maximizing bit times, and keeping clock rates low to
reduce EMI and shielding requirements. For more details,
please refer to the “Applications Information” section of this
datasheet.
Features
n Supports SVGA through QXGA panel resolutions
n 32.5 to 112/170MHz clock support
The LDI chipset is improved over prior generations of FPD-
Link devices and offers higher bandwidth support and longer
cable drive. To increase bandwidth, the maximum pixel clock
rate is increased to 112 MHz and 8 serialized LVDS outputs
are provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects.
n Drives long, low cost cables
n Up to 5.7 Gbps bandwidth
n Pre-emphasis reduces cable loading effects
n Dual pixel architecture supports interface to GUI and
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface
n Transmitter rejects cycle-to-cycle jitter
n 5V tolerant on data and control input pins
n Programmable transmitter data and control strobe select
(rising or falling edge strobe)
The DS90C387A transmitter provides a second LVDS output
clock. Both LVDS clocks are identical. This feature supports
backward compatibility with the previous generation of FPD-
Link Receivers - the second clock allows the transmitter to
interface to panels using a ’dual pixel’ configuration of two
24-bit or 18-bit FPD-Link receivers.
n Backward compatible with FPD-Link
This chipset is an ideal means to solve EMI and cable size
problems for high-resolution flat panel applications. It pro-
n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
Generalized Transmitter Block Diagram
10132002
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS101320
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Generalized Receiver Block Diagram
10132003
Generalized Block Diagrams
10132001
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Derating:
DS90C387 A
18.2mW/˚C above +25˚C
18.2mW/˚C above +25˚C
DS90CF388 A
ESD Rating:
Supply Voltage (VCC
)
−0.3V to +4V
DS90C387A
CMOS/TTL Input Voltage
CMOS/TTL Output
Voltage
−0.3V to +5.5V
>
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
DS90CF388A
6 kV
>
300 V
−0.3V to (VCC + 0.3V)
−0.3V to +3.6V
LVDS Receiver Input
Voltage
>
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
2 kV
>
200 V
LVDS Driver Output
Voltage
−0.3V to +3.6V
Recommended Operating
Conditions
LVDS Output Short
Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature
(Soldering, 4 sec.)
Continuous
+150˚C
Min Nom Max Units
−65˚C to +150˚C
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
3.0
3.3
3.6
V
+260˚C
−10 +25 +70
˚C
V
@
Maximum Package Power Dissipation Capacity 25˚C
100 TQFP Package:
Receiver Input Range
0
2.4
Supply Noise Voltage (VCC
)
100 mVp-p
DS90C387A
2.8W
2.8W
DS90CF388A
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS (Tx inputs, Rx outputs, control inputs and outputs)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
2.0
GND
2.7
VCC
0.8
V
V
VOH
IOH = −0.4 mA
IOH = −2 mA
2.9
2.85
0.1
V
2.7
V
VOL
VCL
IIN
Low Level Output Voltage
Input Clamp Voltage
Input Current
IOL = 2 mA
0.3
−1.5
+15
V
ICL = −18 mA
VIN = 0.4V, 2.5V or VCC
VIN = GND
−0.79
+1.8
0
V
µA
µA
mA
−15
250
IOS
Output Short Circuit Current
VOUT = 0V
−120
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
Change in VOD between
Complimentary Output States
Offset Voltage
RL = 100Ω
345
450
35
mV
mV
∆VOD
VOS
1.125
1.25
1.375
35
V
∆VOS
Change in VOS between
Complimentary Output States
Output Short Circuit Current
Output TRI-STATE® Current
mV
IOS
IOZ
VOUT = 0V, RL = 100Ω
−3.5
1
−10
10
mA
µA
PD = 0V, VOUT = 0V or VCC
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold VCM = +1.2V
+100
mV
mV
µA
Differential Input Low Threshold
Input Current
−100
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
10
10
µA
3
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case
RL = 100Ω, CL = 5 f = 32.5 MHz
115
145
165
210
160
200
230
260
mA
mA
mA
mA
pF,
f = 65 MHz
Worst Case
Pattern
f = 85 MHz
(Figures 1, 3),
DUAL=High
f = 112 MHz
(48-bit RGB)
Transmitter Supply Current
16 Grayscale
100Ω, CL = 5 pF,
16 Grayscale
Pattern
f = 32.5 MHz
f = 65 MHz
f = 85 MHz
f = 112 MHz
92
140
150
170
190
50
mA
mA
mA
mA
µA
100
110
130
4.8
(Figures 2, 3),
DUAL=High
(48-bit RGB)
PD = Low
ICCTZ
Transmitter Supply Current
Power Down
Driver Outputs in TRI-STATE under
Powerdown Mode
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current
Worst Case
CL = 8 pF,
Worst Case
Pattern
f = 32.5 MHz
f = 65 MHz
f = 85 MHz
f = 112 MHz
f = 32.5 MHz
f = 65 MHz
f = 85 MHz
f = 112 MHz
100
150
170
185
45
140
200
220
240
80
mA
mA
mA
mA
mA
mA
mA
mA
µA
(Figures 1, 4),
DUAL = High
(48-bit RGB)
CL = 8 pF,
16 Grayscale
Pattern
Receiver Support Current
16 Grayscale
60
110
130
160
300
(Figures 2, 4),
DUAL = High
(48-bit RGB)
PD = Low
85
110
255
Receiver Supply Current
Power Down
Receiver Outputs stay low
during Powerdown mode.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25˚C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V and ∆V ).
OD
OD
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4
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
TxCLK IN Transition Time (Figure 5)
Min
1.0
Typ
2.0
1.5
T
Max
3.0
Units
ns
TCIT
DUAL=Gnd or Vcc
DUAL=1/2Vcc
1.0
1.7
ns
TCIP
TxCLK IN Period (Figure 6)
DUAL=Gnd or Vcc
DUAL=1/2Vcc
8.928
5.88
0.35T
0.35T
1.5
30.77
15.38
0.65T
0.65T
6.0
ns
ns
TCIH
TCIL
TXIT
TxCLK in High Time (Figure 6)
TxCLK in Low Time (Figure 6)
TxIN Transition Time
0.5T
0.5T
ns
ns
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V
(disabled)
0.14
0.7
ns
LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max)
LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V
(disabled)
0.11
0.16
0.6
0.8
ns
ns
LHLT
LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max)
0.11
1/7 TCIP
2/7 TCIP
0
0.7
ns
ns
ns
ps
ps
ps
ns
ns
ps
ps
ps
ps
ps
ms
ns
TBIT
Transmitter Output Bit Width
DUAL=Gnd or Vcc
DUAL=1/2Vcc
TPPOS
Transmitter Pulse Positions - Normalized
f = 33 to 70 MHz
f = 70 to 112 MHz
−250
−200
+250
+200
0
TCCS
TSTC
THTC
TJCC
TxOUT Channel to Channel Skew
TxIN Setup to TxCLK IN (Figure 6)
TxIN Hold to TxCLK IN (Figure 6)
Transmitter Jitter Cycle-to-cycle (Figures
13, 14) (Note 5), DUAL=Vcc
100
2.7
0
f = 112 MHz
f = 85 MHz
f = 65 MHz
f = 56 MHz
f = 32.5 MHz
85
60
100
75
70
80
100
75
120
110
10
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 8)
Transmitter Powerdown Delay (Figure 10)
100
5
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
1.52
0.5
1.7
0.5
T
Max
2.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
ps
ps
ps
ps
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out
RxCLK OUT Period (Figure 7)
1.0
CHLT
2.0
1.0
RCOP
RCOH
8.928
3.5
30.77
RxCLK OUT High Time (Figure 7)(Note 4)
RxCLK OUT Low Time (Figure 7)(Note 4)
RxOUT Setup to RxCLK OUT (Figure 7)(Note 4)
RxOUT Hold to RxCLK OUT (Figure 7)(Note 4)
f = 112 MHz
f = 85 MHz
f = 112 MHz
f = 85 MHz
f = 112 MHz
f = 85 MHz
f = 112 MHz
f = 85 MHz
4.5
RCOL
RSRC
RHRC
3.5
4.5
2.4
3.0
3.4
4.75
RPLLS
RPDD
RSKM
Receiver Phase Lock Loop Set (Figure 9)
Receiver Powerdown Delay (Figure 11)
Receiver Skew Margin (Figure 12) (Notes 4, 6),
10
1
f = 112 MHz
f = 100 MHz
f = 85MHz
f = 66MHz
170
170
300
300
240
350
350
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested at 112MHz to verify
functional performance.
Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of 3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16). A jitter event of 3ns, represents worse case jump
in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
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AC Timing Diagrams
10132010
FIGURE 1. “Worst Case” Test Pattern
10132011
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
7
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AC Timing Diagrams (Continued)
10132012
FIGURE 3. DS90C387A (Transmitter) LVDS Output Load and Transition Times
10132013
FIGURE 4. DS90CF388A (Receiver) CMOS/TTL Output Load and Transition Times
10132014
FIGURE 5. DS90C387A (Transmitter) Input Clock Transition Time
10132015
FIGURE 6. DS90C387A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
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8
AC Timing Diagrams (Continued)
10132016
FIGURE 7. DS90CF388A (Receiver) Setup/Hold and High/Low Times
10132019
FIGURE 8. DS90C387A (Transmitter) Phase Lock Loop Set Time
10132020
FIGURE 9. DS90CF388A (Receiver) Phase Lock Loop Set Time
9
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AC Timing Diagrams (Continued)
10132021
FIGURE 10. Transmitter Power Down Delay
10132022
FIGURE 11. Receiver Power Down Delay
10132025
C — Setup and Hold Time (Internal data sampling window) defined by RSPOS (receiver input strobe position) min and max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
j
j
j
Cable Skew — typically 10 ps to 40 ps per foot, media dependent
TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
See Applications Informations section for more details.
FIGURE 12. Receiver Skew Margin
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AC Timing Diagrams (Continued)
10132027
FIGURE 13. TJCC Test Setup - DS90C387A
10132028
FIGURE 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter
11
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DS90C387A Pin Descriptions — FPD Link Transmitter
Pin Name
Rn, Gn, Bn,
DE, HSYNC,
VSYNC
AnP
I/O
No.
Description
I
51
TTL level input. This includes: 16 Red, 16 Green, 16 Blue, and 3 control
lines HSYNC, VSYNC, DE (Data Enable).(Note 10)
O
O
I
8
8
1
1
Positive LVDS differential data output.
AnM
Negative LVDS differential data output.
CLKIN
TTL level clock input.
R_FB
I
Programmable data strobe select. Rising data strobe edge selected when
input is high. (Note 10)
R_FDE
I
1
Programmable control (DE) strobe select. Tied high for data active when DE
is high. (Note 10)
CLK1P
CLK1M
PD
O
O
I
1
1
1
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) tri-states the outputs, ensuring low
current at power down. (Note 10)
PLLSEL
PRE
I
I
1
1
PLL range select. This pin must be tied to VCC for auto-range. NC or tied to
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz. (Notes 10, 11)
Pre-emphasis level select. Pre-emphasis is active when input is tied to VCC
through external pull-up resistor. Resistor value determines pre-emphasis
level (see table in application section). For normal LVDS drive level (No
pre-emphasis) leave this pin open (do not tie to ground).(Note 10)
Three-mode select for dual pixel, single pixel, or single pixel input to dual
pixel output operation. Single pixel mode when input is low (only LVDS
channels A0 thru A3 and CLK1 are active) for power savings. Dual mode is
active when input is high. Single in - dual out when input is at 1/2 Vcc. (Note
10)
DUAL
I
1
VCC
I
I
4
6
2
3
3
4
1
Power supply pins for TTL inputs and digital circuitry.
Ground pins for TTL inputs and digital circuitry.
Power supply pin for PLL circuitry.
GND
PLLVCC
PLLGND
LVDSVCC
LVDSGND
CLK2P/NC
I
I
Ground pins for PLL circuitry.
I
Power supply pin for LVDS outputs.
I
Ground pins for LVDS outputs.
O
Additional positive LVDS differential clock output. Identical to CLK1P. No
connect if not used.
CLK2M/NC
O
1
Additional negative LVDS differential clock output. Identical to CLK1M. No
connect if not used.
Note 10: Inputs default to “low” when left open due to internal pull-down resistor.
Note 11: The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time.
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DS90CF388A Pin Descriptions — FPD Link Receiver
Pin Name
AnP
I/O
No.
8
Description
Positive LVDS differential data inputs.
I
I
AnM
8
Negative LVDS differential data inputs.
Rn, Gn, Bn,
DE, HSYNC,
VSYNC
O
51
TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3
control lines— HSYNC (LP), VSYNC (FLM), DE (Data Enable).
RxCLK INP
RxCLK INM
RxCLK OUT
R_FDE
I
I
1
1
1
1
Positive LVDS differential clock input.
Negative LVDS differential clock input.
O
I
TTL level clock output. The falling edge acts as data strobe.
Programmable control (DE) strobe select. Tied high for data active when DE
is high. (Note 10)
PLLSEL
I
1
PLL range select. This pin must be tied to VCC for auto-range. NC or tied to
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz. (Notes 10, 11)
PD
I
1
1
TTL level input. When asserted (low input) the receiver data outputs are low
and clock output is high. (Note 10)
STOPCLK
O
Indicates receiver clock input signal is not present with a logic high. With a
clock input present, a low logic is indicated.
VCC
I
I
I
I
I
I
6
10
1
Power supply pins for TTL outputs and digital circuitry.
Ground pins for TTL outputs and digital circuitry
Power supply for PLL circuitry.
GND
PLLVCC
PLLGND
LVDSVCC
LVDSGND
CNTLE,
CNTLF
2
Ground pin for PLL circuitry.
2
Power supply pin for LVDS inputs.
3
Ground pins for LVDS inputs.
2
No Connect. Make NO Connection to these pins - leave these pins open, do
not tie to ground or VCC
.
13
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LVDS Interface / TFT Data (Color) Mapping
Different color mapping options exist. See National Applica-
only. Also, the DE signal is mapped to two LVDS sub sym-
tion Notes 1127 and 1163 for details.
bols. The DS90CF388A only samples the DE bit on channel
A2. Two FPD-Link receivers may also be used in place of the
DS90CF388A, since the DS90C387A provides two LVDS
clocks. If this is the case, the FPD-Link receiver datasheet
needs to be consulted for recovery mapping information. In
this application, it is possible to recover two signals of: DE,
B17 and B27 from the transmitter.
The LVDS Clock waveshape is shown in Figure 15. Note that
the rising edge of the LVDS clock occurs two LVDS sub
symbols before the current cycle of data. The clock is com-
pose of a 4 LVDS sub symbol HIGH time and a 3 LVDS sub
symbol LOW time. The respective pin (transmitter and re-
ceiver) names are show in Figure 15. As stated above these
names are not the color mapping information (MSB/LSB) but
pin names only.
There are two reserved bits (RES). The DS90CF388A ig-
nores these bits. If using separate FPD-Link receivers, the
corresponding receiver outputs for these two bits should be
left open (NC).
Inputs B17 and B27 are double wide bits. If using the
DS90CF388A, this bits are sampled in the back half of the bit
10132026
FIGURE 15. TTL Data Inputs Mapped to LVDS Outputs 387A/388A
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14
Applications Information
HOW TO CONFIGURE THE DS90C387A AND
TRANSMITTER FEATURES
DS90CF388A FOR MOST COMMON APPLICATION
The transmitter is designed to reject cycle-to-cycle jitter
which may be seen at the transmitter input clock. Very low
cycle-to-cycle jitter is passed on to the transmitter outputs.
This significantly reduces the impact of jitter provided by the
input clock source, and improves the accuracy of data sam-
pling.
1. To configure for single input pixel-to-dual pixel output
application, the DS90C387 “DUAL” pin must be set to 1/2
Vcc=1.65V. This may be implemented using pull-up and
pull-down resistors of 10kΩ. In this configuration, the input
signals (single pixel) are split into odd and even pixel (dual
pixels) starting with the odd (first) pixel outputs A0-to-A3 the
next even (second) pixel outputs to A4-to-A7. The splitting of
the data signal also starts with DE (data enable) transitioning
from logic low to high indicating active data. The "R_FDE"
pin must be set high in this case. The number of clock cycles
during blanking must be an EVEN number. This configura-
tion will allow the user to interface to an LDI receiver
(DS90CF388A) or to two FPD-Link ’notebook’ receivers
(DS90CF384A or DS90CF386).
The transmitter is offered with programmable edge data
strobes for convenient interface with a variety of graphics
controllers. The transmitter can be programmed for rising
edge strobe or falling edge strobe through a dedicated pin. A
rising edge transmitter will inter-operate with a falling edge
receiver without any translation logic.
PRE-EMPHASIS
Pre-Emphasis adds extra current during LVDS logic transi-
tion to reduce the cable loading effects. Pre-emphasis
strength is set via a DC voltage level applied from min to max
(0.75V to Vcc) at the “PRE” pin. A higher input voltage on the
”PRE” pin increases the magnitude of dynamic current dur-
ing data transition. The “PRE” pin requires one pull-up resis-
tor (Rpre) to Vcc in order to set the DC level. There is an
internal resistor network, which cause a voltage drop. Please
refer to the tables below to set the voltage level.
2. To configure for single pixel or dual pixel application using
the DS90C387A/DS90CF388A, the “DUAL” pin must be set
to Vcc (dual) or Gnd (single). In dual mode, the transmitter-
DS90C387A has two LVDS clock outputs enabling an inter-
face to two FPD-Link ’notebook’ receivers (DS90CF384A or
DS90CF386). In single mode, outputs A4-to-A7 and CLK2
are disabled which reduces power dissipation.
The DS90CF388A is able to support single or dual pixel
interface up to 112MHz operating frequency. This receiver
may also be used to interface to a VGA controller with an
integrated LVDS transmitter.
TABLE 1. Pre-Emphasis DC Voltage Level With (Rpre)
Rpre
1MΩ or NC
50kΩ
Resulting PRE Voltage
Effects
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Standard LVDS
9kΩ
50% pre-emphasis
100% pre-emphasis
3kΩ
1kΩ
100Ω
TABLE 2. Pre-Emphasis Needed Per Cable Length
Frequency
PRE Voltage
1.0V
Typical cable length
112MHz
112MHz
80MHz
80MHz
65MHz
56MHz
2 meters
5 meters
2 meters
7 meters
10 meters
10 meters
1.5V
1.0V
1.2V
1.5V
1.0V
Note 12: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating
frequency.
RSKM - RECEIVER SKEW MARGIN
POWER DOWN
RSKM is a chipset parameter and is explained in AN-1059 in
detail. It is the difference between the transmitter’s pulse
position and the receiver’s strobe window. RSKM must be
greater than the summation of: Interconnect skew, LVDS
Source Clock Jitter (TJCC), and ISI (if any). See Figure 12.
Interconnect skew includes PCB traces differences, connec-
tor skew and cable skew for a cable application. PCB trace
and connector skew can be compensated for in the design of
the system. Cable skew is media type and length dependant.
Both transmitter and receiver provide a power down feature.
When asserted current draw through the supply pins is
minimized and the PLLs are shut down. The transmitter
outputs are in TRI-STATE when in power down mode. The
receiver outputs are forced to a active LOW state when in
the power down mode. (See Pin Description Tables). The PD
pin should be driven HIGH to enable the device once VCC is
stable.
15
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cycle-to-cycle basis, is also provided to reduce ISI (Inter-
Symbol Interference). With pre-emphasis and DC balancing,
a low distortion eye-pattern is provided at the receiver end of
the cable. A cable deskew capability has been added to
deskew long cables of pair-to-pair skew of up to +/−1 LVDS
data bit time (up to 80 MHz Clock Rate). These three en-
hancements allow cables 5+ meters in length to be driven
depending upon media and clock rate.
Applications Information (Continued)
DS90C387/DS90CF388
The DS90C387A/CF388A chipset is electrically similar to the
DS90C387/CF388. The DS90C387/CF388 is intended for
improved support of longer cable drive. Cable drive is en-
hanced with a user selectable pre-emphasis feature that
provides additional output current during transitions to coun-
teract cable loading effects. Optional DC balancing on a
Configuration Table
TABLE 3. Transmitter / Receiver configuration table
Condition Configuration
R_FB = VCC
Pin
R_FB (Tx only)
Rising Edge Data Strobe
Falling Edge Data Strobe
Active data DE = High
Active data DE = Low
R_FB = GND
R_FDE = VCC
R_FDE = GND
DUAL=VCC
R_FDE (both Tx and Rx)
DUAL (Tx only)
48-bit color (dual pixel) support
Single-to-dual support
DUAL=1/2VCC
DUAL=Gnd
24-bit color (single pixel) support
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16
Pin Diagram
Transmitter-DS90C387A
10132006
17
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Pin Diagram
Receiver-DS90CF388A
10132007
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18
Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions show in millimeters
Order Number DS90C387AVJD and DS90CF388AVJD
NS Package Number VJD100A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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