DS90C387RVJD/NOPB [TI]
85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA | NEZ | 100 | -10 to 70;
| 型号： | DS90C387RVJD/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA | NEZ | 100 | -10 to 70 驱动 泵 接口集成电路 驱动器 |
| 文件： | 总33页 (文件大小：957K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA
Check for Samples: DS90C387R
1
FEATURES
DESCRIPTION
The DS90C387R transmitter is designed to support
pixel data transmission from a Host to a Flat Panel
Display up to UXGA resolution. It is designed to be
compatible with Graphics Memory Controller Hub
(GMCH) by implementing two data per clock and can
be controlled by a two-wire serial communication
interface. Two input modes are supported: one port of
12-bit( two data per clock) input for 24-bit RGB, and
two ports of 12-bit( two data per clock) input for dual
24-bit RGB( 48-bit total). In both modes, input data
will be clocked on both rising and falling edges in
LVTTL level operation, or clocked on the cross over
of differential clock signals in the low swing operation.
Each input data width will be 1/2 of clock cycle. With
an input clock at 85MHz and input data at 170Mbps,
the maximum transmission rate of each LVDS line is
2
•
Complies with Open LDI Specification for
Digital Display Interfaces
•
•
25 to 85MHz Clock Support
Supports VGA through UXGA Panel
Resolution
•
Up to 4.76Gbps Bandwidth in Dual 24-bit RGB
In-to-Dual Pixel Out Application
•
•
•
•
Dual 12-bit Double Pumped Input DVO Port
Pre-Emphasis Reduces Cable Loading Effects
Drives Long, Low Cost Cables
DC Balance Data Transmission Provided by
Transmitter Reduces ISI Distortion
•
•
•
•
•
•
•
Transmitter Rejects Cycle-to-Cycle Jitter (±2ns
of Input Bit Period)
595Mbps, for
2.38Gbps/4.76Gbps.
a
aggregate throughput rate of
It converts 24/48 bits
Support both LVTTL and Low Voltage Level
Input (Capable of 1.0 to 1.8V)
(Single/Dual Pixel 24-bit color) of data into 4/8 LVDS
(Low Voltage Differential Signaling) data streams.
DS90C387R can be programmed via the two-wire
serial communication interface. The LVDS output pin-
out is identical to DS90C387. Thus, this transmitter
can be paired up with DS90CF388, receiver of the
112MHz LDI chipset or FPD-Link Receivers in non-
DC Balance mode operation which provides GUI/LCD
panel/mother board vendors a wide choice of inter-
operation with LVDS based TFT panels.
Two-Wire Serial Communication Interface up
to 400 KHz
Programmable Input Clock and Control Strobe
Select
Backward Compatible Configuration with
112MHz LDI and FPD-Link
Optional Second LVDS Clock for Backward
Compatibility with FPD-Link Receivers
DS90C387R also comes with features that can be
found on DS90C387. Cable drive is enhanced with a
user selectable pre-emphasis feature that provides
additional output current during transitions to
counteract cable loading effects. DC Balancing on a
cycle-to-cycle basis is also provided to reduce ISI
(Inter-Symbol Interference), control signals (VSYNC,
HSYNC, DE) are sent during blanking intervals. With
pre-emphasis and DC Balancing, a low distortion eye-
pattern is provided at the receiver end of the cable.
These enhancements allow cables 5 to 15+ meters in
length to be driven depending on media characteristic
and pixel clock speed. Pre-emphasis is available in
both the DC Balanced and Non-DC Balanced modes.
In the Non-DC Balanced mode backward
compatibility with FPD-Link Receivers is obtained.
Compatible with TIA/EIA-644
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2014, Texas Instruments Incorporated
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
This chip is an ideal solution to solve EMI and cable size problems for high-resolution flat panel display
applications. It provides a reliable industry standard interface based on LVDS technology that delivers the
bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce
EMI and shielding requirements. For more details, please refer to the “Applications Information” section of this
datasheet.
Table 1. Mode Configuration / Performance Table
Mode
Mode (GUI Out/Cable)
One 12-bit
single/single
25-85
Two 12-bit
dual/dual
25-85
Input Clock Rate (MHz)
Input Data Rate (Mbps)
LVDS data Pairs Out
50-170
50-170
8
4
Ouput Clock Rate (MHz)
Data Rate Out (Mbps) per LVDS channel
Throughput Data Rate Out
25-85
25-85
175-595
2.38Gbps
175-595
4.76Gbps
Generalized Block Diagrams
Figure 1. DS90C387R
2
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
(1)(2)
Absolute Maximum Ratings
Min
−0.3
−0.3
−0.3
Max
+4
Unit
V
Supply Voltage (VCC
)
LVCMOS/LVTTL Output Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
VCC + 0.3
VCC + 0.3
V
Continuous
+150
+150
+260
2.8
°C
°C
°C
W
Storage Temperature
−65
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity at 25°C
Package Derating
100 TQFP Package
18.2mW/°C above +25°C
HBM, 1.5kΩ, 100pF
EIAJ, 0Ω, 200pF
> 2
kV
V
ESD Rating
> 300
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
3.0
Nom
3.3
Max
3.6
Unit
V
All Supply Voltage
Operating Free Air Temperature (TA)
Supply Noise Voltage (VCC) up to 33MHz
−10
+25
+70
100
°C
mVp-p
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LVCMOS/LVTTL DC SPECIFICATIONS ( All pins, except output pins AnP, AnM, CLKnP and CLKnM, BAL, PD pins)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
VREF = VCC3V = VCC
VREF = VCC3V = VCC
ICL = 18 mA
2.0
VCC
0.8
V
V
GND
-0.8
+1.8
0
-1.5
+15
V
VIN = 0.4V, or VCC
VIN = GND
µA
µA
V
−15
VOL
Low level Open Drain Output
Voltage
IOL = 2 mA
0.1
0.3
LVCMOS DC SPECIFICATIONS ( PD pin)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
VREF = VCC3V = VCC
VREF = VCC3V = VCC
ICL = 18 mA
2.9
VCC
0.8
V
V
GND
-0.8
+1.8
0
-1.5
+15
V
VIN = 0.4V, or VCC
VIN = GND
µA
µA
−15
LVDS DRIVER DC SPECIFICATIONS (output pins AnP, AnM, CLKnP and CLKnM)
VOD
Differential Output Voltage
RL = 100Ω
247
345
550
35
mV
mV
ΔVOD
Change in VOD between
Complimentary Output States
VOS
Offset Voltage
1.125
1.25
1.475
35
V
ΔVOS
Change in VOS between
mV
Complimentary Output States
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE Current
VOUT = 0V, RL = 100Ω
−3.5
−11
mA
µA
PD = 0V, VOUT = 0V or VCC
±1
±10
(1) Typical values are given for VCC = 3.3V and T A = +25°C. Device tested in Non-Balanced mode only.
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
3
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Low Voltage Mode DC SPECIFICATIONS( pins D0 to D23, CLKINP, CLKINM, DE, HSYNC,VSYNC)
(2)
VIHLS
VILLS
VREF
Low Swing High Level Input
Voltage, VCC = 3V
VREF
+100mV
1.8
V
V
V
Low Swing Low Level Input
Voltage,VCC = 3V
GND
VREF -
100mV
Differential Input Reference
Voltage, VCC = 3V
Low Swing,VREF = ½VDDQ
0.45
0.5*VDDQ
1
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
ICCTZ
Transmitter Supply Current
Worst Case
RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figure 4), BAL=High
(enabled),
f = 32.5 MHz,
DUAL = VCC
115
75
180
215
235
170
205
225
85
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
f = 32.5 MHz,
DUAL = Gnd
f = 65 MHz,
DUAL = VCC
150
95
VCC = 3.6V
f = 65 MHz,
DUAL = Gnd
f = 85 MHz,
DUAL = VCC
175
110
110
70
f = 85 MHz,
DUAL = Gnd
Transmitter Supply Current, 16
Grayscale Case
RL = 100Ω,
CL = 5 pF,
16 Grayscale Pattern
(Figure 3), BAL =
High (enabled),
VCC = 3.6V
f = 32.5 MHz,
DUAL = VCC
f = 32.5 MHz,
DUAL = Gnd
f = 65 MHz,
DUAL = VCC
135
90
f = 65 MHz,
DUAL = Gnd
f = 85 MHz,
DUAL = VCC
155
100
4.8
f = 85 MHz,
DUAL = Gnd
Transmitter Supply Current,
Power Down
PD = Low
Driver Outputs in TRI-STATE under
Powerdown Mode
(2) Low Swing DC threshold testing is preformed on data and control inputs only. Clock inputs tested by functional testing only.
DIGITAL DC CHARACTERISTICS for Two-Wire Serial Communication Interface
Over recommended operating supply and temperature ranges unless otherwise specified.(1)
Parameters list below only valid when I2CSEL pin = Vcc.
Symbol
VIN(1)
VIN(0)
VOL
Parameter
Logical “ 1 ” input voltage
Logical “ 0 ” input voltage
Conditions
Min
Typ
Max
Unit
V
2.1
0.8
0.4
0.6
V
Serial Bus Low level output voltage IOL= 3mA
IOL= 6mA
V
V
(1) Typical values are given for VCC = 3.3V and T A = +25°C. Device tested in Non-Balanced mode only.
4
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Device driving the transmitter
inputs should comply to this table of recommendations.
Symbol
TCIT
Parameter
TxCLK IN Transition Time (Figure 6)
Min
0.8
Typ
1.2
Max
2.4
Unit
ns
ns
ns
ns
V
DUAL = Gnd or VCC
DUAL = Gnd or VCC
TCIP
TCIH
TCIL
TxCLK IN Period (Figure 7)
11.76
0.4T
0.4T
1.0
T
40
TxCLK in High Time (Figure 7)
TxCLK in Low Time (Figure 7)
Low Swing Voltage Amplitude from GMCH
0.5T
0.5T
0.6T
0.6T
1.8
VDDQ
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)
Symbol
LLHT
Parameter
Min
Typ
Max
Unit
LVDS Low-to-High Transition Time (Figure 5), PRE = no connect (minimum
pre-empahsis).
0.14
0.9
ns
LVDS Low-to-High Transition Time (Figure 5), PRE = VCC (max. pre-
empahsis).
0.11
0.16
0.11
0.7
0.9
0.7
ns
ns
ns
LHLT
LVDS High-to-Low Transition Time (Figure 5), PRE = no connect (mini. pre-
empahsis).
LVDS High-to-Low Transition Time (Figure 5), PRE = VCC (max. pre-
empahsis).
TCCS
TxOUT Channel to Channel Skew
100
0
ps
ps
(2)
TPPOS0
Transmitter Output Pulse Position for Bit0 from
TxCLKout rising edge.
f = 85MHz
-300
1.38
3.06
4.74
6.42
8.10
9.78
+300
1.98
3.66
5.34
7.02
8.70
10.38
TPPOS1
TPPOS2
TPPOS3
TPPOS4
TPPOS5
TPPOS6
Transmitter Output Pulse Position for Bit1 from
TxCLKout rising edge.
1.68
3.36
5.04
6.72
8.40
10.08
ns
ns
ns
ns
ns
ns
Transmitter Output Pulse Position for Bit2 from
TxCLKout rising edge.
Transmitter Output Pulse Position for Bit3 from
TxCLKout rising edge.
Transmitter Output Pulse Position for Bit4 from
TxCLKout rising edge.
Transmitter Output Pulse Position for Bit5 from
TxCLKout rising edge.
Transmitter Output Pulse Position for Bit6 from
TxCLKout rising edge.
TSTC
THTC
TJCC
TxIN Setup to TxCLK IN in low swing mode at 85 MHz (Figure 8)
TxIN Hold to TxCLK IN in low swing mode at 85 MHz (Figure 8)
1.8
2
ns
ns
ps
ps
ps
ms
ns
ns
Transmitter Jitter Cycle-to-cycle (Figure 13
Figure 14) (3), DUAL = Gnd, VCC = 3V
f = 85 MHz
f = 65 MHz
f = 32.5 MHz
110
80
150
120
115
10
75
TPLLS
TPDD
TPDL
Transmitter Phase Lock Loop Set (Figure 9)
Transmitter Powerdown Delay (Figure 10)
Transmitter Input to Output Latency (Figure 11)
100
(4)
f = 32.5/65/85 MHz
1.5TCIP
+4.1
(1) Typical values are given for VCC = 3.3V and T A = +25°C. Device tested in Non-Balanced mode only.
(2) The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT(process,
voltage and temperature) range.
(3) The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is
measured with a cycle-to-cycle jitter of ±2ns applied to the input clock signal while data inputs are switching (see Figure 13 and
Figure 14). A jitter event of 2ns, represents worse case jump in the clock edge from most graphics VGA chips currently available. This
parameter is used when calculating system margin as described in AN-1059.
(4) From V = 1.5V of CLKINP to VDIFF= 0V of CLK1P when R_FB = High, DUAL = Low or High, BAL = Low.
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
DIGITAL SWITCHING CHARACTERISTICS for Two-Wire Serial Communication Interface
Unless otherwise noted, below specifications apply for VCC=+3.3V, load capacitance on output lines = 80 pF. Load
capacitance on output lines can be up to 400 pF provided that external pull-up switch is on board. The following parameters
are the timing relationships between SCL and SDA signals related to the DS90C387R.
Symbol
t1
Parameter
Min
2.5
100
0
Typ
Max
Unit
μs
SCL (Clock) Period
t2
t3
t4
t5
Data in Set-Up Time to SCL High
Data Out Stable after SCL Low
ns
ns
SDA Low Set-Up Time to SCL Low (Start Condition)
SDA High Hold Time after SCL High (Stop Condition)
100
100
ns
ns
AC Timing Diagrams
Figure 2. Two-Wire Serial Communication Interface Timing Diagram when I2CSEL = Vcc
6
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Figure 3. “16 Grayscale” Test Pattern
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Figure 4. “Worst Case” Test Pattern
Figure 5. DS90C387R LVDS Output Load and Transition Times
Figure 6. DS90C387R Input Clock Transition Time
Figure 7. DS90C387R TxCLK IN Period, and High/Low Time (Falling Edge Strobe)
Figure 8. DS90C387R Setup/Hold (Falling Edge Strobe First)
8
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Figure 9. DS90C387R Phase Lock Loop Set Time
Figure 10. DS90C387R Power Down Delay
CLKINP
TPDL
All Data from
E1 and E2
E1
E2
CLK1M
VDIFF = 0V
CLK1P
A0M - A7M
A0P - A7P
All Data from E1 and E2
NOTE: From V = 1.5V of CLKINP to VDIFF= 0V of CLK1P when R_FB = High, DUAL = Low or High, BAL = Low.
Figure 11. DS90C387R Input to Output Latency
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
A. Cycle-to-cycle jitter is less than 150 ps at 85 MHz
B. ISI is dependent on interconnect length; may be zero
Figure 12. Receiver Skew Margin
Figure 13. TJCC Test Setup - DS90C387R
Figure 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter
10
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
DS90C387R PIN DESCRIPTION—LDI TRANSMITTER
Pin Name
I/O
No.
Description
D0-D23
I
24
LVTTL level single-ended inputs or low swing pseduo differential inputs. Reference to VREF pin.
D0-D11 are for 12-bit input mode (24 RGB data); D0-D11 (first 12-bit port) and D12-D23
(second 12-bit port) are for two 12-bit input mode (48 RGB data).
DE
I
1
LVTTL level or low swing level inputs for data enable. This signal is HIGH when input pixel data
is valid to DS90C387R provided that R_FDE = HIGH.
HSYNC
VSYNC
AnP
I
I
1
1
8
8
1
Horizontal Sync input control signal. LVTTL level or low swing level.
Vertical Horizontal Sync input control signal. LVTTL level or low swing level.
Positive LVDS differential data output.
O
O
I
AnM
Negative LVDS differential data output.
CLKINP
In LVTTL level operation, this is a single-ended clock. In low swing operation, this is the positive
differential clock input .
CLKINM
R_FB
I
I
I
1
1
1
In LVTTL level operation, no connect or connect to VREF pin. Do not connect to GND under any
condition. In low swing operation, this is negative differential clock input .
LVTTL level input for selecting the Primary clock edge E1. Falling clock edge selected when
input is HIGH; Rising clock edge selected when input is LOW.(1)
R_FDE
LVTTL level input. Programmable control (DE) strobe select. Tie HIGH for data active when DE
(1)
is HIGH.
CLK1P
CLK1M
PD
O
O
I
1
1
1
Positive LVDS differential clock output.
Negative LVDS differential clock output.
LVCMOS level input. Input = LOW will place the entire device in power down mode. Outputs of
the device will be in TRI-STATE mode to ensure low current at power down.
(1)
Input = HIGH for normal operation.
(1)
PLLSEL
BAL
I
I
1
1
LVTTL level in. Tie to Vcc for normal operation.
LVTTL level input. Mode select for dc balanced or non-dc balanced interface. DC balance is
(1)
active when input is high.
PRE
I
1
Pre-emphasis level select. Pre-emphasis is active when input is tied to VCC through external
pull-up resistor. Resistor value determines pre-emphasis level (see table in application section).
For normal LVDS drive level (minimum pre-emphasis) leave this pin open (do not tie to
ground).(1)
DUAL
VCC
I
I
1
1
LVTTL level input. Input = LOW for one 12-bit input mode, 24 RGB data in, 24 RGB data out.(1)
LVTTL level input. Input = VCC for two 12-bit input mode, 48 RGB data in, 48 RGB data out.(1)
Connect to power supply with voltage stated under Recommended Operating Conditions.
Power supply pin for LVTTL inputs and digital circuitry, pin53.
GND
I
I
4
1
Ground pins for LVTTL inputs and digital circuitry, pins 9, 11, 52, 77.
I2VCC
Connect to power supply with voltage stated under Recommended Operating Conditions, pin
68.
VCC3V
I
3
Connect to power supply with voltage stated under Recommended Operating Conditions, pins
70, 79, 95.
GND3V
SGND
I
I
I
3
1
2
Ground pin(s) for powering the data inputs, pins 71, 80, 96.
Connect to ground, pin 69.
PLLVCC
Connect to power supply with voltage stated under Recommended Operating Conditions.
Power supply pins for PLL circuitry, pin 10, 16.
PLLGND
LVDSVCC
I
I
3
3
Ground pins for PLL circuitry, pins 14, 15, 17.
Connect to power supply with voltage stated under Recommended Operating Conditions.
Power supply pins for LVDS outputs, pins 30, 40, 48.
LVDSGND
CLK2P/NC
CLK2M/NC
I
4
1
1
Ground pins for LVDS outputs, pins 25, 35, 43, 51.
O
O
Additional positive LVDS differential clock output identical to CLK1P. No connect if not used.
Additional negative LVDS differential clock output identical to CLK1M. No connect if not used.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
DS90C387R PIN DESCRIPTION—LDI TRANSMITTER (continued)
Pin Name
VREF
I/O
No.
Description
VREF= 1/2 VDDQ, a ”Fixed “ line of differential input.
I
1
If VREF ≥ 1.8V, indicates input data is in LVTTL mode.
If VREF < 1.1V, indicates input data is in low voltage swing mode.
In low voltage swing mode, input data = logic HIGH = VREF + 100mV.
In low voltage swing mode, input data = logic LOW = VREF - 100mV.
This pin is not to be left floating. When not use in LVTTL mode, tie to Vcc
I2CSEL
I
I
1
1
HIGH to enable two-wire serial communication interface; LOW to disable the interface.
DDREN/I2Cclk
Always HIGH for one 12-bit port and two 12-bit ports operation. When I2CSEL = HIGH, this is
the clock line for the two-wire serial communication interface.
DSEL/I2Cdat
I/O
1
Differential select pin for CLKIN (HIGH = single-ended, LOW = differentail) or when I2CSEL =
HIGH, this is the Bidirectional Data line for the two-wire serial communication interface.
A0
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
Interrupt signal. This is an open drain output, pull-up resistor is required.
Test pin, tie to Vcc.
A1
A2
I
MSEN
O
TST1
TST2
Test pin, no connect. Do not tie to ground.
Reserved pin, tie to ground.
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
Reserved pin, tie to ground.
Reserved pin, no connect. Do not tie to ground.
Reserved pin, tie to ground.
Reserved pin, tie to ground.
Reserved pin, tie to ground.
Reserved pin, tie to ground.
Reserved pin, tie to ground.
Reserved pin, tie to ground.
Table 2. Control Settings for mode selection
Mode
DUAL
12bit
L
Two 12-bit
H
L/H
L
BAL
L/H
L
I2CSEL
DDREN/I2Cclk
CLKIN polarity
H
H
R_FB
DSEL
R_FB
DSEL
CLKIN,single-ended/ differentail
Description
12-bit in, 24-bit pixel out, non-DC Balanced or Two 12-bit in, two 24-bit pixels out, non-DC
DC-Balanced Balanced or DC-Balanced.
Table 3. Relationship between R_FB, DE, HSYNC and VSYNC pins
R_FB
VCC
GND
Primary Edge
Falling
Secondary Edge
Rising
DE latches on
Rising
HSYNC latches on
Falling
VSYNC latches on
Falling
Rising
Falling
Falling
Rising
Rising
Two-Wire Serial Communication Interface Description
The DS90C387R operates as a slave on the Serial Bus, so the SCL line is an input (no clock is generated by the
DS90C387R) and the SDA line is bi-directional. DS90C387R has a 7-bit slave address. The address bits are
controlled by the state of the address select pins A2, A1 and A0, and are set by connecting these pins to ground
for a LOW, (0) , to VCC for a HIGH, (1).
12
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Therefore, the complete slave address is:
A6
A5
A4
A3
A2
A1
A0
MSB
LSB
and is selected as follows:
Address Select Pin
DS90C387R Serial
Bus Slave Address
State
A2
0
A1
0
A0
0
A6:A0 binary
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
The DS90C387R latches the state of the address select pins during the first read or write on the Serial Bus.
Changing the state of the address select pins after the first read or write to any device on the Serial Bus will not
change the slave address of the DS90C387R.
A zero in front of the register address is required as the most left column shown in Table 4. For example, to
access register F, “0F” is the correct way of accessing the register.
Table 4. Register Mapping
Addr
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
VND_IDL(RO)
VND_IDH(RO)
DEV_IDL(RO)
DEV_IDH(RO)
DEV_REV(RO)
RSVD[7:0](RO)
FRQ_LOW[7:0](RO)
FRQ_HIGH[7:0](RO)
RSVD[1:0]
VLOW(RO)
VEN(RW)
HEN(RW)
DSEL(RW)
TSEL(RW)
BSEL(RW)
RSEN(RO)
EDGE(RW)
HTPLG(RO)(1)
PD(RW)
MDI(RW)
RSVD(RW)
MSEL[2:0](RW)
DK[3:1](RW)(1)
DKEN(RW)(1)
CTL[3:1](RW)
CFG[7:0](RO)(1)
VDJK[7:0](RW)(1)
RSVD[3:0](RW)
RSVD[3:0](RO)
RSVD[7:0](RW)
RSVD[7:0](RW)
(1) Features not implemented on DS90C387R
Table 5. Register Field Definitions
Field
Access
RO
Description
VND_IDL
VND_IDH
DEV_IDL
DEV_IDH
DEV_REV
Vendor ID low byte, value is 05h.
Vendor ID high byte, value is 13h.
Device ID low byte, value is 24h.
Device ID high byte, value is 67h.
Device revision, value is 00h.
RO
RO
RO
RO
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
Table 5. Register Field Definitions (continued)
Field
FRQ_LOW
FRQ_HIGH
PD
Access
RO
Description
25 MHz is Low frequency limit for the current mode, value is 19h.
85 MHz is High frequency limit for the current mode, value is 55h.
Power down mode, default = 1.
RO
RW
0 - power down only the LVDS drivers. Output of this device will be in TRI-STATE mode. Other
circuitry are still active.
1 - normal operation.
EDGE
BSEL
DSEL
HEN
RW
RW
RW
RW
RW
RW
Edge select (same function as R_FB pin), default = 1.
0 - input data is rising edge latched (rising edge latched first in 12-bit and two 12-bit mode).
1 - input data is falling edge latched (falling edge latched first in 12-bit and two 12-bit mode).
Input bus select (same as DUAL pin), default = 0.
0 - one 12-bit bus.
1 - two 12-bit bus.
Dual level clock select (same function as DSEL pin), default = 1.
0 - input clock is differential.
1 - input clock is single-ended (up to 65MHz). CLKINM and VREF pin are internally connected.
Horizontal sync enable, default = 1.
0 - HSYNC input is transmitted as fixed LOW.
1 - HSYNC input is transmitted as it is.
VEN
Vertical sync enable, default = 1.
0 - VSYNC input is transmitted as fixed LOW.
1 - VSYNC input is transmitted as it is.
MDI
Monitor Detect Interrupt, default = 1.
0 - Detection signal has changed logical level (write "1" to this bit to clear).
1 - Detection signal has not changed state.
HTPLG(1)
RSEN
RO
RO
Feature not implemented.
This bit is a ”1 “ if a powered on receiver is connected to the transmitter outputs, ” 0 “ otherwsie.
This function is only available for use in DC-coupled systems. Default=0.
TSEL
RW
Interrupt generation method, default=0.
0 - Interrupt bit (MDI) is generated by monitoring RSEN.
1 - Interrupt bit (MDI) is generated by monitoring HTPLG.
Select source for the MSEN output pin. Default valus is 001.
000 - Force MSEN output HIGH (disabled).
001 - Output the value of MDI bit (interrupt). This is default.
010 - Output the value of RSEN bit (receiver detect).
011 - Output the value of HTPLG bit (hot plug detect).
1xx - Reserved.
MSEL [2:0]
RW
VLOW
RO
This bit is an 1 if the VREF signal indicates low swing inputs. Default=1.
It is a 0 if VREF indicates high swing inputs.
General purpose inputs.
CTL [3:1]
CFG [7:0](1)
VDJK [7:0](1)
DK [3:1](1)
DKEN(1)
RW
RO
RW
RW
RW
Feature not implemented.
Reserved.
Feature not implemented.
Feature not implemented.
(1) Features not implemented on DS90C387R
14
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Communicating with the DS90C387R through Registers
There are 31 data registers in the DS90C387R, and can be accessed through sixteen register addresses. All
registers are predefined as read only, or read and write. The device will always attempt to detect if a LCD
panel/monitor is connected.
A Write to the DS90C387R will always include the slave address byte, data register address byte, a data byte.
Reading the DS90C387R can take place either of two ways:
1. If the location latched in the data register addresses is correct , then the read can simply consist of a slave
address byte, followed by retrieving the data byte.
2. If the data register address needs to be set, then a slave address byte, data register address will be sent
first, then the master will repeat start, send the slave address byte and data byte to accomplish a read.
The data byte has the most significant bit first. At the end of a read, the DS90C387R can accept either
Acknowledge or No Acknowledge from the Master (No Acknowledge is typically used as a signal for the slave
that the Master has read its last byte).
Two-Wire Serial Communication Interface for Slave
The DS90C387R slave state machine does not require an internal clock and it supports only byte read and write.
Page mode is not supported. The 7-bit binary address is “0111A2A1A0”, where A2A1A0 are pin programmable to “
1” or “ 0 ” and the “ 0111 ” is hardwired internally.
Figure 15. Byte Read
The master must generate a “ Start ” by sending the 7-bit slave address plus a 0 first, and wait for acknowledge
from DS90C387R. When DS90C387R acknowledges (the 1st ACK) that the master is calling, the master then
sends the data register address byte and waits for acknowledge from the slave. When the slave acknowledges
(the 2nd ACK), the master repeats the “ Start ” by sending the 7-bit slave address plus a 1 (indicating that READ
operation is in progress) and waits for acknowledge from DS90C387R. After the slave responds (the 3rd ACK),
the slave sends the data to the bus and waits for acknowledge from the master. When the master acknowledges
(the 4th ACK), it generates a “ Stop ”. This completes the “ READ ”.
Figure 16. Byte Write
The master must generate a “ Start ”, by sending the 7-bit slave address plus a 0 and wait for acknowledge from
DS90C387R. When DS90C387R acknowledges (the 1st ACK) that the master is calling, the master then sends
the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd
ACK), the master sends the data byte and wait for acknowledge from the slave. When the slave acknowledges
(the 3rd ACK), the master generates a “ Stop ”. This completes the “ WRITE ”.
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
LVDS Interface
Table 6. LVDS data bit naming convention(1)
X
Y
Z
Description
X=R
X=G
X=B
Red
Green
Blue
Y=1
Y=2
Odd (First) Pixel
Even (Second) Pixel
Z=0-7
LVDS bit number (not VGA controller LSB to MSB)
(1) For a 48-bit dual pixel application - LSB (Less Significant Bit) = R16,G16,B16,R26,G26,B26 and MSB
(Most Significant Bit) = R15,G15,B15,R25,G25,B25.
Table 7. 12-bit (two data per clock) data mapping(1)
VGA - TFT Data Signals
Color Bits
Transmitter input pin names
Receiver output pin names
TFT Panel Data Signals
24-bit
DS90C387R
E2-D4
E2-D5
E2-D6
E2-D7
E2-D8
E2-D9
E2-D10
E2-D11
E1-D8
E1-D9
E1-D10
E1-D11
E2-D0
E2-D1
E2-D2
E2-D3
E1-D0
E1-D1
E1-D2
E1-D3
E1-D4
E1-D5
E1-D6
E1-D7
DS90CF388
R16
R17
R10
R11
R12
R13
R14
R15
G16
G17
G10
G11
G12
G13
G14
G15
B16
18-bit
24-bit
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
LSB
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
R0
R1
R2
R3
R4
R5
MSB
LSB
G0
G1
G2
G3
G4
G5
MSB
LSB
B17
B10
B0
B1
B2
B3
B4
B5
B11
B12
B13
B14
MSB
B15
(1) DUAL=GND, BAL=Vcc/GND, only A0-A3 are used
Table 8. Two 12-bit (two data per clock) data mapping(1)
VGA - TFT Data Signals
Color Bits
Transmitter input pin names
Receiver output pin names
TFT Panel Data Signals
24-bit
DS90C387R
DS90CF388
18-bit
24-bit
R0
Port 1-Primary (odd pixel/first RGB pixel)
LSB
R0
E2-D4
R16
(1) DUAL=GND, BAL=Vcc/GND, only A0-A3 are used
16 Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Table 8. Two 12-bit (two data per clock) data mapping(1) (continued)
VGA - TFT Data Signals
Color Bits
Transmitter input pin names
Receiver output pin names
TFT Panel Data Signals
R1
R2
R3
R4
R5
R6
E2-D5
E2-D6
E2-D7
E2-D8
E2-D9
E2-D10
E2-D11
E1-D8
E1-D9
E1-D10
E1-D11
E2-D0
E2-D1
E2-D2
E2-D3
E1-D0
E1-D1
E1-D2
E1-D3
E1-D4
E1-D5
E1-D6
E1-D7
R17
R10
R11
R12
R13
R14
R15
G16
G17
G10
G11
G12
G13
G14
G15
B16
B17
B10
B11
B12
B13
B14
B15
R1
R0
R1
R2
R3
R4
R5
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
MSB
LSB
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
MSB
LSB
B0
B1
B2
B3
B4
B5
MSB
LSB
Port 2-Secondary (even pixel/second RGB pixel)
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
E2-D16
E2-D17
E2-D18
E2-D19
E2-D20
E2-D21
E2-D22
E2-D23
E1-D20
E1-D21
E1-D22
E1-D23
E2-D12
E2-D13
E2-D14
E2-D15
E1-D12
E1-D13
E1-D14
E1-D15
E1-D16
E1-D17
E1-D18
R26
R27
R20
R21
R22
R23
R24
R25
G26
G27
G20
G21
G22
G23
G24
G25
B26
B27
B20
B21
B22
B23
B24
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
R0
R1
R2
R3
R4
R5
MSB
LSB
G0
G1
G2
G3
G4
G5
MSB
LSB
B0
B1
B2
B3
B4
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
Table 8. Two 12-bit (two data per clock) data mapping(1) (continued)
VGA - TFT Data Signals
Color Bits
Transmitter input pin names
Receiver output pin names
TFT Panel Data Signals
MSB
B7
E1-D19
B25
B5 B7
Figure 17. How ds90c387r Latch Data
Table 9. 12-bit (two data per clock) input application data mapping with GMCH.
P0
P1
P1H
P2
P2H
P0L
Low
P0H
High
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
P1L
Low
P2L
Pin Name
High
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
Low
G2[3]
G2[2]
G2[1]
G2[0]
B2[7]
B2[6]
B2[5]
B2[4]
B2[3]
B2[2]
B2[1]
High
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
G0[3]
G0[2]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
R2[7]
R2[6]
R2[5]
R2[4]
R2[3]
R2[2]
R2[1]
R2[0]
G2[7]
G2[6]
G2[5]
18
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Table 9. 12-bit (two data per clock) input application data mapping with GMCH. (continued)
P0
P1
P1H
P2
P2H
P0L
Low
B0[0]
P0H
High
G0[4]
P1L
Low
B1[0]
P2L
Pin Name
High
Low
High
D0
G1[4]
B2[0]
G2[4]
Figure 18. TTL Data Inputs Mapped to LVDS Outputs
Non-DC Balanced Mode (Backward Compatible, BAL=Low, A0 to A3 for Port1, A4 to A7 for Port2)
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
Figure 19. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs
DC Balanced Mode (Data Enabled, BAL=High, A0 to A3 for Port1, A4 to A7 for Port2)
Figure 20. Control Signals Transmitted During Blanking in DC-Balance mode
Table 10. Control Signals Transmitted During Blanking in DC-Balance mode
Control Signal
Signal
Level
Channel
Pattern
DE
HIGH
LOW
HIGH
LOW
HIGH
LOW
CLK1
1111000 or 1110000
1111100 or 1100000
1100000 or 1111100
1110000 or 1111000
1100000 or 1111100
1110000 or 1111000
HSYNC
VSYNC
A0
A1
20
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
APPLICATIONS INFORMATION
How to configure the DS90C387R to work with DS90CF384/DS90CF384A/DS90CF386 or DS90CF388 for
most common application:
1. To configure for single pixel application using the DS90C387R to interface with GMCH host, please see table
below for reference pin connection and configuration. Due to the implementation differences among various
GMCH vendors, the table is using the GMCH vendor located in Santa Clara, California, USA as an example. A
two-wire serial communication interface based EEPROM containing EDID 128 bytes LCD timing information may
be required depending on device driver implementation.
From DS90C387R
data signal connection
To GMCH
D0
D1
D0
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D11
CLKINP
CLKINM
DE
D10
D11
CLK1
CLK0
BLANK
HSYNC
VSYHC
HSYNC
VSYNC
configuration for other pins
DDRENI2Cclk
DSELI2Cdat
A0
I2CCLK
I2CDATA
GND
A1
GND
A2
GND
PLLSEL
Vcc
DUAL
GND
BAL
GND
D12 to D23
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
TST1
No connect
GND
GND
No connect
GND
GND
GND
GND
GND
GND
Vcc
TST2
No connect
VREF
VREF
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
From DS90C387R
MSEN
To GMCH
INT#
2. To configure for single pixel application using the DS90C387R with single DS90CF384 or DS90CF384A or
DS90CF386 LVDS based LCD panel or monitor, the “DUAL” pin must be set to Gnd (single RGB), and “BAL” pin
must be set to Gnd to disable the feature for DS90CF384/DS90CF386 doesn't support DC balance function. For
cable length more than two meters, pre-emphasis feature is recommended. Please see table below for reference
pin connection.
From DS90C387R Output Pins
To LVDS based LCD monitor
data signal connection
A0M
A0P
RxIN0−
RxIN0+
A1M
RxIN1−
A1P
RxIN1+
A2M
RxIN2−
A2P
RxIN2+
CLK1M
CLK1P
RxCLKIN0−
RxCLKIN0+
A3M(valid for 8-bit LCD only; no
connect for 6-bit LCD)
RxIN3−(valid for 8-bit LCD only; no
connect for 6-bit LCD)
A3P(valid for 8-bit LCD only; no
connect for 6-bit LCD)
RxIN3+(valid for 8-bit LCD only; no
connect for 6-bit LCD)
A4M
A4P
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
A5M
A5P
A6M
A6P
A7M
A7P
CLK2M
CLK2P
3. To configure for single pixel or dual pixel application using the DS90C387R with DS90CF388, the “DUAL” pin
must be set to Vcc (dual RGB) or Gnd (single RGB). Also, “BAL” pins on both devices have to in the same logic
state. For cable length more than two meters, pre-emphasis feature is recommended.
4. In dual mode, DS90C387R has two LVDS clock outputs enabling an interface to two FPD-Link 'notebook'
receivers (DS90CF384/DS90CF386). “BAL” pin must be set to Gnd to disable DC balance function for
DS90CF384/DS90CF386 doesn't support DC balance function. In single mode, outputs A4-to-A7 and CLK2 are
disabled which reduces power dissipation. For cable length more than two meters, pre-emphasis feature is
recommended.
The DS90CF388 is able to support single or dual pixel interface up to 112MHz operating frequency. This receiver
may also be used to interface to a VGA controller with an integrated LVDS transmitter without DC balance data
transmission. In this case, the receivers “BAL” pin must be tied low (DC balance disabled).
Features Description:
1. Pre-emphasis: adds extra current during LVDS logic transition to reduce the cable loading effects. Pre-
emphasis strength is set via a DC voltage level applied from min to max (0.75V to Vcc) at the “PRE” pin. A
higher input voltage on the ”PRE” pin increases the magnitude of dynamic current during data transition. The
“PRE” pin requires one pull-up resistor (Rpre) to Vcc in order to set the DC level. There is an internal resistor
network, which cause a voltage drop. Please refer to the tables below to set the voltage level.
22
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Table 11. Pre-emphasis DC voltage level with (Rpre)
Rpre
Resulting PRE
Voltage
Effects
1MΩ or NC
50kΩ
9kΩ
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Standard LVDS
50% pre-emphasis
3kΩ
1kΩ
100Ω
100% pre-emphasis
Table 12. Pre-emphasis needed per cable length
Frequency
85MHz
PRE Voltage
1.5V
Typical cable length
7 meters
65MHz
1.5V
10 meters
2. DC Balance: In the balanced operating modes, in addition to pixel and control information an additional bit is
transmitted on every LVDS data signal line during each cycle of active data as shown in Figure 19. This bit is the
DC balance bit (DCBAL). The purpose of the DC Balance bit is to minimize the short- and long-term DC bias on
the signal lines. This is achieved by selectively sending the pixel data either unmodified or inverted.
The value of the DC balance bit is calculated from the running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall be calculated by subtracting the number of bits of
value 0 from the number of bits value 1 in the current word. Initially, the running word disparity may be any value
between +7 and −6. The running word disparity shall be calculated as a continuous sum of all the modified data
disparity values, where the unmodified data disparity value is the calculated data disparity minus 1 if the data is
sent unmodified and 1 plus the inverse of the calculated data disparity if the data is sent inverted. The value of
the running word disparity shall saturate at +7 and −6.
The value of the DC balance bit (DCBAL) shall be 0 when the data is sent unmodified and 1 when the data is
sent inverted. To determine whether to send pixel data unmodified or inverted, the running word disparity and the
current data disparity are used. If the running word disparity is positive and the current data disparity is positive,
the pixel data shall be sent inverted. If the running word disparity is positive and the current data disparity is zero
or negative, the pixel data shall be sent unmodified. If the running word disparity is negative and the current data
disparity is positive, the pixel data shall be sent unmodified. If the running word disparity is negative and the
current data disparity is zero or negative, the pixel data shall be sent inverted. If the running word disparity is
zero, the pixel data shall be sent inverted.
Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to
reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is
provided at the receiver end of the cable. These enhancements allow cables 5 to 10+ meters in length to be
driven. Quality of the cable can affect the length.
The data enable control signal (DE) is used in the DC balanced mode to distinguish between pixel data and
control information being sent. It must be continuously available to the device in order to correctly separate pixel
data from control information. For this reason, DE shall be sent on the clock signals, LVDS CLK1 and CLK2,
when operating in the DC balanced mode. If the value of the control to be sent is 1 (active display), the value of
the control word sent on the clock signals shall be 1111000 or 1110000. If the value of the control to be sent is 0
(blanking time), the value of the control word sent on the clock signals shall be 1111100 or 1100000.
The control information, such as HSYNC and VSYNC, is always sent unmodified. The value of the control word
to send is determined by the running word disparity and the value of the control to be sent. If the running word
disparity is positive and the value of the control to be sent is 0, the control word sent shall be 1110000. If the
running word disparity is zero or negative and the control word to be sent is 0, the control word sent shall be
1111000. If the running word disparity is positive and the value of the control to be sent is 1, the control word
sent shall be 1100000. If the running word disparity is zero or negative and the value of the control to be sent is
1, the control word sent shall be 1111100. The DC Balance bit shall be sent as 0 when sending control
information during blanking time. See Figure 20.
In backward compatible mode (BAL=low) control and data is sent as regular LVDS data. See Figure 18.
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
Backwards Compatible Mode with FPD-Link
The transmitter provides a second LVDS output clock. Both LVDS clocks will be identical in 'Dual pixel mode'.
This feature supports backward compatibility with the previous generation of devices - the second clock allows
the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit 'notebook' receivers.
Pre-emphasis feature is available for use in both the DC balanced and non-DC balanced (backwards compatible)
modes.
Information on Jitter Rejection:
The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very
low cycle-to-cycle jitter is passed on to the transmitter outputs. This significantly reduces the impact of jitter
provided by the input clock source, and improves the accuracy of data sampling. Data sampling is further
enhanced by automatically calibrated data sampling strobes at the receiver inputs. Timing and control signals
(VSYNC, HSYNC, DE) are sent during blanking intervals to guarantee correct reception of these critical signals.
The transmitter is offered with programmable primary clock edge for convenient interface with a variety of
graphics controllers. The transmitter can be programmed for rising edge strobe or falling edge strobe through a
dedicated pin. A rising edge transmitter will inter-operate with a falling edge receiver without any translation logic.
Transmitter Block Diagram
24
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
DS90C387R
www.ti.com
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
Configuration Table
Table 13. Transmitter / DS90CF388 Receiver configuration table
Pin
Condition
R_FB = VCC
Configuration
Primary clock edge selected as Falling Edge
Primary clock edge selected as Rising Edge
Active data DE = High
R_FB (Tx only)
R_FB = GND
R_FDE = VCC
R_FDE = GND
BAL=VCC
R_FDE (both Tx and Rx)
BAL (both Tx and Rx)
DUAL (Tx only)
Active data DE = Low
DC Balanced enabled
BAL=Gnd
DC Balanced disabled (backward compatible to FPD-Link)
48-bit color (dual pixel) support
DUAL=VCC
DUAL=Gnd
24-bit color (single pixel) support
Pin Diagram
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DE
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
A0M
GND
A0P
V
LVDSVCC
REF
A1M
VCC3V
GND3V
D11
A1P
A2M
D10
A2P
D9
LVDSGND
CLK1M
CLK1P
LVDSVCC
A3M
D8
D7
D6
CLKINP
CLKINM
D5
R
DS90C387
A3P
A4M
D4
A4
P
D3
LVD
A5M
A5P
A6M
A6P
SGND
D2
D1
D0
VCC3V
GND3V
D23
LVDSVCC
A7M
D22
A7P
D21
CLK2M/NC
D20
CLK
2P/NC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Figure 21. Transmitter-DS90C387R
See Package Number NEZ100A
Copyright © 2000–2014, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: DS90C387R
DS90C387R
SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014
www.ti.com
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
Changes from Revision F (April 2013) to Revision G
Page
•
Corrected the pin names in Figure 21 ................................................................................................................................ 25
26
Submit Documentation Feedback
Copyright © 2000–2014, Texas Instruments Incorporated
Product Folder Links: DS90C387R
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90C387RVJD/NOPB
DS90C387RVJDX/NOPB
ACTIVE
TQFP
TQFP
NEZ
100
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-10 to 70
-10 to 70
DS90C387RVJD
>B
Samples
Samples
ACTIVE
NEZ
1000 RoHS & Green
NIPDAU
DS90C387RVJD
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C387RVJDX/NOPB TQFP
NEZ
100
1000
330.0
32.4
18.0
18.0
1.6
24.0
32.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP NEZ 100
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
DS90C387RVJDX/NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS90C387RVJD/NOPB
NEZ
TQFP
100
90
6 x 15
150
322.6 135.9 7620 20.3
15.4 15.45
Pack Materials-Page 3
MECHANICAL DATA
NEZ0100A
TYPICAL
VJD100A (Rev C)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明