DS90CF364 [TI]
+3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 65MHz;
| 型号： | DS90CF364 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 65MHz 光电二极管 显示器 |
| 文件： | 总19页 (文件大小：1098K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CF364A, DS90CF384A
www.ti.com
SNLS040I –JUNE 2000–REVISED APRIL 2013
DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65
MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz
Check for Samples: DS90CF364A, DS90CF384A
1
FEATURES
DESCRIPTION
The DS90CF384A receiver converts the four LVDS
data streams (Up to 1.8 Gbps throughput or 227
Megabytes/sec bandwidth) back into parallel 28 bits
of CMOS/TTL data (24 bits of RGB and 4 bits of
Hsync, Vsync, DE and CNTL). Also available is the
DS90CF364A that converts the three LVDS data
streams (Up to 1.3 Gbps throughput or 170
Megabytes/sec bandwidth) back into parallel 21 bits
of CMOS/TTL data (18 bits of RGB and 3 bits of
Hsync, Vsync and DE). Both Receivers' outputs are
Falling edge strobe. A Rising edge or Falling edge
strobe transmitter (DS90C383A/DS90C363A) will
interoperate with a Falling edge strobe Receiver
without any translation logic.
2
•
20 to 65 MHz Shift Clock Support
•
•
50% Duty Cycle on Receiver Output Clock
Best-in-Class Set & Hold Times on
RxOUTPUTs
•
Rx Power Consumption <142 mW (typ)
@65MHz Grayscale
•
•
•
Rx Power-down Mode <200μW (max)
ESD Rating >7 kV (HBM), >700V (EIAJ)
Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
•
•
•
PLL Requires no External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-lead or 48-lead Packages
The DS90CF384A
/ DS90CF364A devices are
enhanced over prior generation receivers and
provided a wider data valid time on the receiver
output.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
BLOCK DIAGRAMS
Figure 1. DS90CF384A
DGG-56 (TSSOP)
Figure 2. DS90CF364A
DGG-48 (TSSOP)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
DS90CF364A, DS90CF384A
SNLS040I –JUNE 2000–REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
+150°C
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4 sec)
+260°C
+220°C
Solder Reflow Temperature (20 sec for FBGA)
DGG-56 (TSSOP) Package
DS90CF384A
1.61 W
1.89 W
Maximum Package Power Dissipation
Capacity @ 25°C
DGG-48 (TSSOP) Package
DS90CF364A
Package Derating
ESD Rating
DS90CF384AMTD
DS90CF364AMTD
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
12.4 mW/°C above +25°C
15 mW/°C above +25°C
> 7 kV
> 700V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended OperatingConditions
Min
3.0
−10
0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA
Receiver Input Range
)
+25
+70
2.4
°C
V
Supply Noise Voltage (VCC
)
100
mVPP
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS (For Power Down Pin)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
−0.79
+1.8
0
−1.5
+10
V
V IN = 0.4V, 2.5V or VCC
V IN = GND
μA
μA
−10
CMOS/TTL DC SPECIFICATIONS
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IOH = −0.4 mA
IOL = 2 mA
VOUT = 0V
2.7
3.3
0.06
−60
V
V
0.3
−120
mA
(1) Typical values are given for VCC = 3.3V and TA = +25C.
2
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SNLS040I –JUNE 2000–REVISED APRIL 2013
Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V CM = +1.2V
+100
mV
mV
μA
−100
V IN = +2.4V, VCC = 3.6V
V IN = 0V, VCC = 3.6V
±10
±10
μA
RECEIVER SUPPLY CURRENT(2)
ICCRW
ICCRW
ICCRG
ICCRZ
Receiver Supply Current Worst Case
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
49
53
81
49
53
78
28
30
43
10
65
70
105
55
60
90
45
47
60
55
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
Worst Case Pattern,
DS90CF384A (Figure 3
Figure 6)
Receiver Supply Current Worst Case
Receiver Supply Current, 16 Grayscale
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
Worst Case Pattern,
DS90CF364A (Figure 3
Figure 6)
CL = 8 pF,
16 Grayscale Pattern,
(Figure 4 Figure 5 Figure 6)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
Receiver Supply Current
Power Down
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔV OD).
Receiver Switching Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 6)
CMOS/TTL High-to-Low Transition Time (Figure 6)
Min
Typ
2
Max
5
Units
ns
CHLT
1.8
1.96
5
ns
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 13,
Figure 14)
f = 25 MHz
1.20
2.82
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
6.91
12.62
18.33
24.04
29.75
35.46
0.7
7.67
13.38
19.09
24.80
30.51
36.22
1.1
8.53
14.24
19.95
25.66
31.37
37.08
1.4
ns
ns
ns
ns
ns
ns
ns
Receiver Input Strobe Position for Bit 0 (Figure 13,
Figure 14)
f = 65 MHz
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (2) (Figure 15)
2.9
5.1
3.3
5.5
3.6
5.8
ns
ns
ns
ns
ns
ns
ps
ps
7.3
7.7
8.0
9.5
9.9
10.2
12.4
14.6
11.7
13.9
750
500
12.1
14.3
f = 25 MHz
f = 65 MHz
(1) Typical values are given for VCC = 3.3V and TA = +25C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the
DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window -
RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
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Receiver Switching Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
RCOP
RCOH
RCOL
Parameter
Min
15
Typ
T
Max
50
Units
ns
RxCLK OUT Period (Figure 7)
RxCLK OUT High Time (Figure 7)
RxCLK OUT Low Time (Figure 7)
RxOUT Setup to RxCLK OUT (Figure 7)
RxOUT Hold to RxCLK OUT (Figure 7)
f = 65 MHz
5.0
5.0
4.5
4.0
3.5
7.6
6.3
7.3
6.3
5.0
9.0
9.0
ns
ns
RSRC
RHRC
RCCD
RPLLS
RPDD
ns
ns
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 8)
Receiver Phase Lock Loop Set (Figure 9)
7.5
10
1
ns
ms
μs
Receiver Power Down Delay (Figure 12 )
AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
4
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SNLS040I –JUNE 2000–REVISED APRIL 2013
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. “16 Grayscale” Test Pattern (DS90CF384A)
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SNLS040I –JUNE 2000–REVISED APRIL 2013
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Device Pin Name
Signal
Signal Pattern
Signal Frequency
TxCLK IN / RxCLK OUT
TxIN0 / RxOUT0
TxIN1 / RxOUT1
TxIN2 / RxOUT2
TxIN3 / RxOUT3
TxIN4 / RxOUT4
TxIN5 / RxOUT5
TxIN6 / RxOUT6
TxIN7 / RxOUT7
TxIN8 / RxOUT8
TxIN9 / RxOUT9
TxIN10 / RxOUT10
TxIN11 / RxOUT11
TxIN12 / RxOUT12
TxIN13 / RxOUT13
TxIN14 / RxOUT14
TxIN15 / RxOUT15
TxIN16 / RxOUT16
TxIN17 / RxOUT17
TxIN18 / RxOUT18
TxIN19 / RxOUT19
TxIN20 / RxOUT20
Dot Clk
R0
f
f / 16
R1
f / 8
R2
f / 4
R3
f / 2
R4
Steady State, Low
Steady State, Low
f / 16
R5
G0
G1
f / 8
G2
f / 4
G3
f / 2
G4
Steady State, Low
Steady State, Low
f / 16
G5
B0
B1
f / 8
B2
f / 4
B3
f / 2
B4
Steady State, Low
Steady State, Low
Steady State, High
Steady State, High
Steady State, High
B5
HSYNC
VSYNC
ENA
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 5. “16 Grayscale” Test Pattern (DS90CF364A)
6
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SNLS040I –JUNE 2000–REVISED APRIL 2013
Figure 6. DS90CF384A/DS90CF364A (Receiver) CMOS/TTL Output Load and Transition Times
Figure 7. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times
Figure 8. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay
Figure 9. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time
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Figure 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A
Figure 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A
Figure 12. DS90CF384A/DS90CF364A (Receiver) Power Down Delay
8
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SNLS040I –JUNE 2000–REVISED APRIL 2013
Figure 13. DS90CF384A (Receiver) LVDS Input Strobe Position
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Figure 14. DS90CF364A (Receiver) LVDS Input Strobe Position
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
ISI is dependent on interconnect length; may be zero.
Figure 15. Receiver LVDS Input Skew Margin
10
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SNLS040I –JUNE 2000–REVISED APRIL 2013
DS90CF384A PIN DESCRIPTIONS — 56 Lead TSSOP Package — 24-Bit FPD Link Receiver
Pin Name
I/O No.
Description
RxIN+
RxIN−
RxOUT
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
O
28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
O
I
I
GND
I
PLL VCC
I
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
DS90CF364A PIN DESCRIPTIONS — 48 Lead TSSOP Package — 18-Bit FPD Link Receiver
Pin Name
I/O No.
Description
RxIN+
I
I
3
3
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
O
I
I
GND
I
PLL VCC
I
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
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Pin Diagram for TSSOP Packages
Figure 16. DS90CF384A
DGG-56 Package
Figure 17. DS90CF364A
DGG-48 Package
12
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SNLS040I –JUNE 2000–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
DS90CF364AMTD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-10 to 70
-10 to 70
-10 to 70
-10 to 70
-10 to 70
-10 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DGG
48
48
48
48
56
56
38
TBD
Call TI
CU SN
Call TI
CU SN
CU SN
CU SN
Call TI
DS90CF364AMTD
>B
DS90CF364AMTD/NOPB
DS90CF364AMTDX
ACTIVE
NRND
DGG
DGG
DGG
DGG
DGG
38
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Call TI
DS90CF364AMTD
>B
1000
1000
34
TBD
DS90CF364AMTD
>B
DS90CF364AMTDX/NOPB
DS90CF384AMTD/NOPB
DS90CF384AMTDX/NOPB
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DS90CF364AMTD
>B
Green (RoHS
& no Sb/Br)
DS90CF384AMTD
>B
1000
Green (RoHS
& no Sb/Br)
DS90CF384AMTD
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CF364AMTDX
TSSOP
DGG
DGG
48
48
1000
1000
330.0
330.0
24.4
24.4
8.6
8.6
13.2
13.2
1.6
1.6
12.0
12.0
24.0
24.0
Q1
Q1
DS90CF364AMTDX/NOP TSSOP
B
DS90CF384AMTDX/NOP TSSOP
B
DGG
56
1000
330.0
24.4
8.6
14.5
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CF364AMTDX
DS90CF364AMTDX/NOPB
DS90CF384AMTDX/NOPB
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
48
48
56
1000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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