DS90CF386MTD/NOPB [TI]
+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 85MHz | DGG | 56 | -10 to 70;
| 型号： | DS90CF386MTD/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 85MHz | DGG | 56 | -10 to 70 光电二极管 接口集成电路 显示器 |
| 文件： | 总43页 (文件大小：1983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS90CF366, DS90CF386
SNLS055J –NOVEMBER 1999–REVISED MAY 2016
DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz
1 Features
3 Description
The DS90CF386 receiver converts four LVDS (Low
Voltage Differential Signaling) data streams back into
parallel 28 bits of LVCMOS data. Also available is the
DS90CF366 receiver that converts three LVDS data
streams back into parallel 21 bits of LVCMOS data.
The outputs of both receivers strobe on the falling
edge. A rising edge or falling edge strobe transmitter
will interoperate with a falling edge strobe receiver
without any translation logic.
1
•
•
20-MHz to 85-MHz Shift Clock Support
Rx Power Consumption <142 mW (Typical) at
85-MHz Grayscale
•
•
•
Rx Power-Down Mode <1.44 mW (Maximum)
ESD Rating >7 kV (HBM), >700 V (EIAJ)
Supports VGA, SVGA, XGA, and Single Pixel
SXGA
•
•
•
•
PLL Requires No External Components
The receiver LVDS clock operates at rates from
20 MHz to 85 MHz. The device phase-locks to the
input LVDS clock, samples the serial bit streams at
the LVDS data lines, and converts them into parallel
output data. At an incoming clock rate of 85 MHz,
each LVDS input line is running at a bit rate of
595 Mbps, resulting in a maximum throughput of
2.38 Gbps for the DS90CF386 and 1.785 Gbps for
the DS90CF366.
Compatible With TIA/EIA-644 LVDS Standard
Low Profile 56-Pin or 48-Pin TSSOP Package
DS90CF386 Also Available in a 64-Pin, 0.8-mm,
Fine Pitch Ball Grid Array (NFBGA) Package
2 Applications
•
•
•
•
•
Video Displays
Printers and Imaging
Digital Video Transport
Machine Vision
The use of these serial link devices is ideal for
solving EMI and cable size problems associated with
transmitting data over wide, high-speed parallel
LVCMOS interfaces. Both devices are offered in
TSSOP packages. The DS90CF386 is also offered in
a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA)
package which provides a 44% reduction in PCB
footprint compared to the 56-pin TSSOP package.
Open LDI-to-RGB Bridge
Device Information(1)
PART NUMBER
PACKAGE
TSSOP (48)
TSSOP (56)
NFBGA (64)
BODY SIZE (NOM)
12.50 mm × 6.10 mm
14.00 mm × 6.10 mm
8.00 mm × 8.00 mm
DS90CF366
DS90CF386
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Block Diagram (DS90CF366)
ꢀë5{ /able or ꢂ/. Çrace
5{90/C366 21-.it wx
18-.it wD. 5isplay Ünit
wxhÜÇ[20:0]
ꢀë5{ 5ata
100 Q
Graphics Processor Unit
(GPU)
100 Q
100 Q
21-Bit Tx Data
(3 LVDS Data, 1 LVDS Clock)
ꢀë5{ /lock
wx/ꢀY
PLL
100 Q
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90CF366, DS90CF386
SNLS055J –NOVEMBER 1999–REVISED MAY 2016
www.ti.com
Table of Contents
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
Power Supply Recommendations...................... 26
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Switching Characteristics.......................................... 9
6.7 Timing Diagrams....................................................... 9
6.8 Typical Characteristics............................................ 16
Detailed Description ............................................ 17
7.1 Overview ................................................................ 17
7.2 Functional Block Diagrams ..................................... 17
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Examples................................................... 26
11 Device and Documentation Support ................. 28
11.1 Documentation Support ........................................ 28
11.2 Community Resources.......................................... 28
11.3 Trademarks........................................................... 28
11.4 Electrostatic Discharge Caution............................ 28
11.5 Glossary................................................................ 28
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (April 2013) to Revision J
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changed Figure 8 and Figure 9 to clarify that TxIN on Tx is the same as RxOUT on Rx .................................................. 12
Changed title of DS90CF366 mapping to clarify the make-up of the LVDS lines................................................................ 13
Deleted references to power sequencing requirements for FPD-Link I transmitters .......................................................... 19
•
•
•
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
2
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SNLS055J –NOVEMBER 1999–REVISED MAY 2016
5 Pin Configuration and Functions
DGG Package
48-Pin TSSOP
Top View
RxOUT17
RxOUT18
GND
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
2
RxOUT16
RxOUT15
RxOUT14
GND
3
RxOUT19
RxOUT20
NC
4
5
6
RxOUT13
VCC
LVDS_GND
RxIN0-
7
8
RxOUT12
RxOUT11
RxOUT10
GND
RxIN0+
9
RxIN1-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RxIN1+
LVDS_VCC
LVDS_GND
RxIN2-
RxOUT9
VCC
RxOUT8
RxOUT7
RxOUT6
GND
RxIN2+
RxCLKIN-
RxCLKIN+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWR_DWN
RxCLKOUT
RxOUT0
RxOUT5
RxOUT4
RxOUT3
VCC
RxOUT2
RxOUT1
GND
Not to scale
Copyright © 1999–2016, Texas Instruments Incorporated
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SNLS055J –NOVEMBER 1999–REVISED MAY 2016
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DGG Package
56-Pin TSSOP
Top View
RxOUT22
RxOUT23
RxOUT24
GND
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
2
RxOUT21
RxOUT20
RxOUT19
GND
3
4
RxOUT25
RxOUT26
RxOUT27
LVDS_GND
RxIN0-
5
6
RxOUT18
RxOUT17
RxOUT16
VCC
7
8
9
RxIN0+
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RxOUT15
RxOUT14
RxOUT13
GND
RxIN1-
RxIN1+
LVDS_VCC
LVDS_GND
RxIN2-
RxOUT12
RxOUT11
RxOUT10
VCC
RxIN2+
RxCLKIN-
RxCLKIN+
RxIN3-
RxOUT9
RxOUT8
RxOUT7
GND
RxIN3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWR_DWN
RxCLKOUT
RxOUT0
GND
RxOUT6
RxOUT5
RxOUT4
RxOUT3
VCC
RxOUT2
RxOUT1
Not to scale
4
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SNLS055J –NOVEMBER 1999–REVISED MAY 2016
NZC Package
64-Pin NFBGA
Top View
1
2
3
4
5
6
7
8
A
B
C
D
E
F
RxOUT17
VCC
RxOUT15
GND
RxOUT12
VCC
RxOUT8
RxOUT7
RxOUT6
GND
NC
NC
RxOUT16
RxOUT18
RxOUT19
GND
RxOUT11
RxOUT14
RxOUT13
GND
RxOUT4
VCC
RxOUT5
RxOUT3
RxOUT1
GND
RxOUT21
VCC
RxOUT9
RxOUT10
LVDS_GND
RxIN2+
NC
RxOUT20
RxOUT24
RxOUT26
NC
RxOUT2
RxCLKOUT
LVDS_
VCC
RxOUT22
RxOUT23
RxOUT25
RxOUT27
PWR_DWN
PLL_GND
RxIN3-
RxOUT0
PLL_
VCC
NC
RxIN1-
RxIN1+
NC
G
H
LVDS_GND
RxIN0+
RxIN2-
LVDS_GND
RxCLKIN+
PLL_GND
LVDS_
VCC
RxIN0-
LVDS_GND
RxCLKIN-
RxIN3+
Not to scale
Pin Functions
PIN
DS90CF366
TSSOP
DS90CF386
TYPE(1)
DESCRIPTION
NAME
TSSOP
NFBGA
3, 25, 32,
38, 44
4, 28, 36,
44, 52
A4, B1, B6,
D8, E3
GND
G
Ground pins for LVCMOS outputs.
E5, G3, G7,
H5
LVDS GND
LVDS VCC
NC
7, 13, 18
8, 14, 21
G
P
Ground pins for LVDS inputs.
Power supply pin for LVDS inputs.
Pins not connected.
12
6
13
—
E4, H4
B2, C2, C7,
F3, F8, G2
—
PLL GND
PLL VCC
19, 21
20
22, 24
23
F6, G8
F7
G
P
Ground pin for PLL.
Power supply for PLL.
(1) G = Ground, I = Input, O = Output, and P = Power
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Pin Functions (continued)
PIN
DS90CF366
TSSOP
DS90CF386
TYPE(1)
NFBGA
DESCRIPTION
NAME
TSSOP
LVCMOS level input. When asserted (low input) the receiver
outputs are low.
PWR DWN
22
25
E6
I
RxCLKIN+
RxCLKIN-
17
16
18
17
H7
H6
I
I
Positive LVDS differential clock input.
Negative LVDS differential clock input.
LVCMOS level clock output. The falling edge acts as data
strobe.
RxCLKOUT
23
26
E7
O
RxIN0+
9
10
9
H3
H2
G4
F4
F5
G5
H8
G6
E8
C8
D7
B8
C6
B7
A8
A7
A6
C5
D5
B4
A5
D4
C4
A3
B3
A1
C3
D3
D2
C1
E1
F1
E2
G1
F2
H1
I
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
LVCMOS level data output.
Power supply pins for LVCMOS outputs.
RxIN0-
8
I
RxIN1+
11
12
11
16
15
20
19
27
29
30
32
33
34
35
37
38
39
41
42
43
45
46
47
49
50
51
53
54
55
1
I
RxIN1-
10
I
RxIN2+
15
I
RxIN2-
14
I
RxIN3+
—
I
RxIN3-
—
I
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT10
RxOUT11
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
RxOUT17
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT23
RxOUT24
RxOUT25
RxOUT26
RxOUT27
VCC
24
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
2
4
5
—
—
—
2
—
3
—
5
—
—
6
7
28, 36, 42, 48
31, 40, 48, 56 A2, B5, D1, D6
6
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SNLS055J –NOVEMBER 1999–REVISED MAY 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
4
UNIT
Supply voltage, VCC
V
V
V
CMOS/LVCMOS output voltage
LVDS receiver input voltage
DS90CF366, TSSOP package
VCC + 0.3
VCC + 0.3
1.61
Power dissipation capacity at 25°C
DS90CF386
TSSOP package
NFBGA package
1.89
W
2
TSSOP soldering (4 s)
Lead temperature
260
°C
NFBGA soldering, reflow (20 s)
220
Operating junction temperature, TJ
Storage temperature, Tstg
150
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±7000
±700
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
UNIT
VCC
Supply voltage
3.3
V
V
Receiver input
0
2.4
VNOISE
TA
Supply noise voltage
Operating free-air temperature
100
70
mVPP
°C
–10
25
6.4 Thermal Information
DS90CF366
DGG (TSSOP)
48 PINS
67.8
DS90CF386
THERMAL METRIC(1)
DGG (TSSOP)
NZC (NFBGA)
UNIT
56 PINS
64.6
20.6
33.3
1
64 PINS
65.7
23.8
44.9
1
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
22.1
34.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.1
ψJB
34.5
33
44.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
LVCMOS DC SPECIFICATIONS
VIH
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input clamp voltage
2
VCC
0.8
V
V
VIL
GND
VOH
VOL
VCL
IOH = –0.4 mA
IOL = 2 mA
2.7
3.3
0.06
–0.79
1.8
V
0.3
–1.5
15
V
ICL = –18 mA
VIN = 0.4 V, 2.5 V or VCC
VIN = GND
V
uA
uA
mA
IIN
Input current
–10
0
IOS
Output short circuit current
VOUT = 0 V
–60
–120
100
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
Differential input high threshold V CM = 1.2 V
mV
mV
μA
Differential input low threshold
–100
V IN = 2.4 V, VCC = 3.6 V
V IN = 0 V, VCC = 3.6 V
±10
±10
I IN
Input current
μA
RECEIVER SUPPLY CURRENT
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 85 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 85 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 85 MHz
49
53
81
96
49
53
78
90
28
30
43
43
70
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CL = 8 pF, worst case pattern,
DS90CF386, see Figure 1 and
Figure 4
114
135
60
Receiver supply current
worst case
ICCRW
CL = 8 pF, worst case pattern,
DS90CF366, see Figure 1 and
Figure 4
65
100
115
45
CL = 8 pF, 16 grayscale pattern,
see Figure 2, Figure 3, and
Figure 4
47
Receiver supply current,
16 grayscale
ICCRG
60
70
Receiver supply current
ICCRZ
Power Down = low receiver outputs stay low during
power down mode
140
400
μA
power down(2)
(1) Typical values are given for VCC = 3.3 V and TA = 25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔV OD).
8
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SNLS055J –NOVEMBER 1999–REVISED MAY 2016
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
2
MAX UNIT
CLHT
CHLT
CMOS or LVCMOS low-to-high transition time
CMOS or LVCMOS high-to-low transition time
See Figure 4
See Figure 4
3.5
3.5
ns
ns
1.8
f = 85 MHz, see Figure 11 and
Figure 12
RSPos0
Receiver input strobe position for bit 0
0.49
0.84
1.19
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
Receiver input strobe position for bit 1
Receiver input strobe position for bit 2
Receiver input strobe position for bit 3
Receiver input strobe position for bit 4
Receiver input strobe position for bit 5
Receiver input strobe position for bit 6
RxIN skew margin(2)
f = 85 MHz
2.17
3.85
5.53
7.21
8.89
10.57
290
11.76
4.5
2.52
4.2
2.87
4.55
6.23
7.91
9.59
11.27
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
μs
f = 85 MHz
f = 85 MHz
5.88
7.56
9.24
10.92
f = 85 MHz
f = 85 MHz
f = 85 MHz
f = 85 MHz, see Figure 13
See Figure 5
RCOP
RxCLK OUT period
T
5
5
50
7
RCOH
RCOL
RxCLK OUT high time
f = 85 MHz, see Figure 5
f = 85 MHz, see Figure 5
f = 85 MHz, see Figure 5
f = 85 MHz, see Figure 5
25°C, VCC = 3.3 V, see Figure 6
See Figure 7
RxCLK OUT low time
4
6.5
RSRC
RxOUT setup to RxCLK OUT
RxOUT hold to RxCLK OUT
RxCLK IN to RxCLK OUT delay
Receiver phase lock loop set
Receiver power down delay
2
RHRC
3.5
RCCD
5.5
7
9.5
10
1
RPLLS
RPDD
See Figure 10
(1) Typical values are given for VCC = 3.3 V and TA = 25°C.
(2) Receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).
6.7 Timing Diagrams
Figure 1. Test Pattern, Worst Case
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Timing Diagrams (continued)
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and CMOS or LVCMOS I/O.
(2) The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 1 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 2. Test Pattern, 16 Grayscale (DS90CF386)
10
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Timing Diagrams (continued)
Device Pin Name
Signal
Signal Pattern
Signal Frequency
TxCLK IN / RxCLK OUT
TxIN0 / RxOUT0
TxIN1 / RxOUT1
TxIN2 / RxOUT2
TxIN3 / RxOUT3
TxIN4 / RxOUT4
TxIN5 / RxOUT5
TxIN6 / RxOUT6
TxIN7 / RxOUT7
TxIN8 / RxOUT8
TxIN9 / RxOUT9
TxIN10 / RxOUT10
TxIN11 / RxOUT11
TxIN12 / RxOUT12
TxIN13 / RxOUT13
TxIN14 / RxOUT14
TxIN15 / RxOUT15
TxIN16 / RxOUT16
TxIN17 / RxOUT17
TxIN18 / RxOUT18
TxIN19 / RxOUT19
TxIN20 / RxOUT20
Dot Clk
R0
f
f / 16
R1
f / 8
R2
f / 4
R3
f / 2
R4
Steady State, Low
Steady State, Low
f / 16
R5
G0
G1
f / 8
G2
f / 4
G3
f / 2
G4
Steady State, Low
Steady State, Low
f / 16
G5
B0
B1
f / 8
B2
f / 4
B3
f / 2
B4
Steady State, Low
Steady State, Low
Steady State, High
Steady State, High
Steady State, High
B5
HSYNC
VSYNC
ENA
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and CMOS or LVCMOS I/O.
(2) The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 1 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 3. Test Pattern, 16 Grayscale (DS90CF366)
Figure 4. DS90CF3x6 (Receiver) CMOS or LVCMOS Output Load and Transition Times
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Timing Diagrams (continued)
Figure 5. DS90CF3x6 (Receiver) Setup or Hold and High or Low Times
Figure 6. DS90CF3x6 (Receiver) Clock In to Clock Out Delay
Figure 7. DS90CF3x6 (Receiver) Phase Lock Loop Set Time
wx/[Y Lb
(ꢁifferential)
wxLb3
({ingle-ꢀnded)
wxhÜÇ5-1
wxhÜÇ20-1
wxhÜÇ9-1
wxhÜÇ1-1
wxhÜÇ23
wxhÜÇ26
wxhÜÇ18
wxhÜÇ7
wxhÜÇ16
wxhÜÇ24
wxhÜÇ14
wxhÜÇ4
wxhÜÇ5
wxhÜÇ20
wxhÜÇ9
wxhÜÇ1
wxhÜÇ27-1
wxhÜÇ19-1
wxhÜÇ8-1
wxhÜÇ0-1
wxhÜÇ17
wxhÜÇ25
wxhÜÇ15
wxhÜÇ6
wxhÜÇ11
wxhÜÇ22
wxhÜÇ13
wxhÜÇ3
wxhÜÇ10
wxhÜÇ21
wxhÜÇ12
wxhÜÇ2
wxhÜÇ27
wxhÜÇ19
wxhÜÇ8
wxhÜÇ0
wxLb2
({ingle-ꢀnded)
wxLb1
({ingle-ꢀnded)
wxLb0
({ingle-ꢀnded)
Figure 8. DS90CF386 Mapping of 28 LVCMOS Parallel Data to 4D + C LVDS Serialzied Data
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Timing Diagrams (continued)
wx/[Y Lb
(ꢁifferential)
wxLb2
({ingle-ꢀnded)
wxhÜÇ20
wxhÜÇ13
wxhÜÇ6
wxhÜÇ18
wxhÜÇ11
wxhÜÇ4
wxhÜÇ15
wxhÜÇ8
wxhÜÇ1
wxhÜÇ15-1
wxhÜÇ8-1
wxhÜÇ1-1
wxhÜÇ14-1
wxhÜÇ19
wxhÜÇ12
wxhÜÇ5
wxhÜÇ17
wxhÜÇ10
wxhÜÇ3
wxhÜÇ16
wxhÜÇ9
wxhÜÇ2
wxhÜÇ14
wxhÜÇ7
wxhÜÇ0
wxLb1
({ingle-ꢀnded)
wxhÜÇ7-1
wxhÜÇ0-1
wxLb0
({ingle-ꢀnded)
Figure 9. DS90CF366 Mapping of 21 LVCMOS Parallel Data to 3D + C LVDS Serialized Data
Figure 10. DS90CF3x6 (Receiver) Power Down Delay
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Timing Diagrams (continued)
Figure 11. DS90CF386 (Receiver) LVDS Input Strobe Position
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Timing Diagrams (continued)
Figure 12. DS90CF366 (Receiver) LVDS Input Strobe Position
C: Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos: Transmitter output pulse position (min and max)
Cable skew: Typically 10 ps–40 ps per foot, media dependent
RSKM = Cable skew (type, length) + source clock jitter (cycle-to-cycle)(1) + ISI (inter-symbol interference)(2)
(1) Cycle-to-cycle jitter depends on the Tx source. Clock jitter should be maintained to less than 250 ps at 85 MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 13. Receiver LVDS Input Skew Margin
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6.8 Typical Characteristics
Çime (4.0 ns/5Lë)
Çime (20.0 ns/5Lë)
Figure 15. Typical RxOUT Strobe Position at 85 MHz
Figure 14. Parallel PRBS-7 on LVCMOS Outputs at 85 MHz
Çime (4.0 ns/5Lë)
Çime (4.0 ns/5Lë)
Figure 16. Typical RxOUT Setup Time at 85 MHz
(RSRC = 4.5 ns)
Figure 17. Typical RxOUT Hold Time at 85 MHz
(RHRC = 5.9 ns)
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7 Detailed Description
7.1 Overview
The DS90CF386 is a receiver that converts four LVDS (Low Voltage Differential Signaling) data streams into
parallel 28 bits of LVCMOS data (24 bits of RGB and 4 bits of HSYNC, VSYNC, DE, and CNTL). The
DS90CF366 is a receiver that converts three LVDS data streams into parallel 21 bits of LVCMOS data (18 bits of
RGB and 3 bits of HSYNC, VSYNC, and DE). An internal PLL locks to the incoming LVDS clock ranging from 20
to 85 MHz. The locked PLL ensures a stable clock to sample the output LVCMOS data on the Receiver Clock
Out falling edge. These devices feature a PWR DWN pin to put the device into low power mode when there is no
active input data.
7.2 Functional Block Diagrams
100 Ω
100 Ω
4 x LVDS Data
(140 to 595 Mbps on
Each LVDS Channel)
28 x LVCMOS
Outputs
100 Ω
100 Ω
LVDS Clock
(20 to 85 MHz)
100 Ω
PLL
Receiver Clock Out
PWR DWN
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Figure 18. DS90CF386 Block Diagram
100 Q
100 Q
100 Q
3 x [ë5{ 5ꢀtꢀ
(140 to ꢁ9ꢁ abps on ꢂꢀcꢃ
[ë5{ /ꢃꢀnnel)
21 x [ë/ah{
hutputs
[ë5{ /lock
(20 to 8ꢁ aIz)
100 Q
PLL
weceiver /lock hut
ꢄíw 5íꢅ
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Figure 19. DS90CF366 Block Diagram
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7.3 Feature Description
The DS90CF386 and DS90CF366 consist of several key blocks:
•
•
•
•
LVDS Receivers
Phase Locked Loop (PLL)
Serial LVDS-to-Parallel LVCMOS Converter
LVCMOS Drivers
7.3.1 LVDS Receivers
There are five differential LVDS inputs to the DS90CF386 and four differential LVDS inputs to the DS90CF366.
For the DS90CF386, four of the LVDS inputs contain serialized data originating from a 28-bit source transmitter.
For the DS90CF366, three of the LVDS inputs contain serialized data originating from a 21-bit source transmitter.
The remaining LVDS input contains the LVDS clock associated with the data pairs.
7.3.1.1 LVDS Input Termination
The DS90CF386 and DS90CF366 require a single 100-Ω terminating resistor across the true and complement
lines on each differential pair of the receiver input. To prevent reflections due to stubs, this resistor should be
placed as close to the device input pins as possible. Figure 20 shows an example.
Figure 20. LVDS Serialized Link Termination
7.3.2 Phase Locked Loop (PLL)
The FPD Link I devices use an internal PLL to recover the clock transmitted across the LVDS interface. The
recovered clock is then used as a reference to determine the sampling position of the seven serial bits received
per clock cycle. The width of each bit in the serialized LVDS data stream is one-seventh the clock period.
Differential skew (Δt within one differential pair), interconnect skew (Δt of one differential pair to another), and
clock jitter will all reduce the available window for sampling the LVDS serial data streams. Individual bypassing of
each VCC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock to
improve the overall jitter budget.
7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
After the PLL locks to the incoming LVDS clock, the receiver deserializes each LVDS differential data pair into
seven parallel LVCMOS data outputs per clock cycle. For the DS90CF386, the LVDS data inputs map to
LVCMOS outputs according to Figure 8. For the DS90CF366, the LVDS data inputs map to LVCMOS outputs
according to Figure 9.
7.3.4 LVCMOS Drivers
The LVCMOS outputs from the DS90CF386 and DS90CF366 are the deserialized parallel single-ended data
from the serialized LVDS differential data pairs. Each LVCMOS output is clocked by the PLL and strobes on the
RxCLKOUT falling edge. All unused DS90CF386 and DS90CF366 RxOUT outputs can be left floating.
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7.4 Device Functional Modes
7.4.1 Power Sequencing and Power-Down Mode
The DS90CF386 and DS90CF366 may be placed into a power down mode at any time by asserting the PWR
DWN pin (active low). The DS90CF386 and DS90CF366 are also designed to protect themselves from
accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) retain the states they were in when the clocks stopped.
When the receiver board loses power, the receiver inputs are controlled by a failsafe bias circuitry. The LVDS
inputs are High-Z during initial power on and power off conditions. Current is limited to 5 mA per input, thus
avoiding the potential for latch-up when powering the device.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90F386 and DS90CF366 are designed for a wide variety of data transmission applications. The use of
serialized LVDS data lines in these applications allows for efficient signal transmission over a narrow bus width,
thereby reducing cost, power, and space.
8.2 Typical Applications
Figure 21 and Figure 22 show typical applications of the DS90CF386 and DS90CF366 for displays when used as
an OpenLDI-to-RGB bridge.
LVDS Cable or PCB Trace
DS90CF386 28-Bit Rx
24-Bit RGB Display Unit
RxOUT
[27:0]
LVDS Data
100 Ω
100 Ω
100 Ω
Graphics Processor Unit (GPU)
28-Bit Tx Data
(4 LVDS Data, 1 LVDS Clock)
100 Ω
LVDS
Clock
RxCLK
100 Ω
PLL
100 Ω
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Figure 21. Typical DS90CF386 Application Block Diagram
ꢀë5{ /able or ꢂ/. Çrace
5{90/C366 21-.it wx
18-.it wD. 5isplay Ünit
wxhÜÇ[20:0]
ꢀë5{ 5ata
100 Q
Graphics Processor Unit
(GPU)
100 Q
100 Q
21-Bit Tx Data
(3 LVDS Data, 1 LVDS Clock)
ꢀë5{ /lock
wx/ꢀY
PLL
100 Q
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Figure 22. Typical DS90CF366 Application Block Diagram
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Typical Applications (continued)
8.2.1 Design Requirements
For this design example, follow the requirements in Table 1.
Table 1. Design Parameters
PARAMETER
DESIGN REQUIREMENTS
LVDS clock must be within 20 MHz to 85 MHz.
Operating frequency
DS90CF386: No higher than 24 bpp. The maximum supported resolution is 8-bit RGB.
DS90CF366: No higher than 18 bpp. The maximum supported resolution is 6-bit RGB.
Bit resolution
Determine the appropriate mapping required by the panel display following the DS90CF386 or
DS90CF366 outputs.
Bit data mapping
RSKM (Receiver skew margin)
Input termination for RxIN±
RxIN± board trace impedance
LVCMOS outputs
Ensure that there is acceptable margin between Tx pulse position and Rx strobe position.
Inputs require a 100 Ω ± 10% resistor across each LVDS differential pair. Place as close as
possible to IC input pins.
Design differential trace impedance with 100 Ω ±5%
If unused, leave pins floating. Series resistance on each LVCMOS output optional to reduce
reflections from long board traces. If used, 33-Ω series resistance is typical.
Use a 0.1-µF capacitor to minimize power supply noise. Place as close as possible to VCC
pins.
DC power supply coupling capacitors
8.2.2 Detailed Design Procedure
To design with the DS90CF386 or DS90CF366, determine the following:
•
•
•
•
Cable Interface
Bit Resolution and Operating Frequency
Bit Mapping from Receiver to Endpoint Panel Display
RSKM Interoperability with Transmitter Pulse Position Margin
8.2.2.1 Cables
A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The
DS90CF366 requires four pairs of signal wires and the DS90CF386 requires five pairs of signal wires. The ideal
cable interface has a constant 100-Ω differential impedance throughout the path. It is also recommended that
cable skew remain below 120 ps (assuming 85 MHz clock rate) to maintain a sufficient data sampling window at
the receiver.
Depending upon the application and data rate, the interconnecting media between Tx and Rx may vary. For
example, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is
less critical. For higher speed or long distance applications, the media's performance becomes more critical.
Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs).
For example, twin-coax cables have been demonstrated at distances as long as five meters and with the
maximum data transfer of 2.38 Gbps (DS90CF366) and 1.785 Gbps (DS90CF386).
8.2.2.2 Bit Resolution and Operating Frequency Compatibility
The bit resolution of the endpoint panel display reveals whether there are enough bits available in the
DS90CF386 or DS90CF366 to output the required data per pixel. The DS90CF386 has 28 parallel LVCMOS
outputs and can therefore provide a bit resolution up to 24 bpp (bits per pixel). In each clock cycle, the remaining
bits are the three control signals (HSync, VSync, DE) and one spare bit. The DS90CF366 has 21 parallel
LVCMOS outputs and can therefore provide a bit resolution up to 18 bpp (bits per pixel). In each clock cycle, the
remaining bits are the three control signals (HSync, VSync, DE).
The number of pixels per frame and the refresh rate of the endpoint panel display indicate the required operating
frequency of the deserializer clock. To determine the required clock frequency, refer to Equation 1.
f_Clk = [H_Active + H_Blank] × [V_Active + V_Blank] × f_Vertical
where
•
H_Active = Active Display Horizontal Lines
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•
•
•
•
•
H_Blank = Blanking Period Horizontal Lines
V_Active = Active Display Vertical Lines
V_Blank = Blanking Period Vertical Lines
f_Vertical = Refresh Rate (in Hz)
f_Clk = Operating Frequency of LVDS clock
(1)
In each frame, there is a blanking period associated with horizontal rows and vertical columns that are not
actively displayed on the panel. These blanking period pixels must be included to determine the required clock
frequency. Consider the following example to determine the required LVDS clock frequency:
•
•
•
•
•
H_Active = 640
H_Blank = 40
V_Active = 480
V_Blank = 41
f_Vertical = 59.95 Hz
Thus, the required operating frequency is determined with Equation 2.
[640 + 40] × [480 + 41] × 59.95 = 21239086 Hz ≈ 21.24 MHz
(2)
Since the operating frequency for the PLL in the DS90CF386 and DS90CF366 ranges from 20 to 85 MHz, the
DS90CF386 and DS90CF366 can support a panel display with the aforementioned requirements.
If the specific blanking interval is unknown, the number of pixels in the blanking interval can be approximated to
20% of the active pixels. Equation 3 can be used as a conservative approximation for the operating LVDS clock
frequency:
f_Clk ≈ H_Active × V_Active × f_Vertical × 1.2
(3)
Using this approximation, the operating frequency for the example in this section is estimated with Equation 4.
640 × 480 × 59.95 × 1.2 = 22099968 Hz ≈ 22.10 MHz
(4)
8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
Ensure that the LVCMOS outputs are mapped to align with the endpoint display RGB mapping requirements
following the deserializer. See the following for two popular mapping topologies for 8-bit RGB data.
1. LSBs are mapped to RxIN3±.
2. MSBs are mapped to RxIN3±.
Table 2 and Table 3 depict how these two popular topologies can be mapped to the DS90CF386 outputs.
Table 2. 8-Bit Color Mapping with LSBs on RxIN3±
LVDS INPUT
CHANNEL
LVDS BIT STREAM
POSITION
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN6
TxIN7
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT18
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
RxIN0
MSB
MSB
RxIN1
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Table 2. 8-Bit Color Mapping with LSBs on RxIN3± (continued)
LVDS INPUT
CHANNEL
LVDS BIT STREAM
POSITION
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
TxIN19
TxIN20
TxIN21
TxIN22
TxIN24
TxIN25
TxIN26
TxIN27
TxIN5
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT5
B4
B5
B6
RxIN2
B7
MSB
Horizontal sync
Vertical sync
Data enable
LSB
HSYNC
VSYNC
DE
R0
R1
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
RxOUT10
RxOUT11
RxOUT16
RxOUT17
RxOUT23
G0
LSB
LSB
RxIN3
G1
B0
B1
GP
General purpose
Table 3. 8-Bit Color Mapping with MSBs on RxIN3±
LVDS INPUT
CHANNEL
LVDS BIT STREAM
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
POSITION
TxIN0
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT5
RxOUT10
RxOUT11
RxOUT16
RxOUT17
RxOUT23
R0
R1
LSB
TxIN1
TxIN2
R2
RxIN0
TxIN3
R3
TxIN4
R4
TxIN6
R5
TxIN7
G0
LSB
LSB
TxIN8
G1
TxIN9
G2
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN24
TxIN25
TxIN26
TxIN27
TxIN5
G3
RxIN1
G4
G5
B0
B1
B2
B3
B4
RxIN2
B5
HSYNC
VSYNC
DE
R6
Horizontal sync
Vertical sync
Data enable
R7
MSB
MSB
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
G6
RxIN3
G7
B6
B7
MSB
GP
General purpose
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In the case where either DS90CF386 or DS90CF366 is used to support 18 bpp, Table 2 is commonly used,
where RxIN3± (if applicable) is left as No Connect. With this mapping, MSBs of RGB data are retained on
RXIN0±, RXIN1±, and RXIN2± while the two LSBs for the original 8-bit RGB resolution are ignored from RxIN3±.
8.2.2.4 RSKM Interoperability
One of the most important factors when designing the receiver into a system application is assessing how much
RSKM (Receiver Skew Margin) is available. In each LVDS clock cycle, the LVDS data stream carries seven
serialized data bits. Ideally, the Transmit Pulse Position for each bit will occur every (n × T)/7 seconds, where
n = Bit Position and T = LVDS Clock Period. Likewise, ideally the Rx Strobe Position for each bit will occur every
((n + 0.5) × T)/7 seconds. However, in real systems, both LVDS Tx and Rx will have non-ideal pulse and strobe
position for each bit position due to the effects of cable skew, clock jitter, and ISI. This concept is illustrated in
Figure 23.
wspos1
wspos0
max
min
max
min
Çppos0
.it 0 [eft aꢀrgin
.it 0 wight aꢀrgin
Çppos1
.it 1 [eft aꢀrgin
.it 1 wight aꢀrgin
Çppos2
Ldeal wx {trobe
ꢀosition
Ldeal wx {trobe
ꢀosition
max
max
min
min
max
min
.it0
.it1
Figure 23. RSKM Measurement Example
All left and right margins for Bits 0-6 must be considered in order to determine the absolute minimum for the
whole LVDS bit stream. This absolute minimum corresponds to the RSKM.
To improve RSKM performance between LVDS transmitter and receiver, designers often either advance or delay
the LVDS clock compared to the LVDS data. Moving the LVDS clock compared to the LVDS data can improve
the location of the setup and hold time for the transmitter compared to the setup and hold time for the receiver.
If there is less left bit margin than right bit margin, the LVDS clock can be delayed so that the Rx strobe position
for incoming data appears to be delayed. If there is less right bit margin than left bit margin, all the LVDS data
pairs can be delayed uniformly so that the LVDS clock and Rx strobe position for incoming data appear to
advance. To delay an LVDS data or clock pair, designers either add more PCB trace length or install a capacitor
between the LVDS transmitter and receiver. It is important to note that when using these techniques, all
serialized bit positions are shifted right or left uniformly.
When designing the DS90CF386 or DS90CF366 receiver with a third-party OpenLDI transmitter, users must
calculate the skew margin budget (RSKM) based on the Tx pulse position and the Rx strobe position to ensure
error-free transmission. For more information about calculating RSKM, refer to Application Note, Receiver Skew
Margin for Channel Link I and FPD Link I Devices (SNLA249).
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8.2.3 Application Curves
The following application curves are examples taken with a DS90C385A serializer interfacing to a DS90CF386
deserializer with nominal temperature (25ºC) and voltage supply (3.3 V) at an operating frequency of 85 MHz.
Çime (4.0 ns/5Lë)
Çime (2.0 ns/5Lë)
Figure 25. LVDS CLKIN Aligned With LVCMOS RxCLKOUT
Figure 24. LVDS RxIN0± Aligned With LVCMOS
RxCLKOUT
Çime (4.0 ns/5Lë)
Çime (20.0 ns/5Lë)
Figure 26. RxOUT Strobe On Falling Edge Of RxCLKOUT
Figure 27. PRBS-7 Output On RxOUT Channels
Copyright © 1999–2016, Texas Instruments Incorporated
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DS90CF366, DS90CF386
SNLS055J –NOVEMBER 1999–REVISED MAY 2016
www.ti.com
9 Power Supply Recommendations
Proper power supply decoupling is important to ensure a stable power supply with minimal power supply noise.
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach, three parallel-connected decoupling capacitors (multi-layered ceramic type in surface
mount form factor) between each VCC (VCC, PLL VCC, LVDS VCC) and the ground plane(s) are recommended.
The three capacitor values are 0.1 μF, 0.01 μF, and 0.001 μF. The preferred capacitor size is 0402. An example
is shown in Figure 28. The designer should employ wide traces for power and ground and ensure each capacitor
has its own via to the ground plane. This helps to reduce overall inductance with regards to power supply
filtering. If board space is limiting the number of bypass capacitors, the PLL VCC should receive the most filtering.
Next would be the LVDS VCC pins and finally the logic VCC pins.
Figure 28. Recommended Bypass Capacitor Decoupling
Configuration for VCC, PLL VCC, and LVDS VCC
10 Layout
10.1 Layout Guidelines
As with any high speed design, board designers must maximize signal integrity by limiting reflections and
crosstalk that can adversely affect high frequency and EMI performance. The following practices are
recommended layout guidelines to optimize device performance.
•
Ensure that differential pair traces are always closely coupled to eliminate noise interference from other
signals and take full advantage of the common mode noise canceling effect of the differential signals.
•
•
•
•
Maintain equal length on signal traces for a given differential pair.
Limit impedance discontinuities by reducing the number of vias on signal traces.
Eliminate any 90º angles on traces and use 45º bends instead.
If a via must exist on one signal polarity, mirror the via implementation on the other polarity of the differential
pair.
•
•
Match the differential impedance of the selected physical media. This impedance should also match the value
of the termination resistor that is connected across the differential pair at the receiver's input.
When possible, use short traces for LVDS inputs.
10.2 Layout Examples
The following images show an example layout of the DS90CF386. Traces in blue correspond to the top layer and
the traces in green correspond to the bottom layer. Note that differential pair inputs to the DS90CF386 are tightly
coupled and close to the connector pins. In addition, observe that the power supply decoupling capacitors are
placed as close as possible to the power supply pins with through vias in order to minimize inductance. The
principles illustrated in this layout can also be applied to the 48-pin DS90CF366.
26
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Copyright © 1999–2016, Texas Instruments Incorporated
Product Folder Links: DS90CF366 DS90CF386
DS90CF366, DS90CF386
www.ti.com
SNLS055J –NOVEMBER 1999–REVISED MAY 2016
Layout Examples (continued)
Figure 29. Example Layout With DS90CF386 (U1)
100-Q [ë5{
Çerminations close to
wxLb pins
33 Q {ꢀŒ]ꢀ• wꢀ•]•š}Œ•
occasionally used to
reduce reflections
Figure 30. Example Layout Close-Up
Copyright © 1999–2016, Texas Instruments Incorporated
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Product Folder Links: DS90CF366 DS90CF386
DS90CF366, DS90CF386
SNLS055J –NOVEMBER 1999–REVISED MAY 2016
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
Application Note, Receiver Skew Margin for Channel Link I and FPD Link I Devices, SNLA249
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Copyright © 1999–2016, Texas Instruments Incorporated
Product Folder Links: DS90CF366 DS90CF386
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DGG
DGG
DGG
DGG
DGG
NZC
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90CF366MTD/NOPB
DS90CF366MTDX/NOPB
DS90CF386MTD
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
NFBGA
48
48
56
56
56
64
38
RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-235C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-4-260C-72 HR
-10 to 70
-10 to 70
-10 to 70
-10 to 70
-10 to 70
-10 to 70
DS90CF366MTD
>B
ACTIVE
NRND
1000 RoHS & Green
SN
Call TI
SN
DS90CF366MTD
>B
34
34
Non-RoHS
& Green
DS90CF386MTD
>B
DS90CF386MTD/NOPB
DS90CF386MTDX/NOPB
DS90CF386SLC/NOPB
ACTIVE
ACTIVE
ACTIVE
RoHS & Green
DS90CF386MTD
>B
1000 RoHS & Green
360 RoHS & Green
SN
DS90CF386MTD
>B
SNAGCU
DS90CF386
SLC
>B
DS90CF386SLCX/NOPB
ACTIVE
NFBGA
NZC
64
2000 RoHS & Green
SNAGCU
Level-4-260C-72 HR
-10 to 70
DS90CF386
SLC
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CF366MTDX/NOPB TSSOP
DS90CF386MTDX/NOPB TSSOP
DS90CF386SLCX/NOPB NFBGA
DGG
DGG
NZC
48
56
64
1000
1000
2000
330.0
330.0
330.0
24.4
24.4
16.4
8.6
8.6
8.3
13.2
14.5
8.3
1.6
1.8
2.3
12.0
12.0
12.0
24.0
24.0
16.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CF366MTDX/NOPB
DS90CF386MTDX/NOPB
DS90CF386SLCX/NOPB
TSSOP
TSSOP
NFBGA
DGG
DGG
NZC
48
56
64
1000
1000
2000
367.0
367.0
356.0
367.0
367.0
356.0
45.0
45.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90CF366MTD/NOPB
DS90CF386MTD
DGG
DGG
DGG
DGG
TSSOP
TSSOP
TSSOP
TSSOP
48
56
56
56
38
34
34
34
495
495
495
495
10
10
10
10
2540
2540
2540
2540
5.79
5.79
5.79
5.79
DS90CF386MTD
DS90CF386MTD/NOPB
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS90CF386SLC/NOPB
NZC
NFBGA
64
360
12 x 30
150
322.6 135.9 7620
10
12.5 12.95
Pack Materials-Page 4
MECHANICAL DATA
NZC0064A
SLC64A (Rev C)
www.ti.com
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
3
5
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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Copyright © 2023, Texas Instruments Incorporated
相关型号：
DS90CF386SLC
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link?85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link?85 MHz
NSC
DS90CF386SLCX/NOPB
IC QUAD LINE RECEIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver
NSC
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