DS90CR216AMTD [TI]
+3.3V 上升沿数据选通 LVDS 接收器 21 位频道链接 - 66MHz | DGG | 48 | -40 to 85;
| 型号： | DS90CR216AMTD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +3.3V 上升沿数据选通 LVDS 接收器 21 位频道链接 - 66MHz | DGG | 48 | -40 to 85 光电二极管 接口集成电路 |
| 文件： | 总38页 (文件大小：2177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H –MAY 2000–REVISED JANUARY 2016
DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver
28-Bit (or 21-Bit) Channel Link-66 MHz
1 Features
3 Description
The DS90CR286A receiver converts the four LVDS
data streams back into parallel 28 bits of LVCMOS
data. Also available is the DS90CR216A receiver that
converts the three LVDS data streams back into
parallel 21 bits of LVCMOS data. The outputs of both
receivers strobe on the rising edge.
1
•
20 to 66 MHz Shift Clock Support
•
•
•
50% Duty Cycle on Receiver Output Clock
Best–in–Class Set and Hold Times on Rx Outputs
Rx Power Consumption < 270 mW (Typ) at 66
MHz Worst Case
•
•
•
•
•
Rx Power-Down Mode < 200 μW (Max)
ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
PLL Requires No External Components
Compatible with TIA/EIA-644 LVDS Standard
The receiver LVDS clock operates at rates from 20 to
66 MHz. The device phase-locks to the input clock,
samples the serial bit streams at the LVDS data lines,
and converts them into parallel output data. At an
incoming clock rate of 66 MHz, each LVDS input line
is running at a bit rate of 462 Mbps, resulting in a
maximum throughput of 1.848 Gbps for the
DS90CR286A and 1.386 Gbps for the DS90CR216A.
Low Profile 56-Pin or 48-Pin DGG (TSSOP)
Package
•
•
Operating Temperature: −40°C to 85°C
The DS90CR286A and DS90CR216A devices are
enhanced over prior generation receivers and provide
a wider data valid time on the receiver output. The
use of these serial link devices is ideal for solving
EMI and cable size problems associated with
transmitting data over wide, high speed parallel
LVCMOS interfaces. Both devices are offered in
TSSOP packages.
Automotive Q Grade Available - AEC-Q100 Grade
3 Qualified
2 Applications
•
•
•
•
•
Video Displays
Automotive Infotainment
Industrial Printers and Imaging
Digital Video Transport
Machine Vision
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
14.00 mm x 6.10 mm
14.00 mm x 6.10 mm
12.50 mm × 6.10 mm
DS90CR286AMTD TSSOP (56)
DS90CR286AQMT TSSOP (56)
DS90CR216AMTD TSSOP (48)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Block Diagram (DS90CR216A)
[ë5{ /ꢀble or ꢁ/. Çrꢀce
5{90/w216! 21-.it wx
18-.it wD. 5isplꢀy Ünit
wxhÜÇꢂ20:0]
[ë5{ 5ꢀtꢀ
Graphics Processor Unit (GPU)
21-Bit Tx Data
(3 LVDS Data, 1 LVDS Clock)
[ë5{ /lock
wx/[Y
PLL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H –MAY 2000–REVISED JANUARY 2016
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ............................................... 17
Power Supply Recommendations...................... 23
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics: Receiver ......................... 7
6.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagrams ..................................... 14
7.3 Feature Description................................................. 15
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Examples................................................... 23
11 Device and Documentation Support ................. 25
11.1 Device Support...................................................... 25
11.2 Related Links ........................................................ 25
11.3 Community Resources.......................................... 25
11.4 Trademarks........................................................... 25
11.5 Electrostatic Discharge Caution............................ 25
11.6 Glossary................................................................ 25
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (August 2015) to Revision H
Page
•
•
•
•
•
•
•
•
Changed Figure 6 and Figure 7 to clarify that TxIN on Tx is the same as RxOUT on Rx .................................................... 9
Changed "limit output amplitude" to "reduce reflections from long board traces" for clarification........................................ 18
Deleted 0.01-µF and 0.001-µF caps from required DC power supply coupling capacitors ................................................. 18
Deleted "Setup and Hold Time" label from the Rx strobe window diagram to clarify RSKM concept ................................. 21
Changed direction of Rx strobe position shift for correct left and right RSKM margin shift behavior .................................. 21
Added new Application Note reference for RSKM improvement.......................................................................................... 21
Added improved layout guidelines........................................................................................................................................ 23
Changed Figure 28 graphic to clarify the use of series resistors on LVCMOS output ........................................................ 24
Changes from Revision F (February 2013) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changed specification title to clarify 3.3 V LVCMOS and not standard 5 V CMOS............................................................... 6
Changed title and graphic of figure to clarify 3.3 V LVCMOS and not standard 5 V CMOS ................................................. 8
Changed title of DS90CR286A mapping to clarify the make-up of the LVDS lines ............................................................... 9
Changed title of DS90CR216A mapping to clarify the make-up of the LVDS lines ............................................................... 9
Added cycle-to-cycle jitter value of 250 ps instead of TBD ps ............................................................................................. 12
•
•
•
•
•
Changes from Revision E (February 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................. 3
2
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Product Folder Links: DS90CR216A DS90CR286A DS90CR286A-Q1
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www.ti.com
SNLS043H –MAY 2000–REVISED JANUARY 2016
5 Pin Configuration and Functions
DGG Package
56-Pin TSSOP
DS90CR286A Top View
DGG Package
48-Pin TSSOP
DS90CR216A Top View
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SNLS043H –MAY 2000–REVISED JANUARY 2016
www.ti.com
DS90CR286A Pin Functions — DGG0056A Package — 28-Bit Channel Link Receiver
PIN
I/O , TYPE
PIN DESCRIPTION
NAME
NO.
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-,
RxIN3+, RxIN3-
10, 9,
Positive and negative LVDS differential data inputs. 100-Ω termination resistors
should be placed between RxIN+ and RxIN- receiver inputs as close as
possible to the receiver pins for proper signaling.
12, 11,
16, 15,
20, 19
I, LVDS
Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor
should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close
as possible to the receiver pins for proper signaling.
RxCLKIN+,
RxCLKIN-
18,
17
I, LVDS
7, 6, 5, 3,
2, 1, 55, 54,
53, 51, 50, 49,
47, 46, 45, 43,
42, 41, 39, 38,
37, 35, 34, 33,
32, 30, 29, 27
RxOUT[27:0]
O, LVCMOS
LVCMOS level data outputs.
RxCLK OUT
PWR DWN
VCC
26
O, LVCMOS
I, LVCMOS
Power
LVCMOS Ievel clock output. The rising edge acts as the data strobe.
LVCMOS level input. When asserted low, the receiver outputs are low.
Power supply pins for LVCMOS outputs.
25
56, 48, 40, 31
52, 44, 36,
28, 4
GND
Power
Ground pins for LVCMOS outputs.
PLL VCC
23
Power
Power
Power
Power
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
24, 22
13
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
21, 14, 8
DS90CR216A Pin Functions — DGG0048A Package — 21-Bit Channel Link Receiver
PIN
I/O , TYPE
PIN DESCRIPTION
NAME
NO.
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-
9, 8,
11, 10,
15, 14
Positive and negative LVDS differential data inputs. 100-Ω termination resistors
should be placed between RxIN+ and RxIN- receiver inputs as close as
possible to the receiver pins for proper signaling.
I, LVDS
Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor
should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close
as possible to the receiver pins for proper signaling.
RxCLKIN+,
RxCLKIN-
17,
16
I, LVDS
5, 4, 2, 1, 47,
46, 45, 43, 41,
40, 39, 37, 35,
34, 33, 31, 30,
29, 27, 26, 24
RxOUT[20:0]
O, LVCMOS
LVCMOS level data outputs.
RxCLK OUT
PWR DWN
VCC
23
O, LVCMOS
I, LVCMOS
Power
LVCMOS Ievel clock output. The rising edge acts as the data strobe.
LVCMOS level input. When asserted low, the receiver outputs are low.
Power supply pins for LVCMOS outputs.
22
48, 42, 36, 28
44, 38, 32,
25, 3
GND
Power
Ground pins for LVCMOS outputs.
PLL VCC
20
Power
Power
Power
Power
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
21, 19
12
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
18, 13, 7
4
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www.ti.com
SNLS043H –MAY 2000–REVISED JANUARY 2016
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
see
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
Supply voltage (VCC
)
4
(VCC + 0.3 V)
(VCC + 0.3 V)
150
LVCMOS output voltage
V
LVDS receiver input voltage
Junction temperature
V
°C
°C
°C
Lead temperature (soldering, 4 sec)
Storage temperature, Tstg
260
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
6.2 ESD Ratings
VALUE
±7000
±700
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3.0
–40
0
NOM
3.3
MAX
3.6
UNIT
Supply voltage (VCC
)
V
°C
Operating free air temperature (TA)
Receiver input range
25
85
2.4
V
Supply noise voltage (VNOISE
)
100
mVPP
6.4 Thermal Information
DS90CR286A/-Q1
DS90CR216A
DGG (TSSOP)
48 PINS
67.8
THERMAL METRIC(1)
DGG (TSSOP)
56 PINS
64.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
20.6
22.1
33.3
34.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.0
1.1
ψJB
33.0
34.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNLS043H –MAY 2000–REVISED JANUARY 2016
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6.5 Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LVCMOS DC SPECIFICATIONS (For PWR DWN Pin)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
2
VCC
0.8
V
V
GND
VCL
ICL = −18 mA
–0.79
1.8
0
–1.5
10
V
V IN = 0.4 V, 2.5 V or VCC
V IN = GND
μA
μA
IIN
Input Current
–10
2.7
LVCMOS DC SPECIFICATIONS
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IOH = −0.4 mA
IOL = 2 mA
3.3
0.06
–60
V
V
0.3
VOUT = 0 V
–120
mA
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
VCM = +1.2V
100
mV
mV
μA
–100
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
±10
±10
IIN
Input Current
μA
RECEIVER SUPPLY CURRENT
CL = 8 pF, Worst Case
Pattern, DS90CR286A
(Figure 1 Figure 2),
TA=−10°C to +70°C
f = 33 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
49
53
81
53
65
70
mA
mA
mA
mA
ICCRW
ICCRW
ICCRW
Receiver Supply Current Worst Case
105
70
CL = 8 pF, Worst Case
Pattern, DS90CR286A
(Figure 1 Figure 2),
TA=−40°C to +85°C
Receiver Supply Current Worst Case
Receiver Supply Current Worst Case
f = 66 MHz
81
105
mA
CL = 8 pF, Worst Case
Pattern, DS90CR216A
(Figure 1 Figure 2),
TA=−10°C to +70°C
f = 33 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
49
53
78
53
55
60
90
60
mA
mA
mA
mA
CL = 8 pF, Worst Case
Pattern, DS90CR216A
(Figure 1 Figure 2),
TA=−40°C to +85°C
ICCRW
ICCRZ
Receiver Supply Current Worst Case
Receiver Supply Current Power Down
f = 66 MHz
78
10
90
55
mA
Power Down = Low Receiver Outputs Stay
Low during Power Down Mode
μA
(1) Typical values are given for VCC = 3.3 V and TA = 25ºC.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔV OD).
6
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SNLS043H –MAY 2000–REVISED JANUARY 2016
6.6 Switching Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
TYP
2
MAX UNIT
CLHT
CHLT
LVCMOS Low-to-High Transition Time (Figure 2)
LVCMOS High-to-Low Transition Time (Figure 2)
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.8
1.4
5
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10)
RSPos1 Receiver Input Strobe Position for Bit 1
RSPos2 Receiver Input Strobe Position for Bit 2
RSPos3 Receiver Input Strobe Position for Bit 3
RSPos4 Receiver Input Strobe Position for Bit 4
RSPos5 Receiver Input Strobe Position for Bit 5
RSPos6 Receiver Input Strobe Position for Bit 6
1
4.5
2.15
5.8
8.1
8.5
11.9
15.6
19.2
22.9
9.15
12.6
16.3
19.9
23.6
f = 40 MHz
11.6
15.1
18.8
22.5
Receiver Input Strobe Position for Bit 0
(Figure 9, Figure 10)
RSPos0
0.7
1.1
1.4
ns
RSPos1 Receiver Input Strobe Position for Bit 1
RSPos2 Receiver Input Strobe Position for Bit 2
RSPos3 Receiver Input Strobe Position for Bit 3
RSPos4 Receiver Input Strobe Position for Bit 4
RSPos5 Receiver Input Strobe Position for Bit 5
RSPos6 Receiver Input Strobe Position for Bit 6
2.9
5.1
7.3
9.5
11.7
13.9
490
400
15
3.3
5.5
3.6
5.8
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
f = 66 MHz
7.7
8
9.9
10.2
12.4
14.6
12.1
14.3
f = 40 MHz
f = 66 MHz
RSKM
RxIN Skew Margin(2) (Figure 11)
RCOP
RCOH
RCOL
RSRC
RHRC
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
RxCLK OUT Period (Figure 3)
T
12.2
11
50
RxCLK OUT High Time (Figure 3)
10
RxCLK OUT Low Time (Figure 3)
10
f = 40 MHz
RxOUT Setup to RxCLK OUT (Figure 3)
RxOUT Hold to RxCLK OUT (Figure 3)
RxCLK OUT High Time (Figure 3)
6.5
6
11.6
11.6
7.6
6.3
7.3
6.3
5
5
RxCLK OUT Low Time (Figure 3)
5
f = 66 MHz
RxOUT Setup to RxCLK OUT (Figure 3)
RxOUT Hold to RxCLK OUT (Figure 3)
RxCLK IN to RxCLK OUT Delay at 25°C, VCC = 3.3 V(3) (Figure 4)
Receiver Phase Lock Loop Set (Figure 5)
Receiver Power Down Delay (Figure 8)
4.5
4
3.5
7.5
10
1
(1) Typical Values are given for VCC = 3.3 V and TA = 25ºC
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver
(RCCD). The total latency for the DS90CR215/DS90CR285 transmitter and DS90CR216A/DS90CR286A receiver is: (T + TCCD) + (2*T
+ RCCD), where T = Clock period.
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Figure 1. “Worst Case” Test Pattern
[ë/ah{ hutput
Figure 2. LVCMOS Output Load and Transition Times
Figure 3. Setup/Hold and High/Low Times
Figure 4. Clock In to Clock Out Delay
8
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SNLS043H –MAY 2000–REVISED JANUARY 2016
Figure 5. Phase Lock Loop Set Time
wx/[Y Lb
(ꢁifferential)
wxLb3
({ingle-ꢀnded)
wxhÜÇ5-1
wxhÜÇ20-1
wxhÜÇ9-1
wxhÜÇ1-1
wxhÜÇ23
wxhÜÇ26
wxhÜÇ18
wxhÜÇ7
wxhÜÇ16
wxhÜÇ24
wxhÜÇ14
wxhÜÇ4
wxhÜÇ5
wxhÜÇ20
wxhÜÇ9
wxhÜÇ1
wxhÜÇ27-1
wxhÜÇ19-1
wxhÜÇ8-1
wxhÜÇ0-1
wxhÜÇ17
wxhÜÇ25
wxhÜÇ15
wxhÜÇ6
wxhÜÇ11
wxhÜÇ22
wxhÜÇ13
wxhÜÇ3
wxhÜÇ10
wxhÜÇ21
wxhÜÇ12
wxhÜÇ2
wxhÜÇ27
wxhÜÇ19
wxhÜÇ8
wxhÜÇ0
wxLb2
({ingle-ꢀnded)
wxLb1
({ingle-ꢀnded)
wxLb0
({ingle-ꢀnded)
Figure 6. DS90CR286A Mapping of 28 LVCMOS Parallel Data to 4D + C LVDS Serialized Data
wx/[Y Lb
(ꢁifferential)
wxLb2
({ingle-ꢀnded)
wxhÜÇ20
wxhÜÇ13
wxhÜÇ6
wxhÜÇ18
wxhÜÇ11
wxhÜÇ4
wxhÜÇ15
wxhÜÇ8
wxhÜÇ1
wxhÜÇ15-1
wxhÜÇ8-1
wxhÜÇ1-1
wxhÜÇ14-1
wxhÜÇ7-1
wxhÜÇ0-1
wxhÜÇ19
wxhÜÇ12
wxhÜÇ5
wxhÜÇ17
wxhÜÇ10
wxhÜÇ3
wxhÜÇ16
wxhÜÇ9
wxhÜÇ2
wxhÜÇ14
wxhÜÇ7
wxhÜÇ0
wxLb1
({ingle-ꢀnded)
wxLb0
({ingle-ꢀnded)
Figure 7. DS90CR216A Mapping of 21 LVCMOS Parallel Data to 3D + C LVDS Serialized Data
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Figure 8. Power Down Delay
Figure 9. DS90CR286A LVDS Input Strobe Position
10
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SNLS043H –MAY 2000–REVISED JANUARY 2016
Figure 10. DS90CR216A LVDS Input Strobe Position
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2)
(1) Cycle-to-cycle jitter depends on the Tx source. if a Channel Link I Source Transmitter is used, clock jitter is
maintained to less than 250 ps at 66 MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 11. Receiver LVDS Input Skew Margin
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6.7 Typical Characteristics
Çime (20.0 ns/5Lë)
Çime (5.0 ns/ꢀLë)
Figure 12. Parallel PRBS-7 on LVCMOS Outputs at 66 MHz
Figure 13. Typical RxOUT Strobe Position at 66 MHz
Çime (5.0 ns/ꢀLë)
Çime (5.0 ns/ꢀLë)
Figure 14. Typical RxOUT Setup Time at 66 MHz
(RSRC = 7.1 ns)
Figure 15. Typical RxOUT Hold Time at 66 MHz
(RHRC = 7.0 ns)
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7 Detailed Description
7.1 Overview
The DS90CR286A and DS90CR286A-Q1 are receivers that convert four LVDS (Low Voltage Differential
Signaling) data streams into parallel 28 bits of LVCMOS data (24 bits of RGB and 4 bits of HSYNC, VSYNC, DE,
and CNTL). The DS90CR216A is a receiver that converts three LVDS data streams back into parallel 21 bits of
LVCMOS data (18 bits of RGB and 3 bits of HSYNC, VSYNC, and DE). An internal PLL locks to the incoming
LVDS clock ranging from 20 to 66 MHz. The locked PLL ensures a stable clock to sample the output LVCMOS
data on the Receiver Clock Out rising edge. These devices feature a PWR DWN pin to put the device into low
power mode when there is no active input data.
7.2 Functional Block Diagrams
4 x [ë5{ 5ꢀtꢀ
(140 to 462 abps on
9ꢀcꢁ [ë5{ /ꢁꢀnnel)
28 x [ë/ah{
hutputs
[ë5{ /lock
(20 to 66 aIz)
PLL
weceiver /lock hut
ꢂíw 5íꢃ
Figure 16. DS90CR286A Block Diagram
3 x [ë5{ 5ꢀtꢀ
(140 to 462 abps on
9ꢀcꢁ [ë5{ /ꢁꢀnnel)
21 x [ë/ah{
hutputs
[ë5{ /lock
(20 to 66 aIz)
PLL
weceiver /lock hut
ꢂíw 5íꢃ
Figure 17. DS90CR216A Block Diagram
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7.3 Feature Description
The DS90CR286A and DS90CR216A consist of several key blocks:
•
•
•
•
LVDS Receivers
Phase Locked Loop (PLL)
Serial LVDS-to-Parallel LVCMOS Converter
LVCMOS Drivers
7.3.1 LVDS Receivers
There are five differential LVDS inputs to the DS90CR286A and four differential LVDS inputs to the
DS90CR216A. Four of the LVDS inputs contain serialized data originating from a 28-bit source transmitter. For
the DS90CR216A, three of the LVDS inputs contain serialized data originating from a 21-bit source transmitter.
The remaining LVDS input contains the LVDS clock associated with the data pairs.
7.3.1.1 LVDS Input Termination
The DS90CR286A and DS90CR216A require a single 100-Ω terminating resistor across the true and
complement lines on each differential pair of the receiver input. To prevent reflections due to stubs, this resistor
should be placed as close to the device input pins as possible. Figure 18 shows an example.
Figure 18. LVDS Serialized Link Termination
7.3.2 Phase Locked Loop (PLL)
The Channel Link I devices use an internal PLL to recover the clock transmitted across the LVDS interface. The
recovered clock is then used as a reference to determine the sampling position of the seven serial bits received
per clock cycle. The width of each bit in the serialized LVDS data stream is one-seventh the clock period.
Differential skew (Δt within one differential pair), interconnect skew (Δt of one differential pair to another) and
clock jitter will all reduce the available window for sampling the LVDS serial data streams. Individual bypassing of
each VCC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock to
improve the overall jitter budget.
7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
After the PLL locks to the incoming LVDS clock, the receiver deserializes each LVDS differential data pair into
seven parallel LVCMOS data outputs per clock cycle. For the DS90CR286A, the LVDS data inputs map to
LVCMOS outputs according to Figure 6. For the DS90CR216A, the LVDS data inputs map to LVCMOS outputs
according to Figure 7.
7.3.4 LVCMOS Drivers
The LVCMOS outputs from the DS90CR286A and DS90CR216A are the deserialized parallel single-ended data
from the serialized LVDS differential data pairs. Each LVCMOS output is clocked by the PLL and strobes on the
RxCLKOUT rising edge. All unused DS90CR286A and DS90CR216A RxOUT outputs can be left floating.
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7.4 Device Functional Modes
7.4.1 Power Down Mode
The DS90CR286A and DS90CR216A may be placed into a power down mode at any time by asserting the PWR
DWN pin (active low). The DS90CR286A and DS90CR216A are also designed to protect themselves from
accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) retain the states they were in when the clocks stopped.
When the receiver board loses power, the receiver inputs are shorted to VCC through an internal diode. Current is
limited to 5 mA per input, thus avoiding the potential for latch-up when powering the device.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90CR286A and DS90CR216A are designed for a wide variety of data transmission applications. The use
of serialized LVDS data lines in these applications allows for efficient signal transmission over a narrow bus
width, thereby reducing cost, power, and space.
8.2 Typical Applications
[ë5{ /ꢀble or ꢁ/. Çrꢀce
5{90/w286! 28-.it wx
24-.it wD. 5isplꢀy Ünit
wxhÜÇꢂ27:0]
[ë5{ 5ꢀtꢀ
Graphics Processor Unit (GPU)
28-Bit Tx Data
(4 LVDS Data, 1 LVDS Clock)
[ë5{ /lock
wx/[Y
PLL
Figure 19. Typical DS90CR286A Application Block Diagram
[ë5{ /ꢀble or ꢁ/. Çrꢀce
5{90/w216! 21-.it wx
18-.it wD. 5isplꢀy Ünit
wxhÜÇꢂ20:0]
[ë5{ 5ꢀtꢀ
Graphics Processor Unit (GPU)
21-Bit Tx Data
(3 LVDS Data, 1 LVDS Clock)
[ë5{ /lock
wx/[Y
PLL
Figure 20. Typical DS90CR216A Application Block Diagram
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Typical Applications (continued)
8.2.1 Design Requirements
For this design example, ensure that the following requirements are observed.
Table 1. Design Parameters
DESIGN PARAMETER
DESIGN REQUIREMENTS
LVDS clock must be within 20-66 MHz.
Operating Frequency
DS90CR286A: No higher than 24 bpp. The maximum supported resolution is 8-bit RGB.
DS90CR216A: No higher than 18 bpp. The maximum supported resolution is 6-bit RGB.
Bit Resolution
Determine the appropriate mapping required by the panel display following the DS90CR286A
or DS90CR216A outputs.
Bit Data Mapping
RSKM (Receiver Skew Margin)
Input Termination for RxIN±
RxIN± Board Trace Impedance
LVCMOS Outputs
Ensure that there is acceptable margin between Tx pulse position and Rx strobe position.
100 Ω ± 10% resistor across each LVDS differential pair. Place as close as possible to IC
input pins.
Design differential trace impedance with 100 Ω ± 5%
If unused, leave pins floating. Series resistance on each LVCMOS output optional to reduce
reflections from long board traces. If used, 33-Ω series resistance is typical.
Use a 0.1-µF capacitor to minimize power supply noise. Place as close as possible to VCC
pins.
DC Power Supply Coupling Capacitors
8.2.2 Detailed Design Procedure
To design with the DS90CR286A or DS90CR216A, determine the following:
•
•
•
•
Cable Interface
Bit Resolution and Operating Frequency
Bit Mapping from Receiver to Endpoint Panel Display
RSKM Interoperability with Transmitter Pulse Position Margin
8.2.2.1 Cables
A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The
DS90CR216A requires four pairs of signal wires and the DS90CR286A requires five pairs of signal wires. The
ideal cable interface has a constant 100-Ω differential impedance throughout the path. It is also recommended
that cable skew remain below 150 ps (assuming 66 MHz clock rate) to maintain a sufficient data sampling
window at the receiver.
Depending upon the application and data rate, the interconnecting media between Tx and Rx may vary. For
example, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is
less critical. For higher speed or long distance applications, the media's performance becomes more critical.
Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs).
For example, twin-coax cables have been demonstrated at distances as long as five meters and with the
maximum data transfer of 1.386 Gbps (DS90CR216A) and 1.848 Gbps (DS90CR286A).
8.2.2.2 Bit Resolution and Operating Frequency Compatibility
The bit resolution of the endpoint panel display reveals whether there are enough bits available in the
DS90CR286A or DS90CR216A to output the required data per pixel. The DS90CR286A has 28 parallel
LVCMOS outputs and can therefore provide a bit resolution up to 24 bpp (bits per pixel). In each clock cycle, the
remaining bits are the three control signals (HSync, VSync, DE) and one spare bit. The DS90CR216A has 21
parallel LVCMOS outputs and can therefore provide a bit resolution up to 18 bpp (bits per pixel). In each clock
cycle, the remaining bits are the three control signals (HSync, VSync, DE).
The number of pixels per frame and the refresh rate of the endpoint panel display indicate the required operating
frequency of the deserializer clock. To determine the required clock frequency, refer to the following formula:
f_Clk = [H_Active + H_Blank] × [V_Active + V_Blank] × f_Vertical
where
•
H_Active = Active Display Horizontal Lines
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•
•
•
•
•
H_Blank = Blanking Period Horizontal Lines
V_Active = Active Display Vertical Lines
V_Blank = Blanking Period Vertical Lines
f_Vertical = Refresh Rate (in Hz)
f_Clk = Operating Frequency of LVDS clock
(1)
In each frame, there is a blanking period associated with horizontal rows and vertical columns that are not
actively displayed on the panel. These blanking period pixels must be included to determine the required clock
frequency. Consider the following example to determine the required LVDS clock frequency:
•
•
•
•
•
H_Active = 640
H_Blank = 40
V_Active = 480
V_Blank = 41
f_Vertical = 59.95 Hz
Thus, the required operating frequency is determined below:
[640 + 40] x [480 + 41] x 59.95 = 21239086 Hz ≈ 21.24 MHz
(2)
Since the operating frequency for the PLL in the DS90CR286A and DS90CR216A ranges from 20-66 MHz, the
DS90CR286A and DS90CR216A can support a panel display with the aforementioned requirements.
If the specific blanking interval is unknown, the number of pixels in the blanking interval can be approximated to
20% of the active pixels. The following formula can be used as a conservative approximation for the operating
LVDS clock frequency:
f_Clk ≈ H_Active x V_Active x f_Vertical x 1.2
(3)
Using this approximation, the operating frequency for the example in this section is estimated below:
640 x 480 x 59.95 x 1.2 = 22099968 Hz ≈ 22.10 MHz
(4)
8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
Ensure that the LVCMOS outputs are mapped to align with the endpoint display RGB mapping requirements
following the deserializer. Two popular mapping topologies for 8-bit RGB data are shown below:
1. LSBs are mapped to RxIN3±.
2. MSBs are mapped to RxIN3±.
The following tables depict how these two popular topologies can be mapped to the DS90CR286A outputs.
Table 2. 8-Bit Color Mapping with LSBs on RxIN3±
LVDS INPUT
CHANNEL
LVDS BIT STREAM
POSITION
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN6
TxIN7
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT18
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
RxIN0
MSB
RxIN1
MSB
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Table 2. 8-Bit Color Mapping with LSBs on RxIN3± (continued)
LVDS INPUT
CHANNEL
LVDS BIT STREAM
POSITION
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
TxIN19
TxIN20
TxIN21
TxIN22
TxIN24
TxIN25
TxIN26
TxIN27
TxIN5
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT5
B4
B5
B6
RxIN2
B7
MSB
Horizontal Sync
Vertical Sync
Data Enable
LSB
HSYNC
VSYNC
DE
R0
R1
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
RxOUT10
RxOUT11
RxOUT16
RxOUT17
RxOUT23
G0
LSB
LSB
RxIN3
G1
B0
B1
GP
General Purpose
Table 3. 8-Bit Color Mapping with MSBs on RxIN3±
LVDS INPUT
CHANNEL
LVDS BIT STREAM
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
POSITION
TxIN0
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT5
RxOUT10
RxOUT11
RxOUT16
RxOUT17
RxOUT23
R0
R1
LSB
TxIN1
TxIN2
R2
RxIN0
TxIN3
R3
TxIN4
R4
TxIN6
R5
TxIN7
G0
LSB
LSB
TxIN8
G1
TxIN9
G2
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN24
TxIN25
TxIN26
TxIN27
TxIN5
G3
RxIN1
G4
G5
B0
B1
B2
B3
B4
RxIN2
B5
HSYNC
VSYNC
DE
R6
Horizontal Sync
Vertical Sync
Data Enable
R7
MSB
MSB
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
G6
RxIN3
G7
B6
B7
MSB
GP
General Purpose
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In either the case where the DS90CR216A is used or the DS90CR286A must support 18 bpp, Table 2 is
commonly used. With this mapping, MSBs of RGB data are retained on RXIN0±, RXIN1±, and RXIN2± while the
two LSBs for the original 8-bit RGB resolution are ignored from RxIN3±.
8.2.2.4 RSKM Interoperability
One of the most important factors when designing the receiver into a system application is assessing how much
RSKM (Receiver Skew Margin) is available. In each LVDS clock cycle, the LVDS data stream carries seven
serialized data bits. Ideally, the Transmit Pulse Position for each bit will occur every (n x T)/7 seconds, where n =
Bit Position and T = LVDS Clock Period. Likewise, ideally the Receive Strobe Position for each bit will occur
every ((n + 0.5) x T)/7 seconds. However, due to the effects of cable skew, clock jitter, and ISI, both LVDS
transmitter and receiver in real systems will have a minimum and maximum pulse and strobe position,
respectively, for each bit position. This concept is illustrated in Figure 21:
wspos1
wspos0
max
min
max
min
Çppos0
.it 0 [eft aꢀrgin
.it 0 wight aꢀrgin
Çppos1
.it 1 [eft aꢀrgin
.it 1 wight aꢀrgin
Çppos2
Ldeal wx {trobe
ꢀosition
Ldeal wx {trobe
ꢀosition
max
max
min
min
max
min
.it0
.it1
Figure 21. RSKM Measurement Example
All left and right margins for Bits 0-6 must be considered in order to determine the absolute minimum for the
whole LVDS bit stream. This absolute minimum corresponds to the RSKM.
To improve RSKM performance between LVDS transmitter and receiver, designers often either advance or delay
the LVDS clock compared to the LVDS data. Moving the LVDS clock compared to the LVDS data can improve
the location of the setup and hold time for the transmitter compared to the setup and hold time for the receiver.
If there is less left bit margin than right bit margin, the LVDS clock can be delayed so that the Rx strobe position
for incoming data appears to be delayed. If there is less right bit margin than left bit margin, all the LVDS data
pairs can be delayed uniformly so that the LVDS clock and Rx strobe position for incoming data appear to
advance. To delay an LVDS data or clock pair, designers either add more PCB trace length or install a capacitor
between the LVDS transmitter and receiver. It is important to note that when using these techniques, all
serialized bit positions are shifted right or left uniformly.
When designing the DS90CR286A or DS90CR216A receiver with a third-party OpenLDI transmitter, users must
calculate the skew margin budget (RSKM) based on the Tx pulse position and the Rx strobe position to ensure
error-free transmission. For more information about calculating RSKM, refer to Application Note SNLA249.
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8.2.3 Application Curves
The following application curves are examples taken with a DS90C385 serializer interfacing to a DS90CR286A
deserializer in nominal temperature (25ºC) at an operating frequency of 66 MHz.
ÇxLb7
ÇxLb6
ÇxLb4
ÇxLb3
ÇxLb2
ÇxLb1
ÇxLb0
Çime (ꢁ.0 nsꢀ5Lë)
Çime (2.ꢂ nsꢀ5Lë)
Figure 23. LVDS CLKIN aligned with LVCMOS RxCLKOUT
Figure 22. LVDS RxIN0± aligned with LVCMOS RxCLKOUT
Çime (ꢁ.0 nsꢀ5Lë)
Çime (20.0 nsꢀ5Lë)
Figure 24. RxOUT Strobe on Rising Edge of RxCLKOUT
Figure 25. PRBS-7 Output on RxOUT Channels
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9 Power Supply Recommendations
Proper power supply decoupling is important to ensure a stable power supply with minimal power supply noise.
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface
mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are
0.1 μF, 0.01 μF and 0.001 μF. The preferred capacitor size is 0402. An example is shown in Figure 26. The
designer should employ wide traces for power and ground and ensure each capacitor has its own via to the
ground plane. If board space is limiting the number of bypass capacitors, the PLL VCC should receive the most
filtering/bypassing. Next would be the LVDS VCC pins and finally the logic VCC pins.
Figure 26. Recommended Bypass Capacitor Decoupling Configuration
10 Layout
10.1 Layout Guidelines
As with any high speed design, board designers must maximize signal integrity by limiting reflections and
crosstalk that can adversely affect high frequency and EMI performance. The following practices are
recommended layout guidelines to optimize device performance.
•
Ensure that differential pair traces are always closely coupled to eliminate noise interference from other
signals and take full advantage of the common mode noise canceling effect of the differential signals.
•
•
•
•
Maintain equal length on signal traces for a given differential pair.
Limit impedance discontinuities by reducing the number of vias on signal traces.
Eliminate any 90º angles on traces and use 45º bends instead.
If a via must exist on one signal polarity, mirror the via implementation on the other polarity of the differential
pair.
•
•
Match the differential impedance of the selected physical media. This impedance should also match the value
of the termination resistor that is connected across the differential pair at the receiver's input.
When possible, use short traces for LVDS inputs.
10.2 Layout Examples
The following images show an example layout of the DS90CR286A.Traces in blue correspond to the top layer
and the traces in green correspond to the bottom layer. Note that differential pair inputs to the DS90CR286A are
tightly coupled and close to the connector pins. In addition, observe that the power supply decoupling capacitors
are placed as close as possible to the power supply pins with through vias in order to minimize inductance. The
principles illustrated in this layout can also be applied to the 48-pin DS90CR216A.
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Layout Examples (continued)
Figure 27. Example Layout With DS90CR286A (U1)
100-Q [ë5{
Çerminations close to
wxLb pins
33 Q {ꢀŒ]ꢀ• wꢀ•]•š}Œ•
occasionally used to
reduce reflections
Figure 28. Example Layout Close-up
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DS90CR216A
DS90CR286A
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
DS90CR286A-Q1
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: DS90CR216A DS90CR286A DS90CR286A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DGG
DGG
DGG
DGG
DGG
DGG
DGG
DGG
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90CR216AMTD
DS90CR216AMTD/NOPB
DS90CR216AMTDX/NOPB
DS90CR286AMTD
NRND
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
48
48
48
56
56
56
56
56
38
Non-RoHS
& Green
Call TI
Level-2-235C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-235C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DS90CR216AMTD
>B
ACTIVE
ACTIVE
NRND
38
RoHS & Green
SN
SN
DS90CR216AMTD
>B
1000 RoHS & Green
DS90CR216AMTD
>B
34
34
Non-RoHS
& Green
Call TI
SN
DS90CR286AMTD
>B
DS90CR286AMTD/NOPB
DS90CR286AMTDX/NOPB
DS90CR286AQMT/NOPB
DS90CR286AQMTX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RoHS & Green
DS90CR286AMTD
>B
1000 RoHS & Green
34 RoHS & Green
1000 RoHS & Green
SN
DS90CR286AMTD
>B
SN
DS90CR286AQ
MT
SN
DS90CR286AQ
MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS90CR286A, DS90CR286A-Q1 :
Catalog : DS90CR286A
•
Automotive : DS90CR286A-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CR216AMTDX/
NOPB
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
48
56
56
1000
1000
1000
330.0
330.0
330.0
24.4
24.4
24.4
8.6
8.6
8.6
13.2
14.5
14.5
1.6
1.8
1.8
12.0
12.0
12.0
24.0
24.0
24.0
Q1
Q1
Q1
DS90CR286AMTDX/
NOPB
DS90CR286AQMTX/
NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CR216AMTDX/NOPB
DS90CR286AMTDX/NOPB
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
48
56
56
1000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
DS90CR286AQMTX/
NOPB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90CR216AMTD
DS90CR216AMTD
DGG
DGG
DGG
DGG
DGG
DGG
DGG
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
48
48
48
56
56
56
56
38
38
38
34
34
34
34
495
495
495
495
495
495
495
10
10
10
10
10
10
10
2540
2540
2540
2540
2540
2540
2540
5.79
5.79
5.79
5.79
5.79
5.79
5.79
DS90CR216AMTD/NOPB
DS90CR286AMTD
DS90CR286AMTD
DS90CR286AMTD/NOPB
DS90CR286AQMT/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
3
5
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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