DS90CR281 [TI]
28-Bit Channel Link;
| 型号： | DS90CR281 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 28-Bit Channel Link |
| 文件： | 总15页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CR281,DS90CR282
DS90CR281/DS90CR282 28-Bit Channel Link
Literature Number: SNLS113A
July 1997
DS90CR281/DS90CR282
28-Bit Channel Link
ground) are needed. This provides a 80% reduction in re-
quired cable width, which provides a system cost savings,
reduces connector physical size and cost, and reduces
shielding requirements due to the cables’ smaller form fac-
tor.
General Description
The DS90CR281 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR282 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 40 MHz, 28 bits of TTL data are trans-
mitted at a rate of 280 Mbps per LVDS data channel. Using
The 28 CMOS/TTL inputs can support a variety of signal
combinations. For example, 7 4-bit nibbles or 3 9-bit (byte +
parity) and 1 control.
Features
n Narrow bus reduces cable size and cost
a
40 MHz clock, the data throughput is 1.12 Gbit/s
(140 Mbytes/s).
±
n
1V common mode range (ground shifting)
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data bus and one clock, up to 58 conductors are required.
With the Channel Link chipset as few as 11 conductors (4
data pairs, 1 clock pair and a minimum of one
n 290 mV swing LVDS data transmission
n 1.12 Gbit/s data throughput
n Low swing differential current mode drivers reduce EMI
n Rising edge data strobe
n Power down mode
n Offered in low profile 56-lead TSSOP package
Block Diagrams
DS90CR281
DS90CR282
DS012638-27
DS012638-1
Order Number DS90CR281MTD
See NS Package Number MTD56
Order Number DS90CR282MTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS012638
www.national.com
Connection Diagrams
DS90CR281
DS90CR282
DS012638-2
DS012638-3
Typical Application
DS012638-19
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
MTD56(TSSOP) Package:
DS90CR281
1.63W
1.61W
DS90CR282
Package Derating:
DS90CR281
12.5 mW/˚C above +25˚C
12.4 mW/˚C above +25˚C
Supply Voltage (VCC
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
DS90CR282
CMOS/TTL Input Voltage
CMOS/TTL Ouput Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
This device does not meet 2000V ESD rating (Note 4).
Recommended Operating
Conditions
continuous
+150˚C
Min Max Units
Junction Temperature
Storage Temperature Range
Lead Temperature
Supply Voltage (VCC
)
4.5
−10 +70
2.4
5.5
V
˚C
V
−65˚C to +150˚C
Operating Free Air Temperature (TA)
Receiver Input Range
0
(Soldering, 4 sec.)
+260˚C
Supply Noise Voltage (VCC
)
100 mVP-P
@
Maximum Package Power Dissipation +25˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
2.0
GND
3.8
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = −0.4 mA
IOL = 2 mA
4.9
0.1
V
0.3
V
ICL = −18 mA
−0.79
−1.5
V
±
±
10
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
5.1
µA
mA
IOS
Output Short Circuit Current
−120
LVDS DRIVER DC SPEClFlCATIONS
VOD
Differential Output Voltage
Change in VOD between
RL = 100Ω
250
1.1
290
450
35
mV
mV
∆VOD
Complementary Output States
Common Mode Voltage
VCM
1.25 1.375
35
V
∆VCM
Change in VCM between
mV
Complementary Output States
Output Short Circuit Current
Output TRI-STATE® Current
IOS
IOZ
VOUT = OV, RL = 100Ω
−2.9
−5
mA
µA
±
±
10
Power Down = 0V, VOUT = 0V or VCC
1
LVDS RECEIVER DC SPECIFlCATIONS
VTH
Differential Input High
Threshold
VCM = +1.2V
+100
mV
VTL
IIN
Differential Input Low Threshold
Input Current
−100
mV
µA
µA
<
<
±
±
±
±
VIN = +2.4V
VIN = 0V
VCC = 5.5V
1
1
10
10
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current,
Worst Case
RL = 100Ω, CL = 5 pF,
f = 32.5 MHz
f = 37.5 MHz
34
36
1
51
mA
mA
µA
Worst Case Pattern (Figures 1, 2)
Power Down = Low
53
25
ICCTZ
Transmitter Supply Current,
Power Down
3
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max Units
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current,
Worst Case
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
55
60
1
75
80
10
mA
mA
µA
Worst Case Pattern (Figures 1, 3)
Power Down = Low
ICCRZ
Receiver Supply Current,
Power Down
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 5.0V and T = +25˚C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V and ∆V ).
OD
OD
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V ≥ 1000V
CC
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 2)
LVDS High-to-Low Transition Time (Figure 2)
TxCLK IN Transition Time (Figure 4)
Min
Typ
0.75
0.75
Max
1.5
Units
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLT
1.5
TCIT
8
TCCS
TxOUT Channel-to-Channel Skew (Note 5) (Figure 5)
Transmitter Output Pulse Position for Bit 0 (Figure 16)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 16)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 6)
350
350
7.5
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
f = 20 MHz
−200
6.3
150
7.2
12.8
20
13.6
20.8
28
14.6
21.5
28.5
35.6
42.9
300
3.9
27.2
34.5
42.2
−100
2.9
35.2
42.6
100
3.3
f = 40 MHz
6.1
6.6
7.1
9.7
10.2
13.5
17.4
20.8
T
10.7
14.1
17.8
21.4
50
13
17
20.3
25
TCIH
TxCLK IN High Time (Figure 6)
0.35T 0.5T 0.65T
TCIL
TxCLK IN Low Time (Figure 6)
0.35T 0.5T 0.65T
TSTC
TxIN Setup to TxCLK IN (Figure 6)
f = 20 MHz
f = 40 MHz
14
8
THTC
TCCD
TxIN Hold to TxCLK IN (Figure 6)
2.5
5
2
@
TxCLK IN to TxCLK OUT Delay 25˚C,
9.7
VCC = 5.0V (Figure 8)
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Powerdown Delay (Figure 14)
10
ms
ns
100
Note 5: This limit based on bench characterization.
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
RxCLK OUT Period (Figure 7)
Min
Typ
3.5
2.7
T
Max
6.5
6.5
50
Units
ns
CHLT
ns
RCOP
RSKM
25
ns
Receiver Skew Margin (Note 6)
VCC = 5V, TA = 25˚C (Figure 17)
f = 20 MHz
f = 40 MHz
1.1
ns
ps
700
RCOH
RCOL
RSRC
RHRC
RCCD
RxCLK OUT High Time (Figure 7)
RxCLK OUT Low Time (Figure 7)
RxOUT Setup to RxCLK OUT (Figure 7)
RxOUT Hold to RxCLK OUT (Figure 7)
f = 20 MHz
f = 40 MHz
19
6
ns
ns
f = 20 MHz
f = 40 MHz
21.5
10.5
ns
ns
f = 20 MHz
f = 40 MHz
14
ns
ns
4.5
f = 20 MHz
f = 40 MHz
16
6.5
7.6
ns
ns
ns
@
RxCLK IN to RxCLK OUT Delay 25˚C,
11.9
VCC = 5.0V (Figure 9)
RPLLS
RPDD
Receiver Phase Lock Loop Set (Figure 11)
Receiver Powerdown Delay (Figure 15 )
10
1
ms
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on the type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
AC Timing Diagrams
DS012638-4
FIGURE 1. “WORST CASE” Test Pattern
DS012638-5
DS012638-6
FIGURE 2. DS90CR281 (Transmitter) LVDS Output Load and Transition Timing
5
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AC Timing Diagrams (Continued)
DS012638-7
DS012638-8
FIGURE 3. DS90CR282 (Receiver) CMOS/TTL Output Load and Transition Timing
DS012638-9
FIGURE 4. DS90CR281 (Transmitter) Input Clock Transition Time
DS012638-10
Measurements at V = 0V
diff
Measurements at V = 0V
diff
TCCS measured between earliest and latest initial LVDS edges.Measurements at V = 0V
diff
→
TxCLK OUT Differential Low High Edge
FIGURE 5. DS90CR281 (Transmitter) Channel-to-Channel Skew and Pulse Width
DS012638-11
FIGURE 6. DS90CR281 (Transmitter) Setup/Hold and High/Low Times
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AC Timing Diagrams (Continued)
DS012638-12
FIGURE 7. (Receiver) DS90CR282 Setup/Hold and High/Low Times
DS012638-13
FIGURE 8. DS90CR281 (Transmitter) Clock In to Clock Out Delay
DS012638-14
FIGURE 9. DS90CR282 (Receiver) Clock In to Clock Out Delay
DS012638-15
FIGURE 10. DS90CR281 (Transmitter) Phase Lock Loop Set Time
7
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AC Timing Diagrams (Continued)
DS012638-16
FIGURE 11. DS90CR282 (Receiver) Phase Lock Loop Set Time
DS012638-17
FIGURE 12. Seven Bits of LVDS in One Clock Cycle
DS012638-18
FIGURE 13. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR281)
DS012638-23
FIGURE 14. Transmitter Powerdown Delay
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AC Timing Diagrams (Continued)
DS012638-24
FIGURE 15. Receiver Powerdown Delay
DS012638-25
FIGURE 16. Transmitter LVDS Output Pulse Position Measurement
DS012638-26
SW — Setup and Hold Time (Internal data sampling window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — Typically 10 ps–40 ps per foot
FIGURE 17. Receiver LVDS Input Skew Margin
9
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DS90CR281 Pin Description—Channel Link Transmitter (Tx)
Pin Name
I/O No.
Description
TxIN
I
28
4
TTL Level inputs
TxOUT+
O
O
I
Positive LVDS differential data output
Negative LVDS differential data output
TxOUT−
4
TxCLK IN
1
TTL level clock input. The rising edge acts as data strobe
Positive LVDS differential clock output
TxCLK OUT+
TxCLK OUT−
PWR DOWN
O
O
I
1
1
Negative LVDS differential clock output
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down
VCC
I
I
I
I
I
I
4
5
1
2
1
3
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
DS90CR282 Pin Description—Channel Link Receiver (Rx)
Pin Name
I/O No.
Description
RxIN+
I
I
4
4
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level outputs
RxIN−
RxOUT
O
I
28
1
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
Positive LVDS differential clock input
Negative LVDS differential clock input
I
1
O
I
1
TTL level clock output. The rising edge acts as data strobe
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
1
I
4
GND
I
5
Ground pins for TTL outputs
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I
1
Power supply for PLL
I
2
Ground pin for PLL
I
1
Power supply pin for LVDS inputs
I
3
Ground pins for LVDS inputs
Applications Information
####
AN-
Topic
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For ex-
ample, for lower data rate (clock rate) and shorter cable
AN-916
Cable Information
CABLES: A cable interface between the transmitter and re-
ceiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR211/212) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR281/282) requires five pairs of signal wires.
The ideal cable/connector interface would have a constant
100Ω differential impedance throughout the path. It is also
recommended that cable skew remain below 350 ps ( 40
MHz clock rate) to maintain a sufficient data sampling win-
dow at the receiver.
<
lengths ( 2m), the media electrical performance is less criti-
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable construc-
tions provide tighter skew (matched electrical length be-
tween the conductors and pairs). Twin-coax for example, has
been demonstrated at distances as great as 10 meters and
with the maximum data transfer of 1.12 Gbit/s. Additional ap-
plications information can be found in the following National
Interface Application Notes:
@
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point ap-
plications include flat ribbon, flex, twisted pair and
Twin-Coax. All are available in a variety of configurations and
options. Flat ribbon cable, flex and twisted pair generally per-
form well in short point-to-point applications while Twin-Coax
####
AN-
Topic
AN-1035
PCB Design Guidelines for LVDS and Link
Devices
AN-806
AN-905
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
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10
ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider-
ations will limit reflections and crosstalk which adversely ef-
fect high frequency performance and EMI.
Applications Information (Continued)
is good for short and long applications. When using ribbon
cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling be-
tween adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All ex-
tended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmis-
sion parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
UNUSED INPUTS: All unused inputs at the TxIN inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a ter-
minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor be-
tween the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18 shows an example. No additional pull-up or
pull-down resistors are necessary as with some other differ-
ential technologies such as PECL. Surface mount resistors
are recommended to avoid the additional inductance that ac-
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re-
duce stubs and effectively terminate the differential lines.
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can-
celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped-
ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui-
ties which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ-
ential impedance of the selected physical media (this imped-
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For
a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
ramic type in surface mount form factor) between each VCC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 19. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive
the most filtering/bypassing. Next would be the LVDS VCC
pins and finally the logic VCC pins.
DS012638-20
FIGURE 18. LVDS Serialized Link Termination
11
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low jitter LVDS clock. These measures provide more margin
for channel-to-channel skew and interconnect skew as a part
of the overall jitter/skew budget.
Applications Information (Continued)
COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR-
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differ-
ential noise margin. Common mode protection is of more im-
portance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
±
Ground to +2.4V. This allows for a 1.0V shifting of the cen-
ter point due to ground potential differences and common
mode noise.
POWER SEQUENCING AND POWERDOWN MODE: Out-
puts of the CHANNEL LINK transmitter remain in TRI-STATE
until the power supply reaches 3V. Clock and data outputs
will begin to toggle 10 ms after VCChas reached 4.5V and the
Powerdown pin is above 2V. Either device may be placed
into a powerdown mode at any time by asserting the Power-
down pin (active low). Total power dissipation for each de-
vice will decrease to 5 µW (typical).
DS012638-21
FIGURE 19. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER: The CHANNEL LINK devices employ a
PLL to generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
40 MHz clock has a period of 25 ns which results in a data bit
width of 3.57 ns. Differential skew (∆t within one differential
pair), interconnect skew (∆t of one differential pair to an-
other) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noise signal. Individual bypassing of each VCC to ground
will minimize the noise passed on to the PLL, thus creating a
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or re-
ceiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) re-
tain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
shorted to V
through an internal diode. Current is limited
CC
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.
DS012638-22
FIGURE 20. Single-Ended and Differential Waveforms
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12
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CR281MTD or DS90CR282MTD
NS Package Number MTD56
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