DS90LV011AHMFX/NOPB [TI]
高温 3V LVDS 差动驱动器 | DBV | 5 | -40 to 125;
| 型号： | DS90LV011AHMFX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高温 3V LVDS 差动驱动器 | DBV | 5 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总28页 (文件大小：2141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
DS90LV011AH 高温3V LVDS 差分驱动器
1 特性
3 说明
• –40°C 至125°C 工作温度范围
• 符合TIA/EIA-644-A 标准
• >400Mbps (200MHz) 转换速率
• 700ps（100ps 典型值）最大差动偏斜
• 1.5ns 最大传播延迟
DS90LV011AH 是一款针对高数据速率和低功耗应用进
行优化的LVDS 驱动器。DS90LV011AH 是一款电流模
式驱动器，即使在高频率条件下也能够保持较低的功率
耗散。此外，它还能够最大限度地降低短路故障电流。
该器件旨在利用低电压差分信号 (LVDS) 技术以支持超
过400Mbps (200MHz) 的数据速率。
• 3.3V 单电源
• ±350mV 差分信号传输
该器件采用 5 引脚 SOT-23 封装。为简化 PCB 布局，
已对 LVDS 输出进行排列。差分驱动器输出可提供低
电磁干扰 (EMI)，其典型的低输出摆幅为 350mV。
DS90LV011AH 可与配套的单通道线路接收器
DS90LT012AH 或任何 TI 的 LVDS 接收器搭配使用，
以提供高速LVDS 接口。
• 断电保护（TRI-STATE 中的输出）
• 引脚排列简化了PCB 布局
• 低功率耗散（3.3V 典型电压下为23mW）
• 5 引脚SOT-23 封装
• 引脚与SN65LVDS1 兼容
2 应用
器件信息(1)
• 板对板通信
• 测试和测量
• 电机驱动器
• LED 视频墙
• 无线基础设施
• 电信基础设施
• 多功能打印机
• NIC 卡
封装尺寸（标称值）
器件型号
封装
SOT-23 (5)
DS90LV011AH
2.90mm × 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 机架式服务器
• 超声波扫描仪
功能图
连接图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS198
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes............................................9
9 Application and Implementation..................................10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................13
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 18
12 Device and Documentation Support..........................19
12.1 Documentation Support.......................................... 19
12.2 接收文档更新通知................................................... 19
12.3 支持资源..................................................................19
12.4 Trademarks.............................................................19
12.5 Electrostatic Discharge Caution..............................19
12.6 术语表..................................................................... 19
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings(1) (2) ................................4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
Information.................................................................... 19
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2019) to Revision C (July 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• Corrected pin description table. Pin 3 should be OUT- and pin 4 should be OUT+............................................3
Changes from Revision A (April 2013) to Revision B (January 2019)
Page
• 添加了器件信息表、ESD 等级表、热性能信息表、典型特性部分、特性说明部分、器件功能模式、应用和
实施部分、电源相关建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分。........ 1
• Changed the Absolute Maximum Ratings tablenote...........................................................................................4
• Moved the ESD parameters in the Absolute Maximum Ratings table to the ESD Ratings table........................4
• Changed the Temperature (TA) parameter in the Recommended Operating Conditions table to Junction
temperature (TJ)..................................................................................................................................................4
Changes from Revision * (April 2013) to Revision A (April 2013)
Page
• 已将国家数据表的版面布局更改为TI 格式......................................................................................................... 1
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
5 Pin Configuration and Functions
图5-1. DBV Package 5-Pin SOT-23 Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VDD
I
I
Power supply pin, +3.3 V ± 0.3 V
Ground pin
2
GND
3
OUT-
OUT+
TTL IN
O
O
I
Inverting driver output pin
Noninverting driver output pin
LVTTL/LVCMOS driver input pins
4
5
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1) (2)
MIN
−0.3
−0.3
−0.3
MAX
4
UNIT
V
Supply voltage (VDD
)
LVCMOS input voltage (TTL IN)
LVDS output voltage (OUT±)
LVDS output short circuit current
3.6
3.9
24
V
V
mA
mW
mW/°C
°C
DBV Package
902
7.22
260
150
150
Maximum package power
dissipation at +25°C
Derate DBV Package (above +25°C)
Lead temperature range soldering (4 sec.)
Maximum Junction Temperature
Storage temperature, Tstg
°C
−65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) (1.5 kΩ,
100 pF)
9000
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) (0 Ω, 0 pF)
2000
V(ESD)
Electrostatic discharge
V
900
EIAJ (0 Ω, 200 pF)
4000
IEC direct (330 Ω, 150 pF)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±9000 V may actually have higher performance.
(2) JJEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
6.3 Recommended Operating Conditions
MIN
3
NOM
3.3
MAX
3.6
UNIT
V
Supply voltage (VDD
)
Junction temperature (TA)
Junction temperature (TJ)
+25
+125
+130
°C
−40
°C
6.4 Thermal Information
DS90LV011AH
DBV (SOT-23)
5 PINS
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
177.7
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
104.4
43.5
19.3
ψJT
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
DS90LV011AH
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
UNIT
Junction-to-board characterization parameter
43.2
°C/W
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
MAX UNIT
6.5 Electrical Characteristics
over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN
MIN
TYP
350
3
|VOD
|
Output Differential Voltage
VOD Magnitude Change
Offset Voltage
250
450
35
mV
mV
V
RL = 100 Ω
(图7-1 and 图7-2)
ΔVOD
VOS
1.125
0
1.22
1
1.375
25
RL = 100 Ω
(图7-1)
Offset Magnitude Change
Power-off Leakage
mV
μA
mA
ΔVOS
IOFF
OUT+,
OUT−
VOUT = 3.6 V or GND, VDD = 0 V
VOUT+ and VOUT− = 0 V
±1
±10
−24
IOS
Output Short Circuit Current(4)
−6
−5
3
Differential Output Short Circuit
Current(4)
IOSD
VOD = 0 V
mA
−12
COUT
VIH
VIL
Output Capacitance
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Clamp Voltage
Input Capacitance
pF
V
2
VDD
0.8
GND
V
IIH
VIN = 3.3 V or 2.4 V
VIN = GND or 0.5 V
ICL = −18 mA
±2
±1
±10
±10
μA
μA
V
TTL IN
IIL
VCL
CIN
−1.5
−0.6
3
5
7
pF
mA
mA
No Load
8
IDD
Power Supply Current
VIN = VDD or GND
RL = 100 Ω
VDD
10
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD
.
(2) All typicals are given for: VDD = +3.3V and TA = +25°C.
(3) The DS90LV011AH is a current mode device and only function with datasheet specification when a resistive load is applied to the
drivers outputs.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
6.6 Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified.(1) (2) (3) (4)
PARAMETER
TEST CONDITIONS
MIN
0.3
0.3
0
TYP
1
MAX UNIT
tPHLD
tPLHD
tSKD1
tSKD3
tSKD4
tTLH
Differential Propagation Delay High to Low
1.5
1.5
0.7
1
ns
ns
Differential Propagation Delay Low to High
1.1
0.1
0.2
0.4
0.5
0.5
250
(5)
ns
Differential Pulse Skew |tPHLD − tPLHD
Differential Part to Part Skew(6)
Differential Part to Part Skew(7)
Transition Low to High Time
|
0
ns
RL = 100Ω, CL = 15 pF
(图7-3 and 图7-4)
0
1.2
1
ns
0.2
0.2
200
ns
tTHL
Transition High to Low Time
1
ns
fMAX
Maximum Operating Frequency(8)
MHz
(1) All typicals are given for: VDD = +3.3V and TA = +25°C.
(2) These parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage, temperature) ranges.
(3) CL includes probe and fixture capacitance.
(4) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤1 ns, tf ≤1 ns (10%-90%).
(5) tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the
negative going edge of the same channel.
(6) tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
(7) tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
(8) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD
>
250mV. The parameter is specified by design. The limit is based on the statistical analysis of the device over the PVT range by the
transitions times (tTLH and tTHL).
6.7 Typical Characteristics
图6-1. Loaded Supply Current vs Power Supply Voltage
图6-2. No Load Supply Current vs Power Supply Voltage
图6-3. Output Short-Circuit Current vs Power Supply Voltage
图6-4. Differential Output Short-Circuit Current vs Power
Supply Voltage
图6-5. . Output Differential Voltage vs Power Supply Voltage
图6-6. Offset Voltage vs Power Supply Voltage
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
7 Parameter Measurement Information
图7-1. Differential Driver DC Test Circuit
图7-2. Differential Driver Full Load DC Test Circuit
图7-3. Differential Driver Propagation Delay and Transition Time Test Circuit
图7-4. Differential Driver Propagation Delay and Transition Time Waveforms
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
8 Detailed Description
8.1 Overview
The DS90LV011AH is a single-channel, low-voltage differential signaling (LVDS) line driver with a balanced
current source design. It operates from a single supply that is nominally 3.3 V, but can be as low as 3.0 V and as
high as 3.6 V. The input signal to the DS90LV011AH is an LVCMOS/LVTTL signal. The output of the device is a
differential signal complying with the LVDS standard (TIA/EIA-644). The differential output signal operates with a
signal level of 350 mV, nominally, at a common-mode voltage of 1.2 V. This low differential output voltage results
in low electromagnetic interference (EMI). The differential nature of the output provides immunity to common-
mode coupled signals that the driven signal may experience.
The DS90LV011AH is primarily used in point-to-point configurations, as seen in 图 9-1. This configuration
provides a clean signaling environment for the fast edge rates of the DS90LV011AH and other LVDS drivers.
The DS90LV011AH is connected through a balanced media which may be a standard twisted pair cable, a
parallel pair cable, or simply PCB traces to a LVDS receiver. Typically, the characteristic differential impedance of
the media is in the range of 100 Ω. The DS90LV011AH device is intended to drive a 100-Ω transmission line.
The 100-Ωtermination resistor is selected to match the media and is located as close to the LVDS receiver input
pins as possible.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 DS90LV011AH Driver Functionality
As can be seen in 表 8-1, the driver signle-ended input to differential output relationship is defined. When the
driver input is left open, the differential output is undefined.
表8-1. DS90LV011AH Driver Functionality
INPUT
OUTPUTS
LVCMOS/LVTTL IN
OUT +
OUT -
H
L
H
L
?
L
H
?
Open
8.3.2 Driver Output Voltage and Power-On Reset
The DS90LV011AH driver operates and meets all the specified performance requirements for supply voltages in
the range of 3.0 V to 3.6 V. When the supply voltage drops below 1.5 V (or is turning on and has not yet reached
1.5 V), power-on reset circuitry set the driver output to a high-impedance state.
8.3.3 Driver Offset
An LVDS-compliant driver is required to maintain the common-mode output voltage at 1.2 V (±75 mV). The
DS90LV011AH incorporates sense circuitry and a control loop to source common-mode current and keep the
output signal within specified values. Further, the device maintains the output common-mode voltage at this set
point over the full 3.0-V to 3.6-V supply range.
8.4 Device Functional Modes
The device has one mode of operation that applies when operated within 节6.3.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The DS90LV011AH device is a single-channel LVDS driver. The functionality of this device is simple, yet
extremely flexible, leading to its use in designs ranging from wireless base stations to desktop computers. The
varied class of potential applications share features and applications discussed in the paragraphs below. The
DS90LV011AH has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the
device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the
receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
9.2 Typical Application
图9-1. Point-to-Point Application
9.2.1 Design Requirements
表9-1 lists the design parameters for this example
表9-1. Design Parameters
DESIGN PARAMETERS
Driver Supply Voltage (VDD
Driver Input Voltage
EXAMPLE VALUE
3 to 3.6 V
0 to VDD
0 to 400 Mbps
100 Ω
)
Signaling Rate
Interconnect Characteristic Impedance
Number of Receiver Nodes
1
Ground shift between driver and receiver
±1 V
9.2.2 Detailed Design Procedure
9.2.2.1 Driver Supply Voltage
DS90LV011AH is a LVDS that is operated from a single supply. The device can support operation with a supply
as low as 3.0 V and as high as 3.6 V. The driver output voltage is dependent upon the chosen supply voltage.
The minimum output voltage stays within the specified LVDS limits (247 mV to 450 mV) for a 3.3-V supply. If the
supply range is between 3.0 V and 3.6 V, the minimum output voltage may be as low as 150 mV. If a
communication link is designed to operate with a supply within this lower range, the channel noise margin will
need to be looked at carefully to ensure error-free operation.
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
9.2.2.2 Driver Bypass Capacitance
Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths
between power and ground. At low frequencies, a good digital power supply offers very low-impedance paths
between its terminals. However, as higher frequency currents propagate through power traces, the source is
quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address
this shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board-level do a good job up into
the kHz range. Due to their size and length of their leads, they tend to have large inductance values at the
switching frequencies of modern digital circuitry. To solve this problem, one must resort to the use of smaller
capacitors (nF to μF range) installed locally next to the integrated circuit.
Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass
capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,
a typical capacitor with leads has a lead inductance around 5 nH.
The value of the bypass capacitors used locally with LVDS chips can be determined by 方程式 1 and 方程式 2
according to Johnson1 equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in
supply current of 1 A covers the whole range of LVDS devices offered by Texas Instruments. In this example, the
maximum power supply noise tolerated is 200 mV. However, this figure varies depending on the noise budget
available in the design. 1
DIMaximum Step Change Supply Current
æ
ö
Cchip
=
´ TRise Time
ç
÷
DVMaximum Power Supply Noise
è
ø
(1)
1A
æ
ö
CLVDS
=
´ 200 ps = 0.001mF
ç
è
÷
ø
0.2V
(2)
图 9-2 lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10 µF)
and the value of capacitance found above (0.001 µF). TI recommends that the user place the smallest value of
capacitance as close to the chip as possible.
3.3 V
0.1 µF
0.001 µF
图9-2. Recommended LVDS Bypass Capacitor Layout
9.2.2.3 Driver Input Votlage
DS90LV011AH input is designed to support a wide input voltage range. The input stage can accept signals as
high as 3.6 V when the supply voltage is 3.6 V.
9.2.2.4 Driver Output Voltage
DS90LV011AH driver output has a 1.2-V common-mode voltage, with a nominal differential output signal of 350
mV. This 350 mV is the absolute value of the differential swing (VOD = |V+–V–|). The peak-to-peak differential
voltage is twice this value, or 700 mV. LVDS receiver thresholds are ±100 mV. With these receiver decision
thresholds, it is clear that the disadvantage of operating the driver with a lower supply will be noise margin. With
fully compliant LVDS drivers and receivers, we would expect a minimum of ~150 mV of noise margin (247-mV
minimum output voltage –100-mV maximum input requirement). If we operate the DS90LV011AH with a supply
in the range of 3.0 V to 3.6 V, the minimum noise margin will drop to 150 mV.
1
Howard Johnson & Martin Graham.1993. High Speed Digital Design –A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
9.2.2.5 Interconnecting Media
The physical communication channel between the driver and the driver may be any balanced and paired metal
conductors meeting the requirements of the LVDS standard, the key points of which are included here. This
media may be a twisted-pair, twinax, flat ribbon cable, or PCB traces. The nominal characteristic impedance of
the interconnect media should be between 100 Ωand 120 Ωwith a variation of no more than 10% (90 Ωto 132
Ω).
9.2.2.6 PCB Transmission Lines
As per the LVDS Owner's Manual Design Guide, 4th Edition, 图 9-3 depicts several transmission line structures
commonly used in printed-circuit boards (PCBs). Each structure consists of a signal line and return path with a
uniform cross section along its length. A microstrip is a signal trace on the top (or bottom) layer, separated by a
dielectric layer from its return path in a ground or power plane. A stripline is a signal trace in the inner layer, with
a dielectric layer in between a ground plane above and below the signal trace. The dimensions of the structure
along with the dielectric material properties determine the characteristic impedance of the transmission line (also
called controlled-impedance transmission line).
When two signal lines are placed close by, they form a pair of coupled transmission lines. 图 9-3 shows
examples of edge-coupled microstrip lines, and edge-coupled or broad-side-coupled striplines. When excited by
differential signals, the coupled transmission line is referred to as a differential pair. The characteristic
impedance of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is
the differential impedance of the differential pair. In addition to the trace dimensions and dielectric material
properties, the spacing between the two traces determines the mutual coupling and impacts the differential
impedance. When the two lines are immediately adjacent; for example, S is less than 2 W, the differential pair is
called a tightly-coupled differential pair. To maintain constant differential impedance along the length, it is
important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry
between the two lines.
Single-Ended Microstrip
Single-Ended Stripline
W
W
T
H
H
T
H
≈
’
≈
∆
«
5.98 H
’
÷
◊
1.9 2 H+ T
87
[
]
60
Z0
=
ln
Z0
=
ln
∆
∆
÷
÷
0.8 W + T
er +1.41
0.8 W + T
er
[
]
«
◊
Edge-Coupled
Edge-Coupled
S
S
H
H
Differential Microstrip
Differential Stripline
s
s
≈
’
÷
≈
’
÷
-0.96 ì
-2.9 ì
H
H
∆
∆
Zdiff = 2 ì Z0
ì
1- 0.48 ì e
Zdiff = 2 ì Z0
ì
1- 0.347e
∆
«
÷
◊
∆
«
÷
◊
Co-Planar Coupled
Microstrips
Broad-Side Coupled
Striplines
W
W
W
G
S
G
H
S
H
图9-3. Controlled-Impedance Transmission Lines
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
9.2.3 Termination Resistor
As shown earlier, an LVDS communication channel employs a current source driving a transmission line that is
terminated with a resistive load. This load serves to convert the transmitted current into a voltage at the receiver
input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling
rate), the termination resistance should be matched to the characteristic impedance of the transmission line. The
designer should ensure that the termination resistance is within 10% of the nominal media characteristic
impedance. If the transmission line is targeted for 100-Ω impedance, the termination resistance should be
between 90 Ω and 110 Ω. The line termination resistance should be placed as close to the receiver as possible
to minimize the stub length from the resistor to the receiver.
9.2.4 Application Curve
图9-4. DS90LV011AH Performance: Data Rate vs Cable Length
10 Power Supply Recommendations
The DS90LV011AH driver is designed to operate from a single power supply with supply voltage in the range of
3.0 V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate
equipment. In these cases, separate supplies would be used at each location. The expected ground potential
difference between the driver power supply and the driver power supply would be less than |±1 V|. Board level
and local device level bypass capacitance should be used.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
11.1.1 Microstrip vs. Stripline Topologies
As per the LVDS Application and Data Handbook, printed-circuit boards usually offer designers two transmission
line options: Microstrip and stripline. Microstrips are traces on the outer layer of a PCB, as shown in 图11-1.
图11-1. Microstrip Topology
On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and
susceptibility problems because the reference planes effectively shield the embedded traces. However, from the
standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends
routing LVDS signals on microstrip transmission lines when possible. The PCB traces allow designers to specify
the necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 12, 23,
and 34 provide formulas for ZO and tPD for differential and single-ended traces. 2 3 4
图11-2. Stripline Topology
11.1.2 Dielectric Type and Board Construction
The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually
provides adequate performance for use with LVDS signals. If rise or fall times of LVCMOS/LVTTL signals are
less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™
4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters
pertaining to the board construction that can affect performance. The following set of guidelines were developed
experimentally through several designs involving LVDS devices:
• Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
• All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
• Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
• Solder mask over bare copper with solder hot-air leveling
2
Howard Johnson & Martin Graham.1993. High Speed Digital Design –A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
3
Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.
4
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
11.1.3 Recommended Stack Layout
Following the choice of dielectrics and design specifications, the designer must decide how many levels to use in
the stack. To reduce the LVCMOS/LVTTL to LVDS crosstalk, it is good practice to have at least two separate
signal planes as shown in 图11-3.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Routed Plane (TTL/CMOS Signals)
图11-3. Four-Layer PCB Board
Note
The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and
ground planes tightly coupled, the increased capacitance acts as a bypass for transients.
One of the most common stack configurations is the six-layer board, as shown in 图11-4.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Ground Plane
Layer 5: Ground Plane
Layer 4: Routed Plane (TTL Signals)
图11-4. Six-Layer PCB Board
In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one
ground plane. The result is improved signal integrity, but fabrication is more expensive. Using the 6-layer board
is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers
and referenced planes in addition to ensuring reference to a ground plane for signal layers 1 and 6.
11.1.4 Separation Between Traces
The separation between traces depends on several factors, but the amount of coupling that can be tolerated
usually dictates the actual separation. Low-noise coupling requires close coupling between the differential pair of
an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-Ω differential and
thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same
electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection.
In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance
between two traces must be greater than two times the width of a single trace, or three times its width measured
from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The
same rule should be applied to the separation between adjacent LVDS differential pairs, whether the traces are
edge-coupled or broad-side-coupled.
W
LVDS
Pair
Minimum spacing as
defined by PCB vendor
Differential Traces
S =
W
í 2 W
Single-Ended Traces
TTL/CMOS
Trace
W
图11-5. 3-W Rule for Single-Ended and Differential Traces (Top View)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
Exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk
and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signal path.
Using successive 45° turns tends to minimize reflections.
11.1.5 Crosstalk and Ground Bounce Minimization
To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close to its
originating trace as possible. A ground plane usually achieves this. Because the returning currents always
choose the path of lowest inductance, they are most likely to return directly under the original trace, thus
minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as
short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of
electromagnetic field strength. Discontinuities in the ground plane increase the return path inductance and
should be avoided.
11.1.6 Decoupling
Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance
path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. TI
recommends placing a via immediately adjacent to the pin to avoid adding trace inductance. Placing a power
plane closer to the top of the board reduces the effective via length and its associated inductance.
V
GND
Via
CC
Via
TOP signal layer + GND fill
1 plane
4 mil
6 mil
V
DD
2 mil
Buried capacitor
>
GND plane
Signal layer
GND plane
Signal layers
V
plane
CC
Signal layer
GND plane
Buried capacitor
>
V
2 plane
DD
4 mil
6 mil
BOTTOM signal layer + GND fill
Typical 12-Layer PCB
图11-6. Low Inductance, High-Capacitance Power Connection
Bypass capacitors should be placed close to VDD pins. They can be placed conveniently near the corners or
underneath the package to minimize the loop area. This extends the useful frequency range of the added
capacitance. Small-physical-size capacitors, such as 0402 or even 0201, or X7R surface-mount capacitors
should be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power
and ground plane through vias tangent to the pads of the capacitor as shown in 图11-7(a).
An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30
MHz or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a
few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly
used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground
at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.
Refer back to Figure 8 for some examples. Many high-speed devices provide a low-inductance GND connection
on the backside of the package. This center dap must be connected to a ground plane through an array of vias.
The via array reduces the effective inductance to ground and enhances the thermal performance of the small
Surface Mount Technology (SMT) package. Placing vias around the perimeter of the dap connection ensures
proper heat spreading and the lowest possible die temperature. Placing high-performance devices on opposing
sides of the PCB using two GND planes (as shown in 图 9-3) creates multiple paths for heat transfer. Often
thermal PCB issues are the result of one device adding heat to another, resulting in a very high local
temperature.
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
Multiple paths for heat transfer minimize this possibility. In many cases the GND dap that is so important for heat
dissipation makes the optimal decoupling layout impossible to achieve due to insufficient pad-to-dap spacing as
shown in 图 11-7(b). When this occurs, placing the decoupling capacitor on the backside of the board keeps the
extra inductance to a minimum. It is important to place the VDD via as close to the device pin as possible while
still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the pad and into the
via barrel. This will result in a poor solder connection.
V
DD
INœ
0402
(a)
IN+
0402
(b)
图11-7. Typical Decoupling Capacitor Layouts
At least two or three times the width of an individual trace should separate single-ended traces and differential
pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength
of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long
parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as
shown in 图11-8.
Layer 1
Layer 6
图11-8. Staggered Trace Layout
This configuration lays out alternating signal traces on different layers. Thus, the horizontal separation between
traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path,
TI recommends having an adjacent ground via for every signal via, as shown in 图 11-9. Note that vias create
additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4.
Signal Via
Signal Trace
Uninterrupted Ground Plane
Signal Trace
Uninterrupted Ground Plane
Ground Via
图11-9. Ground Via Location (Side View)
Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground
bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create
discontinuities that increase returning current loop areas.
To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and
so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the
same area, as opposed to mixing them together, helps reduce susceptibility issues.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
11.2 Layout Example
图11-10. Example DS90LV011AH Layout
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: DS90LV011AH
DS90LV011AH
ZHCSJ91C –SEPTEMBER 2005 –REVISED JULY 2021
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, LVDS Owner's Manual dseign guide
• Texas Instruments, AN-808 Long Transmission Lines and Data Signal Quality application note
• Texas Instruments, AN-977 LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report #1
application note
• Texas Instruments, AN-971 An Overview of LVDS Technology application note
• Texas Instruments, AN-916 A Practical Guide to Cable Selection application note
• Texas Instruments, AN-805 Calculating Power Dissipation for Differential Line Drivers application note
• Texas Instruments, AN-903 A Comparison of Differential Termination Techniques application note
• Texas Instruments, AN-1194 Failsafe Biasing of LVDS Interfaces application note
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
Rogers™ is a trademark of Rogers Corporation.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: DS90LV011AH
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90LV011AHMF/NOPB
DS90LV011AHMFX/NOPB
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
1000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
N04
N04
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV011AHMF/NOPB SOT-23
DBV
DBV
5
5
1000
3000
178.0
178.0
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
DS90LV011AHMFX/NOP SOT-23
B
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90LV011AHMF/NOPB
DS90LV011AHMFX/NOPB
SOT-23
SOT-23
DBV
DBV
5
5
1000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明