DS90LV027M/NOPB [TI]
LVDS 双路高速差动驱动器 | D | 8 | 0 to 70;
| 型号： | DS90LV027M/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVDS 双路高速差动驱动器 | D | 8 | 0 to 70 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV027
www.ti.com
SNLS003C –JUNE 1998–REVISED APRIL 2013
DS90LV027 LVDS Dual High Speed Differential Driver
Check for Samples: DS90LV027
1
FEATURES
DESCRIPTION
The DS90LV027 is a dual LVDS driver device
optimized for high data rate and low power
applications. The DS90LV027 is a current mode
driver allowing power dissipation to remain low even
at high frequency. In addition, the short circuit fault
current is also minimized. The device is in a 8-lead
SOIC package. The DS90LV027 has a flow-through
design for easy PCB layout. The differential driver
outputs provides low EMI with its low output swings
typically 340 mV. Perfect for high speed transfer of
clock and data. Pair with any of TI's LVDS receivers.
23
•
Ultra Low Power Dissipation
•
Operating Range above 155 Mbps
Flow-through pinout simplifies PCB layout
Conforms to TIA/EIA-644 Standard
8-Lead SOIC Package Saves Space
VCM ±1V center around 1.2V
•
•
•
•
•
•
Low Differential Output Swing Typical 340 mV
Power Off Protection (outputs in high
impedance)
Connection Diagram
Figure 1. Dual-In-Line
See Package Number D (R-PDSO-G8)
Functional Diagram
Truth Table(1)
Input/Output
DI
L
DO+
L
DO−
H
H
H
L
DI > 0.8V and DI < 2.0V
X
X
(1) H = Logic high level
L = Logic low level
X = indeterminant
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
DS90LV027
SNLS003C –JUNE 1998–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VCC
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to +3.9V
Input Voltage (DI)
Output Voltage (DO±)
Maximum Package Power Dissipation @ +25°C
D Package
1190 mW
9.5 mW/°C above +25°C
−65°C to +150°C
Derate D Package
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
+260°C
(2)
ESD Rating
(HBM 1.5 kΩ, 100 pF)
≥ 4.5 kV
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 4.5 kV
Recommended Operating Conditions
Min
3.0
0
Typ
3.3
25
Max
3.6
70
Units
V
Supply Voltage (VCC
)
Temperature (TA)
°C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1) (2) (3)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
DIFFERENTIAL DRIVER CHARACTERISTICS
VOD
ΔVOD
VOH
VOL
VOS
ΔVOS
IOZD
IOXD
IOSD
VIH
Output Differential Voltage
VOD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
RL = 100Ω (Figure 2)
DO+,
DO−
250
0
340
10
450
35
mV
mV
V
1.43
1.09
1.25
5
1.6
0.9
0.9
0
V
1.6
25
V
Offset Magnitude Change
TRI-STATE® Leakage
Power-off Leakage
mV
μA
μA
mA
V
VOUT = VCC or GND
0
±1
±10
±10
−6
VOUT = 3.6V or GND, VCC = 0V
0
±1
Output Short Circuit Current
Input High Voltage
−4
DI
2.0
VCC
0.8
±10
±10
VIL
Input Low Voltage
GND
V
IIH
Input High Current
VIN = 3.6V or 2.4V
VIN = GND or 0.5V
ICL = −18 mA
±1
±1
−0.8
1
μA
μA
V
IIL
Input Low Current
VCL
ICC
Input Clamp Voltage
Power Supply Current
−1.5
No Load
VIN = VCC or GND
VCC
4
mA
mA
RL = 100Ω
8
11
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD
.
(2) All typicals are given for: VCC = +3.3V and TA = +25°C.
(3) The DS90LV027 is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers
outputs.
2
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Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV027
DS90LV027
www.ti.com
SNLS003C –JUNE 1998–REVISED APRIL 2013
Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified.
(1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIFFERENTIAL DRIVER CHARACTERISTICS
tPHLD
tPLHD
tSKD
tTLH
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
RL = 100Ω, CL = 5 pF
(Figure 3 and Figure 4)
1.5
1.5
0
3.4
3.5
0.1
1
6
6
ns
ns
ns
ns
ns
Differential Skew |tPHLD − tPLHD
Transition Low to High Time
Transition High to Low Time
|
1.9
3
0
tTHL
0
1
3
(1) CL includes probe and fixture capacitance.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 6 ns, tf ≤ 6 ns (10%-90%).
PARAMETER MEASUREMENT INFORMATION
Figure 2. Differential Driver DC Test Circuit
Figure 3. Differential Driver Propagation Delay and Transition Time Test Circuit
Figure 4. Differential Driver Propagation Delay and Transition Time Waveforms
Copyright © 1998–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS90LV027
DS90LV027
SNLS003C –JUNE 1998–REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
Table 1. Device Pin Descriptions
Pin #
2, 3
6, 7
5, 8
4
Name
DI
Description
TTL/CMOS driver input pins
Non-inverting driver output pin
Inverting driver output pin
Ground pin
DO+
DO−
GND
1
VCC
Positive power supply pin,
+3.3V ± 0.3V
4
Submit Documentation Feedback
Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV027
DS90LV027
www.ti.com
SNLS003C –JUNE 1998–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 4
Copyright © 1998–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS90LV027
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90LV027M/NOPB
DS90LV027MX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
90LV
027M
ACTIVE
2500 RoHS & Green
SN
90LV
027M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV027MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DS90LV027MX/NOPB
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90LV027M/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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