DS90LV028AQDQFRQ1 [TI]
汽车类 LVDS 双路差动线路接收器 | DQF | 8 | -40 to 125;
| 型号： | DS90LV028AQDQFRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 LVDS 双路差动线路接收器 | DQF | 8 | -40 to 125 光电二极管 接口集成电路 |
| 文件： | 总24页 (文件大小：1297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV028A-Q1
ZHCSR68 –AUGUST 2020
DS90LV028A-Q1 汽车类LVDS 双路差动线路接收器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
DS90LV028A-Q1 是一款双路 CMOS 差分线路接收
器，专为需要超低功率损耗、低噪声和高数据速率的应
用而设计。该器件旨在利用低电压差动信号 (LVDS) 技
术支持超过400Mbps (200MHz) 的数据速率。
– 温度等级2：-40°C 至+105°C
• >400Mbps (200MHz) 的开关速率
• 50ps 差分延迟（典型值）
• 0.1ns 通道间延迟（典型值）
• 2.5ns 最大传播延迟
• 3.3V 电源设计
• 直通引脚排列
DS90LV028A-Q1 可接受低电压（350mV 典型值）差
分输入信号，并将其转换为 3V CMOS 输出电平。
DS90LV028A-Q1 采用了直通式设计，可简化 PCB 布
局。
• 在断电模式下，LVDS 输入端具有高阻抗
• 低功耗设计（3.3V 静态条件下为18mW）
• LVDS 输入可接受LVDS/CML/LVPECL 信号
• 符合ANSI/TIA/EIA-644 标准
DS90LV028A-Q1 和配套的 LVDS 线路驱动器
DS90LV027AQ 为高速点对点接口应用提供了高功率
PECL/ECL 器件的全新替代方案。
器件信息(1)
2 应用
封装尺寸（标称值）
器件型号
封装
DS90LV028A-Q1
WSON (DQF 8)
2.00mm x 2.00mm
• 电子销售终端(EPOS) 应用
• 汽车信息娱乐系统与仪表组
• 汽车音响主机
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
RIN1-
RIN1+
RIN2-
RIN2+
R
ROUT1
R
ROUT2
功能图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS672
DS90LV028A-Q1
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Table of Contents
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................13
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Examples.....................................................14
12 Device and Documentation Support..........................15
12.1 支持资源..................................................................15
12.2 Trademarks.............................................................15
12.3 静电放电警告.......................................................... 15
12.4 术语表..................................................................... 15
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD and Latch-Up Ratings.........................................4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Typical Performance Curves.......................................6
7 Parameter Measurement Information............................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
Information.................................................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
August 2020
*
Initial Release
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5 Pin Configuration and Functions
RIN1-
8
7
6
5
1
2
3
4
VCC
RIN1+
ROUT
1
RIN2+
RIN2-
ROUT
2
GND
图5-1. DQF Package WSON 8 Pin Top View
Pin Functions
Pin Number
Name
Description
1
4
2
3
6
7
8
5
RIN1-
RIN2-
RIN1+
RIN2+
Inverting receiver input pin
Non-inverting receiver input pin
Receiver output pin
ROUT
ROUT
VCC
2
1
Power supply pin, +3.3V +/- 0.3V
Ground pin
GND
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6 Specifications
6.1 Absolute Maximum Ratings
MIN
−0.3
−0.3
−0.3
MAX
4
UNIT
V
Supply Voltage (VCC
Input Voltage (RIN+, RIN−)
Output Voltage (ROUT
)
3.9
V
)
VCC+0.3
260
V
Lead Temperature Range Soldering
Maximum Junction Temperature
Storage temperature, Tstg
(4 sec.)
°C
°C
°C
125
150
−65
6.2 ESD and Latch-Up Ratings
VALUE
±4000
±1250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
Positive I-Test Latch-Up
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Positive I-Test Latchup , per AEC Q100-004 at maximum ambient temperature (all
signal pins)
I-Test+
+100
-100
-70
mA
mA
mA
Negative I-Test Latchup, per AEC Q100-004 at maximum ambient temperature
(all signal pins except pin 3)
I-Test-
Negative I-Test Latch-Up
Negative I-Test Latchup, per AEC Q100-004 at maximum ambient temperature
(pin 3)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. .
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage (VCC
)
+3.0
+0.5
−40
+3.3
25
+3.6
+2.1
105
V
Receiver Input Voltage
V
Operating Free Air Temperature (TA)
°C
6.4 Thermal Information
DS90LV028A-Q1
DQF (WSON)
8 PINS
104.0
THERMAL METRIC(1)
UNIT
RθJA
RθJC(bot)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
33.3
Junction-to-board thermal resistance
27.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
27.4
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2)
Symbol
VTH
VTL
Parameter
Conditions
Pin
Min
Typ
Max
+100
Units
mV
Differential Input High Threshold
Differential Input Low Threshold
VCM(1) = +1.2 V, 0.5 + (|VID|/2) V, 2.1 - (|VID|/2(2)
mV
uA
uA
uA
V
−100
RIN+,
VIN = +2.8V
VCC = 3.6V or 0V
VIN = 0V
±1
±1
+10
+10
+20
−10
−10
-20
2.7
RIN−
IIN
Input Current
VIN = +3.6V
VCC = 0V
IOH = −0.4 mA, VID (2) = +200 mV
IOL = 2 mA, VID (2) = −200 mV
VOUT = 0V (3)
VOH
VOL
IOS
Output High Voltage
3.1
0.3
Output Low Voltage
0.5
V
ROUT
Output Short Circuit Current
Input Clamp Voltage
mA
V
−100
−1.5
−50
−0.8
5.4
−15
VCL
ICC
ICL = −18 mA
No Load Supply Current
VID (2) = +200 mV or -200mV
VCC
9
mA
(1) VCM is input common mode voltage |(VRIN+ + VRIN-)/2|
(2) VID is input differential voltage (VRIN+ - VRIN-
)
6.6 Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(2) (4) (5)
Symbol
tPHLD
tPLHD
tSKD1
tSKD2
tSKD3
tSKD4
tTLH
Parameter
Conditions
Min
Typ
Max
Units
Differential Propagation Delay High to Low
CL = 15 pF
1.0
1.0
0
1.6
1.7
50
2.5
2.5
650
0.5
1.0
1.5
800
800
ns
Differential Propagation Delay Low to High
VID = 200 mV
ns
(6)
ps
Differential Pulse Skew |tPHLD − tPLHD
|
(图7-1 and 图7-2)
Differential Channel-to-Channel Skew-same device (7)
Differential Part to Part Skew (8)
Differential Part to Part Skew (9)
Rise Time
0
0.1
ns
0
ns
0
ns
325
225
250
ps
tTHL
Fall Time
ps
fMAX
Maximum Operating Frequency (10)
MHz
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified (such as VID).
(2) All typicals are given for: VCC = +3.3V and TA = +25°C.
(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
(4) CL includes probe and jig capacitance.
(5) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤3 ns for RIN.
(6) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge
of the same channel.
(7) tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple
receivers within the integrated circuit.
(8) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC and within 5°C of each other within the operating temperature range.
(9) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
(10) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:
60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes).
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6.7 Typical Performance Curves
图6-2. Output Low Voltage vs Power Supply
图6-1. Output High Voltage vs Power Supply
Voltage
Voltage
图6-4. Differential Transition Voltage vs Power
图6-3. Output Short Circuit Current vs Power
Supply Voltage
Supply Voltage
图6-5. Differential Propagation Delay vs Power
图6-6. Differential Propagation Delay vs
Supply Voltage
Differential Input Voltage
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图6-8. Transition Time vs Power Supply Voltage
图6-7. Differential Propagation Delay vs Common-
Mode Voltage
图6-9. Differential Skew vs Power Supply Voltage
图6-10. Differential Propagation Delay vs Load
图6-12. Transition Time vs Load
图6-11. Differential Propagation Delay vs Load
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图6-13. Transition Time vs Load
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7 Parameter Measurement Information
图7-1. Receiver Propagation Delay and Transition Time Test Circuit
图7-2. Receiver Propagation Delay and Transition Time Waveforms
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8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in a simple point-to-point configuration as is shown
in 图 9-1. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The
receiver is connected to the source through a impedance controlled 100 Ωdifferential PCB traces. A termination
resistor of 100 Ω should be used, and is located as close to the receiver input pins as possible. The termination
resistor converts the driver output (current mode) into a voltage that is detected by the receiver.
8.2 Functional Block Diagram
RIN1-
R
ROUT1
RIN1+
RIN2-
RIN2+
R
ROUT2
8.3 Feature Description
The DS90LV028A-Q1 differential line receiver is capable of detecting signals as low as 100 mV, over a common-
mode range of 0.5 + (VID/2) V to 2.1 - (VID/2) V. This is related to the driver offset voltage which is typically
+1.2V. The driven signal is centered around this voltage and may shift ±0.5V around this center point. The ±0.5V
shifting may be the result of a ground potential difference between the driver's ground reference and the
receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a recommended operating input voltage range of +0.5V
to +2.1V (measured from each pin to ground). The device will operate for receiver input voltages up to VCC, but
exceeding VCC will turn on the ESD protection circuitry which will clamp the bus voltages.
8.4 Device Functional Modes
表8-1. Truth Table
INPUTS
[RIN+] − [RIN−]
VID ≥0.1V
OUTPUT
ROUT
H
L
VID ≤−0.1V
(1)
?
−0.1V ≤VID ≤0.1V
(1) ? indicates state is indeterminate
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS application
notes and design guides.
9.2 Typical Application
图9-1. Balanced System Point-to-Point Application
9.2.1 Design Requirements
When using LVDS devices, it is important to remember to specify controlled impedance PCB traces. All
components of the transmission media must have a matched differential impedance of 100 Ω. They must not
introduce major impedance discontinuities.
9.2.2 Detailed Design Procedure
9.2.2.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1 μF and 0.01 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to
the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling.
Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or
greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board
between the supply and ground.
9.2.2.2 Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90 Ω and 110 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a
single resistor across the pair at the receiver end will suffice.
Surface mount 1% resistors are the best. PCB stubs, component lead, and the distance from the termination to
the receiver inputs should be minimized. The distance between the termination resistor and the receiver should
be < 10 mm (12 mm MAX).
9.2.2.3 Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5 kΩ to 15 kΩ range to minimize loading and waveform distortion to the driver. The common-
mode bias point ideally should be set to approximately 1.2 V to be compatible with the internal circuitry. Please
refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces”(SNLA051)for more information.
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9.2.2.4 Probing LVDS Transmission Lines
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
9.2.3 Application Curves
图9-2. Power Supply Current vs Frequency
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10 Power Supply Recommendations
Bypass capacitors must be used on power pins. TI recommends using high-frequency, ceramic, 0.1-µF and
0.01-µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device
supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple vias must
be used to connect the decoupling capacitors to the power planes. A 10-µF bulk capacitor, 35-V (or greater)
solid tantalum capacitor must be connected at the power entry point on the printed-circuit board between the
supply and ground.
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11 Layout
11.1 Layout Guidelines
11.1.1 Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission trace and
termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the
IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-
mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm
apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the
differential lines is much more likely to appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997 mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number of vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
11.1.2 PC Board Considerations
Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to
put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
11.2 Layout Examples
图11-1. WSON Thermal Land Pad and Pin Pads
DS90LV028A
DS90LV027A
DO- 1
1
2
3
4
VCC
16
15
14
13
1
2
3
4
8
7
6
5
RIN1-
RIN1+
RIN2+
RIN2-
VCC
DI 1
DI 2
Series Termination (optional)
ROUT1
ROUT2
GND
DO+ 1
DO+ 2
DO- 2
LVCMOS
Inputs
LVCMOS
Outputs
Decoupling Cap
(Bottom Layer)
GND
Decoupling Cap
(Bottom Layer)
Input Termination
(Required)
图11-2. Simplified DS90LV027A and DS90LV028A Layout
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12 Device and Documentation Support
12.1 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
12.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.3 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.4 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90LV028AQDQFRQ1
DS90LV028AQDQFTQ1
ACTIVE
ACTIVE
WSON
WSON
DQF
DQF
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
D28Q
D28Q
Samples
Samples
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2023
OTHER QUALIFIED VERSIONS OF DS90LV028A-Q1 :
Catalog : DS90LV028A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV028AQDQFRQ1 WSON
DS90LV028AQDQFTQ1 WSON
DQF
DQF
8
8
3000
250
178.0
178.0
8.4
8.4
2.25
2.25
2.25
2.25
1.0
1.0
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90LV028AQDQFRQ1
DS90LV028AQDQFTQ1
WSON
WSON
DQF
DQF
8
8
3000
250
205.0
205.0
200.0
200.0
33.0
33.0
Pack Materials-Page 2
PACKAGE OUTLINE
DQF0008A
WSON - 0.8 mm max height
S
C
A
L
E
6
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.05 C
0.05
0.00
SYMM
(0.2) TYP
4
5
SYMM
2X 1.5
6X 0.5
8
1
0.3
8X
0.2
0.1
0.05
0.7
0.5
C A B
PIN 1 ID
0.6
0.4
7X
4220563/A 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQF0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SEE SOLDER MASK
DETAIL
SYMM
(0.8)
8
8X (0.25)
1
SYMM
6X (0.5)
(R0.05) TYP
4
5
7X (0.7)
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220563/A 03/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQF0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.8)
8X (0.25)
1
8
SYMM
6X (0.5)
(R0.05) TYP
5
4
SYMM
(1.7)
7X (0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
4220563/A 03/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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