DS90LV032A [TI]
3V 400Mbps LVDS 四路差动线路接收器;
| 型号： | DS90LV032A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3V 400Mbps LVDS 四路差动线路接收器 驱动 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总18页 (文件大小：975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV032A
www.ti.com
SNLS011C –JULY 1999–REVISED APRIL 2013
DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver
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1
FEATURES
DESCRIPTION
The DS90LV032A is a quad CMOS differential line
receiver designed for applications requiring ultra low
power dissipation and high data rates. The device is
designed to support data rates in excess of 400 Mbps
(200 MHz) utilizing Low Voltage Differential Signaling
(LVDS) technology.
23
•
>400 Mbps (200 MHz) switching rates
0.1 ns channel-to-channel skew (typical)
0.1 ns differential skew (typical)
•
•
•
•
•
•
•
•
•
3.3 ns maximum propagation delay
3.3V power supply design
The DS90LV032A accepts low voltage (350 mV
typical) differential input signals and translates them
to 3V CMOS output levels. The receiver supports a
TRI-STATE® function that may be used to multiplex
outputs. The receiver also supports open, shorted
and terminated (100Ω) input Fail-safe. The receiver
output will be HIGH for all fail-safe conditions.
Power down high impedance on LVDS inputs
Low Power design (40mW @ 3.3V static)
Interoperable with existing 5V LVDS networks
Accepts small swing (350 mV typical) VID
Supports open, short and terminated input fail-
safe
The DS90LV032A and companion LVDS line driver
(eg. DS90LV031A) provide a new alternative to high
power PECL/ECL devices for high speed point-to-
point interface applications.
•
•
Compatible with ANSI/TIA/EIA-644
Industrial temp. operating range (-40°C to
+85°C)
•
Available in SOIC and TSSOP Packaging
Connection Diagram
Order Number DS90LV032ATM
or DS90LV032ATMTC
D-16 and PW-16 Packages
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
DS90LV032A
SNLS011C –JULY 1999–REVISED APRIL 2013
www.ti.com
Functional Diagram
Truth Table
ENABLES
INPUTS
OUTPUT
EN
EN*
RIN+ − RIN−
ROUT
L
H
X
Z
H
L
All other combinations of ENABLE inputs
V
ID ≥ 0.1V
V
ID ≤ −0.1V
Full Fail-safe OPEN/SHORT or
Terminated
H
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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(1)
Absolute Maximum Ratings
Supply Voltage (VCC
Input Voltage (RIN+, RIN−
Enable Input Voltage (EN, EN*)
Output Voltage (ROUT
)
−0.3V to +4V
−0.3V to +3.9V
)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
)
Maximum Package Power Dissipation @ +25°C
D Package
1025 mW
866 mW
PW Package
Derate D Package
8.2 mW/°C above +25°C
6.9 mW/°C above +25°C
−65°C to +150°C
Derate PW Package
Storage Temperature Range
Lead Temperature Range
(Soldering 4 sec.)
+260°C
+150°C
Maximum Junction Temperature
(2)
ESD Rating
(HBM 1.5 kΩ, 100 pF)
(EIAJ 0 Ω, 200 pF)
≥ 4.5 kV
≥ 250 V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) ESD Rating:
HBM (1.5 kΩ, 100 pF) ≥ 4.5 kV
EIAJ (0 Ω, 200 pF) ≥ 250 V
Recommended Operating Conditions
Min
+3.0
GND
Typ
Max
+3.6
+3.0
Units
Supply Voltage (VCC
)
+3.3
V
V
Receiver Input Voltage
Operating Free Air
Temperature (TA)
−40
25
+85
°C
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Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1)
Symbol
VTH
Parameter
Conditions
Pin
Min
Typ
+20
−20
Max
Units
mV
mV
V
Differential Input High Threshold
Differential Input Low Threshold
Common-Mode Voltage Range
Input Current
VCM = +1.2V(2)
RIN+
RIN−
,
+100
VTL
−100
0.1
(3)
VCMR
IIN
VID = 200 mV peak to peak
2.3
+10
+10
+20
VIN = +2.8V
VIN = 0V
VCC = 3.6V or 0V
−10
−10
-20
2.7
±1
±1
μA
μA
μA
V
VIN = +3.6V
VCC = 0V
VOH
Output High Voltage
IOH = −0.4 mA, VID = +200 mV
IOH = −0.4 mA, Input terminated
IOH = −0.4 mA, Input shorted
IOL = 2 mA, VID = −200 mV
ROUT
3.0
3.0
3.0
0.1
−48
±1
2.7
V
2.7
V
VOL
IOS
IOZ
VIH
VIL
II
Output Low Voltage
Output Short Circuit Current
Output TRI-STATE Current
Input High Voltage
0.25
−120
+10
VCC
0.8
V
(4)
Enabled, VOUT = 0V
−15
−10
2.0
mA
μA
V
Disabled, VOUT = 0V or VCC
EN,
EN*
Input Low Voltage
GND
−10
−1.5
V
Input Current
VIN = 0V or VCC, Other Input = VCC or GND
ICL = −18 mA
±1
−0.8
10
+10
μA
V
VCL
ICC
Input Clamp Voltage
No Load Supply Current
Receivers Enabled
EN, EN* = VCC or GND, Inputs Open
EN, EN* = 2.4V or 0.5V, Inputs Open
EN = GND, EN* = VCC, Inputs Open
VCC
15
15
5
mA
mA
mA
10
ICCZ
No Load Supply Current
Receivers Disabled
3
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
(2) VCC is always higher than RIN+ and RIN− voltage. RIN− and RIN+ are allowed to have a voltage range −0.2V to VCC − VID/2. However, to
be compliant with AC specifications, the common voltage range is 0.1V to 2.3V
(3) The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs
shorted is valid over a common-mode range of 0V to 2.3V. A VID up to VCC − 0V may be applied to the RIN+/ RIN− inputs with the
Common-Mode voltage set to VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to
400mV. Skew specifications apply for 200mV ≤ VID ≤ 800mV over the common-mode range .
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
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Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1) (2) (3) (4)
Symbol
tPHLD
tPLHD
tSKD1
tSKD2
tSKD3
tSKD4
tTLH
Parameter
Conditions
CL = 10 pF
Min
1.8
1.8
0
Typ
Max
3.3
3.3
0.35
0.5
1.0
1.5
1.2
1.2
12
Units
ns
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
VID = 200 mV
ns
(5)
Differential Pulse Skew |tPHLD − tPLHD
|
(Figure 1 and Figure 2)
0.1
0.1
ns
(3)
Differential Channel-to-Channel Skew-same device
0
ns
(4)
Differential Part to Part Skew
ns
(6)
Differential Part to Part Skew
ns
Rise Time
0.35
0.35
8
ns
tTHL
Fall Time
ns
tPHZ
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 2 kΩ
ns
tPLZ
CL = 10 pF
6
12
ns
tPZH
(Figure 3 and Figure 4)
11
17
ns
tPZL
11
17
ns
(7)
fMAX
Maximum Operating Frequency
All Channels Switching
200
250
MHz
(1) All typicals are given for: VCC = +3.3V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN
.
(3) tSKD2, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on
the same chip with any event on the inputs.
(4) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC, and within 5°C of each other within the operating temperature range.
(5) tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel
(6) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
(7) fMAX generator input conditions: tr = tf < 1ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output Criteria:
60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), Load = 10 pF (stray plus probes)
PARAMETER MEASUREMENT INFORMATION
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
CL includes load and test jig capacitance.
S1 = VCC for tPZL, and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
Figure 3. Receiver TRI-STATE Delay Test Circuit
Figure 4. Receiver TRI-STATE Delay Waveforms
TYPICAL APPLICATION
Balanced System
Figure 5. Point-to-Point Application
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APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the application notes
found at: http://www.ti.com/ww/en/analog/interface/lvds.shtml.
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the
drivers . The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90LV032A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V
common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.
The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting
may be the result of a ground potential difference between the driver's ground reference and the receiver's
ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input
pins have a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.
Power Decoupling Recommendations
Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF
in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the
printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes A
10µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit
board.
PC Board considerations
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on
the differential lines is much more likely to appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number of vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
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Termination
Use a resistor which best matches the differential impedance of your transmission line. The resistor should be
between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the
pair at the receiver end.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs should be minimized. The distance between the termination resistor and the receiver
should be <10mm (12mm MAX)
Probing LVDS Transmission Lines
Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by
the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤
10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive.
Fail-Safe Feature
The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.
1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output
to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or
power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω
termination resistor across the input pins. The unplugged cable can become a floating antenna which can
pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a
valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs
shorted and no external common-mode voltage applied.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.
The footprint of the DS90LV032A is the same as the industry standard 26LS32 Quad Differential (RS-422)
Receiver.
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PIN DESCRIPTIONS
Pin No.
2, 6,
10, 14
1, 7,
9, 15
3, 5,
11, 13
4
Name
Description
RIN+
Non-inverting receiver input pin
RIN−
Inverting receiver input pin
Receiver output pin
ROUT
EN
EN*
VCC
GND
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +3.3V ± 0.3V
Ground pin
12
16
8
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Typical Characteristics
Figure 6. ICC vs Frequency, four channels switching
Figure 7. Typical Common-Mode Range variation with
respect to amplitude of differential input
Figure 8. Typical Pulse Skew variation versus common-
mode voltage
Figure 9. Variation in High to Low Propagation Delay versus
VCM
Figure 10. Variation in Low to High Propagation Delay versus VCM
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SNLS011C –JULY 1999–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
DS90LV032ATM
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
SOIC
SOIC
D
16
16
16
16
16
16
16
16
48
TBD
Call TI
Call TI
Level-1-260C-UNLIM
Call TI
DS90LV032A
TM
DS90LV032ATM/NOPB
DS90LV032ATMTC
ACTIVE
NRND
D
48
92
Green (RoHS
& no Sb/Br)
CU SN
DS90LV032A
TM
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
TBD
Call TI
DS90LV
032AT
DS90LV032ATMTC/NOPB
DS90LV032ATMTCX
DS90LV032ATMTCX/NOPB
DS90LV032ATMX
ACTIVE
NRND
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Call TI
DS90LV
032AT
2500
2500
2500
2500
TBD
Call TI
DS90LV
032AT
ACTIVE
NRND
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Call TI
DS90LV
032AT
TBD
Call TI
DS90LV032A
TM
DS90LV032ATMX/NOPB
ACTIVE
SOIC
D
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
DS90LV032A
TM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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1-Nov-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV032ATMTCX
TSSOP
PW
PW
16
16
2500
2500
330.0
330.0
12.4
12.4
6.95
6.95
8.3
8.3
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
DS90LV032ATMTCX/NO TSSOP
PB
DS90LV032ATMX
SOIC
D
D
16
16
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
10.3
10.3
2.3
2.3
8.0
8.0
16.0
16.0
Q1
Q1
DS90LV032ATMX/NOPB SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90LV032ATMTCX
TSSOP
TSSOP
PW
PW
16
16
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
DS90LV032ATMTCX/NOP
B
DS90LV032ATMX
SOIC
SOIC
D
D
16
16
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
DS90LV032ATMX/NOPB
Pack Materials-Page 2
IMPORTANT NOTICE
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