DS90LV049QMT/NOPB [TI]
汽车类 LVDS 双路高速差动收发器 | PW | 16 | -40 to 125;
| 型号： | DS90LV049QMT/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 LVDS 双路高速差动收发器 | PW | 16 | -40 to 125 |
| 文件： | 总21页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV049Q
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SNLS300D –MAY 2008–REVISED APRIL 2013
DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair
Check for Samples: DS90LV049Q
1
FEATURES
DESCRIPTION
The DS90LV049Q is a dual CMOS flow-through
differential line driver-receiver pair designed for
applications requiring ultra low power dissipation,
exceptional noise immunity, and high data
throughput. The device is designed to support data
rates in excess of 400 Mbps utilizing Low Voltage
Differential Signaling (LVDS) technology.
2
•
•
•
•
•
AECQ-100 Grade 1
Up to 400 Mbps Switching Rates
Flow-Through Pinout Simplifies PCB Layout
50 ps Typical Driver Channel-to-Channel Skew
50 ps Typical Receiver Channel-to-Channel
Skew
The DS90LV049Q drivers accept LVTTL/LVCMOS
signals and translate them to LVDS signals. The
receivers accept LVDS signals and translate them to
3 V CMOS signals. The LVDS input buffers have
internal failsafe biasing that places the outputs to a
known H (high) state for floating receiver inputs. In
addition, the DS90LV049Q supports a TRI-STATE
function for a low idle power state when the device is
not in use.
•
•
•
•
•
3.3 V Single Power Supply Design
TRI-STATE Output Control
Internal Fail-Safe Biasing of Receiver Inputs
Low Power Dissipation (70 mW at 3.3 V Static)
High Impedance on LVDS Outputs on Power
Down
•
•
Conforms to TIA/EIA-644-A LVDS Standard
Available in Low Profile 16 Pin TSSOP
Package
The EN and EN inputs are ANDed together and
control the TRI-STATE outputs. The enables are
common to all four gates.
Connection Diagram
Functional Diagram
RIN1-
RIN1+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
RIN1-
ROUT1
ROUT2
GND
VDD
R1
R2
ROUT1
ROUT2
DIN2
RIN1+
RIN2+
RIN2-
RIN2+
RIN2-
DOUT2-
DOUT2+
DOUT1+
DOUT1-
DIN2
DIN1
EN
DOUT2-
DOUT2+
D2
D1
Figure 1. TSSOP Package
See Package Number PW0016A
DOUT1+
DOUT1-
DIN1
EN
EN
AND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS90LV049Q
SNLS300D –MAY 2008–REVISED APRIL 2013
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Truth Table
EN
L or Open
H
EN
L or Open
L or Open
H
LVDS Out
OFF
LVCMOS Out
OFF
ON
ON
L or Open
H
OFF
OFF
OFF
H
OFF
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VDD
LVCMOS Input Voltage (DIN
LVDS Input Voltage (RIN+, RIN-
)
−0.3 V to +4 V
−0.3 V to (VDD + 0.3 V)
−0.3 V to +3.9 V
−0.3 V to (VDD + 0.3 V)
−0.3 V to (VDD + 0.3 V)
−0.3 V to +3.9 V
100 mA
)
)
Enable Input Voltage (EN, EN)
LVCMOS Output Voltage (ROUT
)
LVDS Output Voltage (DOUT+, DOUT-
LVCMOS Output Short Circuit Current (ROUT
LVDS Output Short Circuit Current (DOUT+, DOUT−
)
)
)
24 mA
LVDS Output Short Circuit Current Duration (DOUT+, DOUT−
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
)
Continuous
−65°C to +150°C
+260°C
+135°C
Maximum Junction Temperature
Maximum Package Power Dissipation @ +25°C
PW0016A Package
1146 mW
Derate PW0016A Package
Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
10.4 mW/°C above +25°C
96.0°C/W
30.0°C/W
θJC
ESD Rating
(3)
HBM
≥ 8 kV
≥ 250 V
(4)
MM
(5)
CDM
≥ 1250 V
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
+3.0
−40
Typ
+3.3
+25
Max
+3.6
+125
Units
V
Supply Voltage (VDD
)
Operating Free Air Temperature (TA)
°C
2
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Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
(1)(2)(3)
Parameter
Test Conditions
Pin
Min
Typ
Max
Units
LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Clamp Voltage
2.0
GND
−10
VDD
0.8
V
V
DIN
EN
EN
VIN = VDD
1
+10
+10
μA
μA
V
IIL
VIN = GND
ICL = −18 mA
−10
−0.1
−0.6
VCL
−1.5
LVDS Output DC Specifications (Driver Outputs)
| VOD
|
Differential Output Voltage
250
350
1
450
35
mV
ΔVOD
Change in Magnitude of VOD for
Complementary Output States
|mV|
RL = 100 Ω
(Figure 2)
VOS
Offset Voltage
1.125
1.23
1
1.375
25
V
ΔVOS
Change in Magnitude of VOS for
Complementary Output States
|mV|
(4)
IOS
Output Short Circuit Current
ENABLED,
DIN = VDD, DOUT+ = 0 V or
DIN = GND, DOUT− = 0 V
−5.8
−9.0
mA
DOUT−
DOUT+
IOSD
IOFF
IOZ
Differential Output Short Circuit
Current
−5.8
±1
−9.0
+20
+10
mA
μA
μA
ENABLED, VOD = 0 V
(4)
Power-off Leakage
VOUT = 0 V or 3.6 V
VDD = 0 V or Open
−20
−10
Output TRI-STATE Current
EN = 0 V and EN = VDD
VOUT = 0 V or VDD
±1
LVDS Input DC Specifications (Receiver Inputs)
VTH
Differential Input High Threshold
Differential Input Low Threshold
Common-Mode Voltage Range
−15
−15
35
mV
mV
V
VCM = 1.2 V, 0.05 V, 2.35 V
VID = 100 mV, VDD=3.3 V
VTL
-100
0.05
VCMR
3
RIN+
RIN-
VDD=3.6 V
VIN =0 V or 2.8 V
−12
−10
±4
±1
+12
μA
μA
IIN
Input Current
VDD=0 V
VIN =0 V or 2.8 V or 3.6 V
+10
LVCMOS Output DC Specifications (Receiver Outputs)
VOH
VOL
IOZ
Output High Voltage
IOH = -0.4 mA, VID= 200 mV
IOL = 2 mA, VID = 200 mV
Disabled, VOUT =0 V or VDD
2.7
-10
3.3
0.05
±1
V
V
Output Low Voltage
ROUT
0.25
+10
Output TRI-STATE Current
μA
General DC Specifications
(5)
IDD
Power Supply Current
EN = 3.3 V
EN = 0 V
21
15
35
25
mA
mA
VDD
IDDZ
TRI-State Supply Current
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VTH, VTL, VOD and ΔVOD
.
(2) All typical values are given for: VDD = +3.3 V, TA = +25°C.
(3) The DS90LV049Q drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to
their outputs. The typical range of the resistor values is 90 Ω to 110 Ω.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
(5) Both driver and receiver inputs are static. All LVDS outputs have 100 Ω load. All LVCMOS outputs are floating. None of the outputs
have any lumped capacitive load.
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Units
Switching Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
(1)(2)
Parameter
LVDS Outputs (Driver Outputs)
Test Conditions
Min
Typ
Max
tPHLD
tPLHD
tSKD1
tSKD2
tSKD3
tTLH
Differential Propagation Delay High to Low
0.7
0.7
2
2
ns
ns
Differential Propagation Delay Low to High
(3) (4)
Differential Pulse Skew |tPHLD − tPLHD
|
0
0
0.05
0.05
0.4
0.5
1.0
1
ns
RL = 100 Ω
(Figure 3 and Figure 4)
(3) (5)
Differential Channel-to-Channel Skew
ns
(3) (6)
Differential Part-to-Part Skew
0
ns
(3)
Rise Time
0.2
0.2
0.4
0.4
1.5
1.5
3
ns
(3)
tTHL
Fall Time
1
ns
tPHZ
tPLZ
tPZH
tPZL
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
3
ns
3
ns
RL = 100 Ω
(Figure 5 and Figure 6)
1
1
6
ns
3
6
ns
(7)
fMAX
Maximum Operating Frequency
250
MHz
LVCMOS Outputs (Receiver Outputs)
tPHL
tPLH
tSK1
tSK2
tSK3
tTLH
tTHL
tPHZ
tPLZ
tPZH
tPZL
fMAX
Propagation Delay High to Low
0.5
0.5
0
2
3.5
3.5
0.4
0.5
1.0
1.4
1.4
8
ns
ns
Propagation Delay Low to High
2
(8)
Pulse Skew |tPHL − tPLH
|
0.05
0.05
ns
(9)
Channel-to-Channel Skew
(Figure 7 and Figure 8)
0
ns
(10)
Part-to-Part Skew
0
ns
Rise Time(3)
Fall Time(3)
0.3
0.3
3
0.9
0.75
5.6
ns
ns
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
ns
3
5.4
8
ns
(Figure 9 and Figure 10)
2.5
2.5
4.6
7
ns
4.6
7
ns
(11)
Maximum Operating Frequency
250
MHz
(1) All typical values are given for: VDD = +3.3 V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
(3) These parameters are ensured by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage, temperature) ranges.
(4) tSKD1 or differential pulse skew is defined as |tPHLD − tPLHD|. It is the magnitude difference in the differential propagation delays between
the positive going edge and the negative going edge of the same driver channel.
(5) tSKD2 or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two
driver channels on the same device.
(6) tSKD3 or differential part-to-part skew is defined as |tPLHD Max − tPLHD Min| or |tPHLD Max − tPHLD Min|. It is the difference between the
minimum and maximum specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of
each other within the operating temperature range.
(7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, VOD
250 mV, all channels switching.
>
(8) tSK1 or pulse skew is defined as |tPHL − tPLH|. It is the magnitude difference in the propagation delays between the positive going edge
and the negative going edge of the same receiver channel.
(9) tSK2 or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the
same device.
(10) tSK3 or part-to-part skew is defined as |tPLH Max − tPLH Min| or |tPHL Max − tPHL Min|. It is the difference between the minimum and maximum
specified propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating
temperature range.
(11) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V . Output Criteria: duty cycle =
45%/55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching.
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Parameter Measurement Information
Power
Supply
VDD
EN
DOUT+
SMU
SMU
DIN
SMU
100 W
D
DOUT-
Figure 2. Driver VOD and VOS Test Circuit
Power
Supply
Oscilloscope
VDD
EN
Z0 = 50 W
DOUT+
C = 15 pF Distributed
Transmission Line
Transmission Line
DC Block
DIN
Signal
Generator
Transmission Line
100 W
50 W
50 W
D
DC Block
DOUT-
50 W
Z0 = 50 W
C = 15 pF Distributed
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
Figure 4. Driver Propagation Delay and Transition Time Waveforms
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Parameter Measurement Information (continued)
2.4 V
3.3 V
2.4 V
Oscilloscope
VDD
1 kW
100 W
1 kW
950 W
950 W
DOUT+
Transmission Line
Transmission Line
DIN
50 W
50 W
D
DOUT-
Z0 = 50 W
C = 15 pF Distributed
EN
Z0 = 50 W
C = 15 pF Distributed
50 W
Signal
Generator
Transmission Line
Figure 5. Driver TRI-STATE Delay Test Circuit
Figure 6. Driver TRI-STATE Delay Waveform
Power
Supply
Z0 = 50 W
Oscilloscope
VDD
C = 15 pF Distributed
RIN+
100 W
RIN-
Transmission Line
ROUT
Signal
Generator
Transmission Line
R
Transmission Line
950 W
50 W
Z0 = 50 W
C = 15 pF Distributed
EN
Power
Supply
Figure 7. Receiver Propagation Delay and Transition Time Test Circuit
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Parameter Measurement Information (continued)
Figure 8. Receiver Propagation Delay and Transition Time Waveforms
Power Supplies
1 kW
VDD
Oscilloscope
2.5 V
1.4 V
1.0 V
RIN+
100 W
RIN-
ROUT
950 W
Transmission Line
R
50 W
Z0 = 50 W
C = 15 pF Distributed
EN
Z0 = 50 W
50 W
C = 15 pF Distributed
Signal
Generator
Transmission Line
Figure 9. Receiver TRI-STATE Delay Test Circuit
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Parameter Measurement Information (continued)
EN
3 V
1.5 V
1.5 V
0 V
3 V
1.5 V
1.5 V
EN
0 V
VOH
tPHZ
tPZH
OUT
0.5 V
50%
50%
VDD / 2
VDD / 2
tPZL
tPLZ
0.5 V
OUT
VOL
Figure 10. Receiver TRI-STATE Delay Waveforms
Typical Application
Figure 11. Point-to-Point Application
APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes: LVDS Owner's Manual (lit #550062-003), AN-805 (SNOA233), AN-808 (SNLA028), AN-903 (SNLA034),
AN-916 (SNLA219, AN-971(SNLA165), AN-977 (SNLA166).
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 11. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is located as close to
the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into
a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be taken into account.
The TRI-STATE function allows the device outputs to be disabled, thus obtaining an even lower power state
when the transmission of data is not required.
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The DS90LV049Q has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1 μF and 0.001 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple
vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or greater solid
tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply
and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (that is,
cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they
leave the IC (stubs should be < 10 mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than
traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
TERMINATION
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs should be minimized. The distance between the termination resistor and the receiver
should be < 10 mm (12 mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
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CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100 Ω. They should not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple
coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling
effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is
rejected by the receiver.
FAIL-SAFE FEATURE
An LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating receiver inputs.
The DS90LV049Q has two receivers, and if an application requires a single receiver, the unused receiver inputs
should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by
internal high value pull up and pull down current sources to set the output to a HIGH state. This internal circuitry
will ensure a HIGH, stable output state for open inputs.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pull up and pull down resistors should be in the 5 kΩ to 15 kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
For more information on failsafe biasing of LVDS interfaces, please refer to AN-1194 (SNLA051).
PIN DESCRIPTIONS
Pin No.
10, 11
6, 7
Name
DIN
Description
Driver input pins, LVCMOS levels. There is a pull-down current source present.
Non-inverting driver output pins, LVDS levels.
DOUT+
DOUT−
RIN+
5, 8
Inverting driver output pins, LVDS levels.
2, 3
Non-inverting receiver input pins, LVDS levels. There is a pull-up current source present.
Inverting receiver input pins, LVDS levels. There is a pull-down current source present.
Receiver output pins, LVCMOS levels.
1, 4
RIN-
14, 15
9, 16
12
ROUT
EN, EN
VDD
Enable and Disable pins. There are pull-down current sources present at both pins.
Power supply pin.
13
GND
Ground pin.
10
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Typical Performance Curves
Differential Output Voltage
Power Supply Current
vs
vs
Load Resistor
Frequency
90
75
60
45
30
15
0
0.45
VDD = 3.3 V
All
Switching
TA = 25o C
RL = 100 W
CL = 15 pF
VID = 0.4 V
VIN = 3.3 V
VDD = 3.3 V
TA = 25o C
0.40
0.35
0.30
0.25
Single
Receiver
Switching
Single
Driver
Switching
0.1
1
10
100
1000
40
60
80
100
120
140
160
Resistor Load - RL [W]
Frequency - f [MHz]
Figure 12.
Figure 13.
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SNLS300D –MAY 2008–REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90LV049QMT/NOPB
DS90LV049QMTX/NOPB
ACTIVE
TSSOP
TSSOP
PW
16
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
90LV049
QMT
ACTIVE
PW
2500 RoHS & Green
SN
90LV049
QMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV049QMTX/NOPB TSSOP
PW
16
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DS90LV049QMTX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90LV049QMT/NOPB
16
92
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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