DS90LV049TMT/NOPB [TI]

暂无描述;


型号：	DS90LV049TMT/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	暂无描述驱动器
文件：	总14页 (文件大小：288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS90LV049Q

DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair

Literature Number: SNLS300C

December 1, 2008

DS90LV049Q

Automotive LVDS Dual Line Driver and Receiver Pair

General Description

Features

The DS90LV049Q is a dual CMOS flow-through differential

line driver-receiver pair designed for applications requiring ul-

tra low power dissipation, exceptional noise immunity, and

high data throughput. The device is designed to support data

rates in excess of 400 Mbps utilizing Low Voltage Differential

Signaling (LVDS) technology.

AECQ-100 Grade 1

■

Up to 400 Mbps switching rates

Flow-through pinout simplifies PCB layout

50 ps typical driver channel-to-channel skew

50 ps typical receiver channel-to-channel skew

3.3 V single power supply design

The DS90LV049Q drivers accept LVTTL/LVCMOS signals

and translate them to LVDS signals. The receivers accept

LVDS signals and translate them to 3 V CMOS signals. The

LVDS input buffers have internal failsafe biasing that places

the outputs to a known H (high) state for floating receiver in-

puts. In addition, the DS90LV049Q supports a TRI-STATE

function for a low idle power state when the device is not in

use.

TRI-STATE output control

Internal fail-safe biasing of receiver inputs

Low power dissipation (70 mW at 3.3 V static)

■

High impedance on LVDS outputs on power down

Conforms to TIA/EIA-644-A LVDS Standard

Available in low profile 16 pin TSSOP package

■

The EN and EN inputs are ANDed together and control the

TRI-STATE outputs. The enables are common to all four

gates.

Connection Diagram

Functional Diagram

Dual-In-Line

30064201

Order Number DS90LV049QMT

Order Number DS90LV049QMTX (Tape and Reel)

See NS Package Number MTC16

30064202

Truth Table

L or Open

LVDS Out

OFF

LVCMOS Out

OFF

L or Open

OFF

300642

www.national.com

Maximum Package Power Dissipation @ +25°C

MT Package

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

1146 mW

Derate MT Package

10.4 mW/°C above +25°C

Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)

ꢀθ_JA

96.0°C/W

30.0°C/W

Supply Voltage (V_DD

)

−0.3 V to +4 V

−0.3 V to (V_DD+ 0.3 V)

ꢀθ_JC

ESD Rating

HBM (Note 1)

LVCMOS Input Voltage (D_IN)

LVDS Input Voltage (R_IN+, R_IN-

)

−0.3 V to +3.9 V

−0.3 V to (V_DD+ 0.3 V)

≥ 8 kV

≥ 250 V

≥ 1250 V

Enable Input Voltage (EN, EN)

LVCMOS Output Voltage (R_OUT

LVDS Output Voltage

MM (Note 2)

)

CDM (Note 3)

(D_OUT+, D_OUT-

LVCMOS Output Short Circuit

Current (R_OUT

LVDS Output Short Circuit

Current (D_OUT+, D_OUT−

)

−0.3 V to +3.9 V

100 mA

Note 1: Human Body Model, applicable std. JESD22-A114C

Note 2: Machine Model, applicable std. JESD22-A115-A

)

Note 3: Field Induced Charge Device Model, applicable std.

JESD22-C101-C

)

24 mA

Recommended Operating

Conditions

LVDS Output Short Circuit

Current Duration(D_OUT+, D_OUT−

Storage Temperature Range

Lead Temperature Range

Soldering (4 sec.)

)

Continuous

−65°C to +150°C

Min

+3.0

Typ

+3.3

Max

+3.6

Units

Supply Voltage (V_DD

Operating Free Air

Temperature (T_A)

)

+260°C

+135°C

Maximum Junction Temperature

−40

+25

+125

°C

Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 5, 7, 9)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)

V_IH

V_IL

I_IH

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

Input Clamp Voltage

2.0

GND

−10

V_DD

0.8

D_IN

V_IN= V_DD

+10

μA

I_IL

V_IN= GND

I_CL= −18 mA

−10

−0.1

−0.6

V_CL

−1.5

LVDS Output DC Specifications (Driver Outputs)

| V_OD

Differential Output Voltage

250

350

450

Change in Magnitude of V_ODfor

Complementary Output States

Offset Voltage

|mV|

ΔV_OD

R_L= 100 Ω

(Figure 1)

V_OS

1.125

1.23

1.375

Change in Magnitude of V_OSfor

Complementary Output States

|mV|

ΔV_OS

D_OUT−

D_OUT+

I_OS

Output Short Circuit Current (Note

17)

ENABLED,

D_IN= V_DD, D_OUT+= 0 V or

D_IN= GND, D_OUT−= 0 V

−5.8

−9.0

I_OSD

I_OFF

Differential Output Short Circuit

Current (Note 17)

−5.8

±1

−9.0

+20

μA

ENABLED, V_OD= 0 V

Power-off Leakage

V_OUT= 0 V or 3.6 V

V_DD= 0 V or Open

−20

−10

I_OZ

Output TRI-STATE Current

EN = 0 V and EN = V_DD

V_OUT= 0 V or V_DD

±1

+10

www.national.com

Symbol

Parameter

Conditions

V_CM= 1.2 V, 0.05 V, 2.35 V

V_ID= 100 mV, V_DD=3.3 V

Min

Typ

Max

Units

LVDS Input DC Specifications (Receiver Inputs)

V_TH

V_TL

V_CMR

I_IN

Differential Input High Threshold

Differential Input Low Threshold

Common-Mode Voltage Range

Input Current

−15

-100

0.05

−12

R_IN+

V_DD=3.6 V

±4

±1

+12

μA

R_IN-

V_IN=0 V or 2.8 V

V_DD=0 V

−10

+10

μA

V_IN=0 V or 2.8 V or 3.6 V

LVCMOS Output DC Specifications (Receiver Outputs)

V_OH

V_OL

I_OZ

Output High Voltage

I_OH= -0.4 mA, V_ID= 200 mV

I_OL= 2 mA, V_ID= 200 mV

Disabled, V_OUT=0 V or V_DD

2.7

-10

3.3

0.05

±1

Output Low Voltage

R_OUT

0.25

+10

Output TRI-STATE Current

μA

General DC Specifications

I_DD

Power Supply Current (Note 6)

TRI-State Supply Current

EN = 3.3 V

EN = 0 V

V_DD

I_DDZ

Switching Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 7, 16)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS Outputs (Driver Outputs)

t_PHLD

t_PLHD

t_SKD1

Differential Propagation Delay High to Low

Differential Propagation Delay Low to High

0.7

Differential Pulse Skew |t_PHLD− t_PLHD

(Notes 8, 10)

0.05

0.4

0.5

R_L= 100 Ω

(Figure 2 and Figure 3)

t_SKD2

Differential Channel-to-Channel Skew

(Notes 8, 11)

t_SKD3

t_TLH

t_THL

t_PHZ

t_PLZ

t_PZH

t_PZL

f_MAX

Differential Part-to-Part Skew (Notes 8, 12)

Rise Time (Note 8)

1.0

0.2

0.4

1.5

Fall Time (Note 8)

Disable Time High to Z

Disable Time Low to Z

R_L= 100 Ω

(Figure 4 and Figure 5)

Enable Time Z to High

Enable Time Z to Low

Maximum Operating Frequency (Note 19)

250

MHz

LVCMOS Outputs (Receiver Outputs)

t_PHL

t_PLH

t_SK1

t_SK2

t_SK3

t_TLH

t_THL

t_PHZ

t_PLZ

t_PZH

t_PZL

f_MAX

Propagation Delay High to Low

Propagation Delay Low to High

Pulse Skew |t_PHL− t_PLH| (Note 13)

Channel-to-Channel Skew (Note 14)

Part-to-Part Skew (Note 15)

Rise Time(Note 8)

0.5

3.5

0.4

0.5

1.0

1.4

0.05

(Figure 6 and Figure 7)

0.3

0.9

0.75

5.6

Fall Time(Note 8)

Disable Time High to Z

Disable Time Low to Z

5.4

(Figure 8 and Figure 9)

Enable Time Z to High

2.5

4.6

Enable Time Z to Low

4.6

Maximum Operating Frequency (Note 20)

250

MHz

Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

www.national.com

Note 5: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V_TH, V_TL

V_ODand ΔV_OD

Note 6: Both, driver and receiver inputs are static. All LVDS outputs have 100 Ω load. All LVCMOS outputs are floating. None of the outputs have any lumped

capacitive load.

Note 7: All typical values are given for: V_DD= +3.3 V, T_A= +25°C.

Note 8: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,

temperature) ranges.

Note 9: The DS90LV049Q drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs.

The typical range of the resistor values is 90 Ω to 110 Ω.

Note 10: t_SKD1or differential pulse skew is defined as |t_PHLD− t_PLHD|. It is the magnitude difference in the differential propagation delays between the positive

going edge and the negative going edge of the same driver channel.

Note 11: t_SKD2or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two driver channels

on the same device.

Note 12: t_SKD3or differential part-to-part skew is defined as |t_{PLHD Max}− t_{PLHD Min}| or |t_{PHLD Max}− t_{PHLD Min}|. It is the difference between the minimum and maximum

specified differential propagation delays. This specification applies to devices at the same V_DDand within 5°C of each other within the operating temperature

range.

Note 13: t_SK1or pulse skew is defined as |t_PHL− t_PLH|. It is the magnitude difference in the propagation delays between the positive going edge and the negative

going edge of the same receiver channel.

Note 14: t_SK2or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the same device.

Note 15: t_SK3or part-to-part skew is defined as |t_{PLH Max}− t_{PLH Min}| or |t_{PHL Max}− t_{PHL Min}|. It is the difference between the minimum and maximum specified

propagation delays. This specification applies to devices at the same V_DDand within 5°C of each other within the operating temperature range.

Note 16: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O= 50 Ω, t_r≤ 1 ns, and t_f≤ 1 ns.

Note 17: Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only.

Note 18: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.

Note 19: f_MAXgenerator input conditions: t_r= t_f< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, V_OD> 250 mV, all channels

switching.

Note 20: f_MAXgenerator input conditions: t_r= t_f< 1 ns (0% to 100%), 50% duty cycle, V_ID= 200 mV, V_CM= 1.2 V . Output Criteria: duty cycle = 45%/55%, V_OH

2.7 V, V_OL< 0.25 V, all channels switching.

Parameter Measurement Information

30064203

FIGURE 1. Driver V_ODand V_OSTest Circuit

30064204

FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit

www.national.com

30064205

FIGURE 3. Driver Propagation Delay and Transition Time Waveforms

30064206

FIGURE 4. Driver TRI-STATE Delay Test Circuit

www.national.com

30064207

FIGURE 5. Driver TRI-STATE Delay Waveform

30064209

FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit

30064210

FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms

www.national.com

30064211

FIGURE 8. Receiver TRI-STATE Delay Test Circuit

30064214

FIGURE 9. Receiver TRI-STATE Delay Waveforms

Typical Application

30064208

FIGURE 10. Point-to-Point Application

www.national.com

field cancellation is much better with the closer traces. In ad-

dition, noise induced on the differential lines is much more

likely to appear as common-mode which is rejected by the

receiver.

Applications Information

General application guidelines and hints for LVDS drivers and

receivers may be found in the following application notes:

LVDS Owner's Manual (lit #550062-003), AN-805, AN-808,

AN-903, AN-916, AN-971, AN-977.

Match electrical lengths between traces to reduce skew.

Skew between the signals of a pair means a phase difference

between signals which destroys the magnetic field cancella-

tion benefits of differential signals and EMI will result. (Note

the velocity of propagation, v = c/Er where c (the speed of

light) = 0.2997 mm/ps or 0.0118 in/ps). Do not rely solely on

the autoroute function for differential traces. Carefully review

dimensions to match differential impedance and provide iso-

lation for the differential lines. Minimize the number or vias

and other discontinuities on the line.

LVDS drivers and receivers are intended to be primarily used

in an uncomplicated point-to-point configuration as is shown

in Figure 10. This configuration provides a clean signaling

environment for the fast edge rates of the drivers. The receiv-

er is connected to the driver through a balanced media which

may be a standard twisted pair cable, a parallel pair cable, or

simply PCB traces. Typically, the characteristic differential

impedance of the media is in the range of 100 Ω. A termination

resistor of 100 Ω (selected to match the media), and is located

as close to the receiver input pins as possible. The termination

resistor converts the driver output current (current mode) into

a voltage that is detected by the receiver. Other configurations

are possible such as a multi-receiver configuration, but the

effects of a mid-stream connector(s), cable stub(s), and other

impedance discontinuities as well as ground shifting, noise

margin limits, and total termination loading must be taken into

account.

Avoid 90° turns (these cause impedance discontinuities). Use

arcs or 45° bevels.

Within a pair of traces, the distance between the two traces

should be minimized to maintain common-mode rejection of

the receivers. On the printed circuit board, this distance

should remain constant to avoid discontinuities in differential

impedance. Minor violations at connection points are allow-

able.

The TRI-STATE function allows the device outputs to be dis-

abled, thus obtaining an even lower power state when the

transmission of data is not required.

TERMINATION

Use a termination resistor which best matches the differential

impedance or your transmission line. The resistor should be

between 90 Ω and 130 Ω. Remember that the current mode

outputs need the termination resistor to generate the differ-

ential voltage. LVDS will not work without resistor termination.

Typically, connecting a single resistor across the pair at the

receiver end will suffice.

The DS90LV049Q has a flow-through pinout that allows for

easy PCB layout. The LVDS signals on one side of the device

easily allows for matching electrical lengths of the differential

pair trace lines between the driver and the receiver as well as

allowing the trace lines to be close together to couple noise

as common-mode. Noise isolation is achieved with the LVDS

signals on one side of the device and the TTL signals on the

other side.

Surface mount 1% to 2% resistors are best. PCB stubs, com-

ponent lead, and the distance from the termination to the

receiver inputs should be minimized. The distance between

the termination resistor and the receiver should be < 10 mm

(12 mm MAX).

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high fre-

quency ceramic (surface mount is recommended) 0.1 μF and

0.001 μF capacitors in parallel at the power supply pin with

the smallest value capacitor closest to the device supply pin.

Additional scattered capacitors over the printed circuit board

will improve decoupling. Multiple vias should be used to con-

nect the decoupling capacitors to the power planes. A 10 μF

(35 V) or greater solid tantalum capacitor should be connect-

ed at the power entry point on the printed circuit board be-

tween the supply and ground.

PROBING LVDS TRANSMISSION LINES

Always use high impedance (> 100 kΩ), low capacitance

(< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.

Improper probing will give deceiving results.

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is important

to remember:

Use controlled impedance media. The cables and connectors

you use should have a matched differential impedance of

about 100 Ω. They should not introduce major impedance

discontinuities.

PC BOARD CONSIDERATIONS

Use at least 4 PCB layers (top to bottom); LVDS signals,

ground, power, TTL signals.

Balanced cables (e.g. twisted pair) are usually better than

unbalanced cables (ribbon cable, simple coax.) for noise re-

duction and signal quality. Balanced cables tend to generate

less EMI due to field canceling effects and also tend to pick

up electromagnetic radiation a common-mode (not differential

mode) noise which is rejected by the receiver.

Isolate TTL signals from LVDS signals, otherwise the TTL

may couple onto the LVDS lines. It is best to put TTL and

LVDS signals on different layers which are isolated by a pow-

er/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side)

connectors as possible.

FAIL-SAFE FEATURE

DIFFERENTIAL TRACES

An LVDS receiver is a high gain, high speed device that am-

plifies a small differential signal (20 mV) to CMOS logic levels.

Due to the high gain and tight threshold of the receiver, care

should be taken to prevent noise from appearing as a valid

signal.

Use controlled impedance traces which match the differential

impedance of your transmission medium (i.e. cable) and ter-

mination resistor. Run the differential pair trace lines as close

together as possible as soon as they leave the IC (stubs

should be < 10 mm long). This will help eliminate reflections

and ensure noise is coupled as common-mode. In fact, we

have seen that differential signals which are 1 mm apart ra-

diate far less noise than traces 3 mm apart since magnetic

The receiver's internal fail-safe circuitry is designed to source/

sink a small amount of current, providing fail-safe protection

(a stable known state of HIGH output voltage) for floating re-

ceiver inputs.

www.national.com

The DS90LV049Q has two receivers, and if an application

requires a single receiver, the unused receiver inputs should

be left OPEN. Do not tie unused receiver inputs to ground or

any other voltages. The input is biased by internal high value

pull up and pull down current sources to set the output to a

HIGH state. This internal circuitry will guarantee a HIGH, sta-

ble output state for open inputs.

of higher noise levels. The pull up and pull down resistors

should be in the 5 kΩ to 15 kΩ range to minimize loading and

waveform distortion to the driver. The common-mode bias

point should be set to approximately 1.2 V (less than 1.75 V)

to be compatible with the internal circuitry.

For more information on failsfe biasing of LVDS interfaces

please refer to AN-1194.

External lower value pull up and pull down resistors (for a

stronger bias) may be used to boost fail-safe in the presence

Pin Descriptions

Pin No.

Name

Description

Driver input pins, LVCMOS levels. There is a pull-down current source

present.

D_IN

10, 11

D_OUT+

D_OUT−

6, 7

5, 8

Non-inverting driver output pins, LVDS levels.

Inverting driver output pins, LVDS levels.

Non-inverting receiver input pins, LVDS levels. There is a pull-up current

source present.

R_IN+

2, 3

Inverting receiver input pins, LVDS levels. There is a pull-down current

source present.

R_IN-

R_OUT

1, 4

14, 15

9, 16

Receiver output pins, LVCMOS levels.

Enable and Disable pins. There are pull-down current sources present

at both pins.

EN, EN

V_DD

Power supply pin.

Ground pin.

GND

Typical Performance Curves

Differential Output Voltage

vs Load Resistor

Power Supply Current

vs Frequency

30064221

30064219

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead (0.100″ Wide) Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90LV049QMT

Order Number DS90LV049QMTX (Tape and Reel)

NS Package Number MTC16

www.national.com

Notes

www.national.com

Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products

www.national.com/amplifiers

Design Support

Amplifiers

WEBENCH® Tools

App Notes

www.national.com/webench

www.national.com/appnotes

www.national.com/refdesigns

www.national.com/samples

www.national.com/evalboards

www.national.com/packaging

www.national.com/quality/green

www.national.com/contacts

Audio

www.national.com/audio

www.national.com/timing

www.national.com/adc

www.national.com/interface

www.national.com/lvds

www.national.com/power

www.national.com/switchers

www.national.com/ldo

Clock and Timing

Data Converters

Interface

Reference Designs

Samples

Eval Boards

LVDS

Packaging

Power Management

Switching Regulators

LDOs

Green Compliance

Distributors

Quality and Reliability www.national.com/quality

LED Lighting

Voltage Reference

PowerWise® Solutions

www.national.com/led

Feedback/Support

Design Made Easy

Solutions

www.national.com/feedback

www.national.com/easy

www.national.com/vref

www.national.com/powerwise

www.national.com/solutions

www.national.com/milaero

www.national.com/solarmagic

www.national.com/AU

Serial Digital Interface (SDI) www.national.com/sdi

Mil/Aero

Temperature Sensors

Wireless (PLL/VCO)

www.national.com/tempsensors Solar Magic®

www.national.com/wireless

Analog University®

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Technical

Support Center

Email: support@nsc.com

Tel: 1-800-272-9959

National Semiconductor Europe

Technical Support Center

Email: europe.support@nsc.com

German Tel: +49 (0) 180 5010 771

English Tel: +44 (0) 870 850 4288

National Semiconductor Asia

Pacific Technical Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Technical Support Center

Email: jpn.feedback@nsc.com

www.national.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Medical

Security

Logic

Space, Avionics and Defense www.ti.com/space-avionics-defense

Transportation and Automotive www.ti.com/automotive

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DS90LV049TMT/NOPB [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E