DS90LV110ATMTX/NOPB [TI]
具有失效防护的 1:10 LVDS 数据/时钟分配器 | PW | 28 | -40 to 85;
| 型号： | DS90LV110ATMTX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有失效防护的 1:10 LVDS 数据/时钟分配器 | PW | 28 | -40 to 85 时钟 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总18页 (文件大小：739K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV110AT
www.ti.com
SNOSAC2J –AUGUST 2004–REVISED APRIL 2013
DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe
Check for Samples: DS90LV110AT
1
FEATURES
DESCRIPTION
DS90LV110A is a 1 to 10 data/clock distributor
utilizing LVDS (Low Voltage Differential Signaling)
technology for low power, high speed operation. Data
paths are fully differential from input to output for low
noise generation and low pulse width distortion. The
design allows connection of 1 input to all 10 outputs.
LVDS I/O enable high speed data transmission for
point-to-point interconnects. This device can be used
as a high speed differential 1 to 10 signal distribution
/ fanout replacing multi-drop bus applications for
higher speed links with improved signal quality. It can
also be used for clock distribution up to 200MHz.
2
•
•
Low jitter 400 Mbps fully differential data path
145 ps (typ) of pk-pk jitter with PRBS = 223−1
data pattern at 400 Mbps
•
•
•
•
Single +3.3 V Supply
Balanced output impedance
Output channel-to-channel skew is 35ps (typ)
Differential output voltage (VOD) is 320mV (typ)
with 100Ω termination load.
•
•
•
•
LVDS receiver inputs accept LVPECL signals
LVDS input failsafe
The DS90LV110A accepts LVDS signal levels,
LVPECL levels directly or PECL with attenuation
networks.
Fast propagation delay of 2.8 ns (typ)
Receiver open, shorted, and terminated input
failsafe
The LVDS outputs can be put into TRI-STATE by use
of the enable pin.
•
•
28 lead TSSOP package
Conforms to ANSI/TIA/EIA-644 LVDS standard
For more details, please refer to the APPLICATION
INFORMATION section of this datasheet.
Connection Diagram
Order Number DS90LV110ATMT
PW0028A Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
DS90LV110AT
SNOSAC2J –AUGUST 2004–REVISED APRIL 2013
www.ti.com
Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VDD-VSS
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to +4V
−0.3V to +4V
+150°C
LVCMOS/LVTTL Input Voltage (EN)
LVDS Receiver Input Voltage (IN+, IN−)
LVDS Driver Output Voltage (OUT+, OUT−)
Junction Temperature
Storage Temperature Range
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 sec.)
Maximum Package Power
Dissipation at 25°C
28 Lead TSSOP
2.115 W
Package Derating
28 Lead TSSOP
28 Lead TSSOP
16.9 mW/°C above +25°C
59.1 °C/W
θJA
(4-Layer, 2 oz. Cu, JEDEC)
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
> 8 kV
ESD Rating:
> 250 V
(1) “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be verified. They are not meant to imply that the
device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
Units
V
Supply Voltage (VDD - VSS
)
3.3
Receiver Input Voltage
VDD
+85
V
Operating Free Air Temperature
-40
+25
°C
2
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SNOSAC2J –AUGUST 2004–REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
LVCMOS/LVTTL DC SPECIFICATIONS (EN)
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Clamp Voltage
2.0
VDD
0.8
V
V
VSS
VIN = 3.6V or 2.0V; VDD = 3.6V
VIN = 0V or 0.8V; VDD = 3.6V
ICL = −18 mA
±7
±7
±20
±20
−1.5
μA
μA
V
IIL
VCL
−0.8
LVDS OUTPUT DC SPECIFICATIONS (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10)
VOD
Differential Output Voltage
RL = 100Ω
250
260
320
320
450
425
35
mV
mV
|mV|
V
RL = 100Ω, VDD = 3.3V, TA = 25°C
ΔVOD
VOS
Change in VOD between Complimentary Output States
(2)
Offset Voltage
1.125
1.25
1.375
35
ΔVOS
IOZ
Change in VOS between Complimentary Output States
|mV|
Output TRI-STATE Current
EN = 0V,
VOUT = VDD or GND
±1
±10
μA
IOFF
Power-Off Leakage Current
Output Short Circuit Current
VDD = 0V; VOUT = 3.6V or GND
VOUT+ OR VOUT− = 0V or VDD
VOUT+ = VOUT−
±1
12
6
±10
24
μA
ISA,ISB
ISAB
|mA|
|mA|
(3)
Both Outputs Shorted
12
LVDS RECEIVER DC SPECIFICATIONS (IN)
VTH
VTL
VCMR
IIN
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
Input Current
VCM = +0.05V or +1.2V or +3.25V,
VDD = 3.3V
0
0
+100
mV
mV
V
−100
VID = 100mV, VDD = 3.3V
VIN = +3.0V, VDD = 3.6V or 0V
VIN = 0V, VDD = 3.6V or 0V
0.05
3.25
±10
±10
±1
±1
μA
μA
SUPPLY CURRENT
ICCD Total Supply Current
RL = 100Ω, CL = 5 pF, 200 MHz,
125
160
mA
EN = High
No Load, 200 MHz, EN = High
EN = Low
80
15
125
29
mA
mA
ICCZ
TRI-STATE Supply Current
(1) All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
(2) VOS is defined as (VOH + VOL) / 2.
(3) Only one output can be shorted at a time. Don't exceed the package absolute maximum rating.
Copyright © 2004–2013, Texas Instruments Incorporated
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
TLHT
Parameter
Conditions
Min
Typ
390
390
145
Max
550
550
Units
ps
(1)
(1)
Output Low-to-High Transition Time, 20% to 80%, Figure 4
Output High-to-Low Transition Time, 80% to 20%, Figure 4
THLT
TDJ
ps
LVDS Data Jitter, Deterministic (Peak-to-
VID = 300mV; PRBS=223-1 data;
VCM = 1.2V at 400 Mbps (NRZ)
ps
(2)
Peak)
(2)
TRJ
LVDS Clock Jitter, Random
VID = 300mV;
2.8
ps
VCM = 1.2V at 200 MHz clock
TPLHD
TPHLD
TSKEW
TCCS
TPHZ
TPLZ
Propagation Low to High Delay, Figure 5
2.2
2.2
2.8
2.8
20
3.6
3.9
ns
ns
ps
ps
ns
ns
ns
ns
Propagation High to Low Delay, Figure 5
(1)
Pulse Skew |TPLHD - TPHLD
|
340
91
(1)
Output Channel-to-Channel Skew, Figure 6
35
Disable Time (Active to TRI-STATE) High to Z, Figure 1
Disable Time (Active to TRI-STATE) Low to Z, Figure 1
Enable Time (TRI-STATE to Active) Z to High, Figure 1
Enable Time (TRI-STATE to Active) Z to Low, Figure 1
3.0
1.8
10.0
7.0
6.0
6.0
TPZH
TPZL
23.0
23.0
(1) The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage and temperature) range.
(2) The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT
test board and HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable
exhibit a TDJ = 26ps and TRJ = 1.3 ps
AC TIMING DIAGRAMS
Figure 1. Output active to TRI-STATE and TRI-STATE to active output time
4
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SNOSAC2J –AUGUST 2004–REVISED APRIL 2013
Figure 2. LVDS Driver TRI-STATE Circuit
Figure 3. LVDS Output Load
Figure 4. LVDS Output Transition Time
Figure 5. Propagation Delay Low-to-High and High-to-Low
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Figure 6. Output 1 to 10 Channel-to-Channel Skew
APPLICATION INFORMATION
INPUT FAIL-SAFE
The receiver inputs of the DS90LV110A have internal fail-safe biasing for short, open, and teminated input
conditions.
LVDS INPUTS TERMINATION
The LVDS Receiver input must have a 100Ω termination resistor placed as close as possible across the input
pins.
UNUSED CONTROL INPUTS
The EN control input pin has internal pull down device. If left open, the 10 outputs will default to TRI-STATE.
EXPANDING THE NUMBER OF OUTPUT PORTS
To expand the number of output ports, more than one DS90LV110A can be used. Total propagation delay
through the devices should be considered to determine the maximum expansion. Adding more devices will
increase the output jitter due to each pass.
PCB LAYOUT AND POWER SYSTEM BYPASS
Circuit board layout and stack-up for the DS90LV110A should be designed to provide noise-free power to the
device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the
PCB power system which improves power supply filtering, especially at high frequencies, and makes the value
and placement of external bypass capacitors less critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum
capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the
power supply voltage being used. It is recommended practice to use two vias at each power pin of the
DS90LV110A as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up
to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass
components.
The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding
and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be
effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via
placement also improves signal integrity on signal transmission lines by providing short paths for image currents
which reduces signal distortion. The planes should be pulled back from all transmission lines and component
mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric
separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so
minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component
mounting pads.
6
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SNOSAC2J –AUGUST 2004–REVISED APRIL 2013
There are more common practices which should be followed when designing PCBs for LVDS signaling. Please
see Application Note: AN-1108(SNLA008) for additional information.
INPUT INTERFACING
The DS90LV110A accepts differential signals and allow simple AC or DC coupling. With a wide common mode
range, the DS90LV110A can be DC-coupled with all common differential drivers (that is, LVPECL, LVDS, CML).
Figure 7, Figure 8, and Figure 9 illustrate typical DC-coupled interface to common differential drivers.
LVDS
Driver
DS90LV110A
Receiver
100W Differential T-Line
OUT+
OUT-
IN+
100W
IN-
Figure 7. Typical LVDS Driver DC-Coupled Interface to DS90LV110A Input
CML3.3V or CML2.5V
Driver
V
CC
DS90LV110A
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 8. Typical CML Driver DC-Coupled Interface to DS90LV110A Input
LVPECL
Driver
DS90LV110A
Receiver
100W Differential T-Line
IN+
IN-
OUT+
OUT-
100W
50W
50W
Figure 9. Typical LVPECL Driver DC-Coupled Interface to DS90LV110A Input
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OUTPUT INTERFACING
The DS90LV110A outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to
most common differential receivers. Figure 10 illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
DS90LV110A
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
IN-
OUT-
Figure 10. Typical DS90LV110A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
DS90LV110A PIN DESCRIPTIONS
Pin Name
# of Pin
Input/Output
Description
IN+
1
1
I
I
Non-inverting LVDS input
Inverting LVDS input
IN -
OUT+
OUT -
EN
10
10
1
O
O
I
Non-inverting LVDS Output
Inverting LVDS Output
This pin has an internal pull-down when left open. A logic low on the
Enable puts all the LVDS outputs into TRI-STATE and reduces the
supply current.
VSS
VDD
3
2
P
P
Ground (all ground pins must be tied to the same supply)
Power Supply (all power pins must be tied to the same supply)
8
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SNOSAC2J –AUGUST 2004–REVISED APRIL 2013
MULTI-DROP APPLICATIONS
POINT-TO-POINT DISTRIBUTION APPLICATIONS
For applications operating at data rate greater than 400Mbps, a point-to-point distribution application should be
used. This improves signal quality compared to multi-drop applications due to no stub PCB trace loading. The
only load is a receiver at the far end of the transmission line. Point-to-point distribution applications will have a
wider LVDS bus lines, but data rate can increase well above 400Mbps due to the improved signal quality.
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Typical Performance Characteristics
Output Voltage (VOD) vs. Resistive Load (RL)
Peak-to-Peak Output Jitter at VCM = +0.4V vs. VID
Peak-to-Peak Output Jitter at VCM = +1.2V vs. VID
Peak-to-Peak Output Jitter at VCM = +2.9V vs. VID
10
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SNOSAC2J –AUGUST 2004–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision I (April 2013) to Revision J
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90LV110ATMT
NRND
TSSOP
TSSOP
TSSOP
PW
28
28
28
48
Non-RoHS
& Green
Call TI
Level-3-235C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
DS90LV
110ATMT
DS90LV110ATMT/NOPB
DS90LV110ATMTX/NOPB
ACTIVE
ACTIVE
PW
48
RoHS & Green
SN
SN
DS90LV
110ATMT
PW
2500 RoHS & Green
DS90LV
110ATMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV110ATMTX/NOPB TSSOP
PW
28
2500
330.0
16.4
6.8
10.2
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 28
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
DS90LV110ATMTX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90LV110ATMT
DS90LV110ATMT
PW
PW
PW
TSSOP
TSSOP
TSSOP
28
28
28
48
48
48
495
495
495
8
8
8
2514.6
2514.6
2514.6
4.06
4.06
4.06
DS90LV110ATMT/NOPB
Pack Materials-Page 3
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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